INTEGRAL IL9270N

TECHNICAL DATA
DTMF RECEIVER
IL9270
High-Performance Silicon-Gate CMOS
The IL9270N/D is a complete DTMF receiver integrating both the
bandsplit filter and digital decoder functions. The filter section uses
switched capacitor techniques for high- and low-group filters and dialtone rejection. Digital counting techniques are employed in the decoder
to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External
component count is minimized by on-chip provision of a differential
input amplifier, clock-oscillator and latched 3-state bus interface.
• Complete receiver in an 18-pin package.
• Excellent performance.
• CMOS, single 5 volt operation.
• Minimum board area.
• Central office quality.
• Low power consumption.
D SUFFIX
SOIC
ORDERING INFORMATION
IL9270N/D
TA = -10° to 70° C
LOGIC DIAGRAM
PIN ASSIGNMENT
* Connect to GND
PIN 9 = GND
PIN 18 = VCC
PINS 5,6 = NO CONNECTION
IL9270
PIN DESCRIPTIONS
NAME
PIN
DESCRIPTION
ESt
16
Early steering output. Presents a logic high immediately when the digital
algorithm detects a recognizable tone-pair (signal condition). Any momentary
loss of signal condition will cause ESt to return to a logic low.
GS
3
Gain Select. Gives access to output of front-end differential amplifier for
connection of feedback resistor.
IC
5,6
IN+
1
Non-Inverting Input
IN-
2
Inverting Input
C1
7
Clock Input
C2
8
Clock Output
Q1-Q4
11-14
3-state data outputs. When enabled by OE, provide the code corresponding to the
last valid tone-pair received.
StD
15
Delayed steering output. Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on
St/GT falls below VTSt.
St/GT
17
Steering input/guard time output (bi-directional). A voltage greater than VTSt,
detected at St causes the device to register the detected tone-pair and update the
output latch. A voltage less than VTSt frees the device to accept a new tone-pair.
The GT output acts to reset the external steering time-constant; its state is a
function of ESt and the voltage on St.
OE
10
3-state output enable (input). Logic high enables the outputs Q1-Q4. Internal
pull-up.
VCC
18
Positive power supply, +5 V.
VREF
4
Reference voltage output, nominally VCC /2. May be used to bias the inputs at
mid-rail.
GND
9
Negative power supply, normally connected to 0 V.
Internal Connection. Must be tied to GND.
Connections to the front-end
differential amplifier.
3.579545 MHz crystal connected between
these pins completes internal oscillator.
FUNCTIONAL DESCRIPTION
The IL9270 monolithic DTMF receivers offer small size,
low power consumption and high performance. The
architecture consists of a bandsplit filter section, which
separates the high and low tones of a receiver pair,
followed by a digital counting section which verifies the
frequency and duration of the received tones before
passing the corresponding code to the output bus.
Filter Section
Separation of the low-group and high-group tones is
achieved byapplying the dual-tone signal to the inputs of
two filters - a sixth order for the high group and an eight
order for the low group. The band-widths of which
correspond to the bands enclosing the low-group and
high-group tones (see Figure 1). The filter section also
incorporates notches at 350 Hz and 440 Hz for
exceptional dial-tone rejection. Each filter output is
followed by a second order switched-capacitor section
which smooths the signals prior to limiting. Limiting is
performed by high-gain comparators which are provided
with hysteresis to prevent detection of unwanted lowlevel signals and noise; the outputs of the comparators
provide full-rail logic swings at the frequencies of the
incoming tones.
IL9270
Decoder Section
Guard Time Adjustment
The decoder uses digital counting techniques to
determine the frequencies of the limited tones and to
verify that they correspond to standard DTMF
frequencies. A complex averaging algorithm protects
against tone simulation by extraneous signals, such as
voice, while providing tolerance to small frequency
deviations and variations. This averaging algorithm has
been developed to ensure an optimum combination of
immunity to “talk-off” and tolerance to the presence of
interfering signals (“third tones”) and noise. When the
detector recognizes the simultaneous presence of two
valid tones (referred to as “signal condition” in some
industry specifications), it raises the “early steering” flag
(ESt). Any subsequent loss of signal-condition will
cause Est to fall.
Steering Circuit
Before registration of a decoded tone-pair, the receiver
checks for a valid signal duration (referred to as
“character-recognition-condition”). This check is
performed by an external RC time-constant driven by
ESt. A logic high on ESt causes VC (see Figure 2) to rise
as the capacitor discharges. Provided signal-condition is
maintained (ESt remains high) for the validation period
(tGTP), VC reaches the threshold (VTSt) of the steering
logic to register the tone-pair, latching its corresponding
4-bit code (see Figure 3) into the output latch. At this
point, the GT output is activated and drives VC to VCC.
GT continues to drive high as long as ESt remains high.
Finally after a short delay to allow the output latch to
settle, the “delayed-steering” output flag, StD, goes high,
signaling that a received tone-pair has been registered.
The contents of the output latch are made available on
the 4-bit output bus by raising the 3-state control input
(OE) to a logic high. The steering circuit works in
reverse to validate the interdigit pause between signals.
Thus, as well as rejecting signals too short to be
considered valid, the receiver will tolerate signal
interruptions (“drop-out”) too short to be considered a
valid pause. The facility, together with the capability of
selecting the steering time-constants externally, allows
the designer to tailor performance to meet a wide variety
of system requirements.
In many situations not requiring independent selection of
receive and pause, the simple steering circuit of Figure 2
is applicable. Component values are chosen according to
the following formula:
tREC = tDP + tGTP
tID = tDA + tGTA
The value of tDP is a parameter of the device and tREC is
the minimum signal duration to be recognized by the
receiver. A value for C of 0.1 µF is recommended for
most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a tREC of
40 ms would be 300 k.
Different steering arrangements may be esed to select
independently the guard-times for tone-present (tGTP) and
tone-absent (tGTA). This may be necessary to meet
system specifications which place both accept and reject
limits on both tone duration and inter-digital pause.
Guard-time adjustment also allows the designer to tailor
system parameters such as talk-off and noise immunity.
Increasing tREC improves talk-off performance, since it
reduces the probability that tones simulated by speech
will maintain signal condition for long enough to be
registered. On the other hand, a relatively short tREC with
a long tDO would be appropriate for extremely noisy
environments where fast acquisition time and immunity
to drop-outs would be requirements. Design information
for guard-time adjustment is show in Figure 4.
Input Configuration
The input arrangement of the IN9270 provides a
differential-input operational amplifier as well as a bias
source (VREF) which is used to bias the inputs at mid-rail.
Provision is made for connection of a feedback resistor
to the op-amp output (GS) for adjustment of gain.
In a single-ended configuration, the input pins are
connected as shown in Figure 5 with the op-amp
connected for unity gain and VREF biasing the input at
1/2VCC. Figure 6 shows the differential configuration,
which permits the adjustment of gain with the feedback
resistor R5.
IL9270
MAXIMUM RATINGS*
Symbol
Parameter
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
IIN
DC InputCurrent, per Pin
PD
Tstg
Power Dissipation in Still Air,
Value
Unit
-0.3 to +6.0
V
-0.3 to VCC +0.3
V
10
mA
500
mW
-65 to +150
°C
**
Plastic DIP
Storage Temperature
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**
Derating: -10 mW/°C from 65°C to 70°C.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
4.75
5.25
V
VIN
DC Input Voltage (Referenced to GND)
1.5
3.5
V
TA
Operating Temperature
-10
+70
°C
PO
Power Consumption ( f = 3.579 MHz, VCC = 5 V)
-
45
mW
tr, tf
Input Rise and Fall Time
0
110
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
IL9270
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND, VCC = 5 V ± 5%,
TA = -10 to +70°C)
Guaranteed Limits
Symbol
Parameter
Test Conditions
Min
Typ
Max
3.6
Unit
VIH
Minimum High-Level
Input Voltage
VOUT =5 V
V
VIL
Maximum Low-Level
Input Voltage
VOUT =5 V
VOH
Minimum High-Level
Output Voltage
No Load
VOL
Maximum Low-Level
Output Voltage
No Load
0.05
V
IIN
Maximum Input Leakage
Current
VIN=VCC or GND
±0.1
µA
ISO
Maximum Pull Up
(Source) Current
OE = 0 V
24
µA
IOL
Minimum Output-Low
(Sink) Current
VOUT =0.4 V
0.8
mA
IOH
Minimum Output-High
(Source) Current
VOUT =4.6 V
0.35
mA
ICC
Maximum Quiescent
Supply Current (per
Package)
VIN =VCC
VTSt
Steering Threshold
Voltage
RIN
Input Impedance (Signal
Inputs 1,2)
@ 1 KHz
8
VREF
Output Voltage
No Load
2.4
ROR
Output Resistance
IOZ
Maximum Three-State
Leakage current
1.4
4.97
V
2.2
11
mA
2.5
V
MΩ
2.8
10
Output in HighImpedance State
VIN =VIL
VOUT=VCC or GND
V
V
kΩ
±0.1
µA
IL9270
OPERATING CHARACTERISTICS
Gain Setting Amplifier
Symbol
Parameter
Test Conditions
GND< VIN < VCC
Typ
Unit
±100
nA
IN
Input Leakage Current
RIN
Input Resistance
10
MΩ
VOS
Input Offset Voltage
±25
mV
PSRR
Power Supply Rejection
1 KHz
60
dB
CMRR
Common Mode Rejection
-3.0 V < VIN < 3.0 V
60
dB
DC Open Loop Voltage Gain
65
dB
fC
Open Loop Unity Gain Bandwidth
1.5
MHz
VO
Output Voltage Swing
4.5
VPP
CL
Tolerable Resistive Load (GS)
100
pF
RL:
Tolerable Resistive Load (GS)
50
KΩ
VCM
Common Mode Range
3.0
VPP
AVOL
RL ≥100 KΩ to GND
No Load
AC ELECTRICAL CHARACTERISTICS (All Voltages referenced to GND. VCC = 5.0 V, GND = 0 V, TA
= -10 to +70°C, FCLK = 3.579545 Mhz, using test circuit of Figure 5)
Parameter
Guaranteed Limits
Min
Typ
Max
Unit
Notes
-29
dBm
1,2,3,5,6,9
27.5
m VRMS
1,2,3,5,6,9
+1
dBm
1,2,3,5,6,9
883
m VRMS
SIGNAL CONDITION
Valid Input Signal
MIN
Level (each tone of
composite signal)
MAX
NON-ACCEPT LEVEL
±1.5%
±2 Hz
Freq. Deviation Accept Limit
Freq. Deviation Reject Limit
±3.5%
Nom.
2,3,5,9
Nom.
2,3,5
Third Tone Tolerance
-2.5
dB
2,3,4,5,7,9,10
Dial Tone Tolerance
+18
dB
2,3,4,5,8,9,10
IL9270
TIMING REQUIREMENTS (All Voltages referenced to GND. VCC = 5.0 V, GND = 0 V, TA = -10 to +70°C,
FCLK = 3.579545 Mhz, using test circuit of Figure 5)
Symbol
Parameter
Guaranteed
Limits
Min
Max
Unit
Notes
tDP
Tone Present Detection Time (Figure 7)
5
18
ms
Refer to
tDA
Tone Absent Detection Time (Figure 7)
0.5
10
ms
Fig. 7
tREC
Maximum Tone Detection Accept (Figure 7)
40
ms
(User
Adjustable)
tREC
Minimum Tone Detection Reject (Figure 7)
tID
Maximum Interdigit Pause Accept (Figure 7)
tDO
Minimum Interdigit Pause Reject (Figure 7)
tPQ
Maximum Propagation Delay (St to Q) (Figure 7)
tPSED
20
ms
ms
Refer to
“Guard Time
ms
Adjustment”
11
µs
OE = VCC
Maximum Propagation Delay (St to StD) (Figure 7)
16
µs
tQSED
Maximum Output Data Set Up (Q to StD) (Figure 7)
5
µs
tPTE
Maximum
Propagation Delay
ENABLE
75
ns
tPTD
(OE to Q) (Figure 7)
DISABLE
460
ns
fCLK
Crystal/Clock Frequency
3.581
MHz
CLO
Clock Output (C2)
30
pF
Notes:
40
20
3.5759
Capacitive
Load
RL= 10 KΩ
CL= 50 pF
1. dBm = decibels above or below a reference power of 1 mW into a 600 Ω load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40 ms, Tone pause = 40 ms.
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have an equal amlitude.
6. Tone pair is deviated by ±1.5% ±2 Hz.
7. Bandwidth limited (3 KHz) Gaussian Noise.
8. The precise dial tone frequencies are (350 Hz and 440 Hz) ±2%.
9. For an error rate of less than 1 in 10,000.
10. Referenced to the lowest level frequency component in DTMF signal.
Figure 1. Typical Filter Characteristic
IL9270
tGTA = (RC) ln
( )
tGTA = (RC) ln
(
VCC
VTST
VCC
)
VCC - VTST
Figure 2. Basic Steering Circuit
FLOW
FHIGH
KEY
OE
Q4
Q3
Q2
Q1
697
1209
1
H
0
0
0
1
697
1336
2
H
0
0
1
0
697
1477
3
H
0
0
1
1
770
1209
4
H
0
1
0
0
770
1336
5
H
0
1
0
1
770
1477
6
H
0
1
1
0
852
1209
7
H
0
1
1
1
852
1336
8
H
1
0
0
0
852
1477
9
H
1
0
0
1
941
1336
0
H
1
0
1
0
941
1209
*
H
1
0
1
1
941
1477
#
H
1
1
0
0
697
1633
A
H
1
1
0
1
770
1633
B
H
1
1
1
0
852
1633
C
H
1
1
1
1
941
1633
D
H
0
0
0
0
ANY
L
Z
Z
Z
Z
“L = Logic Low, H = Logic High, Z = High Impedance”
Figure 3. Logic Table
IL9270
tGTP= (RPC) ln
(
tGTA = (R1 C) ln
(
VCC
)
VCC - VTST
VCC
VTST
)
R1 R2
RP =
R1 + R2
a) Descreasing tGTP ( tGTP < tGTA )
tGTP= (R1C) ln
(
tGTA = (RPC) ln
(
)
VCC
VCC - VTST
VCC
VTST
)
R1 R2
RP =
R1 + R2
b) Descreasing tGTA ( tGTP > tGTA )
Figure 4.Guard Time Adjustment
Figure 5. Single Ended Input Configuration
IL9270
Figure 6. Differential Input Configuration
TIMING DIAGRAM
A.
B.
C.
D.
E.
F.
G.
Short tone bursts: detected. Tone duration is invalid.
Tone #n is detected. Tone duration is valid. Decoded to outputs.
End of tone #n is detected and validated.
3 State outputs disabled (high impedance).
Tone #n+1 detected. Tone duration is valid. Decoded to outputs.
Tristate outputs are enabled. Acceptable drop out of tone #n+1 does not register at outputs.
End of tone #n+1 is detected and validated.
IL9270
EXPANDED LOGIC DIAGRAM
IL9270
N SUFFIX PLASTIC DIP
(MS - 001AC)
A
Dimension, mm
18
10
B
1
9
Symbol
MIN
MAX
A
22.35
23.37
B
6.1
7.11
5.33
C
F
L
C
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
-T- SEATING
PLANE
N
G
M
K
H
D
J
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 013AD)
Dimension, mm
A
18
10
H
B
1
G
9
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
10.1
10.5
B
7.4
7.6
C
2.35
2.65
D
0.33
0.51
F
0.4
1.27
1.27
G
H
J
0°
8°
K
0.1
0.3
M
0.23
0.32
P
10
10.65
R
0.25
0.75