TECHNICAL DATA IN7406 Hex Inverter Buffers/Drivers with Open-Collector High-Voltage Outputs The IN7406 monolithic TTL hex inverter buffers/drivers feature high-voltage open collector outputs for interfacing with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and are also characterized for use as inverter buffers for driving TTL inputs. • • • • • Minimum breakdown Voltages is 30 V Maximum sink Current is 40 mÀ Converts TTL Voltage Levels to MOS Levels Open-Collector Driver for Indicator Lamps and Relays Inputs Fully Compatible with MOST TTL Circuits. ORDERING INFORMATION IN7406N Plastic IN7406D SOIC IZ7406 Chip TA = -10° to 70° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Output A Y L Z H L Z = High Impedance Y=A PIN 14 =VCC PIN 7 = GND INTEGRAL 1 IN7406 MAXIMUM RATINGS * Symbol Parameter Value Unit VCC Supply Voltage 7.0 V VIN Input Voltage 5.5 V VOUT Output Voltage 30 V Tstg Storage Temperature Range -65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 5.25 V VCC Supply Voltage 4.75 VIH High Level Input Voltage 2.0 VIL Low Level Input Voltage 0.8 V UOH High Level Output Voltage 30 V IOL Low Level Output Current 40 mA TA Ambient Temperature Range +70 °C -10 V DC ELECTRICAL CHARACTERISTICS Guaranteed Limit Symbol Parameter Test Conditions Min Max Unit VIK Input Clamp Voltage VCC = 4.75V, IIN = -12 mA -1.5 V IOH High Level Output Current VCC = 4.75V, VOH =30V 0.25 mA VOL Low Level Output Voltage VCC = 4.75V, IOL = 16 mA 0.4 V VCC = 4.75V, IOL = 40 mA 0.7 IIH High Level Input Current VCC = 5.25V, VIN = 2.4 V 0.04 mA IIL Low Level Input Current VCC = 5.25V, VIN = 0.4 V -1.6 mA ICC Supply Current VCC = 5.25V Outputs High 48 mA Outputs Low 51 INTEGRAL 2 IN7406 AC ELECTRICAL CHARACTERISTICS (T = 25°C, VCC = 5.0 V, CL = 15 pF, RL = 110 Ω, Input t r = tf = 10 ns) Symbol Parameter Min Max Unit tPLH Propagation Delay Time, Low to High Level Output (from Input to Output) 18 ns tPHL Propagation Delay Time, High to Low Level Output (from Input to Output) 28 ns Figure 1. Switching Waveforms * Includes all probe and jig capacitance Figure 2. Test Circuit INTEGRAL 3 IN7406 CHIP PAD DIAGRAM IZ7406 12 11 10 09 08 13 Chip marking ËÍ3 07 01 06 03 02 04 05 1.45 ± 0.03 (0,0) Pad size 0.140 x 0.140 mm (Pad size is given as per metallization layer) Thickness of chip 0,46±0,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 Symbol A1 Y1 A2 Y2 A3 Y3 GND Y4 A4 Y5 A5 Y6 A6 VCC INTEGRAL X 0.090 0.090 0.460 0.830 1.220 1.220 1.220 1.220 1.220 0.830 0.460 0.090 0.090 0.090 Y 0.380 0.090 0.090 0.090 0.090 0.380 0.630 0.880 1.170 1.170 1.170 1.170 0.880 0.630 4