IN74HC221A DUAL MONOSTABLE MULTIVIBRATOR • • • • The IN74HC221A is identical in pinout to the LS/ALS221. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. There are two trigger inputs, A INPUT (negative edge) and B INPUT (positive edge). These inputs are valid for rising/falling signals The device may also be triggered by using the RESET input (positive-edge) because of the Schmitt-trigger input; after triggering the output maintains the MONOSTABLE state for the time period determined by the external resistor REXT and capacitor CEXT. Taking RESET low breaks this MONOSTABLE STATE. If the next trigger pulse occurs during the MONOSTABLE period it makes the MONOSTABLE period longer. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC 16 1 16 1 ORDERING INFORMATION IN74HC221AN Plastic IN74HC221AD SOIC IZ74HC221AZ Chip TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM DEXT DEXT CEXT CEXT REXT D SUFFIX SOIC REXT PIN 16 =VCC PIN 8 = GND 1A 1 16 1B 2 15 V CC 1REXT/CEXT 1RESET 3 14 1CEXT 1Q 4 13 1Q 2Q 5 12 2Q 2CEXT 6 11 2RESET 2REXT/CEXT 7 10 2B GND 8 9 2A FUNCTION TABLE A Inputs B RESET H H Outputs Q Q Note X L H L* H* (1) CEXT, REXT, DEXT are external components. * H X H L H* (2) DEXT is a clamping diode. L H The external capacitor is charged to VCC in the stand-by state, i.e. no trigger. When the supply voltage is turned off L H CX is discharged mainly through an internal parasitic diode. If CX is sufficiently large and VCC decreases rapidy, X X L L H there will be some possibility of damaging the I.C. with a X = don’t care surge current or latch-up. If the voltage supply filter * - except for monostable period capacitor is large enough and VCC decrease slowly, the surge current is automatically limited and damage the I.C. is avoided. The maximum forward current of the parasitic diode is approximately 20 mA. 1 Note Output Enable Inhibit Inhibit Output Enable Output Enable Inhibit IN74HC221A MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA ±20 A , B, RESET ±30 CEXT, REXT IOUT DC Output Current, per Pin mA ±25 ICC DC Supply Current, VCC and GND Pins mA ±50 PD Power Dissipation in Still Air, Plastic DIP** 750 mW SOIC Package** 500 Tstg Storage Temperature -65 to +150 °C 260 TL Lead Temperature, 1 mm from Case for 10 °C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time - RESET VCC =2.0 V VCC =4.5 V (Figure 2) VCC =6.0 V A A or B Min 3.0 * 0 Max 6.0 VCC Unit V V +125 °C 1000 ns 500 400 No Limit RX External Timing Resistor VCC <4.5 V 10 1000 kΩ 2.0 1000 VCC ≥ 4.5 V CX External Timing Capacitor 0 No µF Limit * The IN74HC221 will function at 2.0 V but for optimum pulse width stability, VCC should be above 3.0 V. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 -55 0 0 0 - IN74HC221A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V ≤85 ≤125 -55°C to °C °C 25 °C 0.3 0.3 0.3 VIL Maximum Low - VOUT ≤ 0.1 V or 2.0 0.9 0.9 0.9 Level Input Voltage VCC=0.1 V 4.5 1.2 1.2 1.2 6.0 IOUT ≤ 20 µA 1.5 1.5 1.5 VIH Minimum High-Level VOUT ≤ 0.1 V or 2.0 3.15 3.15 3.15 Input Voltage VCC=0.1 V 4.5 4.2 4.2 4.2 6.0 IOUT ≤ 20 µA 0.1 0.1 0.1 VOL Maximum Low-Level VIN=VIH or VIL 2.0 0.1 0.1 0.1 Output Voltage 4.5 IOUT ≤ 20 µA 0.1 0.1 0.1 6.0 VIN=VIH or VIL 4.5 0.26 0.33 0.4 IOUT ≤ 4.0 mA VIN=VIH or VIL 6.0 0.26 0.33 0.40 IOUT ≤ 5.2 mA 1.9 1.9 1.9 VOH Minimum High- VIN=VIH or VIL 2.0 4.4 4.4 4.4 Level Output IOUT ≤ -20 µA 4.5 5.9 5.9 5.9 Voltage 6.0 VIN=VIH or VIL 4.5 3.98 3.84 3.70 IOUT ≤ -4.0 mA VIN=VIH or VIL 6.0 5.48 5.34 5.2 IOUT ≤ -5.2 mA IIL Maximum Low- VIL=GND 6.0 -0.1 -1.0 -1.0 Level Output VIH=VCC Current IIH Minimum High- VIL=GND 6.0 0.1 1.0 1.0 Level Input Current VIH=VCC VIL=GND 6.0 8.0 80 160 ICC Maximum Quiescent Supply VIН=VCC Current (per IOUT=0 µA Package) Standby State 0.13 0.11 0.08 ICC1 Maximum Supply VIL=GND 2.0 1.6 1.3 1.0 Current (per VIH=VCC 4.5 3.2 2.6 2.0 Package) Active IOUT=0 µA 6.0 State VIN = 0.5 VCC 3 Unit V V V V µA µA µA mA IN74HC221A AC ELECTRICAL CHARACTERISTICS Parameter Symbol tPHL Maximum Propagation Delay A, B - Q RESET - Q Test Conditions VCC V VIL=0 V VIH=VCC tLH=tHL=6 ns CL=50 pF CEXT=0 REXT=5 kΩ 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 V VIL=0 VIH=VCC tLH=tHL=6 ns CL=50 pF CEXT=0 REXT=5 kΩ 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 220 44 37 245 49 42 200 40 34 75 16 14 275 55 47 305 61 52 250 50 43 95 20 17 330 66 56 370 74 63 300 60 51 110 22 20 - 10 20 10 20 10 20 RESET - Q tPLH Maximum Propagation Delay A, B - Q RESET - Q RESET - Q tTLH, tTHL CIN CPD trec tw tWQ Maximum Output Transition Time, Any Output(Figures 2 and 3) VIL=0 V VIH=VCC tLH=tHL=6 нс CL=50 pF Maximum A , B, RESET Input CX, RX Capacitance Power Dissipation Capacitance (Per Multivibrator) PD=CPDVCC2f+ICCVCC Minimum Recovery Time, VIL=0 V Inactive to A or B VIH=VCC tLH=tHL=6 нс (Figure 2) CL=50 pF Minimum V V IL=0 A, RESET Pulse Width VIH=VCC tLH=tHL=6 ns pF CL=50 B CEXT=0 REXT=5 kΩ Minimum Pulse Width СEXT =0 пФ (Figure 4) REXT=5 kΩ СEXT =1 nF REXT=10 kΩ СEXT =1 µF REXT=10 kΩ * ТА=25±10°C 4 Guaranteed Limit ≤85 ≤125 -55°C to °C °C 25°C 180 225 270 36 45 54 31 38 46 180 225 270 36 45 54 31 38 46 195 245 295 39 49 59 33 42 50 180* 5.0 Unit ns ns ns pF pF 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns 2.0 4.5 6.0 2.0 4.5 6.0 5.0 25 9 7 30 11 9 95 19 16 115 23 20 105* 110 22 19 135 27 23 ns 2.0 4.5 6.0 2.0 4.5 6.0 0.80* 0.75* 0.70* 80* 75* 70* ns µs IN74HC221A Figure 1. Switching Waveforms RESET Figure 2. Switching Waveforms Figure 3. Test Circuit 5 IN74HC221A TIMING DIAGRAM REXT/CEXT EXPANDED LOGIC DIAGRAM REXT/CEXT CEXT 6 IN74HC221A CHIP PAD DIAGRAM IZ74HC221A 2.1 ±0.03 14 13 12 11 09 16 Chip marking 15HC221 (x=0.140, y=0.884) 08 1 02 10 03 04 05 06 1.8 ±0.03 15 07 (0,0) Pad size 0.106 x 0.106 mm (Pad size is given as per passivation layer) Thickness of chip 0,46±0,02 mm Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 Symbol 1A 1B 1RESET 1Q 2Q 2CEXT 2REXT/CEXT GND 2A 2B 2RESET 2Q 1Q 1CEXT 1REXT/CEXT VCC PAD LOCATION X 0.152 0.157 0.458 0.715 1.310 1.585 1.836 1.847 1.836 1.837 1.536 1.278 0.684 0.408 0.158 0.147 7 Y 0.419 0.132 0.134 0.122 0.122 0.122 0.132 0.690 1.275 1.562 1.560 1.572 1.572 1.572 1.562 1.004