ISSI IS41LV8205A 2M x 8 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE ® FEBRUARY 2005 FEATURES DESCRIPTION • Fast Page Mode Access Cycle • TTL compatible inputs and outputs • Refresh Interval: -- 2,048 cycles/32 ms • Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden • Single power supply: 3.3V ± 10% • Byte Write and Byte Read operation via two CAS • Lead-free available The ISSI IS41LV8205A is 2,097,152 x 8-bit high-performance CMOS Dynamic Random Access Memory. The Fast Page Mode allows 2,048 random accesses within a single row with access cycle time as short as 20 ns per 4bit word. These features make the IS41LV8205A ideally suited for high-bandwidth graphics, digital signal processing, highperformance computing systems, and peripheral applications. The IS41LV8205A is packaged in 28-pin 300-mil SOJ with JEDEC standard pinouts. PRODUCT SERIES OVERVIEW Part No. IS41LV8205A Refresh Voltage 2K 3.3V ± 10% KEY TIMING PARAMETERS Parameter -50 -60 Unit RAS Access Time (tRAC) 50 60 ns CAS Access Time (tCAC) 14 15 ns Column Address Access Time (tAA) 25 30 ns PIN CONFIGURATION Fast Page Mode Cycle Time (tPC) 20 25 ns 28 Pin SOJ Read/Write Cycle Time (tRC) 85 104 ns VDD 1 28 GND I/O0 2 27 I/O7 I/O1 3 26 I/O6 I/O2 4 25 I/O5 I/O3 5 24 I/O4 A0-A10 Address Inputs WE 6 23 CAS RAS 7 22 OE I/O0-7 Data Inputs/Outputs NC 8 21 A9 WE Write Enable A10 9 20 A8 OE Output Enable A0 10 19 A7 RAS Row Address Strobe A1 11 18 A6 CAS Column Address Strobe A2 12 17 A5 A3 13 16 A4 VDD Power VDD 14 15 GND GND Ground NC No Connection PIN DESCRIPTIONS Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 1 ISSI IS41LV8205A ® FUNCTIONAL BLOCK DIAGRAM OE WE CAS CAS CONTROL LOGIC WE CONTROL LOGIC CAS OE CONTROL LOGIC WE OE RAS CLOCK GENERATOR RAS DATA I/O BUS COLUMN DECODER SENSE AMPLIFIERS ROW DECODER REFRESH COUNTER ADDRESS BUFFERS A0-A10 DATA I/O BUFFERS RAS I/O0-I/O7 MEMORY ARRAY 2,097,152 x 8 TRUTH TABLE Function RAS CAS WE OE Address tR/tC I/O Standby H H X X X High-Z Read L L H L ROW/COL DOUT Write: Word (Early Write) L L L X ROW/COL DIN Read-Write L L H→L L→H ROW/COL DOUT, DIN L→H→L L→H→L L L H L L X ROW/COL ROW/COL DOUT DOUT L H X X ROW/NA High-Z H→L L X X X High-Z Hidden Refresh Read Write(1) RAS-Only Refresh CBR Refresh Note: 1. EARLY WRITE only. 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 ISSI IS41LV8205A ® Functional Description Auto Refresh Cycle The IS41LV8205A is CMOS DRAMs optimized for highspeed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 11 address bits. These are entered 11 bits (A0-A10) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter ten bits. To retain data, 2,048 refresh cycles are required in each 32 ms period. There are two ways to refresh the memory: Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. 1. By clocking each of the 2,048 row addresses (A0 through A10) with RAS at least once every 32 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Power-On After application of the VDD supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VDD or be held at a valid VIH to avoid current surges. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 3 ISSI IS41LV8205A ® ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters Rating Unit VT Voltage on Any Pin Relative to GND 3.3V –0.5 to +4.6 V VDD Supply Voltage 3.3V –0.5 to +4.6 V IOUT Output Current 50 mA PD Power Dissipation 1 W TSTG Storage Temperature –55 to +125 °C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol VDD VIH VIL Parameter Supply Voltage Input High Voltage Input Low Voltage 3.3V 3.3V 3.3V Min. Typ. Max. Unit 3.0 2.0 –0.3 3.3 — — 3.6 VDD + 0.3 0.8 V V V CAPACITANCE(1,2) Symbol CIN1 CIN2 CIO Parameter Input Capacitance: A0-A10(A11) Input Capacitance: RAS, CAS, WE, OE Data Input/Output Capacitance: I/O0-I/O3 Max. Unit 5 7 7 pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 ISSI IS41LV8205A ® ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Test Condition IIL Input Leakage Current IIO VDD Speed Min. Max. Unit Any input 0V ≤ VIN ≤ VDD Other inputs not under test = 0V –5 5 µA Output Leakage Current Output is disabled (Hi-Z) 0V ≤ VOUT ≤ VDD –5 5 µA VOH Output High Voltage Level IOH = –5.0 mA, VDD = 5V IOH = –2.0 mA, VDD = 3.3V 2.4 — V VOL Output Low Voltage Level IOL = 4.2 mA, VDD = 5V IOL = 2 mA, VDD = 3.3V — 0.4 V ICC1 Standby Current: TTL RAS, CAS ≥ VIH 3.3V — 1 mA ICC2 Standby Current: CMOS RAS, CAS ≥ VDD – 0.2V 3.3V — 1 mA ICC3 Operating Current: Random Read/Write(2,3) Average Power Supply Current RAS, CAS, Address Cycling, tRC = tRC (min.) -50 -60 — — 150 140 mA ICC4 Operating Current: Fast Page Mode(2,3,4) Average Power Supply Current RAS= VIL, CAS ≥ VIH tRC = tRC (min.) -50 -60 — — 150 140 mA ICC5 Refresh Current: RAS-Only(2,3) Average Power Supply Current RAS Cycling, CAS ≥ VIH tRC = tRC (min.) -50 -60 — — 150 140 mA ICC6 Refresh Current: CBR(2,3,5) Average Power Supply Current RAS, CAS Cycling tRC = tRC (min.) -50 -60 — — 150 140 mA Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each Fast Page cycle. 5. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 5 ISSI IS41LV8205A ® AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 Symbol Parameter tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(23) CAS Precharge Time(9) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time RAS Hold Time from CAS Precharge CAS to Output in Low-Z(15, 24) CAS to RAS Precharge Time(21) Output Disable Time(19, 24) Output Enable Time(15, 16) Output Enable Data Delay (Write) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs tRAD tRAL tRPC tRSH tRHCP tCLZ tCRP tOD tOE tOED tOEHC tOEP tOES tRCS tRRH tRCH tWCH tWCR tWP tWPZ 6 -60 Min. Max. Min. Max. Units 85 — — — 50 30 8 8 45 19 0 9 0 7 44 — 50 14 25 10K — 10K — — 37 — — — — — 104 — — — 60 40 10 15 45 18 0 10 0 10 55 — 60 15 30 10K — 10K — — 45 — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 14 25 5 14 30 0 5 5 — 8 7 8 5 0 0 25 — — — — — — 15 12 — — — — — — 13 30 5 13 35 0 5 5 — 13 7 8 5 0 0 30 — — — — — — 15 15 — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 — 0 — ns 8 40 — — 10 50 — — ns ns 8 7 — — 10 7 — — ns ns Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 ISSI IS41LV8205A ® AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 Symbol Parameter tRWL -60 Min. Max. Min. Max. Units Write Command to RAS Lead Time 13 — 15 — ns tCWL Write Command to CAS Lead Time(17, 21) 8 — 10 — ns tWCS Write Command Setup Time(14, 17, 20) 0 — 0 — ns tDHR Data-in Hold Time (referenced to RAS) 46 — 55 — ns tACH Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) Fast Page Mode READ or WRITE Cycle Time RAS Pulse Width Access Time from CAS Precharge(15) READ-WRITE Cycle Time(24) Data Output Hold after CAS LOW Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 24) Output Disable Delay from WE CAS Setup Time (CBR REFRESH)(20, 25) CAS Hold Time (CBR REFRESH)( 21, 25) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Auto Refresh Period 2,048 Cycles Transition Time (Rise or Fall)(2, 3) 15 — 15 — ns 8 — 10 — ns 0 8 108 64 — — — — 0 10 133 79 — — — — ns ns ns ns 25 37 20 — — — 32 47 25 — — — ns ns ns 50 — 59 5 0 100K 30 — — 12 63 — 68 5 0 100K 32 — — 15 ns ns ns ns ns 3 10 10 0 10 — — — 3 10 10 0 10 — — — ns ns ns ns — 2 32 50 — 2 32 50 ms ns tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tCOH tOFF tWHZ tCSR tCHR tORD tREF tT (17) AC TEST CONDITIONS Output load: One TTL Load and 50 pF (VDD = 3.3V ±10%) Input timing reference levels: VIH = 2.0V, VIL = 0.8V (VDD = 3.3V ±10%) Output timing reference levels: VOH = 2.0V, VOL = 0.8V (VDD = 3.3V ±10%) Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 7 IS41LV8205A ISSI ® Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD ≥ tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. Determined by falling edge of CAS. 21. Determined by rising edge of CAS. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 23. CAS must meet minimum pulse width. 24. The 3 ns minimum is a parameter guaranteed by design. 25. Enables on-chip refresh and address counters. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 ISSI IS41LV8205A ® READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH CAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Don’t Care Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 9 ISSI IS41LV8205A ® READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS tAR tRAD tRAH tASR tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tRCS tAWD tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tOD tDH Valid DIN Open tOEH OE Don’t Care 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 ISSI IS41LV8205A ® EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don’t Care Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 11 ISSI IS41LV8205A ® FAST-PAGE-MODE READ CYCLE tRASP tRP RAS tPRWC tCAS tCSH tCAS tCRP tRCD tRSH tCAS tCP tCRP tCP CAS tAR tRAH tRAD tASC tASR ADDRESS tCPWD tRAL tCAH tCPWD Row tCAH tASC tAR Column tCAH Column tASC Column tRCS WE tAA tAA tCAC tCAC tOE OE tRAC 12 tCAC tOE tOED tCLZ I/O tAA tOED tCLZ OUT tOE tOED tCLZ OUT OUT Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 ISSI IS41LV8205A ® FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRASP tRP RAS tPRWC tCAS tCSH tCAS tCRP tRCD tRSH tCAS tCP tCRP tCP CAS tAR tRAH tRAD tASC tASR ADDRESS tCPWD tRAL tCAH tCPWD Row tCAH tAR Column tASC Column tCWL tRWD tAWD tCWD tRCS tCAH tASC Column tCWL tRWL tCWL tAWD tCWD tWP tAWD tCWD tWP tWP WE tAA tAA tCAC tCAC tOEA OE tCAC tOEA tOEZ tOED tRAC tOEA tOEZ tOED OUT IN tOEZ tOED tDH tDH tDS tCLZ tCLZ I/O tAA tDS OUT IN tDH tCLZ OUT tDS IN Don’t Care Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 13 ISSI IS41LV8205A ® FAST PAGE MODE EARLY WRITE CYCLE tRASP tRP RAS tCAS tCRP tRHCP tRSH tCAS tPC tCAS tCSH tRCD tCP tCRP tCP CAS tAR tRAL tRAH tRAD tASC tASR ADDRESS Row tCAH tCAH tAR Column tASC Column Column tCWL tWCS tWCH tCAH tASC tCWL tWCH tWCS tWCS tWP tCWL tWP tWCH tWP WE tWCR OE tDHR tDS I/O tDH Valid DIN tDS tDH Valid DIN tDS tDH Valid DIN Don’t Care 14 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 ISSI IS41LV8205A ® RAS RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC CAS tASR ADDRESS tRAH Row I/O Row Open Don’t Care Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 15 ISSI IS41LV8205A ® CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tCHR tRPC tCP tCHR tRPC tCSR tCSR CAS Open I/O Don’t Care HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR CAS tAR tRAD tRAH tASC tASR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Valid Data tOE Open tOD tORD OE Don’t Care 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 ISSI IS41LV8205A ® ORDERING INFORMATION Voltage: 3.3V Speed (ns) Order Part No. Package 50 IS41LV8205A-50J IS41LV8205A-50JL 300-mil SOJ 300-mil SOJ, Lead-free 60 IS41LV8205A-60J IS41LV8205A-60JL 300-mil SOJ 300-mil SOJ, Lead-free Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 02/01/05 17 ISSI PACKAGING INFORMATION ® 300-mil Plastic SOJ Package Code: J N E1 E 1 SEATING PLANE D A B e A2 C b A1 E2 MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 24/26 A — — 3.56 — A1 0.64 — — 0.025 — — A2 2.41 — 2.67 0.095 — 0.105 b 0.41 — 0.51 0.016 — 0.020 B 0.66 — 0.81 0.026 — 0.032 — 0.140 C 0.20 — 0.25 0.008 — 0.010 D 17.02 — 17.27 0.670 — 0.680 E 8.26 — 8.76 0.325 — 0.345 E1 7.49 — 7.75 0.295 — 0.305 E2 6.27 — 7.29 0.247 — 0.287 e 1.27 BSC Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/25/03 ISSI PACKAGING INFORMATION ® 300-mil Plastic SOJ Package Code: J MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 28 MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 32 A — — 3.56 — — 0.140 A — — 3.56 — — 0.140 A1 0.64 — — 0.025 — — A1 0.64 — — 0.025 — — A2 2.41 — 2.67 0.095 — 0.105 A2 2.41 — 2.67 0.095 — 0.105 b 0.41 — 0.51 0.016 — 0.020 b 0.41 — 0.51 0.016 — 0.020 B 0.66 — 0.81 0.026 — 0.032 B 0.66 — 0.81 0.026 — 0.032 C 0.20 — 0.25 0.008 — 0.010 C 0.20 — 0.25 0.008 — 0.010 D 18.29 — 18.54 0.720 — 0.730 D 20.83 — 21.08 0.820 — 0.830 E 8.26 — 8.76 0.325 — 0.345 E 8.26 — 8.76 0.325 — 0.345 E1 7.49 — 7.75 0.295 — 0.305 E1 7.49 — 7.75 0.295 — 0.305 E2 6.27 — 7.29 0.247 — 0.287 E2 6.27 — 7.29 0.247 — 0.287 e 2 1.27 BSC 0.050 BSC e 1.27 BSC 0.050 BSC Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/25/03