TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Data Bus With a Bus-Holder Feature Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space 16K x 16-Bit On-Chip ROM 32K x 16-Bit Dual-Access On-Chip RAM Single-Instruction-Repeat and Block-Repeat Operations for Program Code Block-Memory-Move Instructions for Better Program and Data Management Instructions With a 32-Bit Long Word Operand Instructions With Two- or Three-Operand Reads D D D D D D D D D D D Arithmetic Instructions With Parallel Store and Parallel Load Conditional Store Instructions Fast Return From Interrupt On-Chip Peripherals – Software-Programmable Wait-State Generator and Programmable Bank Switching – On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source – Three Multichannel Buffered Serial Ports (McBSPs) – Enhanced 8-Bit Parallel Host-Port Interface With 16-Bit Data/Addressing – One 16-Bit Timer – Six-Channel Direct Memory Access (DMA) Controller Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes CLKOUT Off Control to Disable CLKOUT On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† (JTAG) Boundary Scan Logic 12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS) 1.8-V Core Power Supply 1.8-V to 3.6-V I/O Power Supply Enables Operation With a SIngle 1.8-V Supply or With Dual Power Supplies Available in a 144-Pin Plastic Thin Quad Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix) ADVANCE INFORMATION D description The TMS320UC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UC5409 unless otherwise specified) is ideal for low-power, high-performance applications. This processor offers very low power consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage systems. This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V systems. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 1999, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 description (continued) The TMS320UC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UC5409 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. For detailed information on the architecture of the ’C5000 family of DSPs, see the TMS320C5000 DSP Family Functional Overview (literature number SPRU307). 109 111 110 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 75 35 74 36 73 A18 A17 VSS A16 D5 D4 D3 D2 D1 D0 RS X2/CLKIN X1 HD3 CLKOUT VSS HPIENA CVDD VSS TMS TCK TRST TDI TDO EMU1/OFF EMU0 TOUT HD2 HPI16 CLKMD3 CLKMD2 CLKMD1 VSS DVDD BDX1 BFSX1 VSS BCLKR1 HCNTL0 VSS BCLKR0 BCLKR2 BFSR0 BFSR2 BDR0 HCNTL1 BDR2 BCLKX0 BCLKX2 VSS HINT CVDD BFSX0 BFSX2 HRDY DV DD V SS HD0 BDX0 BDX2 IACK HBIL NMI INT0 INT1 INT2 INT3 CVDD HD1 VSS BCLKX1 VSS 72 76 34 71 77 33 70 78 32 69 79 31 68 80 30 67 81 29 66 82 28 65 83 27 64 84 26 63 85 25 62 86 24 61 87 23 60 88 22 59 89 21 58 90 20 57 91 19 56 92 18 55 93 17 54 94 16 53 95 15 52 96 14 51 97 13 50 98 12 49 99 11 48 100 10 47 101 9 46 102 8 45 103 7 44 104 6 43 105 5 42 106 4 41 3 40 107 39 108 2 38 1 37 ADVANCE INFORMATION VSS A22 VSS DVDD A10 HD7 A11 A12 A13 A14 A15 CVDD HAS VSS VSS CVDD HCS HR/W READY PS DS IS R/W MSTRB IOSTRB MSC XF HOLDA IAQ HOLD BIO MP/MC DVDD VSS BDR1 BFSR1 143 144 VSS A21 CV DD A9 A8 A7 A6 A5 A4 HD6 A3 A2 A1 A0 DVDD HDS2 VSS HDS1 VSS CVDD HD5 D15 D14 D13 HD4 D12 D11 D10 D9 D8 D7 D6 DV DD VSS A20 A19 TMS320UC5409 PGE PACKAGE†‡ (TOP VIEW) † NC = No internal connection ‡ DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 TMS320UC5409 GGU PACKAGE (BOTTOM VIEW) 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H K L M N The pin assignments table to follow lists each signal quadrant and BGA ball number for the TMS320UC5409GGU (144-pin BGA package). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 ADVANCE INFORMATION J TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 Pin Assignments TMS320UC5409GGU (144-Pin BGA Package)† ADVANCE INFORMATION SIGNAL QUADRANT 1 BGA BALL # SIGNAL QUADRANT 2 BGA BALL # SIGNAL QUADRANT 4 BGA BALL # VSS A22 A1 BFSX1 N13 B1 BDX1 M13 VSS BCLKR1 N1 A19 A13 N2 A20 VSS DVDD C2 C1 DVDD VSS A12 L12 HCNTL0 M3 B11 L13 N3 K10 VSS BCLKR0 VSS DVDD A10 D4 CLKMD1 K4 D6 D10 HD7 D3 A11 D2 CLKMD2 K11 BCLKR2 L4 D7 C10 CLKMD3 K12 BFSR0 M4 D8 A12 D1 B10 HPI16 K13 BFSR2 N4 D9 A10 A13 A14 E4 HD2 J10 BDR0 K5 D10 D9 E3 TOUT J11 HCNTL1 L5 D11 C9 A15 E2 EMU0 J12 BDR2 M5 D12 B9 CVDD E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9 HAS F4 TDO H10 BCLKX2 K6 D13 D8 VSS VSS F3 TDI H11 D14 C8 TRST H12 VSS HINT L6 F2 M6 D15 B8 CVDD F1 TCK H13 CVDD N6 HD5 A8 BGA BALL # SIGNAL QUADRANT 3 A11 HCS G2 TMS G12 BFSX0 M7 CVDD B7 HR/W G1 G13 BFSX2 N7 G3 G11 HRDY L7 VSS HDS1 A7 READY VSS CVDD PS G4 HPIENA G10 DVDD K7 DS H1 F13 N8 F12 VSS HD0 VSS HDS2 M8 DVDD B6 F11 BDX0 L8 A0 C6 IS H2 VSS CLKOUT R/W H3 HD3 C7 D7 A6 MSTRB H4 X1 F10 BDX2 K8 A1 D6 IOSTRB J1 X2/CLKIN E13 IACK N9 A2 A5 MSC J2 RS E12 HBIL M9 A3 B5 XF J3 D0 E11 NMI L9 HD6 C5 HOLDA J4 D1 E10 INT0 K9 A4 D5 IAQ K1 D2 D13 INT1 N10 A5 A4 HOLD K2 D3 D12 INT2 M10 A6 B4 BIO K3 D4 D11 INT3 L10 A7 C4 MP/MC L1 D5 C13 CVDD N11 A8 A3 DVDD L2 A16 C12 HD1 M11 A9 B3 VSS BDR1 L3 C11 CVDD C3 B13 VSS BCLKX1 L11 M1 VSS A17 N12 A21 A2 BFSR1 M2 A18 B12 VSS M12 VSS B2 † DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 terminal functions The following table lists each signal, function, and operating mode(s) grouped by function. Terminal Functions TERMINAL NAME I/O† DESCRIPTION O/Z Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O while the upper seven address pins (A16 to A22) are only used to address external program space. These pins are placed in the high-impedance state when the hold mode is enabled, or when OFF is low. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) (MSB) I/O/Z (LSB) A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (MSB) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) I These pins can be used to address internal memory via the HPI when the HPI16 pin is high (A0 – A15). I/O Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the high-impedance state when OFF is low. ADVANCE INFORMATION DATA SIGNALS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB) The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by the ’UC5409, the bus holders keep the pins at the previous logic level. The data bus holders on the ’UC5409 are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR). (LSB) INITIALIZATION, INTERRUPT, AND RESET OPERATIONS IACK O/Z Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is low. INT0 INT1 INT2 INT3 I External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register and the interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register. NMI I Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When NMI is activated, the processor traps to the appropriate vector location. † I = Input, O = Output, Z = High-impedance, S = Supply POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 Terminal Functions (Continued) TERMINAL NAME I/O† DESCRIPTION RS I Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects various registers and status bits. MP/MC I Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal program ROM is mapped into the upper program memory space. If the pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. MP/MC is only sampled at reset, and the MP/MC bit of the PMST register can override the mode that is selected at reset. I Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the conditional instruction. For the XC instruction, the BIO condition is sampled during the decode phase of the pipeline; all other instructions sample BIO during the read phase of the pipeline. O/Z External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low, and is set high at reset. INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED) MULTIPROCESSING SIGNALS ADVANCE INFORMATION BIO XF MEMORY CONTROL SIGNALS DS PS IS O/Z Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing a particular external memory space. Active period corresponds to valid address information. DS, PS, and IS are placed into the high-impedance state in the hold mode; the signals also go into the high-impedance state when OFF is low. MSTRB O/Z Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low. I Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states. R/W O/Z Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the high-impedance state in hold mode; it also goes into the high-impedance state when OFF is low. IOSTRB O/Z I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low. I Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the ’C54x, these lines go into the high-impedance state. HOLDA O/Z Hold acknowledge. HOLDA indicates that the ’UC5409 is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices. HOLDA also goes into the high-impedance state when OFF is low. MSC O/Z Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC pin goes low during the last of these wait states. If connected to the READY input, MSC forces one external wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF is low. IAQ O/Z Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus. IAQ goes into the high-impedance state when OFF is low. READY HOLD OSCILLATOR/TIMER SIGNALS CLKOUT O/Z Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low. † I = Input, O = Output, Z = High-impedance, S = Supply 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 Terminal Functions (Continued) TERMINAL NAME I/O† DESCRIPTION CLKMD1 CLKMD2 CLKMD3 I Clock mode select signals. These inputs select the mode that the clock generator is initialized to after reset. The logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized to the selected mode. After reset, the clock mode can be changed through software, but the clock mode select signals have no effect until the device is reset again. X2/CLKIN I Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. X1 O Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when OFF is low. O/Z Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low. OSCILLATOR/TIMER SIGNALS (CONTINUED) TOUT MULTICHANNEL BUFFERED SERIAL PORT SIGNALS I/O/Z Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver. BDR0 BDR1 BDR2 I BFSR0 BFSR1 BFSR2 I/O/Z Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR. BCLKX0 BCLKX1 BCLKX2 I/O/Z Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when OFF goes low. BDX0 BDX1 BDX2 O/Z Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted, or when OFF is low. BFSX0 BFSX1 BFSX2 I/O/Z Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the high-impedance state when OFF is low. ADVANCE INFORMATION BCLKR0 BCLKR1 BCLKR2 Serial data receive input HOST-PORT INTERFACE SIGNALS A0 – A15 I These pins can be used to address internal memory via the HPI when the HPI16 pin is high. These pins can be used to read/write internal memory via the HPI when the HPI16 pin is high. The sixteen data pins, D0 to D15, are multiplexed to transfer data between the core CPU and external data/program memory, I/O devices, or HPI in 16-bit mode. The data bus is placed in the high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the high-inmpedance state when OFF is low. D0 – D15 I/O The data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by the ’UC5409, the bus holders keep the pins at the logic level that was most recently driven. The data bus holders of the ’UC5409 are disabled at reset, and can be enabled/disabled via the BH bit of the BSCR. HD0 – HD7 I/O/Z Parallel bidirectional data bus. These pins can also be used as general-purpose I/O pins when the HPI16 pin is high. HD0–HD7 is placed in the high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven by the ’UC5409, the bus holders keep the pins at the logic level that was most recently driven. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR. † I = Input, O = Output, Z = High-impedance, S = Supply POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 Terminal Functions (Continued) TERMINAL NAME I/O† DESCRIPTION HCNTL0 HCNTL1 I Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have internal pullup resistors that are only enabled when HPIENA = 0. HBIL I Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup resistor that is only enabled when HPIENA = 0. HCS I Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input has an internal pullup resistor that is only enabled when HPIENA = 0. HDS1 HDS2 I Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0. HAS I Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0. HR/W I Read/write. HR/W controls the direction of an HPI transfer. R/W has an internal pullup resistor that is only enabled when HPIENA = 0. HRDY O/Z Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the high-impedance state when OFF is low. HINT O/Z Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. The signal goes into the high-impedance state when OFF is low. I HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the ’UC5409 is reset. HPI16 I HPI 16-bit select pin. HPI16 = 1 selects the non-multiplexed mode. The non-multiplexed mode allows hosts with separate address/data buses to access the HPI address range via the 16 address pins (A0–A15). The 16-bit data is also accessible through pins D0 through D15. Host-to-DSP and DSP-to-Host interrupts are not supported. There are no HPIC and HPIA registers in the non-multiplexed mode since HCNTRL0 and HCNTRL1 signals are available. CVDD S DVDD S +VDD. Dedicated 1.8-V power supply for the core CPU +VDD. Dedicated 3.3-V power supply for the I/O pins VSS S Ground ADVANCE INFORMATION HOST-PORT INTERFACE SIGNALS (CONTINUED) HPIENA SUPPLY PNS TEST PINS TCK I IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TDI I IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO O/Z IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low. TMS I IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK. TRST I IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device. † I = Input, O = Output, Z = High-impedance, S = Supply 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 Terminal Functions (Continued) TERMINAL NAME I/O† DESCRIPTION I/O/Z Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. I/O/Z Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF feature, the following apply: TRST = low EMU0 = high EMU1/OFF = low TEST PINS (CONTINUED) EMU0 EMU1/OFF memory The ’UC5409 device provides both on-chip ROM and RAM memories to aid in system performance and integration. on-chip ROM with bootloader The ’5409 features a 16K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the ’5409 programmed with contents unique to any particular application. A security option is available to protect a custom ROM. This security option is described in the TMS320C54x DSP CPU and Peripherals Reference Set, Volume 1 (literature number SPRU131). Note that only the ROM security option, and not the ROM/RAM option, is available on the ’5409 . A bootloader is available in the standard ’5409 on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard ’5409 bootloader provides different ways to download the code to accomodate various system requirements: D D D D D Parallel from 8-bit or 16-bit-wide EPROM Parallel from I/O space 8-bit or 16-bit mode Serial boot from serial ports 8-bit or 16-bit mode Host-port interface boot SPI serial EEPROM 8-bit boot mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 ADVANCE INFORMATION † I = Input, O = Output, Z = High-impedance, S = Supply TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 on-chip ROM with bootloader (continued) The standard on-chip ROM layout is shown in Table 1. Table 1. Standard On-Chip ROM Layout† ADVANCE INFORMATION ADDRESS RANGE DESCRIPTION 0x0000h – 0xBFFFh External program space 0xC000h – 0xF7FFh Reserved 0xF800h – 0xFBFFh Bootloader 0xFC00h – 0xFEFFh Reserved 0xFF00h – 0xFF7Fh Reserved† 0xFF80h – 0xFFFFh Interrupt vector table † In the ’VC5409 ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh in program space. on-chip RAM The ’UC5409 device contains 32K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of four blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. The DARAM is located in the address range 0080h–7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one. 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 memory map Page 0 Program Hex 0000 Page 0 Program Reserved (OVLY = 1) External (OVLY = 0) Reserved (OVLY = 1) External (OVLY = 0) 007F 0080 007F 0080 Hex 0000 005F 0060 On-Chip DARAM (32K words) External External BFFF C000 External BFFF C000 On-Chip ROM (16K Words) FEFF FF00 Interrupts (External) ROM (DROM=1) or External (DROM=0) Reserved FF7F FF80 FF7F FF80 FEFF FF00 Interrupts (On-Chip) FFFF FFFF MP/MC= 1 (Microprocessor Mode) Scratch-Pad RAM 7FFF 8000 7FFF 8000 7FFF 8000 MemoryMapped Registers 007F 0080 On-Chip DARAM (OVLY = 1) External (OVLY = 0) On-Chip DARAM (OVLY = 1) External (OVLY = 0) Data ADVANCE INFORMATION Hex 0000 FFFF Reserved (DROM=1) or External (DROM=0) MP/MC= 0 (Microcomputer Mode) Figure 1. Memory Map relocatable interrupt vector table The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate interrupt service routine with minimal overhead. At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page. NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 extended program memory The ’UC5409 uses a paged extended memory scheme in program space to allow access of up to 8M program memory locations. In order to implement this scheme, the ’UC5409 includes several features that are also present on the ’548/’549 devices: D D ADVANCE INFORMATION D D Twenty-three address lines, instead of sixteen An extra memory-mapped register, the XPC register defines the page selection. This register is memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0. Six extra instructions for addressing extended program space. These six instructions affect the XPC. – FB[D] pmad (23 bits) – Far branch – FBACC[D] Accu[22:0] – Far branch to the location specified by the value in accumulator A or accumulator B – FCALL[D] pmad (23 bits) – Far call – FCALA[D] Accu[22:0] – Far call to the location specified by the value in accumulator A or accumulator B – FRET[D] – Far return – FRETE[D] – Far return with interrupts enabled In addition to these new instructions, two ’54x instructions are extended to use 23 bits in the ’UC5409: – READA data_memory (using 23-bit accumulator address) – WRITA data_memory (using 23-bit accumulator address) All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access only memory within the current page. Program memory in the ’UC5409 is organized into 127 pages that are each 64K in length, as shown in Figure 2. 00 0000 1 0000 Internal 32K Page 0 Page 1 Lower 32K† External 7F 0000 Page 2 Lower 32K† External Page 127 Lower 32K† External 1 7FFF 2 7FFF ... 7F 7FFF 1 8000 2 8000 ... 7F 8000 32K Page 1 Upper 32K External External 0 FFFF ... 2 0000 1 FFFF Page 2 Upper 32K External 2 FFFF Page 127 Upper 32K External ... 7F FFFF † The lower 32K words of pages 1 through 126 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM is mapped to the lower 32K words of all program space pages. Figure 2. Extended Program Memory 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 on-chip peripherals The ’UC5409 device has the following peripherals: D D D D D D Software-programmable wait-state generator with programmable bank-switching wait states An enhanced 8-bit host-port interface (HPI8/16) with 16-bit data/addressing Three multichannel buffered serial ports (McBSPs) One hardware timer A clock generator with a phase-locked loop (PLL) A direct memory access (DMA) controller software-programmable wait-state generator The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the system configuration register (SCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3 and described in Table 2. 15 14 12 11 XPA R/W-0 I/O R/W-111 9 8 Data R/W-111 6 Data R/W-111 5 3 Program R/W-111 2 0 Program R/W-111 LEGEND: R = Read, W = Write Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 ADVANCE INFORMATION The software wait-state generator of the ’UC5409 is similar to that of the ’5410 and it can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power comsumption of the ’UC5409. TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 software-programmable wait-state generator (continued) Table 2. Software Wait-State Register (SWWSR) Bit Fields BIT NO. NAME RESET VALUE 15 XPA 0 Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0 through 5) to select the address range for program space wait states. 14–12 I/O 1 I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 11–9 Data 1 Upper data space. The field value (0–7) corresponds to the base number of wait states for external data space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. 8–6 Data 1 Lower data space. The field value (0–7) corresponds to the base number of wait states for external data space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. FUNCTION ADVANCE INFORMATION Upper program space. The field value (0–7) corresponds to the base number of wait states for external program space accesses within the following addresses: 5–3 Program 1 - XPA = 0: x8000 – xFFFFh XPA = 1: The upper program space bit field has no effect on wait states. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Program space. The field value (0–7) corresponds to the base number of wait states for external program space accesses within the following addresses: 2–0 Program 1 - XPA = 0: x0000–x7FFFh XPA = 1: 00000–FFFFFh The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. The software wait-state multiplier bit of the software wait-state configuration register is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 4 and described in Table 3. 15 1 0 SWSM Reserved R/W-0 R/W-0 LEGEND: R = Read, W = Write Figure 4. Software Wait-State Configuration Register (SWCR) [MMR Address 002Bh] Table 3. Software Wait-State Configuration Register (SWCR) Bit Fields PIN NO. NAME RESET VALUE 15–1 Reserved 0 FUNCTION These bits are reserved and are unaffected by writes. Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2. 0 14 SWSM 0 - SWSM = 0: wait-state base values are unchanged (multiplied by 1). SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 programmable bank-switching wait states The programmable bank-switching logic of the ’UC5409 is functionally equivalent to that of the ’548/’549 devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the data space boundary into program space. The bank-switching control register (BSCR) defines the bank size for bank-switching wait-states. Figure 5 shows the BSCR and its bits are described in Table 4. 15 12 11 10 BNKCMP PS-DS R/W-1111 R/W-1 3 Reserved R-0 2 1 0 HBH BH EXIO R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write Table 4. Bank-Switching Control Register Fields NO. 15–12 11 10–3 2 1 0 BIT NAME RESET VALUE FUNCTION 1111 Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared, resulting in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed. PS - DS 1 Program read – data read access. PS-DS inserts an extra cycle between consecutive accesses of program read and data read or data read and program read. PS-DS = 0 No extra cycles are inserted by this feature. PS-DS = 1 One extra cycle is inserted between consecutive data and program reads. Reserved 0 These bits are reserved and are unaffected by writes. HBH 0 HPI bus holder. HBH controls the HPI bus holder feature. HBH is cleared to 0 at reset. HBH = 0 The bus holder is disabled. HBH = 1 The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the previous logic level. 0 Bus holder. BH controls the data bus holder feature. BH is cleared to 0 at reset. BH = 0 The bus holder is disabled. BH = 1 The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the previous logic level. 0 External bus interface off. The EXIO bit controls the external bus-off function. EXIO = 0 The external bus interface functions as usual. usual EXIO = 1 The address bus, data bus, and control signals become inactive after completing the current bus cycle. cycle Note that the DROM DROM, MP/MC MP/MC, and OVLY bits in the PMST and the HM bit of ST1 cannot be modified when the interface is disabled. BNKCMP BH EXIO POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 ADVANCE INFORMATION Figure 5. Bank-Switching Control Register (BSCR) [MMR Address 0029h] TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 parallel I/O ports The ’UC5409 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The ’UC5409 can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits. enhanced 8-bit host-port interface (HPI8/16) The ’UC5409 host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI found on earlier ’54x DSPs (’542, ’545, ’548, and ’549). The HPI8/16 is an 8-bit parallel port for interprocessor communication. The features of the HPI8/16 include: Standard features: D D D Sequential transfers (with autoincrement) or random-access transfers Host interrupt and ’54x interrupt capability Multiple data strobes and control pins for interface flexibility Enhanced features of the ’UC5409 HPI8/16: ADVANCE INFORMATION D D D Access to entire on-chip RAM through DMA bus Capability to continue transferring during emulation stop Capability to transfer 16-bit address and 16-bit data (non-multiplexed mode) The HPI8/16 functions as a slave and enables the host processor to access the on-chip memory of the ’UC5409. A major enhancement to the ’UC5409 HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP. The HPI8/16 does not have access to external memory. The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for one HPI8/16 cycle. Note that since host accesses are always synchronized to the ’UC5409 clock, an active input clock (CLKIN) is required for HPI8/16 accesses during IDLE states, and host accesses are not allowed while the ’UC5409 reset pin is asserted. In standard 8-bit mode, the HPI8/16 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI8/16 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the ’UC5409. In 16-bit nonmultiplexed mode (HPI16=1), the HPI8/16 can read and write to internal memory via the external address and data pins, A0 – A15 and D0–D15, respectively. HD0–HD7 can be configured as general-purpose input/output (GPIO). The HPI16 non-multiplexed mode does not support the use of the HPID and HPIA registers. Host-to-DSP and DSP-to-host interrupts are also not supported. See Figure 6 for the HPI memory map. 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 enhanced 8-bit host-port interface (HPI8/16) (continued) 0000h Reserved 005Fh 0060h Scratch-Pad RAM 007Fh 0080h On-Chip RAM (32K x 16 Bits) 7FFFh 8000h Reserved FFFFh Figure 6. ’UC5409 HPI Memory Map In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 16-bit HA address bus. The host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA read or write access. Figure 7 shows a block diagram of the HPI16 in nonmultiplexed mode. DATA[15:0] HPI16 PPD[15:0] HINT HPID[15:0] DMA Address[15:0] VCC Internal Memory HOST HCNTL0 HCNTL1 HBIL HAS R/W HR/W Data Strobes READY HRDY ’54xx CPU HDS1, HDS2, HCS Figure 7. Host-Port Interface — Nonmultiplexed Mode host access control Host accesses are controlled by the data strobes (HDS1 and HDS2), along with chip select (HCS), in exactly the same fashion as documented in the HPI nonmultiplexed mode section. host access type In nonmultiplexed mode, only one access type (HPID read/write) is available since the HPIA register is not needed because of direct address inputs, and since the HCNTL pins are not available for access-type selection. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 ADVANCE INFORMATION HPI nonmultiplexed mode TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 HPI16 control register (HPIC) In nonmultiplexed mode, the HPIC register is not accessible via the host. This precludes DSP-to-host or host-to-DSP interrupts, data prefetch via the FETCH bit, and HRDY polling. Extended addressing capability still exists (even without the XHPIA bit) because the HA bus is 16 bits wide. HPI16 address register (HPIA) In nonmultiplexed mode, the HPIA register is not needed because direct address inputs A[15:0] are used as HA[15:0]. The DMA address comes directly from the HA pins. Note that the HA bus is still always latched at the end of the host access (on the rising edge of HDS = HDS1 XNOR HDS2) in order to ensure a valid address during the DMA write access. host data prefetch Since the HPIA register is not used in nonmultiplexed mode, the prefetch mechanism is not supported. Random address accesses in nonmultiplexed mode are still faster than those in multiplexed mode because of the separate address and data buses. ADVANCE INFORMATION host ready logic (HRDY) Hardware HRDY logic operation in nonmultiplexed mode is the same as that in multiplexed mode. HRDY operation during prefetches and HRDY/FETCH bit interaction are not supported with nonmultiplexed mode. host/DSP interrupts Host-to-DSP and DSP-to-host interrupts are not supported by HPI16 in nonmultiplexed mode. other HPI system considerations operation during IDLE2 The HPI can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power. The DSP CPU does not wake up from the IDLE mode during this process. multichannel buffered serial ports The ’UC5409 device has three high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides: D D D Full-duplex communication Double-buffer data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit In addition, the McBSP has the following capabilities: D D D D D D Direct interface to: – T1/E1 framers – MVIP switching-compatible and ST-BUS compliant devices – IOM-2 compliant devices – AC97-compliant devices – Serial peripheral interface (SPIt) devices Multichannel transmit and receive of up to 128 channels A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits µ-law and A-law companding Programmable polarity for both frame synchronization and data clocks Programmable internal clock and frame generation SPI is a trademark of Motorola Inc. 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 multichannel buffered serial ports (continued) The McBSPs consist of separate transmit and receive channels that operate independently. The external interface of each McBSP consists of the following pins: D D D D D D BCLKX BDX BFSX BCLKR BDR BFSR Transmit reference clock Transmit data Transmit frame synchronization Receive reference clock Receive data Receive frame synchronization On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins, respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR). If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until the DRR is available. This structure allows storage of the two previous words while the reception of the current word is in progress. The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP interrupts, event signals, and status flags. The DMA is capable of handling data movement between the McBSPs and memory with no intervention from the CPU. In addition to the standard serial port functions, the McBSP provides programmable clock and frame sync generation. Among the programmable functions are: D D D D D D Frame synchronization pulse width Frame period Frame synchronization delay Clock reference (internal vs. external) Clock division Clock and frame sync polarity The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format. When companding is used, transmit data is encoded according to specified companding law and received data is decoded to 2s complement format. The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to 32 channels in a stream of up to 128 channels can be enabled. The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI) protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave. The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU clock frequency divided by 2. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 ADVANCE INFORMATION The six pins listed are functionally equivalent to the pins of previous serial port interface pins in the ’C5000 family of DSPs. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress. TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 sample rate generator external clock options Although the CLKS pin is not available on the ’5409 PGE and GGU packages, the ’5409 is capable of synchronization to external clock sources. CLKX or CLKR can be used by the sample rate generator for external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to accomodate this option. 15 13 12 11 10 9 8 Reserved 14 XIOEN RIOEN FSXM FSRM CLKXM CLKRM RW RW RW RW RW RW RW 7 6 5 4 3 2 1 0 SCLKME CLKS STAT DX STAT DR STAT FSXP FSRP CLKXP CLKRP RW RW RW RW RW RW RW RW Legend: R = Read, W = Write ADVANCE INFORMATION Figure 8. Pin Control Register (PCR) 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 sample rate generator external clock options (continued) Table 5. Pin Control Register (PCR) Bit Field Description BIT NAME 15 – 14 Reserved FUNCTION Reserved. Pins are not used. Transmit/Receive general-purpose I/O mode ONLY when XRST=0 in the SPCR(1/2) 13 XIOEN XIOEN = 0 XIOEN = 1 DX pin is not a general-purpose output. FSX and CLKX are not general-purpose I/Os. DX pin is a general-purpose output. FSX and CLKX are general-purpose I/Os. These serial port pins do not perform serial port operations. Transmit/Receive general-purpose I/O mode ONLY when RRST=0 in the SPCR(1/2) RIOEN RIOEN = 1 DR and CLKS pins are not general-purpose inputs. FSR and CLKR are not general-purpose I/Os. DR and CLKS pins are general-purpose inputs. FSR and CLKR are general-purpose I/Os. These serial port pins do not perform serial port operations. The CLKS pin is affected by a combination of RRST and RIOEN signals of the receiver. ADVANCE INFORMATION RIOEN = 0 12 Transmit frame synchronization mode 11 FSXM FSRM = 0 FSRM = 1 Frame synchronization signal derived from an external source. Frame synchronization is determined by the sample rate generator frame synchronization mode bit (FSGM) in the SRGR2. Receive frame synchronization mode 10 FSRM FSRM = 0 FSRM = 1 Frame synchronization pulses generated by an external device. FSR is an input pin. Frame synchronization generated internally by the sample rate generator. FSR is an output pin except when GSYNC=1 in the SRGR. Receiver clock mode Case 1: Digital loop-back mode is not set (CLB=0) in SPCR1. CLKRM = 0 CLKRM= 1 9 Receive clock (CLKR) is an input pin driven by an external clock. CLKR is an output pin and is driven by the internal sample rate generator CLKRM Case 2: Digital loop-back mode set (CLB=1) in SPCR1 CLKRM = 0 CLKRM= 1 Receive clock (Not the CLKR pin) is driven by transmit clock (CLKX), which is based on CLKXM bit in the PCR. CLKR pin is in high-impedance mode. CLKR is an output pin and is driven by the transmit clock. The transmit clock is derived based on the CLKXM bit in the PCR. Transmitter clock mode CLKXM = 0 CLKXM= 1 8 CLKXM Receiver/transmitter clock is driven by an external clock with CLK(R/X) as an input pin CLK(R/X) is an output pin and is driven by the internal sample rate generator During SPI mode (CLKSTP is a non-zero value): CLKXM = 0 CLKXM= 1 McBSP is a slave and clock (CLKX) is driven by the SPI master in the system. CLKR is internally driven by CLKX. McBSP is a master and generates the clock (CLKX) to drive its receive clock (CLKR) and the shift clock of the SPI-compliant slaves in the system. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 sample rate generator external clock options (continued) Table 5. Pin Control Register (PCR) Bit Field Description (Continued) BIT NAME FUNCTION Sample rate clock mode extended 7 SCLKME SCLKME = 0 SCLKME = 1 External clock via CLKS or CPU clock is used as a reference by the sample rate generator. External clock via CLKR or CLKX clock is used as a reference by the sample rate generator. 6 CLKS STAT 5 DX STAT DX pin status. DX STAT reflects value on DX pin when it is selected as a general-purpose output. 4 DR STAT DR pin status. DR STAT reflects value on DR pin when it is selected as a general-purpose input. 3–2 FSXP FSRP CLKS pin status. CLKS STAT reflects value on CLKS pin when selected as a general-purpose input. ADVANCE INFORMATION Receive/Transmit frame synchronization polarity. FS(R/X)P = 0 FS(R/X)P = 1 Frame synchronization pulse FS(R/X) is active high Frame synchronization pulse FS(R/X) is active low Transmit clock polarity 1 CLKXP 0 CLKRP CLKXP = 0 CLKXP = 1 Transmit data sampled on rising edge of CLKR Transmit data sampled on falling edge of CLKR Receive clock polarity CLKRP = 0 CLKRP = 1 Receive data sampled on falling edge of CLKR Receive data sampled on rising edge of CLKR The ’5409 sample rate generator has four clock input options that are only available when both the PCR and SRGR2 are used. Table 6 shows the sample rate generator clock input options. Table 6. Sample Rate Generator Clock Input Options MODE SCLKME (PCR.7) CLKSM (SRGR2.13) CLKS pin 0 0 CPU 0 1 CLKR pin 1 0 CLKX pin 1 1 15 14 13 12 11 10 9 8 7 6 5 GSYNC CLKSP CLKSM FSGM FPER RW RW RW RW RW 4 Legend: R = Read, W = Write Figure 9. Sample Rate Generator Register 2 (SRGR2) 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 2 1 0 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 sample rate generator external clock options (continued) Table 7. Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions BIT NAME FUNCTION Sample rate gnereator clock synchronization. Only used when the external clock (CLKS) drives the sample rate generator clock (CLKSM=0) 15 GSYNC GSYNC = 0 GSYNC = 1 The sample rate generator clock (CLKG) is free-running. The sample rate generator clock (CLKG) is running. But CLKG is resynchronized and frame sync signal (FSG) is generated only after detecting the receive frame synchronization signal (FSR). Also, frame period (FPER) is a don’t care because the period is dictated by the external frame sync pulse. CLKS polarity clock edge select. Only used when the external clock (CLKS) drives the sample rate generator clock (CLKSM=0). CLKSP CLKSP = 0 CLKSP = 1 Rising edge of CLKS generates CLKG and FSG. Falling edge of CLKS generates CLKG and FSG. McBSP sample rate generator clock mode 13 CLKSM SCLKME = 0 (in PCR) CLKSM = 0 CLKSM = 1 Sample rate generator clock derived from the CLKS pin Sample rate generator clock derived from CPU clock SCLKME = 1 (in PCR) CLKSM = 0 CLKSM = 1 Sample rate generator clock derived from CLKR pin Smaple rate generator clock derived from CLKX pin Sample rate generator transmit frame synchronization mode. Used when FSXM=1 in the PCR. 12 FSGM 11 – 0 FPER FSGM = 0 FSGN = 1 Transmit frame sync signal (FSX) due to DXR(1/2) copy Transmit frame sync signal driven by the sample rate generator frame sync signal (FSG) Frame period. This determines when the next frame sycn signal should become active. Range: up to 212; 1 to 4096 CLKG periods. hardware timer The ’UC5409 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific control bits. clock generator The clock generator provides clocks to the ’UC5409 device, and consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock input is then divided by two (DIV mode) to generate clocks for the ’UC5409 device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the ’UC5409 device. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 ADVANCE INFORMATION 14 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 clock generator (continued) This clock generator allows system designers to select the clock source. The sources that drive the clock generator are: D D A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of the ’UC5409 to enable the internal oscillator. An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left unconnected. The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes: D ADVANCE INFORMATION D PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved using the PLL circuitry. DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation. The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 – CLKMD3 pins as shown in Table 8. Table 8. Clock Mode Settings at Reset 24 CLKMD1 CLKMD2 CLKMD3 CLKMD RESET VALUE 0 0 0 E007h PLL x 15 0 0 1 9007h PLL x 10 0 1 0 4007h PLL x 5 1 0 0 1007h PLL x 2 1 1 0 F007h PLL x 1 1 1 1 0000h 1/2 (PLL disabled) 1 0 1 F000h 1/4 (PLL disabled) 0 1 1 — POST OFFICE BOX 1443 CLOCK MODE Reserved (Bypass mode) • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 DMA controller The ’UC5409 direct memory access (DMA) controller transfers data between points in the memory map without intervention by the CPU. The DMA controller allows movements of data to and from internal program/data memory, internal peripherals (such as the McBSPs), and external program/data memory to occur in the background of CPU operation. The DMA has six independent programmable channels allowing six different contexts for DMA operation. features D D D D D D D D D The DMA has external memory access. The DMA operates independently of the CPU. The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers. The DMA has higher priority than the CPU for internal accesses. Each channel has independently programmable priorities. Each channel’s source and destination address registers can have configurable indexes through memory on each read and write transfer, respectively. The address may remain constant, be post-incremented, post-decremented, or be adjusted by a programmable value. Each read or write transfer may be initialized by selected events. (Internally only) Each DMA channel is capable of sending interrupts to the CPU. The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words). (Internally only) DMA external access The ’UC5409 DMA supports external accesses to extended program, data memory, and extended I/O memory. D D D D Only two channels are available for external accesses. (One for external reads/one for external writes.) Single-word transfers are supported for external accesses. The DMA does not support transfers from peripherals to external memory. The DMA does not support transfers from external memory to the peripherals. DMA external transfer Unlike the ’5410, the ’5409 DMA mode control register (DMMCRx) has two additional bits; DLAXS (DMMCRn[5]) and SLAXS (DMMCRn[11]). These new bits specify the on/off-chip memory for the source and destination of the program/data/IO spaces. D D When DLAXS is set to 0 (default), the DMA does not perform an external access for the destination. When DLAXS is set to 1, the DMA performs an external access to the destination location. When SLAXS is set to 0 (default), the DMA does not perform an external access for the source. When DLAXS is set to 1, the DMA performs an external access from the source location. Two new registers are added to the ’5409 DMA to support DMA accesses to/from DMA extended data memory, page 1 to page 127. D D The DMA extended source data page register (XSRCDP[6:0]) is located at subbank address 028h. The DMA extended destination data page register (XDSTDP[6:0]) is located at subbank address 029h. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 ADVANCE INFORMATION The DMA has the following features: TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 DMA memory map The DMA memory map, as shown in Figure 10, allows DMA transfers to be unaffected by the status of the MP/MC, DROM, and OVLY bits. Program Hex 010000 Hex 0000 Program Hex xx0000 Reserved 007F 0080 ADVANCE INFORMATION DARAM Internal 32K 7FFF 8000 External External 017FFF 018000 Data Program On-Chip ROM Hex 0000 Reserved 001F 0020 DRR20 0021 DRR10 0022 DXR20 0023 DXR10 0024 Reserved 002F 0030 DRR22 0031 DRR12 0032 DXR22 0033 DXR12 0034 Reserved 0035 0036 RCERA2 0037 XCERA2 0038 Reserved 0039 003A RCERA0 003B XCERA0 003C Reserved 003F 0040 DRR21 0041 DRR11 0042 DXR21 0043 DXR11 0044 Reserved 0049 004A 004B 004C 005F 0060 External BFFF C000 007F 0080 Hex xx0000 Data External Hex 0000 I/O External RCERA1 XCERA1 Reserved ScratchPad RAM DARAM 7FFF 8000 FFFF xxFFFF 01FFFF Page 0 Page n External FFFF xxFFFF Page 5, 6, ... Page 1, 2, ... 127 FFFF Page 0, 1, ... 127 NOTE A: n = 1, 2, 3, or 4 Figure 10. TMS320UC5409 DMA Memory Map DMA priority level Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple DMA channels that are assigned to the same priority level are handled in a round-robin manner. 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 DMA source/destination address modification The DMA provides flexible address-indexing modes for easy implementation of data management schemes such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and can be post-incremented, post-decremented, or post-incremented with a specified index offset. DMA in autoinitialization mode The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and DMGCR). Autoinitialization allows: D D Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the completion of the current block transfer; but with the global reload registers, it can reinitialize these values for the next block transfer any time after the current block transfer begins. Repetitive operation: The CPU does not preload the global reload register with new values for each block transfer but only loads them on the first block transfer. The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields that represent the number of frames and the number of elements per frame to be transferred. D D Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum number of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count of 0 (default value) means the block transfer contains a single frame. Element count. This 16-bit value defines the number of elements per frame. This counter is decremented after the read transfer of each element. The maximum number of elements per frame is 65536 (DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded with the DMA global count reload register (DMGCR). DMA transfers in double-word mode (Internal Only) Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated following each transfer. In this mode, each 32-bit word is considered to be one element. DMA channel index registers The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is the last in the current frame. The normal adjustment value (element index) is contained in the element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame is determined by the selected DMA frame index register (either DMFRI0 or DMFRI1). The element index and the frame index affect address adjustment as follows: D D Element index: For all except the last transfer in the frame, the element index determines the amount to be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by the SIND/DIND bits. Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as selected by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 ADVANCE INFORMATION DMA transfer counting TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 DMA interrupts The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available modes are shown in Table 9. Table 9. DMA Interrupts ADVANCE INFORMATION MODE DINM IMOD INTERRUPT ABU (non-decrement) 1 0 At full buffer only ABU (non-decrement) 1 1 At half buffer and full buffer Multi-Frame 1 0 At block-transfer complete (DMCTRn = DMSEFCn[7:0] = 0) Multi-Frame 1 1 At end of frame and end of block (DMCTRn = 0) Either 0 X No interrupt generated Either 0 X No interrupt generated DMA controller synchronization events The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events and the DSYN values are shown in Table 10. Table 10. DMA Synchronization Events DSYN VALUE 28 DMA SYNCHRONIZATION EVENT 0000b No synchronization used 0001b McBSP0 receive event 0010b McBSP0 transmit event 0011b McBSP2 receive event 0100b McBSP2 transmit event 0101b McBSP1 receive event 0110b McBSP1 transmit event 0111b Reserved 1000b Reserved 1001b Reserved 1010b Reserved 1011b Reserved 1100b Reserved 1101b Timer interrupt event 1110b External interrupt 3 1111b Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 DMA channel interrupt selection The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When the ’UC5409 is reset, the interrupts from these three DMA channels are deselected. The INTSEL bit field in the DMPREC register can be used to select these interrupts, as shown in Table 11. Table 11. DMA Channel Interrupt Selection INTSEL Value IMR/IFR[6] IMR/IFR[7] IMR/IFR[10] IMR/IFR[11] 00b (reset) BRINT2 BXINT2 BRINT1 BXINT1 01b BRINT2 BXINT2 DMAC2 DMAC3 10b DMAC0 DMAC1 DMAC2 DMAC3 Reserved ADVANCE INFORMATION 11b POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 memory-mapped registers The ’UC5409 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to 1Fh. The device also has a set of memory-mapped registers associated with peripherals. Table 12 gives a list of CPU memory-mapped registers (MMRs) available on ’UC5409. Table 13 shows additional peripheral MMRs associated with the ’UC5409. Table 12. CPU Memory-Mapped Registers NAME IMR IFR DESCRIPTION HEX 0 0 Interrupt mask register 1 1 Interrupt flag register 2–5 2–5 Reserved for testing ST0 6 6 Status register 0 ST1 7 7 Status register 1 AL 8 8 Accumulator A low word (15–0) – ADVANCE INFORMATION ADDRESS DEC AH 9 9 Accumulator A high word (31–16) AG 10 A Accumulator A guard bits (39–32) BL 11 B Accumulator B low word (15–0) BH 12 C Accumulator B high word (31–16) BG 13 D Accumulator B guard bits (39–32) TREG 14 E Temporary register TRN 15 F Transition register AR0 16 10 Auxiliary register 0 AR1 17 11 Auxiliary register 1 AR2 18 12 Auxiliary register 2 AR3 19 13 Auxiliary register 3 AR4 20 14 Auxiliary register 4 AR5 21 15 Auxiliary register 5 AR6 22 16 Auxiliary register 6 AR7 23 17 Auxiliary register 7 SP 24 18 Stack pointer register BK 25 19 Circular buffer size register BRC 26 1A Block repeat counter RSA 27 1B Block repeat start address REA 28 1C Block repeat end address PMST 29 1D Processor mode status (PMST) register XPC 30 1E Extended program page register – 31 1F Reserved 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 memory-mapped registers (continued) Table 13. Peripheral Memory-Mapped Registers ADDRESS DESCRIPTION TYPE 20h Data receive register 2 McBSP #0 DRR10 21h Data receive register 1 McBSP #0 DXR20 22h Data transmit register 2 McBSP #0 DXR10 23h Data transmit register 1 McBSP #0 TIM 24h Timer register Timer PRD 25h Timer period counter Timer TCR 26h Timer control register Timer – 27h Reserved SWWSR 28h Software wait-state register External Bus BSCR 29h Bank-switching control register External Bus – 2Ah Reserved SWCR 2Bh Software wait-state control register 2Ch HPI control register HPIC – 2Dh–2Fh External Bus HPI Reserved DRR22 30h Data receive register 2 McBSP #2 DRR12 31h Data receive register 1 McBSP #2 DXR22 32h Data transmit register 2 McBSP #2 DXR12 33h Data transmit register 2 McBSP #2 SPSA2 34h McBSP2 subbank address register McBSP #2 SPSD2 35h McBSP2 subbank data register McBSP #2 – SPSA0 36–37h 38h Reserved McBSP0 subbank address register McBSP #0 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ SPCD0 – GPIOCR GPIOSR – 39h 3Ah–3Bh McBSP0 subbank data register McBSP #0 Reserved 3C General-purpose I/O pins control register GPIO 3D General-purpose I/O pins status register GPIO 3E–3F Reserved DRR21 40h Data receive register 1 McBSP #1 DRR11 41h Data receive register 2 McBSP #1 DXR21 42h Data transmit register 1 McBSP #1 43h Data transmit register 2 McBSP #1 DXR11 – 44h–47h Reserved SPSA1 48h McBSP1 subbank address register McBSP #1 SPCD1 49h McBSP1 subbank data register McBSP #1 – 4Ah–53h Reserved DMPREC 54h DMA channel priority and enable control register DMA DMSA 55h DMA subbank address register DMA DMSDI 56h DMA subbank data register with autoincrement DMA ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ DMSDN 57h DMA subbank data registrer DMA CLKMD 58h Clock mode register PLL – 59h–5Fh Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 ADVANCE INFORMATION NAME DRR20 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 McBSP control registers and subaddresses The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected register. Table 14 shows the McBSP control registers and their corresponding subaddresses. Table 14. McBSP Control Registers and Subaddresses McBSP0 McBSP1 ADVANCE INFORMATION ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ NAME ADDRESS SUB ADDRESS 39h SPCR11 49h 00h Serial port control register 1 39h SPCR21 49h 01h Serial port control register 2 39h RCR11 49h 02h Receive control register 1 39h RCR21 49h 03h Receive control register 2 39h XCR11 49h 04h Transmit control register 1 39h XCR21 49h 05h Transmit control register 2 SRGR10 39h SRGR11 49h 06h Sample rate generator register 1 SRGR20 39h SRGR21 49h 07h Sample rate generator register 2 MCR10 39h MCR11 49h 08h Multichannel register 1 NAME ADDRESS SPCR10 SPCR20 RCR10 RCR20 XCR10 XCR20 DESCRIPTION MCR20 39h MCR21 49h 09h Multichannel register 2 RCERA0 39h RCERA1 49h 0Ah Receive channel enable register partition A RCERB0 39h RCERB1 49h 0Bh Receive channel enable register partition B XCERA0 39h XCERA1 49h 0Ch Transmit channel enable register partition A XCERB0 39h XCERB1 49h 0Dh Transmit channel enable register partition B PCR0 39h PCR1 49h 0Eh Pin control register DMA subbank addressed registers The direct memory access (DMA) controller has several control registers associated with it. The main control register (DMPREC) is a standard memory mapped register. However, the other registers are accessed using the subbank addressing scheme. This allows a set, or subbank of registers to be accessed through a single memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register with autoincrement (DMSDI) is used to access (read or write) the selected register. When the DMSDI register is used to access the subbank, the subbank address is automatically postincremented so that a subsequent access affects the next register within the subbank. This autoincrement feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature is not required, the DMSDN register should be used to access the subbank. Table 15 shows the DMA controller subbank addressed registers and their corresponding subaddresses. 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 DMA subbank addressed registers (continued) Table 15. DMA Subbank Addressed Registers DMA ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADDRESS SUB ADDRESS DMSRC0 56h/57h 00h DMA channel 0 source address register DMDST0 56h/57h 01h DMA channel 0 destination address register DMCTR0 56h/57h 02h DMA channel 0 element count register DMSFC0 56h/57h 03h DMA channel 0 sync select and frame count register DMMCR0 56h/57h 04h DMA channel 0 transfer mode control register DMSRC1 56h/57h 05h DMA channel 1 source address register DMDST1 56h/57h 06h DMA channel 1 destination address register DMCTR1 56h/57h 07h DMA channel 1 element count register DMSFC1 56h/57h 08h DMA channel 1 sync select and frame count register DMMCR1 56h/57h 09h DMA channel 1 transfer mode control register DMSRC2 56h/57h 0Ah DMA channel 2 source address register DMDST2 56h/57h 0Bh DMA channel 2 destination address register DMCTR2 56h/57h 0Ch DMA channel 2 element count register DMSFC2 56h/57h 0Dh DMA channel 2 sync select and frame count register DMMCR2 56h/57h 0Eh DMA channel 2 transfer mode control register DMSRC3 56h/57h 0Fh DMA channel 3 source address register DMDST3 56h/57h 10h DMA channel 3 destination address register DMCTR3 56h/57h 11h DMA channel 3 element count register DMSFC3 56h/57h 12h DMA channel 3 sync select and frame count register DMMCR3 56h/57h 13h DMA channel 3 transfer mode control register DMSRC4 56h/57h 14h DMA channel 4 source address register DMDST4 56h/57h 15h DMA channel 4 destination address register DMCTR4 56h/57h 16h DMA channel 4 element count register DMSFC4 56h/57h 17h DMA channel 4 sync select and frame count register DMMCR4 56h/57h 18h DMA channel 4 transfer mode control register DMSRC5 56h/57h 19h DMA channel 5 source address register DMDST5 56h/57h 1Ah DMA channel 5 destination address register DMCTR5 56h/57h 1Bh DMA channel 5 element count register DMSFC5 56h/57h 1Ch DMA channel 5 sync select and frame count register DMMCR5 56h/57h 1Dh DMA channel 5 transfer mode control register DMSRCP 56h/57h 1Eh DMA source program page address (common channel) DMDSTP 56h/57h 1Fh DMA destination program page address (common channel) DMIDX0 56h/57h 20h DMA element index address register 0 DMIDX1 56h/57h 21h DMA element index address register 1 DMFRI0 56h/57h 22h DMA frame index register 0 DMFRI1 56h/57h 23h DMA frame index register 1 DMGSA 56h/57h 24h DMA global source address reload register DMGDA 56h/57h 25h DMA global destination address reload register DMGCR 56h/57h 26h DMA global count reload register DMGFR 56h/57h 27h DMA global frame count reload register DESCRIPTION POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 ADVANCE INFORMATION NAME TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 interrupts Vector-relative locations and priorities for all internal and external interrupts are shown in Table 16. Table 16. Interrupt Locations and Priorities ADVANCE INFORMATION NAME LOCATION DECIMAL HEX PRIORITY FUNCTION RS, SINTR 0 00 1 Reset (hardware and software reset) NMI, SINT16 4 04 2 Nonmaskable interrupt SINT17 8 08 — Software interrupt #17 SINT18 12 0C — Software interrupt #18 SINT19 16 10 — Software interrupt #19 SINT20 20 14 — Software interrupt #20 SINT21 24 18 — Software interrupt #21 SINT22 28 1C — Software interrupt #22 SINT23 32 20 — Software interrupt #23 SINT24 36 24 — Software interrupt #24 SINT25 40 28 — Software interrupt #25 SINT26 44 2C — Software interrupt #26 SINT27 48 30 — Software interrupt #27 SINT28 52 34 — Software interrupt #28 SINT29 56 38 — Software interrupt #29 SINT30 60 3C — Software interrupt #30 INT0, SINT0 64 40 3 External user interrupt #0 INT1, SINT1 68 44 4 External user interrupt #1 INT2, SINT2 72 48 5 External user interrupt #2 TINT, SINT3 76 4C 6 Timer interrupt BRINT0, SINT4 80 50 7 McBSP #0 receive interrupt (default) BXINT0, SINT5 84 54 8 McBSP #0 transmit interrupt (default) BRINT2, SINT7, DMAC0 88 58 9 McBSP #2 receive interrupt (default) BXINT2, SINT6, DMAC1 92 5C 10 McBSP #2 transmit interrupt (default) INT3, SINT8 96 60 11 External user interrupt #3 HINT, SINT9 100 64 12 HPI interrupt BRINT1, SINT10, DMAC2 104 68 13 McBSP #1 receive interrupt (default) BXINT1, SINT11, DMAC3 108 6C 14 McBSP #1 transmit interrupt (default) DMAC4,SINT12 112 70 15 DMA channel 4 interrupt (default) 116 74 16 DMA channel 5 interrupt (default) 120–127 78–7F — Reserved ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ DMAC5,SINT13 Reserved 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 interrupts (continued) The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 11. The function of each bit is described in Table 17. 15–14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES DMAC5 DMAC4 BXINT1 DMAC3 BRINT1 DMAC2 HINT INT3 BXINT2 DMAC1 BRINT2 DMAC0 BXINT0 BRINT0 TINT INT2 INT1 INT0 Figure 11. IFR and IMR Registers Table 17. IFR and IMR Register Bit Fields BIT FUNCTION NUMBER NAME 15–14 – 13 DMAC5 DMA channel 5 interrupt flag/mask bit 12 DMAC4 DMA channel 4 interrupt flag/mask bit 11 BXINT1/DMAC3 McBSP1 transmit interrupt flag/mask bit 10 BRINT1/DMAC2 McBSP1 receive interrupt flag/mask bit 9 HINT Host to ’54x interrupt flag/mask 8 INT3 External interrupt 3 flag/mask 7 BXINT2/DMAC1 McBSP2 transmit interrupt flag/mask bit 6 BRINT2/DMAC0 McBSP2 receive interrupt flag/mask bit 5 BXINT0 McBSP0 transmit interrupt flag/mask bit 4 BRINT0 McBSP0 receive interrupt flag/mask bit 3 TINT Timer interrupt flag/mask bit 2 INT2 External interrupt 2 flag/mask bit 1 INT1 External interrupt 1 flag/mask bit 0 INT0 External interrupt 0 flag/mask bit POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ADVANCE INFORMATION Reserved for future expansion 35 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 documentation support Extensive documentation supports all TMS320 family generations of devices from product announcement through applications development. The following types of documentation are available to support the design and use of the ’C5000 family of DSPs: D D D D D TMS320C5000 DSP Family Functional Overview (literature number SPRU307) Device-specific data sheets (such as this document) Complete User Guides Development-support tools Hardware and software application reports The four-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of: D D D D Volume 1: CPU and Peripherals (literature number SPRU131) Volume 2: Mnemonic Instruction Set (literature number SPRU172) Volume 3: Algebraic Instruction Set (literature number SPRU179) Volume 4: Applications Guide (literature number SPRU173) ADVANCE INFORMATION The reference set describes in detail the TMS320C54x products currently available, and the hardware and software applications, including algorithms, for fixed-point TMS320 devices. For general background information on DSPs and Texas Instruments (TIt) devices, see the three-volume publication Digital Signal Processing Applications with the TMS320 Family (literature numbers SPRA012, SPRA016, and SPRA017). A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 customers on product information. Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL). TI is a trademark of Texas Instruments Incorporated. 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage I/O range, DVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.0 V Supply voltage core range, CVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.0 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltage values are with respect to VSS. recommended operating conditions Device supply voltage, I/O 1.71 CVDD Device supply voltage, core 1.71 VSS Supply voltage, GND VIH High-level input voltage, I/O VIL Low-level input voltage IOH IOL High-level output current TC Operating case temperature NOM 1.8 MAX V 1.98 V 0 V RS, INTn, NMI, X2/CLKIN, BIO, BCLKR0, BCLKR1, BCLKX0, BCLKX1, HCS, HDS1, HDS2, TCK, CLKMDn, DVDD = 3.3 0.3 V 2.2 DVDD + 0.3 All other inputs 2.0 DVDD + 0.3 " RS, INTn, NMI, X2/CLKIN, BIO, BCLKR0, BCLKR1, BCLKX0, BCLKX1, HCS, HDS1, HDS2, TCK, CLKMDn, DVDD = 3.3 0.3 V All other inputs " –0.3 –0.3 Low-level output current –40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 UNIT 3.6 ADVANCE INFORMATION MIN DVDD 0.6 V V 0.8 –300 µA 1.5 mA 100 °C 37 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 electrical characteristics over recommended operating case temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VOH High-level output voltage IOH = MAX VOL Low-level output voltage IIZ Input current for D[15:0], HD[7:0] outputs in high impedance All other inputs IOL = MAX Bus holders enabled, DVDD = MAX, VI = VSS to DVDD II DVDD = MAX, VO = VSS to DVDD TRST With internal pulldown HPIENA With internal pulldown TMS, TCK, TDI, HPI} With internal pullups, HPIENA = 0 (VI = VSS to DVDD) UNIT V 0.4 only pins All other input input-only ADVANCE INFORMATION MAX 2.4 X2/CLKIN Input current TYP† –175 175 –5 5 –40 40 –5 300 –5 300 –300 5 5 –5 V µ µA µA 5 IDDC Supply current, core CPU CVDD = 1.8 V, fclock = 40 MHz,w TC = 25°C 45 mA IDDP Supply current, pins DVDD = 3.3 V, fclock = 40 MHz,w TC = 25°C 30 mA 5 mA 5 µA 5 pF 5 pF IDD Supply y current, standby Ci Input capacitance IDLE2 PLL × 1 mode, IDLE3 Divide-by-two mode, CLKIN stopped 40 MHz input Co Output capacitance † All values are typical unless otherwise specified. ‡ HPI input signals except for HPIENA. § Clock mode: PLL × 1 with external source PARAMETER MEASUREMENT INFORMATION IOL 50 Ω Tester Pin Electronics VLoad CT IOH Where: IOL IOH VLoad CT = = = = 1.5 mA (all outputs) 300 µA (all outputs) 1.5 V 40 pF typical load circuit capacitance Figure 12. 3.3-V Test Load Circuit 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Output Under Test TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 internal oscillator with external crystal The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD register. The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series resistance of 30 Ω and power dissipation of 1 mW. The circuit shown in Figure 13 represents fundamental-mode operation. recommended operating conditions of internal oscillator with external crystal (see Figure 13) MIN Input clock frequency NOM 10 10 X1 MAX UNIT 20 MHz pF X2/CLKIN ADVANCE INFORMATION fclock C1, C2 Crystal C1 C2 Figure 13. Internal Oscillator With External Crystal POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 divide-by-two clock option The frequency of the external reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate the internal machine cycle. The selection of the clock mode is described in the clock generator section. The external frequency injected must conform to specifications listed in the timing requirements table. switching characteristics over recommended operating conditions [H = 0.5tc(CO)]† (see Figure 13, Figure 14, and the recommended operating conditions table) ADVANCE INFORMATION PARAMETER MIN 10‡ TYP MAX 2tc(CI) 6 † UNIT ns 10 ns tc(CO) td(CIH-CO) Cycle time, CLKOUT tf(CO) tr(CO) Fall time, CLKOUT 2 ns Rise time, CLKOUT 2 ns Delay time, X2/CLKIN high to CLKOUT high/low 3 tw(COL) Pulse duration, CLKOUT low H–2 H–1 H ns tw(COH) Pulse duration, CLKOUT high H–2 H–1 H ns † This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies approaching 0 Hz. ‡ It is recommended that the PLL clocking option be used for maximum frequency operation. timing requirements (see Figure 14) tc(CI) tf(CI) Cycle time, X2/CLKIN MIN MAX 5 † ns 1 ns Fall time, X2/CLKIN UNIT tr(CI) Rise time, X2/CLKIN 1 ns † This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies approaching 0 Hz. tr(CI) tc(CI) tf(CI) X2/CLKIN tc(CO) tw(COH) tf(CO) tr(CO) td(CIH-CO) CLKOUT Figure 14. External Divide-by-Two Clock Timing 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 tw(COL) TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 multiply-by-N clock option The frequency of the external reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator section. The external frequency injected must conform to specifications listed in the timing requirements table. recommended operating conditions PARAMETER MIN [H = 0.5tc(CO)] MAX 10 TYP tc(CI)/N† 4 10 16 UNIT tc(CO) td(CI-CO) Cycle time, CLKOUT tf(CO) tr(CO) Fall time, CLKOUT tw(COL) tw(COH) Pulse duration, CLKOUT low H–2 H–1 H ns Pulse duration, CLKOUT high H–2 H–1 H ns – ms Delay time, X2/CLKIN high/low to CLKOUT high/low ns 2 Rise time, CLKOUT ns 2 tp Transitory phase, PLL lock up time † N = Multiplication factor ns ns ADVANCE INFORMATION switching characteristics over (see Figure 13 and Figure 15) timing requirements (see Figure 15)† tc(CI) ( ) Cycle time, X2/CLKIN MIN MAX Integer PLL multiplier N (N = 1–15) 10N 200N PLL multiplier N = x.5 10N 200N PLL multiplier N = x.25, x.75 10N 100N tf(CI) Fall time, X2/CLKIN tr(CI) Rise time, X2/CLKIN † N = Multiplication factor tr(CI) tc(CI) UNIT ns 8 ns 8 ns tf(CI) X2/CLKIN td(CI-CO) tc(CO) tw(COL) tp CLKOUT tf(CO) tw(COH) tr(CO) Unstable Figure 15. External Multiply-by-One Clock Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 memory and parallel I/O interface timing switching characteristics over recommended operating conditions for a memory read (MSTRB = 0)† (see Figure 16) td(CLKL-A) td(CLKH-A) td(CLKL-MSL) td(CLKL-MSH) PARAMETER Delay time, CLKOUT low to address valid‡ MAX UNIT 0 3 ns Delay time, CLKOUT high (transition) to address valid§ 0 3 ns Delay time, CLKOUT low to MSTRB low 0 3 ns 0 3 ns 0 3 ns 0 3 ns Delay time, CLKOUT low to MSTRB high th(CLKL-A)R Hold time, address valid after CLKOUT low‡ th(CLKH-A)R Hold time, address valid after CLKOUT high§ † Address, PS, and DS timings are all included in timings referenced as address. ‡ In the case of a memory read preceded by a memory read § In the case of a memory read preceded by a memory write ADVANCE INFORMATION MIN timing requirements for a memory read (MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 16) MIN MAX UNIT 2H–10 ns 2H–10 ns ta(A)M ta(MSTRBL) Access time, read data access from address valid tsu(D)R th(D)R Setup time, read data before CLKOUT low 4 ns Hold time, read data after CLKOUT low 0 ns th(A-D)R Hold time, read data after address invalid 0 ns 0 ns Access time, read data access from MSTRB low th(D)MSTRBH Hold time, read data after MSTRB high † Address, PS, and DS timings are all included in timings referenced as address. 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 memory and parallel I/O interface timing (continued) CLKOUT td(CLKL-A) th(CLKL-A)R A[19:0] th(A-D)R tsu(D)R ta(A)M th(D)R D[15:0] td(CLKL-MSL) ADVANCE INFORMATION th(D)MSTRBH td(CLKL-MSH) ta(MSTRBL) MSTRB R/W PS, DS Figure 16. Memory Read (MSTRB = 0) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 memory and parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a memory write (MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 17) ADVANCE INFORMATION td(CLKH-A) td(CLKL-A) PARAMETER Delay time, CLKOUT high to address valid‡ MIN MAX UNIT 0 3 ns Delay time, CLKOUT low to address valid§ 0 3 ns td(CLKL-MSL) td(CLKL-D)W Delay time, CLKOUT low to MSTRB low 0 3 ns 0 5 ns td(CLKL-MSH) td(CLKH-RWL) Delay time, CLKOUT low to MSTRB high –2 3 ns Delay time, CLKOUT high to R/W low –2 3 ns td(CLKH-RWH) td(RWL-MSTRBL) Delay time, CLKOUT high to R/W high –2 3 ns H–2 H+2 ns th(A)W Hold time, address valid after CLKOUT high‡ 0 3 ns th(D)MSH tw(SL)MS Hold time, write data valid after MSTRB high H–3 H+3§ ns Pulse duration, MSTRB low 2H–4 tsu(A)W tsu(D)MSH Setup time, address valid before MSTRB low 2H–4 Delay time, CLKOUT low to data valid Delay time, R/W low to MSTRB low Setup time, write data valid before MSTRB high ten(D–RWL) Enable time, data bus driven after R/W low tdis(RWH–D) Disable time, R/W high to data bus high impedance † Address, PS, and DS timings are all included in timings referenced as address. ‡ In the case of a memory write preceded by a memory write § In the case of a memory write preceded by an I/O cycle 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 2H–5 ns ns 2H+5§ H–5 ns ns 0 ns TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 memory and parallel I/O interface timing (continued) CLKOUT td(CLKH-A) td(CLKL-A) th(A)W A[19:0] td(CLKL-D)W th(D)MSH tsu(D)MSH D[15:0] td(CLKL-MSL) tsu(A)W tdis(RWH-D) td(CLKL-MSH) td(CLKH-RWL) ten(D-RWL) ADVANCE INFORMATION MSTRB td(CLKH-RWH) tw(SL)MS td(RWL-MSTRBL) R/W PS, DS Figure 17. Memory Write (MSTRB = 0) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 45 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 memory and parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a parallel I/O port read (IOSTRB = 0)† (see Figure 18) PARAMETER td(CLKL-A) td(CLKH-ISTRBL) MIN MAX Delay time, CLKOUT low to address valid 0 3 ns Delay time, CLKOUT high to IOSTRB low 0 3 ns 0 3 ns 0 3 ns td(CLKH-ISTRBH) Delay time, CLKOUT high to IOSTRB high th(A)IOR Hold time, address after CLKOUT low † Address and IS timings are included in timings referenced as address. UNIT timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 18) ADVANCE INFORMATION MIN MAX UNIT ta(A)IO ta(ISTRBL)IO Access time, read data access from address valid tsu(D)IOR th(D)IOR Setup time, read data before CLKOUT high 4 ns Hold time, read data after CLKOUT high 0 ns 0 ns Access time, read data access from IOSTRB low th(ISTRBH-D)R Hold time, read data after IOSTRB high † Address and IS timings are included in timings referenced as address. CLKOUT th(A)IOR td(CLKL-A) A[19:0] tsu(D)IOR ta(A)IO th(D)IOR D[15:0] th(ISTRBH-D)R td(CLKH-ISTRBH) ta(ISTRBL)IO td(CLKH-ISTRBL) IOSTRB R/W IS Figure 18. Parallel I/O Port Read (IOSTRB = 0) 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3H–10 ns 2H–10 ns TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 memory and parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a parallel I/O port write (IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 19) MIN MAX UNIT td(CLKL-A) td(CLKH-ISTRBL) Delay time, CLKOUT low to address valid 0 3 ns Delay time, CLKOUT high to IOSTRB low 0 3 ns td(CLKH-D)IOW td(CLKH-ISTRBH) Delay time, CLKOUT high to write data valid H–5 H+3 ns Delay time, CLKOUT high to IOSTRB high 0 3 ns td(CLKL-RWL) td(CLKL-RWH) Delay time, CLKOUT low to R/W low 0 3 ns Delay time, CLKOUT low to R/W high 0 3 ns th(A)IOW Hold time, address valid after CLKOUT low 0 3 ns th(D)IOW Hold time, write data after IOSTRB high H–3 H+3 ns tsu(D)IOSTRBH Setup time, write data before IOSTRB high H–3 H+1 ns H–3 H+3 ns tsu(A)IOSTRBL Setup time, address valid before IOSTRB low † Address and IS timings are included in timings referenced as address. ADVANCE INFORMATION PARAMETER CLKOUT tsu(A)IOSTRBL td(CLKL-A) th(A)IOW A[19:0] td(CLKH-D)IOW th(D)IOW D[15:0] td(CLKH-ISTRBL) td(CLKH-ISTRBH) tsu(D)IOSTRBH IOSTRB td(CLKL-RWH) td(CLKL-RWL) R/W IS Figure 19. Parallel I/O Port Write (IOSTRB = 0) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 ready timing for externally generated wait states timing requirements for externally generated wait states [H = 0.5 tc(CO)]† (see Figure 20, Figure 21, Figure 22, and Figure 23) MIN tsu(RDY) th(RDY) tv(RDY)MSTRB th(RDY)MSTRB ADVANCE INFORMATION tv(RDY)IOSTRB th(RDY)IOSTRB Setup time, READY before CLKOUT low 5 Hold time, READY after CLKOUT low Valid time, READY after MSTRB low‡ 0 Hold time, READY after MSTRB low‡ Valid time, READY after IOSTRB low‡ 4H Hold time, READY after IOSTRB low‡ 5H MAX UNIT ns ns 4H–8 ns ns 5H–8 ns ns tv(MSCL) Valid time, MSC low after CLKOUT low 0 3 ns tv(MSCH) Valid time, MSC high after CLKOUT low 0 3 ns † The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using READY, at least two software wait states must be programmed. ‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT. CLKOUT A[19:0] tsu(RDY) th(RDY) READY tv(RDY)MSTRB th(RDY)MSTRB MSTRB tv(MSCH) tv(MSCL) MSC Wait States Generated Internally Wait State Generated by READY Figure 20. Memory Read With Externally Generated Wait States 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 ready timing for externally generated wait states (continued) CLKOUT A[19:0] D[15:0] th(RDY) tsu(RDY) READY ADVANCE INFORMATION tv(RDY)MSTRB th(RDY)MSTRB MSTRB tv(MSCH) tv(MSCL) MSC Wait States Generated Internally Wait State Generated by READY Figure 21. Memory Write With Externally Generated Wait States POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 49 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 ready timing for externally generated wait states (continued) CLKOUT A[19:0] th(RDY) tsu(RDY) READY tv(RDY)IOSTRB th(RDY)IOSTRB ADVANCE INFORMATION IOSTRB tv(MSCH) tv(MSCL) MSC Wait States Generated Internally Figure 22. I/O Read With Externally Generated Wait States 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Wait State Generated by READY TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 ready timing for externally generated wait states (continued) CLKOUT A[19:0] D[15:0] th(RDY) tsu(RDY) READY ADVANCE INFORMATION tv(RDY)IOSTRB th(RDY)IOSTRB IOSTRB tv(MSCH) tv(MSCL) MSC Wait States Generated Internally Wait State Generated by READY Figure 23. I/O Write With Externally Generated Wait States POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 51 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 HOLD and HOLDA timings switching characteristics over recommended operating conditions for memory control signals and HOLDA, [H = 0.5 tc(CO)] (see Figure 24) PARAMETER MAX UNIT tdis(CLKL-A) tdis(CLKL-RW) Disable time, address, PS, DS, IS high impedance from CLKOUT low 5 ns Disable time, R/W high impedance from CLKOUT low 5 ns tdis(CLKL-S) ten(CLKL-A) Disable time, MSTRB, IOSTRB high impedance from CLKOUT low 5 ns Enable time, address, PS, DS, IS from CLKOUT low 2H+5 ns ten(CLKL-RW) ten(CLKL-S) Enable time, R/W enabled from CLKOUT low 2H+5 ns tv(HOLDA) (HOLDA) tw(HOLDA) ADVANCE INFORMATION MIN Enable time, MSTRB, IOSTRB enabled from CLKOUT low 2 2H+5 ns Valid time, HOLDA low after CLKOUT low 0 5 ns Valid time, HOLDA high after CLKOUT low –2 3 ns Pulse duration, HOLDA low duration 2H–3 ns timing requirements for memory control signals and HOLDA, [H = 0.5 tc(CO)] (see Figure 24) MIN tw(HOLD) tsu(HOLD) Pulse duration, HOLD low Setup time, HOLD low/high before CLKOUT low MAX UNIT 4H+10 ns 10 ns CLKOUT tsu(HOLD) tsu(HOLD) tw(HOLD) HOLD tv(HOLDA) tv(HOLDA) tw(HOLDA) HOLDA tdis(CLKL-A) ten(CLKL-A) A[19:0] PS, DS, IS D[15:0] tdis(CLKL-RW) ten(CLKL-RW) tdis(CLKL-S) ten(CLKL-S) tdis(CLKL-S) ten(CLKL-S) R/W MSTRB IOSTRB Figure 24. HOLD and HOLDA Timings (HM = 1) 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 reset, BIO, interrupt, and MP/MC timings timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 tc(CO)] (see Figure 25, Figure 26, and Figure 27) MAX UNIT th(RS) th(BIO) Hold time, RS after CLKOUT low 0 ns Hold time, BIO after CLKOUT low 0 ns th(INT) th(MPMC) Hold time, INTn, NMI, after CLKOUT low† 0 ns Hold time, MP/MC after CLKOUT low Pulse duration, RS low‡§ 0 ns 4H+5 ns Pulse duration, BIO low, synchronous 2H+5 ns tw(BIO)A tw(INTH)S Pulse duration, BIO low, asynchronous 4H ns Pulse duration, INTn, NMI high (synchronous) 2H+7 ns tw(INTH)A tw(INTL)S Pulse duration, INTn, NMI high (asynchronous) 4H ns Pulse duration, INTn, NMI low (synchronous) 2H+7 ns tw(INTL)A tw(INTL)WKP Pulse duration, INTn, NMI low (asynchronous) 4H ns Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup Setup time, RS before X2/CLKIN low¶ 8 ns Setup time, BIO before CLKOUT low 8 tw(RSL) tw(BIO)S tsu(RS) tsu(BIO) 5 ns 10 ns tsu(INT) Setup time, INTn, NMI, RS before CLKOUT low 8 10 ns tsu(MPMC) Setup time, MP/MC before CLKOUT low 8 ns † The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is corresponding to three CLKOUT sampling sequences. ‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure synchronization and lock-in of the PLL. § Note that RS may cause a change in clock frequency, therefore changing the value of H. ¶ Divide-by-two mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 ADVANCE INFORMATION MIN TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 reset, BIO, interrupt, and MP/MC timings (continued) X2/CLKIN tsu(RS) tw(RSL) RS, INTn, NMI tsu(INT) th(RS) CLKOUT tsu(BIO) th(BIO) ADVANCE INFORMATION BIO tw(BIO)S Figure 25. Reset and BIO Timings CLKOUT tsu(INT) tsu(INT) th(INT) INTn, NMI tw(INTH)A tw(INTL)A Figure 26. Interrupt Timing CLKOUT RS th(MPMC) tsu(MPMC) MP/MC Figure 27. MP/MC Timing 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings switching characteristics over recommended operating conditions for IAQ and IACK [H = 0.5 tc(CO)] (see Figure 28) MIN MAX UNIT td(CLKL-IAQL) td(CLKL-IAQH) Delay time, CLKOUT low to IAQ low 0 3 ns Delay time, CLKOUT low to IAQ high 0 3 ns td(A)IAQ td(CLKL-IACKL) Delay time, address valid to IAQ low 4 ns Delay time, CLKOUT low to IACK low 0 3 ns td(CLKL-IACKH) td(A)IACK Delay time , CLKOUT low to IACK high 0 3 ns 3 ns th(A)IAQ th(A)IACK Hold time, IAQ high after address invalid 0 ns Hold time, IACK high after address invalid 0 ns tw(IAQL) tw(IACKL) Pulse duration, IAQ low 2H–5 ns Pulse duration, IACK low 2H–5 ns Delay time, address valid to IACK low ADVANCE INFORMATION PARAMETER CLKOUT A[19:0] td(CLKL-IAQH) td(CLKL-IAQL) th(A)IAQ td(A)IAQ tw(IAQL) IAQ td(CLKL-IACKL) td(CLKL-IACKH) th(A)IACK td(A)IACK tw(IACKL) IACK MSTRB Figure 28. IAQ and IACK Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 55 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings (continued) switching characteristics over recommended operating conditions for XF and TOUT [H = 0.5 tc(CO)] (see Figure 29 and Figure 30) MIN MAX Delay time, CLKOUT low to XF high PARAMETER 0 3 Delay time, CLKOUT low to XF low 0 3 td(TOUTH) td(TOUTL) Delay time, CLKOUT low to TOUT high 0 3 ns 0 3 ns tw(TOUT) Pulse duration, TOUT td(XF) Delay time, CLKOUT low to TOUT low 2H–10 ADVANCE INFORMATION CLKOUT td(XF) XF Figure 29. XF Timing CLKOUT td(TOUTH) td(TOUTL) TOUT tw(TOUT) Figure 30. TOUT Timing 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 UNIT ns ns TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 multichannel buffered serial port timing timing requirements for McBSP [H=0.5tc(CO)]†(see Figure 31 and Figure 32) tc(BCKRX) tw(BCKRX) MAX UNIT Cycle time, BCLKR/X BCLKR/X ext 4H ns Pulse duration, BCLKR/X high or BCLKR/X low BCLKR/X ext 2H–1 ns tsu(BFRH-BCKRL) (BFRH BCKRL) Setup time, time external BFSR high before BCLKR low th(BCKRL-BFRH) h(BCKRL BFRH) time external BFSR high after BCLKR low Hold time, tsu(BDRV-BCKRL) (BDRV BCKRL) Setup time, time BDR valid before BCLKR low th(BCKRL-BDRV) h(BCKRL BDRV) Hold time, time BDR valid after BCLKR low tsu(BFXH-BCKXL) (BFXH BCKXL) Setup time, time external BFSX high before BCLKX low th(BCKXL-BFXH) h(BCKXL BFXH) Hold time, time external BFSX high after BCLKX low BCLKR int 8 BCLKR ext 1 BCLKR int 0 BCLKR ext 3 BCLKR int 5 BCLKR ext 0 BCLKR int 0 BCLKR ext 4 BCLKX int 7 BCLKX ext 0 BCLKX int 0 BCLKX ext 3 ns ns ns ns ns ns tr(BCKRX) Rise time, BCKR/X BCLKR/X ext 8 ns tf(BCKRX) Fall time, BCKR/X BCLKR/X ext 8 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. switching characteristics for McBSP [H=0.5tc(CO)]† (see Figure 31 and Figure 32) PARAMETER tc(BCKRX) tw(BCKRXH) Cycle time, BCLKR/X Pulse duration, BCLKR/X high tw(BCKRXL) Pulse duration, BCLKR/X low td(BCKRH-BFRV) d(BCKRH BFRV) Delay time, time BCLKR high to internal BFSR valid td(BCKXH-BFXV) d(BCKXH BFXV) Delay time, time BCLKX high to internal BFSX valid MIN MAX BCLKR/X int 4H D – 2‡ D + 2‡ ns BCLKR/X int C – 2‡ C + 2‡ ns BCLKR int –2 2 ns BCLKR ext 3 9 ns BCLKX int 0 4 BCLKX ext 8 11 BCLKX int –1 4 BCLKX ext 3 0§ 9 11 BFSX int 3 –1§ BFSX ext 3 13 BCLKR/X int Disable time,, BCLKX high g to BDX high g impedance following g last data tdis(BCKXH-BDXHZ) di (BCKXH BDXHZ) bit of transfer BCLKX int td(BCKXH-BDXV) d(BCKXH BDXV) Delay time, time BCLKX high to BDX valid td(BFXH-BDXV) d(BFXH BDXV) Delay y time,, BFSX high g to BDX valid ONLY applies when in data delay 0 (XDATDLY = 00b) mode BCLKX ext UNIT ns 7 3 ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ T = BCLKRX period = (1 + CLKGDV) * 2H C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § Minimum delay times also represent minimum output hold times. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 ADVANCE INFORMATION MIN TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 multichannel buffered serial port timing (continued) tc(BCKRX) tw(BCKRXH) tr(BCKRX) tw(BCKRXL) BCLKR td(BCKRH–BFRV) td(BCKRH–BFRV) tr(BCKRX) BFSR (int) tsu(BFRH–BCKRL) th(BCKRL–BFRH) BFSR (ext) th(BCKRL–BDRV) tsu(BDRV–BCKRL) ADVANCE INFORMATION BDR (RDATDLY=00b) Bit (n–1) (n–2) tsu(BDRV–BCKRL) (n–3) (n–4) th(BCKRL–BDRV) BDR (RDATDLY=01b) Bit (n–1) (n–2) tsu(BDRV–BCKRL) BDR (RDATDLY=10b) (n–3) th(BCKRL–BDRV) Bit (n–1) (n–2) Figure 31. McBSP Receive Timings tc(BCKRX) tw(BCKRXH) tw(BCKRXL) tr(BCKRX) tf(BCKRX) BCLKX td(BCKXH–BFXV) td(BCKXH–BFXV) BFSX (int) tsu(BFXH–BCKXL) th(BCKXL–BFXH) BFSX (ext) te(BDFXH–BDX) BDX (XDATDLY=00b) Bit 0 td(BDFXH–BDXV) Bit (n–1) td(BCKXH–BDXV) (n–2) te(BCKXH–BDX) BDX (XDATDLY=01b) Bit (n–1) Bit 0 td(BCKXH–BDXV) (n–2) (n–3) te(BCKXH–BDX) Bit 0 Bit (n–1) Figure 32. McBSP Transmit Timings 58 (n–4) td(BCKXH–BDXV) tdis(BCKXH–BDXHZ) BDX (XDATDLY=10b) (n–3) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 (n–2) TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 multichannel buffered serial port timing (continued) timing requirements for McBSP general-purpose I/O (see Figure 33) MIN Setup time, BGPIOx input mode before CLKOUT high† Hold time, BGPIOx input mode after CLKOUT high† tsu(BGPIO-COH) th(COH-BGPIO) † BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input. MAX UNIT 9 ns 0 ns switching characteristics for McBSP general-purpose I/O (see Figure 33) tsu(BGPIO-COH) MIN MAX 0 5 UNIT ns ADVANCE INFORMATION PARAMETER td(COH-BGPIO) Delay time, CLKOUT high to BGPIOx output mode‡ ‡ BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output. td(COH-BGPIO) CLKOUT th(COH-BGPIO) BGPIOx Input Mode† BGPIOx Output Mode‡ † BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input. ‡ BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output. Figure 33. McBSP General-Purpose I/O Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 59 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 0† (see Figure 34) MASTER SLAVE MIN MIN MAX MAX UNIT tsu(BDRV-BCKXL) th(BCKXL-BDRV) Setup time, BDR valid before BCLKX low 9 – 12H ns Hold time, BDR valid after BCLKX low 0 5 + 12H ns tsu(BFXL-BCKXL) Setup time, BFSX low before BCLKX low 10 ns 32H ns tc(BCKX) Cycle time, BCLKX † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ADVANCE INFORMATION switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 0† (see Figure 34) MASTER‡ PARAMETER MIN th(BCKXL-BFXL) td(BFXL-BCKXH) Hold time, BFSX low after BCLKX low§ Delay time, BFSX low to BCLKX high¶ td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid tdis(BCKXL-BDXHZ) Disable time, BDX high impedance following last data bit from BCLKX low tdis(BFXH-BDXHZ) Disable time, BDX high impedance following last data bit from BFSX high SLAVE MAX T–3 T+4 C–5 C+3 –2 4 C–2 C+3 MIN MAX UNIT ns ns 6H +54 10H + 15 ns ns 2H+ 4 6H + 17 ns td(BFXL-BDXV) Delay time, BFSX low to BDX valid 4H + 2 8H + 17 ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ T = BCLKX period = (1 + CLKGDV) * 2H C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even § FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP ¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). MSB LSB BCLKX th(BCKXL-BFXL) td(BFXL-BCKXH) BFSX tdis(BFXH-BDXHZ) td(BFXL-BDXV) td(BCKXH-BDXV) tdis(BCKXL-BDXHZ) BDX Bit 0 Bit(n-1) tsu(BDRV-BCLXL) BDR Bit 0 (n-2) (n-3) (n-4) th(BCKXL-BDRV) Bit(n-1) (n-2) (n-3) Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 (n-4) TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 0† (see Figure 35) tsu(BDRV-BCKXL) th(BCKXH-BDRV) Setup time, BDR valid before BCLKX low tsu(BFXL-BCKXH) Setup time, BFSX low before BCLKX high MASTER SLAVE MIN MIN Hold time, BDR valid after BCLKX high MAX MAX UNIT 12 2 – 12H ns 4 5 + 12H ns 10 ns 32H ns tc(BCKX) Cycle time, BCLKX † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MASTER‡ PARAMETER SLAVE MIN MAX C–3 C +43 T–5 T+3 MIN MAX UNIT th(BCKXL-BFXL) td(BFXL-BCKXH) Hold time, BFSX low after BCLKX low§ Delay time, BFSX low to BCLKX high¶ td(BCKXL-BDXV) Delay time, BCLKX low to BDX valid –2 6 6H + 5 10H + 15 ns tdis(BCKXL-BDXHZ) Disable time, BDX high impedance following last data bit from BCLKX low –2 4 6H + 3 10H + 17 ns ns ns td(BFXL-BDXV) Delay time, BFSX low to BDX valid D–2 D+4 4H – 2 8H + 17 ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ T = BCLKX period = (1 + CLKGDV) * 2H C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP ¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). MSB LSB BCLKX td(BFXL-BCKXH) th(BCKXL-BFXL) BFSX tdis(BCKXL-BDXHZ) BDX td(BCKXL-BDXV) td(BFXL-BDXV) Bit 0 Bit(n-1) tsu(BDRV-BCKXL) BDR Bit 0 (n-2) (n-3) (n-4) th(BCKXH-BDRV) Bit(n-1) (n-2) (n-3) (n-4) Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 61 ADVANCE INFORMATION switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 0† (see Figure 35) TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 1† (see Figure 36) tsu(BDRV-BCKXH) th(BCKXH-BDRV) Setup time, BDR valid before BCLKX high tsu(BFXL-BCKXL) Setup time, BFSX low before BCLKX low MASTER SLAVE MIN MIN Hold time, BDR valid after BCLKX high MAX MAX UNIT 12 2 – 12H ns 4 5 + 12H ns 10 ns 32H ns tc(BCKX) Cycle time, BCLKX † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ADVANCE INFORMATION switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 10b, CLKXP = 1† (see Figure 36) MASTER‡ PARAMETER MIN th(BCKXH-BFXL) td(BFXL-BCKXL) Hold time, BFSX low after BCLKX high§ Delay time, BFSX low to BCLKX low¶ td(BCKXL-BDXV) Delay time, BCLKX low to BDX valid tdis(BCKXH-BDXHZ) Disable time, BDX high impedance following last data bit from BCLKX high tdis(BFXH-BDXHZ) Disable time, BDX high impedance following last data bit from BFSX high SLAVE MAX T–3 T+4 D–5 D+3 –2 6 D–2 D+3 MIN MAX UNIT ns ns 6H + 5 10H + 15 ns ns 2H + 3 6H + 17 ns td(BFXL-BDXV) Delay time, BFSX low to BDX valid 4H – 2 8H + 17 ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ T = BCLKX period = (1 + CLKGDV) * 2H D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP ¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). LSB MSB BCLKX th(BCKXH-BFXL) td(BFXL-BCKXL) BFSX td(BFXL-BDXV) tdis(BFXH-BDXHZ) tdis(BCKXH-BDXHZ) BDX td(BCKXL-BDXV) Bit 0 Bit(n-1) tsu(BDRV-BCKXH) BDR Bit 0 (n-2) (n-3) th(BCKXH-BDRV) Bit(n-1) (n-2) (n-3) Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 62 POST OFFICE BOX 1443 (n-4) • HOUSTON, TEXAS 77251–1443 (n-4) TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 1† (see Figure 37) MASTER SLAVE MIN MIN MAX MAX UNIT tsu(BDRV-BCKXL) th(BCKXL-BDRV) Setup time, BDR valid before BCLKX low 9 – 12H ns Hold time, BDR valid after BCLKX low 0 5 + 12H ns tsu(BFXL-BCKXL) Setup time, BFSX low before BCLKX low 10 ns 32H ns tc(BCKX) Cycle time, BCLKX † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MASTER‡ PARAMETER SLAVE MIN MAX D–3 D+4 T–5 T+3 MIN MAX UNIT th(BCKXH-BFXL) td(BFXL-BCKXL) Hold time, BFSX low after BCLKX high§ Delay time, BFSX low to BCLKX low¶ td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid –2 6 6H + 5 10H + 15 ns tdis(BCKXH-BDXHZ) Disable time, BDX high impedance following last data bit from BCLKX high –2 4 6H + 3 10H + 17 ns ns ns td(BFXL-BDXV) Delay time, BFSX low to BDX valid C–2 C+4 4H – 2 8H + 17 ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ T = BCLKX period = (1 + CLKGDV) * 2H C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP ¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). MSB LSB BCLKX th(BCKXH-BFXL) td(BFXL-BCKXL) BFSX tdis(BCKXH-BDXHZ) BDX td(BCKXH-BDXV) td(BFXL-BDXV) Bit 0 Bit(n-1) tsu(BDRV-BCKXL) BDR Bit 0 (n-2) (n-3) (n-4) th(BCKXL-BDRV) Bit(n-1) (n-2) (n-3) (n-4) Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 63 ADVANCE INFORMATION switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 1† (see Figure 37) TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 HPI8 timing switching characteristics over recommended operating conditions†‡§¶ [H = 0.5tc(CO)] (see Figure 38, Figure 39, Figure 40, and Figure 41) PARAMETER ten(DSL-HD) Enable time, HD driven from DS low MIN MAX UNIT 2 17 ns Case 1a: Memory accesses when DMAC is active in 16-bit mode and tw(DSH) < 18H Case 1b: Memory accesses when DMAC is active in 16-bit mode and tw(DSH) ≥ 18H ADVANCE INFORMATION td(DSL-HDV1) d(DSL HDV1) Delay y time, DS low to HDx valid for first byte of an HPI read 18H+18 – tw(DSH) 18 Case 1c: Memory access when DMAC is active in 32-bit mode and tw(DSH) < 26H Case 1d: Memory access when DMAC is active in 32-bit mode and tw(DSH) ≥ 26H 26H+18 – tw(DSH) ns 18 Case 2a: Memory accesses when DMAC is inactive and tw(DSH) < 10H 10H+18 – tw(DSH) Case 2b: Memory accesses when DMAC is inactive and tw(DSH) ≥ 10H 18 Case 3: Register accesses 18 td(DSL-HDV2) th(DSH-HDV)R Delay time, DS low to HDx valid for second byte of an HPI read tv(HYH-HDV) td(DSH-HYL) Valid time, HDx valid after HRDY high 5 Delay time, DS high to HRDY low (see Note 1) 10 ns Case 1a: Memory accesses when DMAC is active in 16-bit mode 18H+10 ns Case 1b: Memory accesses when DMAC is active in 32-bit mode 26H+10 ns Case 2: Memory accesses when DMAC is inactive 10H+10 Case 3: Write accesses to HPIC register (see Note 2) 6H+10 td(DSH-HYH) Hold time, HDx valid after DS high, for a HPI read time DS high to HRDY high Delay time, 3 18 ns 5 ns ns 8 ns Delay time, CLKOUT high to HRDY high 8 ns Delay time, CLKOUT high to HINT change 10 ns Delay time, CLKOUT high to HDx output change. HDx is configured as a general-purpose output. 6 ns td(HCS-HRDY) td(COH-HYH) Delay time, HCS low/high to HRDY low/high td(COH-HTX) td(COH-GPIO) NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings. 2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronoulsy, and do not cause HRDY to be deasserted. † DS refers to the logical OR of HCS, HDS1, and HDS2. ‡ HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). § DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are affected by DMAC activity. ¶ GPIO refers to the HD pins when they are configured as general-purpose input/outputs. 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 HPI8 timing (continued) timing requirements†‡§ (see Figure 38, Figure 39, Figure 40, and Figure 41) MAX UNIT Setup time, HBIL valid before DS low 10 ns Hold time, HBIL valid after DS low 5 ns tsu(HSL-DSL) tw(DSL) Setup time, HAS low before DS low 5 ns Pulse duration, DS low 20 ns tw(DSH) tsu(HDV-DSH) Pulse duration, DS high 10 ns Setup time, HDx valid before DS high, HPI write 5 ns th(DSH-HDV)W tsu(GPIO-COH) Hold time, HDx valid after DS high, HPI write 3 ns Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input 3 ns 0 ns th(GPIO-COH) Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input † DS refers to the logical OR of HCS, HDS1, and HDS2. ‡ HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). § GPIO refers to the HD pins when they are configured as general-purpose input/outputs. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ADVANCE INFORMATION MIN tsu(HBV-DSL) th(DSL-HBV) 65 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 HPI8 timing (continued) Second Byte First Byte Second Byte HAS tsu(HBV-DSL) tsu(HSL-DSL) th(DSL-HBV) HAD† Valid Valid tsu(HBV-DSL)‡ th(DSL-HBV)‡ HBIL ADVANCE INFORMATION HCS tw(DSH) tw(DSL) HDS td(DSH-HYH) td(DSH-HYL) HRDY ten(DSL-HD) td(DSL-HDV2) td(DSL-HDV1) th(DSH-HDV)R HD READ Valid Valid tsu(HDV-DSH) Valid tv(HYH-HDV) th(DSH-HDV)W HD WRITE Valid Valid td(COH-HYH) CLKOUT † HAD refers to HCNTL0, HCNTL1, and HR/W. ‡ When HAS is not used (HAS always high) Figure 38. Using HDS to Control Accesses (HCS Always Low) 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Valid TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 HPI8 timing (continued) Second Byte First Byte Second Byte HCS HDS td(HCS-HRDY) HRDY ADVANCE INFORMATION Figure 39. Using HCS to Control Accesses CLKOUT td(COH-HTX) HINT Figure 40. HINT Timing CLKOUT tsu(GPIO-COH) th(GPIO-COH) GPIOx Input Mode† td(COH-GPIO) GPIOx Output Mode† † GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O). Figure 41. GPIOx† Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 67 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 HPI16 timing switching characteristics over recommended operating conditions†‡§¶ [H = 0.5tc(CO)] (see Figure 42 and Figure 43) PARAMETER ten(DSL-HD) ADVANCE INFORMATION td(DSL-HDV1) d(DSL HDV1) Enable time, Dx driven from DS low Delay time, DS low to Dx valid for an HPI read UNIT 7 17 ns 18H+22 – tw(DSH) 22 ns Case 2a: Memory accesses when DMAC is inactive and tw(DSH) < 10H 10H+22 – tw(DSH) Case 2b: Memory accesses when DMAC is inactive and tw(DSH) ≥ 10H 22 Case 3: Register accesses 22 th(DSH-HDV)R tsu(HDV-HYH) Setup time, Dx valid before HRDY rising edge td(DSH-HYL) Delay time, DS or HCS high to HRDY low‡ td(DSH-HYH) d(DSH HYH) Delay y time,, DS high g to HRDY high g § (writes and autoincrement reads) td(COH–GPIO) MAX Case 1a: Memory accesses when DMAC is active in 16-bit mode and tw(DSH) < 18H Case 1b: Memory accesses when DMAC is active in 16-bit mode and tw(DSH) ≥ 18H Hold time, Dx valid after DS rising edge, read§ td(DSL-HYL) td(COH–HTH) MIN 1 8 ns ns 10 Case 1: Memory access when DMAC is active in 16-bit mode 18H+10 Case 2: Memory access when DMAC is inactive 10H+10 ns ns Delay time, HDS or HCS low/high to HRDY low/high 8 ns Delay time, CLKOUT high to HRDY high 8 ns Delay time, CLKOUT rising edge to HDx output change. HDx is configured as a general-purpose output. 6 ns NOTE: The HRDY output is always high when the HCS input is high, regardless of DS timings. † DS refers to the logical OR of HCS, HDS1, or HDS2. ‡ Dx refers to any of the DPI data bus pins (D0, D1, D2, etc.). § DMAC stands for direct memory access (DMA) controller. The HPI16 shares the internal DMA bus with the DMAC, thus HPI16 access times are affected by DMAC activity. ¶ GPIO refers to the HD pins when they are configured as general-purpose input/outputs. 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 HPI16 timing (continued) timing requirements†‡§ [H = 0.5tc(CO)] (see Note 1, Figure 42, and Figure 43) Setup time, HAD valid before DS falling edge†‡ Hold time, HAD valid after DS falling edge†‡ tsu(HAV-DSL) th(DSH-HAV) Setup time, HAD valid before DS falling edge† Hold time, address valid after DS rising edge† tsu(HDV-DSH) th(DSH-HDV)W Setup time, Dx valid before DS high (HPI write) tw(DSL) tw(DSH) tsu(GPIO-COH) th(GPIO-COH) MIN UNIT 10 ns 5 ns ns ns ns Hold time, Dx valid aftere DS high (HPI write) Pulse duration, DS low‡ 3 ns 20 ns Pulse duration, DS high‡ 10 ns Setup time, Dx input valid before CLKOUT high, HDx configured as general-purpose input 2 ns Hold time, Dx input valid after CLKOUT high, HDx configured as general-purpose input 0 ns Cycle time, DS rising edge to next DS rising edge‡ Nonmultiplexed mode (no increment) with no DMA activity. ns (Minimum timings represent WRITEs while maximum timings represent READs) Nonmultiplexed mode (no increment) with 16-bit DMA activity. ns tc(DSH-DSH) (DSH DSH) ADVANCE INFORMATION tsu(HBV-DSL) th(DSL-HBV) † DS refers to the logical OR of HCS and HDS1 and HDS2. ‡ .Dx refers to any of the HPI data bus pins (D0, D1, D2, etc.). § GPIO refers tothe HD pins when they are configured as general-purpose input/outputs. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 69 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 HPI16 timing (continued) HCS tw(DSH) tc(DSH–DSH) HDS tw(DSL) tsu(HBV–DSL) th(DSL–HBV) HR/W th(DSH–HAV) tsu(HAV–DSL) ADVANCE INFORMATION HA[15:0] Valid Address (A[15:0]) Valid Address td(DSL–HDV1) th(DSH–HDV)R td(DSL–HD) D[15:0] Data Valid Data Valid tsu(HDV–HYH) HRDY td(DSL–HYH) Figure 42. Nonmultiplexed Read Timings 70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 HPI16 timing (continued) HCS tc(DSH–DSH) tw(DSH) HDS tsu(HBV–DSL) tw(DSL) th(DSL–HBV) HR/W tsu(HAV–DSL) th(DSH–HAV) Valid Address Valid Address tsu(HDV–DSH) D[15:0] Data Valid ADVANCE INFORMATION HA[15:0] (A[15:0]) th(DSH–HDV)W Data Valid td(DSH–HYH) HRDY td(DSH–HYL) Figure 43. Nonmultiplexed Write Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 71 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 MECHANICAL DATA PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M ADVANCE INFORMATION 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147 / C 10/96 NOTES: B. All linear dimensions are in millimeters. C. This drawing is subject to change without notice. D. Falls within JEDEC MO-136 Thermal Resistance Characteristics 72 PARAMETER °C/W RΘJA 56 RΘJC 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320UC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS101A – APRIL 1999 – REVISED AUGUST 1999 MECHANICAL DATA GGU (S-PBGA-N144) PLASTIC BALL GRID ARRAY PACKAGE 12,10 SQ 11,90 9,60 TYP 0,80 ADVANCE INFORMATION 0,80 N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 0,95 0,85 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45 0,35 0,10 4073221/A 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration Thermal Resistance Characteristics PARAMETER °C/W RΘJA 38 RΘJC 5 MicroStar BGA is a trademark of Texas Instruments Incorporated. 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