AKM AK4117

[AK4117]
AK4117
Low Power 192kHz Digital Audio Receiver
GENERAL DESCRIPTION
The AK4117 is a S/PDIF AES/EBU receiver supporting sample rates up to 192kHz and resolution up to
24-bit. The integrated channel status decoder supports both consumer and professional modes. The
AK4117 can automatically detect a Non-PCM bit stream. Combining the AK4117 with a multi-channel
codec such as AKM’s AK4527B or AK4529 can create a complete AC-3 system. Mode settings can be
controlled via microprocessor serial interface. A low power mode is available for normal speed modes
and the small 24pin VSOP package saves board space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
† AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
† Low jitter Analog PLL
† PLL Lock Range : 32kHz to 192kHz
† Clock Source: PLL or X'tal
† 2-channel Receiver inputs Selector
† Auxiliary digital input
† Detection Functions
- Non-PCM Bit Stream Detection
- DTS-CD Bit Stream Detection
- Sampling Frequency Detection
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
- Unlock & Parity Error Detection
- Validity Flag Detection
† Up to 24bit Audio Data Format
† Audio I/F: Left justified, Right justified (16bit, 18bit, 20bit, 24bit), I2S
† 40-bit Channel Status Buffer
† Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
† Q-subcode Buffer for CD bit stream
† 4-wire Serial µP I/F
† Master Clock Output: 128fs/256fs/512fs
† Operating Voltage: 2.7 to 3.6V
† Small Package: 24pin VSOP
† Ta: -40 to 85°C
MS0157-E-04
2010/08
-1-
[AK4117]
■ Block Diagram
AVSS
RX0
RX1
2 to 1
Input
Selector
AVDD
R
XTI
XTO
X'tal
Clock
Recovery
Oscillator
Clock
Generator
DAIF
Decoder
Audio
I/F
DVDD
DVSS
MCKO
LRCK
BICK
SDTO
DAUX
PDN
AC-3/MPEG
Detect
Error &
STATUS
Detect
Q-subcode
µP I/F
buffer
CSN
CCLK
CDTI
CDTO
UOUT
INT0 INT1
MS0157-E-04
2010/08
-2-
[AK4117]
■ Ordering Guide
AK4117VF
-40 ~ +85 °C
24pin VSOP (0.65mm pitch)
■ Pin Layout
R
1
24
AVSS
AVDD
2
23
PDN
RX1
3
22
INT0
NC
4
21
INT1
RX0
5
20
CSN
DVDD
6
19
CCLK
DVSS
7
18
CDTI
XTI
8
17
CDTO
XTO
9
16
UOUT
LRCK
10
15
NC
BICK
11
14
MCKO
SDTO
12
13
DAUX
Top
View
MS0157-E-04
2010/08
-3-
[AK4117]
PIN/FUNCTION
No.
Pin Name
I/O
Function
External Resistor Pin
12kΩ-5% ~ 13kΩ+5% resistor to AVSS externally.
2
AVDD
Analog Power Supply Pin
3
RX1
I
Receiver Channel 1 (Internal Biased Pin)
No Connect
4
NC
No internal bonding.
5
RX0
I
Receiver Channel 0 (Internal Biased Pin)
6
DVDD
Digital Power Supply Pin
7
DVSS
Digital Ground Pin
8
XTI
I
X'tal Input Pin
9
XTO
O
X'tal Output Pin
10
LRCK
O
Output Channel Clock Pin
11
BICK
O
Audio Serial Data Clock Pin
12
SDTO
O
Audio Serial Data Output Pin
13
DAUX
I
Auxiliary Audio Data Input Pin
14
MCKO
O
Master Clock Output Pin
No Connect
15
NC
No internal bonding.
U-bit Output Pin
16
UOUT
O
When UOUTE bit = “0”, UOUT pin = “L”.
17
CDTO
O
Control Data Output Pin
18
CDTI
I
Control Data Input Pin
19
CCLK
I
Control Data Clock Pin
20
CSN
I
Chip Select Pin
21
INT1
O
Interrupt 1 Pin
22
INT0
O
Interrupt 0 Pin
Power-Down & Reset Pin
23
PDN
I
When “L”, the AK4117 is powered-down and reset, and all output pins go to
“L” and the control registers are reset to default state.
24
AVSS
Analog Ground Pin
Note 1: All input pins except internal biased pins should not be left floating.
1
R
-
MS0157-E-04
2010/08
-4-
[AK4117]
ABSOLUTE MAXIMUM RATINGS
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
min
max
Power Supplies:
Analog
AVDD
-0.3
4.6
Digital
DVDD
-0.3
4.6
|AVSS-DVSS| (Note 3)
0.3
ΔGND
Input Current (Any pins except supplies)
IIN
±10
Input Voltage (Except RX0, RX1 pins)
VIN1
-0.3
DVDD+0.3
(RX0, RX1 pins)
VIN2
-0.3
AVDD+0.3
Ambient Temperature (Power applied)
Ta
-40
85
Storage Temperature
Tstg
-65
150
Note 2. All voltages with respect to ground.
Note 3. AVSS and DVSS must be connected to the same ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
min
typ
Power Supplies:
Analog
AVDD
2.7
3.3
Digital
DVDD
2.7
3.3
Note 2. All voltages with respect to ground.
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=2.7~3.6V)
Parameter
Symbol
min
typ
Input Resistance
Zin
10
Input Voltage
VTH
350
Input Sample Frequency
fs
32
-
max
3.6
AVDD
Units
V
V
max
-
Units
kΩ
mVpp
kHz
192
DC CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=2.7~3.6V; unless otherwise specified)
Parameter
Symbol
min
typ
max
Power Supply Current
Normal operation (PDN= “H”) (Note 4)
14
LP= “0”, CM1-0= “00”
(Note 5)
28
LP= “1”, CM1-0= “00”
(Note 6)
7
14
LP= “1”, CM1-0= “01”
(Note 7)
2
Power down (PDN = “L”)
(Note 8)
10
100
High-Level Input Voltage
VIH
70%DVDD
DVDD+0.3
Low-Level Input Voltage
VIL
DVSS-0.3
30%DVDD
VOH
DVDD-0.4
High-Level Output Voltage
(Iout=-400μA)
VOL
0.4
Low-Level Output Voltage
(Iout=400μA)
Input Leakage Current
Iin
± 10
Note 4. AVDD=DVDD=3.3V.
Note 5. fs=192kHz, X'tal=24.576MHz, PCKS1-0= “10” , CL=20pF. AVDD=5mA (typ), DVDD=9mA (typ).
Note 6. fs=48kHz, X'tal=24.576MHz, CL=20pF. AVDD=4mA (typ), DVDD=3mA (typ).
Note 7. fs=48kHz, X'tal=24.576MHz. The external load current is not included.
Note 8. RX inputs are open and all digital input pins are held at DVDD or DVSS.
MS0157-E-04
Units
V
V
V
mA
V
V
°C
°C
Units
mA
mA
mA
μA
V
V
V
V
μA
2010/08
-5-
[AK4117]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=2.7~3.6V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Crystal Resonator
Frequency
fXTAL
11.2896
External Clock
Frequency
fECLK
2.048
Duty Cycle
dECLK
40
fMCK
1.024
MCKO Output
Frequency
dMCK
40
Duty Cycle
(Note 9)
PLL Clock Recover Frequency (RX0, RX1)
fpll
32
LRCK Timing
Frequency
PLL mode
fs
32
fs
44.1
X’tal mode
fs
8
External Clock mode
dLCK
45
Duty Cycle
Audio Interface Timing
BICK Frequency
fBCK
BICK Duty
dBCK
tMBLR
-20
BICK “↓” to LRCK
tBSD
BICK “↓” to SDTO
tDXH
20
DAUX Hold Time
tDXS
20
DAUX Setup Time
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN “H” Time
tCSW
150
tCSS
50
CSN “↓” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
tDCD
CDTO Delay
tCCZ
CSN “↑” to CDTO Hi-Z
Reset Timing
PDN Pulse Width
tPW
150
Note 9. Except the external clock input.
MS0157-E-04
typ
50
50
-
max
Units
24.576
24.576
60
24.576
60
192
MHz
MHz
%
MHz
%
KHz
192
192
192
55
kHz
kHz
kHz
%
20
15
Hz
%
ns
ns
ns
ns
64fs
50
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2010/08
-6-
[AK4117]
■ Timing Diagram
1/fECLK
VIH
XTI
VIL
tECLKH
tECLKL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
1/fMCK
MCKO
50%DVDD
tMCKH
tMCKL
dMCK = tMCKH x fMCK x 100
= tMCKL x fMCK x 100
1/fs
VIH
LRCK
VIL
tLRH
tLRL
dLCK = tLRH x fs x 100
= tLRL x fs x 100
Figure 1. Clock Timing
LRCK
50%DVDD
tMBLR
50%DVDD
BICK
tBSD
50%DVDD
SDTO
tDXS
tDXH
VIH
DAUX
VIL
Figure 2. Serial Interface Timing
MS0157-E-04
2010/08
-7-
[AK4117]
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDH
tCDS
C1
CDTI
C0
A4
R/W
VIH
VIL
Hi-Z
CDTO
Figure 3. WRITE/READ Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
VIH
D0
VIL
Hi-Z
CDTO
Figure 4. WRITE Data Input Timing
VIH
CSN
VIL
VIH
CCLK
VIL
CDTI
A1
VIH
A0
VIL
tDCD
CDTO
Hi-Z
D7
D6
D5
50%DVDD
Figure 5. READ Data Output Timing 1
MS0157-E-04
2010/08
-8-
[AK4117]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D3
D2
D1
D0
50%DVDD
Figure 6. READ Data Input Timing 2
tPW
PDN
VIL
Figure 7. Power Down & Reset Timing
MS0157-E-04
2010/08
-9-
[AK4117]
OPERATION OVERVIEW
■ Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
The AK4117 has a Non-PCM steam auto-detection function. When the 32-bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC60958 Interface” is detected, the NPCM bit goes to “1”. The 96-bit sync code consists of
0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM to “1”. Once the
NPCM is set to “1”, it will remain “1” until 4096 frames pass through the chip without an additional sync pattern being
detected (Timing diagram: Figure 27 and Figure 28). When those preambles are detected, the burst preambles Pc (burst
information: Table 10) and Pd (length code: Table 11) that follow those sync codes are stored to registers. The AK4117
also has a DTS-CD bitstream auto-detection function. When AK4117 detects DTS-CD bitstreams, the DTSCD bit goes to
“1”. If the next sync code does not occur within 4096 frames, the DTSCD bit goes to “0” until either the AK4117 detects
the stream again. OR’ed value of the NPCM and DTSCD bits are output to the AUTO bit. The AK4117 detects 14bit
sync word of a DTS-CD bitstream, while it does not detect 16bit sync word (0x7FFE8001).
■ 192kHz Clock Recovery
The on-chip, low jitter PLL has a wide lock range of 32kHz to 192kHz and a lock time of less than 20ms. The AK4117
has a sampling frequency detect function (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz) that uses
either clock comparison against the X’tal oscillator or the channel status information. The PLL loses lock when the
received sync interval is incorrect.
■ Clock Operation Mode
The AK4117 has two sources for MCKO and SDTO.
1) MCKO and SDTO source is recovered by PLL from RX input.
2) MCKO source is X’tal or External clock. SDTO source is DAUX input.
The CM1-0 bits select the clock operation mode (Table 1). In Mode 2, the clock source is switched from PLL to X'tal
when the PLL loses lock. In Mode3, even though the clock source is fixed to X'tal, the PLL is also operating. This allows
the monitoring of recovered data such as C bits. For Mode2 and 3, it is recommended that the X’tal frequency and PLL
recovery frequency be set differently.
Mode
0
1
CM1
0
0
CM0
0
1
UNLCK
PLL
X'tal
Clock source SDTO
ON
ON(Note)
PLL
RX
Default
OFF
ON
X'tal
DAUX
0
ON
ON
PLL
RX
2
1
0
1
ON
ON
X'tal
DAUX
3
1
1
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off.
Table 1. Clock Operation Mode select
MS0157-E-04
2010/08
- 10 -
[AK4117]
■ Master Clock Output
The AK4117 has a master clock output pin, MCKO. In PLL mode, PCKS1-0 bits select the MCKO frequency as shown
in Table 2. When MCKO=512fs, MCKO goes to “L” when fs=96kHz and 192kHz. When MCKO=256fs, MCKO goes to
“L” when fs=192kHz. When LP bit is set to “1”, the AK4117 is in low power mode (default). In low power mode, PLL
lock range is up to 48kHz and the MCKO frequency is fixed to 256fs.
In the X’tal mode, XCKS1-0 bits select the ratio of the X’tal frequency to fs (sampling frequency). The DIV bit selects
the ratio (x1 or x1/2) of the MCKO frequency to the X’tal frequency (Table 3).
LP
PCKS1
0
0
1
1
x
0
1
PCKS0
0
1
0
1
x
MCKO
512fs
256fs
128fs
N/A
256fs
fs [kHz]
32 ∼ 48
32 ∼ 96
32 ∼ 192
N/A
32 ∼ 48
Default
Table 2. Master Clock Frequency Select
(PLL mode: Clock operation mode 0, 2(UNLCK=0))
XCKS1
0
0
1
1
XCKS0
0
1
0
1
X’tal
or
EXT
128fs
256fs
512fs
1024fs
fs [kHz]
MCKO
DIV=0
128fs
256fs
512fs
1024fs
DIV=1
64fs
128fs
256fs
512fs
EXTCLK [MHz]
2.048
16
8
N/A
N/A
4.096
32
16
8
N/A
8.192
64
32
16
8
11.2896
88.2
44.1
N/A
N/A
X’tal [MHz]
12.288 24.576
96
192
48
96
N/A
48
N/A
N/A
Default
Table 3. Master Clock Frequency Select
(X’tal mode: Clock operation mode 1, 2(UNLCK=1), 3)
MS0157-E-04
2010/08
- 11 -
[AK4117]
■ Clock Source
The following circuits are available to feed a clock into the XTI pin of AK4117.
1) X’tal mode
The X’tal with proper value should be connected between XTI and XTO pins.
XTI
AK4117
XTO
Figure 8. X’tal mode (EXCK= “0”)
Note: External capacitance depends on the crystal oscillator (Typ.10-40pF).
2) External clock mode
EXCK bit should be set to “1” and the proper frequency clock input into the XTI pin. XTO pin should be left open.
XTI
External Clock
AK4117
XTO
Figure 9. External clock mode (EXCK= “1”)
3) OFF mode
CM1-0 bits should be set to “00” and XTL1-0 bits to “11” respectively. XTI and XTO pins should be left open. The
XTI pin can also be connected to ground externally.
XTI
AK4117
XTO
Figure 10. OFF mode (CM1-0= “00”, XTL1-0= “11”)
MS0157-E-04
2010/08
- 12 -
[AK4117]
■ Sampling Frequency and Pre-emphasis Detection
The AK4117 has two methods for detecting the sample frequency:
1) Clock comparison between recovered clock and the X’tal oscillator
FS3-0 bits indicate the detected RX input frequency referred to X’tal frequency. XTL1-0 bits select the reference
X’tal frequency (Table 4).
2) Sampling frequency information on channel status
When XTL1-0= “11”, FS3-0 bits indicate the decoded sampling frequency information from channel status.
XTL1
0
0
1
1
XTL0
0
1
0
1
X’tal Frequency
11.2896MHz
12.288MHz
24.576MHz
(Use channel status)
Default
Table 4. Reference X’tal frequency
Except XTL1-0= “11”
XTL1-0= “11”
Consumer
Register output
fs
Professional mode
mode
Clock comparison
(Note 11)
(Note 10)
Byte3
Byte0
Byte4
FS3
FS2
FS1
FS0
Bit3,2,1,0
Bit7,6
Bit6,5,4,3
0
0
44.1kHz
0000
01
0
0
0000
44.1kHz ± 3%
0
0
0
1
Reserved
Reserved
0001
(Others)
0
0
48kHz
0010
10
1
0
0000
48kHz ± 3%
0
0
32kHz
0
0
1
1
1
1
1
1
0000
32kHz ± 3%
1
0
88.2kHz
(1000)
00
0
0
1010
88.2kHz ± 3%
1
0
96kHz
(1010)
00
1
0
0010
96kHz ± 3%
1
1
176.4kHz
(1100)
00
0
0
1011
176.4kHz ± 3%
1
1
192kHz
(1110)
00
1
0
0011
192kHz ± 3%
Note 10. At least ±3% range is identified as the value in the Table 5. In case of an intermediate frequency of these two,
FS3-0 bits indicate the nearer value. When the frequency is much larger than 192kHz or much smaller than
32kHz, FS3-0 bits may indicate “0001”.
Note 11. In consumer mode, Byte3 Bit3-0 are copied to FS3-0.
Table 5. Sampling frequency information
The pre-emphasis information is detected and reported on the PEM bit. This information is extracted from channel 1 by
default (CS12=0). It can be switched to channel 2 by changing the CS12 bit in the control register.
PEM
Pre-emphasis
0
1
OFF
ON
Consumer mode
Professional mode
Byte 0
Bits 3-5
≠ 0X100
0X100
Byte 0
Bits 2-4
≠110
110
Table 6. Pre-emphasis information
MS0157-E-04
2010/08
- 13 -
[AK4117]
■ System Reset and Power-Down
The AK4117 has a full power-down mode for all circuits that is activated by the PDN pin, and a partial power-down
mode activated by the PWN bit. The RSTN bit initializes the internal registers and timing. The AK4117 should be reset
once at power-up by bringing PDN pin = “L”.
PDN Pin:
All analog and digital circuits are placed in power-down and reset modes by bringing PDN= “L”. All the registers
are initialized and clocks are stopped. Read/write operations to the registers are disabled.
RSTN Bit (Address 00H; D0):
All the registers except RSTN, PWN, XTL1-0 and EXCK are initialized by bringing RSTN bit = “0”. The internal
timings are also initialized. When RSTN bit= “0”, clocks are output, but SDTO is “L”. All register writes except
RSTN, PWN, XTL1-0 and EXCK are disabled. Reading from the registers is enabled.
PWN Bit (Address 00H; D1):
Clock recovery mode is initialized by bringing PWN bit = “0”. Clocks from the PLL are stopped while the X’tal
clocks continue to be output. Unlike the PDN pin operation described above, internal registers and mode settings
are not initialized. Read/write operations to the registers are enabled.
■ Biphase Input
Two receiver inputs (RX0 and RX1) are available. Each input includes an amplifier for unbalance loads that can accept
350mVpp or greater signal. The IPS bit selects the receiver channel (Table 7). When the UOUTE bit = “1”, the U bit
(user data) can be output from the UOUT pin.
IPS
0
1
INPUT Data
RX0
RX1
Default
Table 7. Recovery Data Select
UOUT
SDTO
R191
R190
L0
R0
L191
R191
L31
L1
L0
L30
R31
R30
L32
L31
LRCK
2
(except I S)
LRCK
(I2S)
Figure 11. UOUT output timing
MS0157-E-04
2010/08
- 14 -
[AK4117]
■ Biphase signal input circuit
0.1uF
RX
75Ω
Coax
75Ω
AK4117
Figure 12. Consumer Input Circuit (Coaxial Input)
Note: When using a coaxial input, if the coupling level to this input from the next RX input
line pattern exceeds 50mV, incorrect operation may occur. This can be reduced or
prevented by adding a decoupling capacitor.
3.3V
3.3V
Optical
Fiber
470
RX
O/E
Optical Receiver
AK4117
Figure 13. Consumer Input Circuit (Optical Input; Using 3.3V Optical Receiver)
MS0157-E-04
2010/08
- 15 -
[AK4117]
■ Q-subcode buffers
The AK4117 has a Q-subcode buffer for CD application. The AK4117 takes Q-subcode into registers under the following
conditions:
1)
2)
3)
4)
The sync word (S0,S1) consists of at least 16 “0”s.
The start bit is “1”.
Those 7-bits Q-W follows to the start bit.
The distance between two start bits is 8-16 bits.
The QINT bit in the control register goes “1” when the new Q-subcode differs from old one, and goes “0” when QINT bit
is read.
S0
S1
S2
S3
:
S97
S0
S1
S2
S3
:
1
0
0
1
1
:
1
0
0
1
1
:
2
3
4
5
6
7
8
*
0
0
0
0
0
0
0
0…
0
0
0
0
0
0
0
0…
Q2 R2 S2
T2
U2 V2 W2 0…
Q3 R3 S3
T3
U3 V3 W3 0…
:
:
:
:
:
:
:
:
Q97 R97 S97 T97 U97 V97 W97 0…
0
0
0
0
0
0
0
0…
0
0
0
0
0
0
0
0…
Q2 R2 S2
T2
U2 V2 W2 0…
Q3 R3 S3
T3
U3 V3 W3 0…
:
:
:
:
:
:
:
:
↑
Q
Q2
Q3 Q4
CTRL
Q5
Q6
Q7 Q8
ADRS
(*) number of "0" : min=0; max=8.
Figure 14. Configuration of U-bit(CD)
Q9
Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
TRACK NUMBER
INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE
SECOND
FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO
ABSOLUTE MINUTE
ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME
CRC
G(x)=x16+x12+x5+1
Figure 15. Q-subcode
Addr
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
D7
D6
D5
D4
Q9
Q8
···
···
Q17
Q16
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
Q81
Q80
···
···
Figure 16. Q-subcode register map
MS0157-E-04
D3
···
···
···
···
···
···
···
···
···
···
D2
···
···
···
···
···
···
···
···
···
···
D1
Q3
Q11
···
···
···
···
···
···
···
Q75
D0
Q2
Q10
···
···
···
···
···
···
···
Q74
2010/08
- 16 -
[AK4117]
■ Interrupt Handling
There are eight events which cause the INT1-0 pins to go “H”.
1. UNLCK: PLL unlock state detect
“1” when the PLL loses lock. The AK4117 loses lock when the distance between two preambles is
not correct or when those preambles are not correct.
2. PAR:
Parity error or biphase coding error detection
“1” when parity error or biphase coding error is detected, updated every sub-frame cycle. Reading
this register resets it.
3. AUTO:
Non-PCM or DTS-CD Bit Stream detection
The OR function of NPCM and DTSCD bits is output to the AUTO bit.
4. V:
Validity flag detection
“1” when validity flag is detected. Updated every sub-frame cycle.
5. AUDION: Non-audio detection
“1” when the “AUDIO” bit in recovered channel status indicates “1”. Updated every block cycle.
6. STC:
Sampling frequency or pre-emphasis information change detection
“1” when FS3-0 or PEM bit changes. Reading this register resets it.
7. QINT:
U bit (Q-subcode) sync flag
“1” when the Q-subcode differs from old one, and stays “1” until this register is read. Updated
every sync code cycle for Q-subcode. Reading this register resets it.
8. CINT:
Channel status sync flag
“1” when received C bits differ from old ones, and stays “1” until this register is read. Updated
every block cycle. Reading this register resets it.
INT1-0 pins output an OR’ed signal based on the above eight interrupt events. When masked, the interrupt event does not
affect the operation of the INT1-0 pins (the masks do not affect the resisters (UNLCK, PAR, etc.) themselves). Once
INT0 pin goes to “H”, it maintains “H” for 1024 cycles (this value can be changed by the EFH1-0 bits) after all events
not masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are cleared.
UNLCK, AUTO, V and AUDION bits indicate the interrupt status events above in real time. Once PAR, STC, QINT or
CINT bit goes to “1”, it stays “1” until the register is read. INT pin holds “H” for one sub-frame, then goes to “L” in this
case.
When the AK4117 loses lock, the channel status bits are initialized. In this initial state, INT0 outputs the OR’ed signal
between UNLCK and PAR bits. INT1 outputs the OR’ed signal to AUTO, V and AUDION. INT1-0 pins are “L” when
the PLL is OFF (Clock Operation Mode 1).
UNLCK
1
0
0
Event
PAR
x
1
0
Others
x
x
x
SDTO Pin
“L”
Previous Data
Output
Table 8. Interrupt handling
MS0157-E-04
2010/08
- 17 -
[AK4117]
Interrupt
(UNLCK, PAR,..)
(Interrupt)
INT0 pin
Hold Time (max: 4096/fs)
INT1 pin
Hold Time = 0
Register (PAR,STC,
CINT,QINT)
Reset
Hold ”1”
Register
(others)
Command
MCKO,BICK,LRCK
(UNLCK)
READ 05H
Free Run
(fs: around 20kHz)
MCKO,BICK,LRCK
(except UNLCK)
SDTO
(UNLCK)
SDTO
(PAR error)
Previous Data
SDTO
(others)
Normal Operation
Figure 17. INT1-0 pin timing
MS0157-E-04
2010/08
- 18 -
[AK4117]
PDN pin ="L" to "H"
Initialize
Read 05H
INT0/1 pin ="H"
No
Yes
Release
Muting
Mute DAC output
Read 05H
(Each Error Handling)
Read 05H
(Resets registers)
No
INT0/1 pin ="H"
Yes
Figure 18. Interrupt Handling Sequence Example 1
MS0157-E-04
2010/08
- 19 -
[AK4117]
PDN pin ="L" to "H"
Initialize
Read 05H
No
INT1 pin ="H"
Yes
Read 05H
and
Detect QSUB= “1”
(Read Q-buffer)
QCRC = “0”
No
New data
is invalid
Yes
INT1 pin ="L"
No
Yes
New data
is valid
Figure 19. Interrupt Handling Sequence Example (for Q/CINT)
MS0157-E-04
2010/08
- 20 -
[AK4117]
■ Audio Serial Interface Format
The DIF2-0 bits can select six serial data formats as shown in Table 9. In all formats, the serial data is MSB-first, 2’s
compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on the rising edge of
BICK. BICK outputs 64fs clock. When the SDTO format is equal or less than 20 bits (Mode 0-2), LSBs in the sub-frame
are truncated. In Modes 3-7, the last four LSBs are auxiliary data (see Figure 20).
When a Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, the AK4117 continues to output the
last normal sub-frame data from SDTO repeatedly until the error is removed. When an Unlock Error occurs, the AK4117
outputs “0” from SDTO. When using the DAUX pin, the data is transformed and output from SDTO. The DAUX pin is
used in Clock Operation Modes 1, 3 and in the unlock state of Mode 2. The input data format to DAUX should be
left-justified except in Mode 5. In Mode 5, both the input data format of DAUX and the output data format of SDTO are
I2S.
sub-frame of IEC60958
0
3 4
preamble
7 8
11 12
27 28 29 30 31
Aux.
V U C P
LSB
MSB
MSB
LSB
23
0
AK4117 Audio Data (MSB First)
Figure 20. Bit configuration
Mode
0
1
2
3
4
5
6
7
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
DAUX
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
SDTO
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
LRCK
H/L
H/L
H/L
H/L
H/L
L/H
Default
Reserved
Table 9. Audio data format
MS0157-E-04
2010/08
- 21 -
[AK4117]
LRCK
0
1
2
15
16
17
31
0
1
2
15
16
17
31
0
1
0
1
0
1
BICK
(64fs)
15
14
1
0
15
14
1
0
SDTO
15:MSB, 0:LSB
Rch Data
Lch Data
Figure 21. Mode 0 Timing
LRCK
0
1
2
9
10
12
11
31
0
1
2
9
10
11
12
31
BICK
(64fs)
23
22
21
20
1
0
23
22
21
20
1
0
SDTO
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 22. Mode 3 Timing
LRCK
0
1
2
21
22
24
23
31
0
1
2
21
22
23
24
31
BICK
(64fs)
23
22 21
2
1
0
23 22
3
2
1
0
23 22
SDTO
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 23. Mode 4 Timing
LRCK
0
1
2
22
24
23
25
31
0
1
2
21
22
23
24
25
31
0
1
BICK
(64fs)
SDTO
23
22 21
2
1
23 22
0
3
2
1
0
23
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 24. Mode 5 Timing
MS0157-E-04
2010/08
- 22 -
[AK4117]
■ Serial Control Interface
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C1-0 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition
of CSN. The maximum speed of CCLK is 5MHz. PDN= “L” resets the registers to their default values.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
WRITE
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
CDTI
READ
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
C1,C0:
R/W:
A4-A0:
D7-D0:
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Chip Address (Fixed to “00”)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 25. 4-wire Serial Control I/F Timing
MS0157-E-04
2010/08
- 23 -
[AK4117]
■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
Power Down Control
0
0
0
EXCK
XTL1
XTL0
PWN
RSTN
01H
Clock Control
LP
PCKS1
PCKS0
DIV
XCKS1
XCKS0
CM1
CM0
02H
Input/Output Control
IPS
UOUTE
CS12
EFH1
EFH0
DIF2
DIF1
DIF0
03H
INT0 MASK
MULK0
MPAR0
MAUT0
MV0
MAUD0
MSTC0
MCIT0
MQIT0
04H
INT1 MASK
MULK1
MPAR1
MAUT1
MV1
MAUD1
MSTC1
MCIT1
MQIT1
05H
Receiver status 0
UNLCK
PAR
AUTO
V
AUDION
STC
CINT
QINT
06H
Receiver status 1
0
DTSCD
NPCM
PEM
FS3
FS2
FS1
FS0
07H
Receiver status 2
0
0
0
0
0
0
CCRC
QCRC
08H
RX Channel Status Byte 0
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
09H
RX Channel Status Byte 1
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
0AH
RX Channel Status Byte 2
CR23
CR22
CR21
CR20
CR19
CR18
CR17
CR16
0BH
RX Channel Status Byte 3
CR31
CR30
CR29
CR28
CR27
CR26
CR25
CR24
0CH
RX Channel Status Byte 4
CR39
CR38
CR37
CR36
CR35
CR34
CR33
CR32
0DH
Burst Preamble Pc Byte 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
0EH
Burst Preamble Pc Byte 1
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
0FH
Burst Preamble Pd Byte 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
10H
Burst Preamble Pd Byte 1
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
11H
Q-subcode Address / Control
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
12H
Q-subcode Track
Q17
Q16
Q15
Q14
Q13
Q12
Q11
Q10
13H
Q-subcode Index
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
14H
Q-subcode Minute
Q33
Q32
Q31
Q30
Q29
Q28
Q27
Q26
15H
Q-subcode Second
Q41
Q40
Q39
Q38
Q37
Q36
Q35
Q34
16H
Q-subcode Frame
Q49
Q48
Q47
Q46
Q45
Q44
Q43
Q42
17H
Q-subcode Zero
Q57
Q56
Q55
Q54
Q53
Q52
Q51
Q50
18H
Q-subcode ABS Minute
Q65
Q64
Q63
Q62
Q61
Q60
Q59
Q58
19H
Q-subcode ABS Second
Q73
Q72
Q71
Q70
Q69
Q68
Q67
Q66
1AH
Q-subcode ABS Frame
Q81
Q80
Q79
Q78
Q77
Q76
Q75
Q74
Note: When PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timing is reset and all registers except RSTN, PWN, XTL1-0 and EXCK
bits are initialized to their default values.
All data can be written to the registers even if PWN bit is “0”.
MS0157-E-04
2010/08
- 24 -
[AK4117]
■ Register Definitions
Addr
Register Name
00H Power Down Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
EXCK
R/W
0
D3
XTL1
R/W
0
D2
XTL0
R/W
0
D1
PWN
R/W
1
D0
RSTN
R/W
1
D1
CM1
R/W
0
D0
CM0
R/W
0
RSTN: Timing Reset & Register Initialize
0: Reset & Initialize (except RSTN, PWN, XTL1-0 and EXCK bits)
1: Normal Operation (Default)
PWN: Power-Down for Clock Recovery Part
0: Power Down
1: Normal Operation (Default)
XTL1-0: Reference X’tal Frequency Select (Table 4; Default: 00)
EXCK: External Clock Mode Select
0: X’tal mode (Default)
1: External clock mode (Feedback resistor of X’tal oscillator circuit is open.)
Addr
Register Name
01H Clock Control
R/W
Default
D7
LP
R/W
1
D6
PCKS1
R/W
0
D5
PCKS0
R/W
1
D4
DIV
R/W
0
D3
D2
XCKS1 XCKS0
R/W
R/W
0
1
CM1-0: Master Clock Operation Mode Select (Table 1; Default: 00)
XCKS1-0: Master Clock Frequency Select at X’tal Mode (Table 3; Default: 01)
DIV: Master Clock Output Select at X’tal Mode
0: Same frequency as X’tal (Default)
1: Half frequency of X’tal
PCKS1-0: Master Clock Frequency Select at PLL Mode (Table 2; Default: 01)
LP: Low Power Mode Select (Table 2)
0: Normal mode
1: Low power mode (Default)
In low power mode, fs cannot exceed 48kHz.
MS0157-E-04
2010/08
- 25 -
[AK4117]
Addr
Register Name
02H Format Control
R/W
Default
D7
IPS
R/W
0
D6
UOUTE
R/W
0
D5
CS12
R/W
0
D4
EFH1
R/W
0
D3
EFH0
R/W
1
D2
DIF2
R/W
1
D1
DIF1
R/W
0
D0
DIF0
R/W
0
DIF2-0: Audio Data Format Control (Table 9; Default: 100)
EFH1-0: INT0 Pin Hold Count Select
00: 512 LRCK
10: 2048 LRCK
01: 1024 LRCK (Default)
11: 4096 LRCK
CS12: Channel Status Select
0: Channel 1 (Default)
1: Channel 2
This bit selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3-0, Pc, Pd
and CRC.
UOUTE: U-bit Output Enable
0: Disable (Default)
1: Enable. U-bit is output from UOUT pin.
IPS: Input Recovery Data Select (Table 7)
0: RX0 (Default)
1: RX1
MS0157-E-04
2010/08
- 26 -
[AK4117]
Addr
Register Name
03H INT0 MASK
R/W
Default
MQIT0:
MCIT0:
MSTC0:
MAUD0:
MV0:
MAUT0:
MPAR0:
MULK0:
D7
D6
D5
MULK0 MPAR0 MAUT0
R/W
R/W
R/W
0
0
1
D4
MV0
R/W
1
D3
D2
D1
MAUD0 MSTC0 MCIT0
R/W
R/W
R/W
1
1
1
D0
MQIT0
R/W
1
Mask Enable for QINT bit
Mask Enable for CINT bit
Mask Enable for STC bit
Mask Enable for AUDION bit
Mask Enable for V bit
Mask Enable for AUTO bit
Mask Enable for PAR bit
Mask Enable for UNLOCK bit
0: Mask disable
1: Mask enable
The factor which mask bit is set to “0” affects INT0 pin operation.
Addr
Register Name
04H INT0 MASK
R/W
Default
MQIT1:
MCIT1:
MSTC1:
MAUD1:
MV1:
MAUT1:
MPAR1:
MULK1:
D7
D6
D5
MULK1 MPAR1 MAUT1
R/W
R/W
R/W
1
1
0
D4
MV1
R/W
0
D3
D2
D1
MAUD1 MSTC1 MCIT1
R/W
R/W
R/W
0
1
1
D0
MQIT1
R/W
1
Mask Enable for QINT bit
Mask Enable for CINT bit
Mask Enable for STC bit
Mask Enable for AUDION bit
Mask Enable for V bit
Mask Enable for AUTO bit
Mask Enable for PAR bit
Mask Enable for UNLOCK bit
0: Mask disable
1: Mask enable
The factor whose mask bit is set to “0” affects INT1 pin operation.
MS0157-E-04
2010/08
- 27 -
[AK4117]
Addr
Register Name
05H Receiver status 0
R/W
Default
D7
UNLCK
RD
0
D6
PAR
RD
0
D5
AUTO
RD
0
D4
V
RD
0
D3
AUDION
RD
0
D2
STC
RD
0
D1
CINT
RD
0
D0
QINT
RD
0
QINT: Q-subcode Buffer Interrupt
0: No change
1: Changed
This bit goes to “1” when Q-subcode stored in register addresses 11H to 1AH is updated.
CINT: Channel Status Buffer Interrupt
0: No change
1: Changed
This bit goes to “1” when C-bit stored in register addresses 08H to 0CH changes.
STC: Sampling Frequency or Pre-emphasis Information Change Detection
0: No detect
1: Detect
This bit goes to “1” when either the FS3-0 or PEM bit changes.
AUDION: Audio Bit Output
0: Audio
1: Non Audio
This bit is made by encoding channel status bits.
V: Validity Bit
0: Valid
1: Invalid
AUTO: Non-PCM or DTS-CD Bit Steam Auto Detection
0: No detect
1: Detect
This bit outputs the OR’ed value of NPCM and DTSCD bits.
PAR: Parity Error or Biphase Error Status
0:No Error
1:Error
This bit goes to “1” if a parity error or biphase error is detected in the sub-frame.
UNLCK: PLL Lock Status
0: Lock
1: Unlock
QINT, CINT, STC and PAR bits are initialized when 05H is read.
MS0157-E-04
2010/08
- 28 -
[AK4117]
Addr
Register Name
06H Receiver status 1
R/W
Default
D7
0
RD
0
D6
DTSCD
RD
0
D5
NPCM
RD
0
D4
PEM
RD
0
D3
FS3
RD
0
D2
FS2
RD
0
D1
FS1
RD
0
D0
FS0
RD
1
D3
0
RD
0
D2
0
RD
0
D1
CCRC
RD
0
D0
QCRC
RD
0
FS3-0: Sampling Frequency Detection (Table 5)
PEM: Pre-emphasis Detect
0: OFF
1: ON
This bit is made by encoding the channel status bits.
NPCM: Non-PCM Bit Stream Auto Detection
0: No detect
1: Detect
DTSCD: DTS-CD Bit Stream Auto Detect
0: No detect
1: Detect
Addr
Register Name
07H Receiver status 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
QCRC: Cyclic Redundancy Check for Q-subcode
0: No Error
1: Error
CCRC: Cyclic Redundancy Check for Channel Status
0: No Error
1: Error
This bit is enabled only in professional mode and only for the channel selected by the CS12 bit.
MS0157-E-04
2010/08
- 29 -
[AK4117]
Addr
08H
09H
0AH
0BH
0CH
Register Name
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
R/W
Default
D7
CR7
CR15
CR23
CR31
CR39
D6
CR6
CR14
CR22
CR30
CR38
D5
CR5
CR13
CR21
CR29
CR37
D4
CR4
CR12
CR20
CR28
CR36
D3
CR3
CR11
CR19
CR27
CR35
D2
CR2
CR10
CR18
CR26
CR34
D1
CR1
CR9
CR17
CR25
CR33
D0
CR0
CR8
CR16
CR24
CR32
D2
PC2
PC10
PD2
PD10
D1
PC1
PC9
PD1
PD9
D0
PC0
PC8
PD0
PD8
RD
Not initialized
CR39-0: Receiver Channel Status Byte 4-0
All 40 bits are updated at the same time every block (192 frames) cycle.
Addr
0DH
0EH
0FH
10H
Register Name
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
R/W
Default
D7
PC7
PC15
PD7
PD15
D6
PC6
PC14
PD6
PD14
D5
PC5
PC13
PD5
PD13
D4
PC4
PC12
PD4
PD12
D3
PC3
PC11
PD3
PD11
RD
Not initialized
PC15-0: Burst Preamble Pc Byte 0 and 1
PD15-0: Burst Preamble Pd Byte 0 and 1
Addr
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
Q8
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
RD
Not initialized
Q2-81: Q-subcode (Figure 14 and Figure 15)
All 80 bits are updated at the same time every sync code cycle for Q-subcode.
MS0157-E-04
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[AK4117]
■ Burst Preambles in non-PCM Bitstreams
sub-frame of IEC60958
0
3 4
preamble
7 8
Aux.
11 12
27 28 29 30 31
LSB
MSB V U C P
16 bits of bitstream
0
Pa Pb Pc Pd
15
Burst_payload
stuffing
repetition time of the burst
Figure 26. Data structure in IEC60958
Preamble word
Pa
Pb
Pc
Pd
Length of field
Contents
16 bits
sync word 1
16 bits
sync word 2
16 bits
Burst info
16 bits
Length code
Table 10. Burst preamble words
MS0157-E-04
Value
0xF872
0x4E1F
see Table 11
numbers of bits
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[AK4117]
Bits of Pc value
contents
0-4
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without extension
MPEG-2 data with extension
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
reserved, shall be set to “0”
error-flag indicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
data type dependent info
bit stream number, shall be set to “0”
Table 11. Fields of burst info Pc
5, 6
7
8-12
13-15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
0
0
1
0
repetition time of burst
in IEC958 frames
MS0157-E-04
≤4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
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[AK4117]
■ Non-PCM Bitstream timing
1) When Non-PCM preamble does not arrive within 4096 frames,
PDN pin
Bit stream
Pa Pb Pc1 Pd1
Pa Pb Pc2 Pd2
Repetition time
Pa Pb Pc3 Pd3
>4096 frames
AUTO bit
Pc Register
“0”
Pd Register
“0”
Pc1
Pc2
Pd1
Pc3
Pd2
Pd3
Figure 27. Timing example 1
2) When Non-PCM bitstream stops (when MULK0=0),
INT0 hold time
INT0 pin
<20mS (Lock time)
Bit stream
Pa Pb Pc1 Pd1
Stop
Pa Pb Pcn Pdn
2~3 Syncs (B,M or W)
<Repetition time
AUTO bit
Pc Register
Pd Register
Pc0
Pc1
Pd0
Pcn
Pd1
Pdn
Figure 28. Timing example 2
MS0157-E-04
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[AK4117]
SYSTEM DESIGN
Figure 29 is a system connection diagram. An evaluation board is available which demonstrates application circuits, the
optimum layout, power supply arrangements and measurement results.
12k
3.3V Supply
S/PDIF
(see Figure 12-14)
+
10u 0.1u
(Shield)
10u
+
3.3V Supply
1
R
AVSS
24
2
AVDD
PDN
23
3
RX1
INT0
22
4
NC
INT1
21
5
RX0
CSN
20
6
DVDD
CCLK
19
7
DVSS
CDTI
18
8
XTI
CDTO
17
9
XTO
UOUT
16
10
LRCK
NC
15
11
BICK
MCKO
14
12
SDTO
DAUX
13
0.1u
AK4117
Microcontroller
C
(see Figure 8-10)
C
DSP
AD/DA
Figure 29. Typical Connection Diagram
Notes:
(1) “C” depends on the X’tal. (Typ.10-40pF)
(2) AVSS and DVSS must be connected the same ground plane.
MS0157-E-04
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[AK4117]
PACKAGE
24pin VSOP (Unit: mm)
1.25±0.2
*7.8±0.15
13
A
7.6±0.2
*5.6±0.2
24
12
1
0.22±0.1
0.65
0.15±0.05
0.1±0.1
0.5±0.2
Detail A
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Material & Lead finish
Package molding compound: Epoxy
Lead frame material:
Cu
Lead frame surface treatment: Solder (Pb free) plate
MS0157-E-04
2010/08
- 35 -
[AK4117]
MARKING
AKM
AK4117VF
AAXXXX
Contents of AAXXXX
AA:
Lot#
XXXX: Date Code
REVISION HISTORY
Date (YY/MM/DD)
02/05/27
02/12/12
Revision
00
01
Reason
First Edition
Error
Correction
Page
Contents
3
Pin Lay Out
Pin#14: MCLK → MCKO
Audio Serial Interface Format
21
“The DIF2-0 pins can select...” → “The DIF2-0 bits can select...”
03/01/23
02
Error
Correction
1
04/04/19
03
Error
Correction
16
32
10/08/11
04
Error
Correction
11
General Description
“Mode settings can be controlled via microprocessor serial
interface or via dedicated pin.”
→ “Mode settings can be controlled via microprocessor serial
interface.”
Figure 16.Q-subcode register map
Addr = 16H~1FH → 11H~1AH
Table 11. Fields of burst info Pc
Value 7: reserved → MPEG2 AAC ADTS;
repetition time of burst: 1024
Value 14: reserved → ATRAC;
repetition time of burst: 512
Value 15: reserved → ATRAC2/3;
repetition time of burst: 1024
Value 27: (Reserved for MPEG-4 AAC data) → reserved
Value 28: MPEG-2 AAC data → reserved
Table 3. EXTCLK range was changed.
MS0157-E-04
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[AK4117]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or
third parties arising from the use of these information herein. AKM assumes no liability for infringement of any
patent, intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any
and all claims arising from the use of said product in the absence of such notification.
MS0157-E-04
2010/08
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