AKM AK4671_10

[AK4671]
AK4671
Stereo CODEC with MIC/RCV/HP-AMP
GENERAL DESCRIPTION
The AK4671 is a stereo CODEC with a built-in Microphone-Amplifier, Receiver-Amplifier and
Headphone-Amplifier. The AK4671 features dual PCM I/F in addition to audio I/F that allows easy
interfacing in mobile phone designs with Bluetooth I/F. The AK4671 is available in a 57pin BGA, utilizing
less board space than competitive offerings.
1.
2.
3.
4.
5.
6.
7.
8.
FEATURES
Recording Function (Stereo CODEC)
• 4 Stereo Input Selector x 2ch
• 4 Stereo Inputs (Single-ended) or 2 Stereo Input (Full-differential)
• MIC Amplifier: +30dB ∼ −12dB, 3dB step
• Digital ALC (Automatic Level Control): +36dB ∼ −54dB, 0.375dB Step, Mute
• Wind-noise Reduction Filter
• Stereo Separation Emphasis
• 5-band Programmable Notch Filter
• Audio Interface Format: 16bit MSB justified, I2S, DSP Mode
Playback Function (Stereo CODEC)
• Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control): +36dB ∼ −54dB, 0.375dB Step, Mute
• Stereo Separation Emphasis
• 5-band EQ
• Stereo Line Output
• Mono Receiver-Amp
- BTL Output
- Output Power: [email protected] (AVDD=3.3V)
• Stereo Headphone-Amp
- Output Power: [email protected] (AVDD=3.3V)
• Analog Mixing: 4 Stereo Input
• Audio Interface Format:
- 16bit MSB justified, 16bit LSB justified, 16-24bit I2S, DSP Mode
Dual PCM I/F for Baseband & Bluetooth Interface
• Sample Rate Converter (Up sample: up to x6: Down sample: down to x1/6)
• Sample Rate: 8kHz
• Digital Volume
• Audio Interface Format:
- 16bit Linear, 8bit A-law, 8bit μ-law
- Short/Long Frame, I2S, MSB justified
10bit SAR ADC
• 3 Input Selector
Power Management
Master Clock:
(1) PLL Mode
• Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz,
24MHz, 26MHz, 27MHz (MCKI pin)
1fs (LRCK pin)
32fs or 64fs (BICK pin)
(2) External Clock Mode
• Frequencies: 256fs, 384fs, 512fs, 768fs or 1024fs (MCKI pin)
Output Master Clock Frequencies: 32fs/64fs/128fs/256fs
Sampling Rate (Stereo CODEC):
MS0666-E-02
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-1-
[AK4671]
• PLL Slave Mode (LRCK pin): 8kHz ∼ 48kHz
• PLL Slave Mode (BICK pin): 8kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode:
8kHz ∼ 48kHz (256fs, 384fs), 8kHz ∼ 26kHz (512fs, 768fs),
8kHz ∼ 13kHz (1024fs)
9. μP I/F: 4-wire Serial / I2C Bus (Ver 1.0, 400kHz Fast Mode)
10. Master/Slave mode
11. Ta = −30 ∼ 85°C
12. Power Supply:
• AVDD, PVDD, SAVDD: 2.2 ∼ 3.6V
• DVDD, TVDD2, TVDD3: 1.6 ∼ 3.6V
13. Package : 57pin BGA (5mm x 5mm, 0.5mm pitch)
■ Block Diagram
AVDD
VSS1
SAIN1 SAIN2 SAIN3
VCOM
SAVDD
VSS3
DVDD
VSS4
GPO1
GPO2
PMSAD
MDT
PMMP
MPWR
CSN
A/D
MIC Power
Supply
Control
Register
MIC-Amp
PMADL or PMADR
RIN1/IN1−
A/D
LIN2/IN2+
External
MIC
CDTO
PMMICL
LIN1/IN1+
Internal
MIC
I2C
HPF
PDN
PMMICR
PFSEL=0
PMADL
or
PMADR
RIN2/IN2−
LIN3/IN3+
PFSEL=1
PMDAL
or
PMDAR
or
PMSRA
RIN3/IN3−
LIN4/IN4+
PMLO1
LOUT1/RCP
PMLOOPR
PMLOOPL
PMAINR3
PMAINR4
PMAINL4
PMAINL3
PMAINR2
PMAINL2
PMAINL1
PMAINR1
RIN4/IN4−
HPF
LPF
BICK
Stereo
Separation
Audio
I/F
5-band
Notch
ALC
LRCK
SDTO
SDTI
MIX
PMDAL
or
PMDAR
SVOLA
PMDAL or PMDAR or PMSRA
D/A
Stereo Line Out
or
Mono Receiver
CCLK/SCL
CDTI/SDA
M DATT 5-band
I SMUTE
EQ
X
S
E
L
MCKI
MCKO
PMRO1
ROUT1/RCN
PMPLL
PLL
PMLO2
PMLO2S
PMPCM
VCOC
VCOCBT
LOUT2
Headphone Out
PMRO2
PLLBT
PMSRA
PMRO2S
ROUT2
SRC-A
BICKA
MUTET
SVOLB
PCM
I/F A
PMSRB
SDTOA
PMLO3
SRC-B
LOUT3/LOP
Stereo Line Out
SDTIA
DATT-B
DATT-C
PMRO3
ROUT3/LON
BVOL
PVDD
VSS2
SYNCA
TVDD2
PCM
I/F B
BICKB
SYNCB
SDTOB
SDTIB
TVDD3
Figure 1. Block Diagram
MS0666-E-02
2010/06
-2-
[AK4671]
■ Ordering Guide
−30 ∼ +85°C
57pin BGA (0.5mm pitch)
Evaluation board for AK4671
AK4671EG
AKD4671
■ Pin Layout
9
8
7
6
AK4671
5
Top View
4
3
2
1
A
B
C
D
E
F
G
H
J
9
TEST
LOUT2
ROUT2
VCOM
VCOCBT
VSS2
SDTOA
SYNCA
GPO2
8
AVDD
VSS1
MUTET
VCOC
PVDD
TVDD2
BICKA
CDTI
/SDA
SDTIA
LOUT1
/RCP
ROUT3
/LON
RIN4
/IN4−
LIN3
/IN3+
LIN2
/IN2+
LIN1
/IN1+
ROUT1
/RCN
LOUT3
/LOP
LIN4
/IN4+
RIN3
/IN3−
RIN2
/IN2−
RIN1
/IN1−
VSS4
DVDD
CCLK
/SCL
CSN
/CAD0
I2C
BICK
MCKI
MCKO
PDN
LRCK
MDT
A
7
6
5
4
3
2
1
Top View
NC
SAIN2
SAVDD
TVDD3
SDTOB
BICKB
SDTO
CDTO
MPWR
SAIN3
SAIN1
VSS3
SYNCB
SDTIB
SDTI
GPO1
B
C
D
E
F
G
H
J
MS0666-E-02
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-3-
[AK4671]
PIN/FUNCTION
No. Pin Name
A1 MDT
B1 MPWR
C1 SAIN3
C2 SAIN2
D1 SAIN1
D2 SAVDD
E1 VSS3
E2 TVDD3
F2 SDTOB
F1 SYNCB
G2 BICKB
G1 SDTIB
H1 SDTI
J1 GPO1
I/O
I
O
I
I
I
O
I/O
I/O
I
I
O
J2
CDTO
O
H2
SDTO
O
H3
PDN
I
J3
H4
J4
LRCK
MCKI
MCKO
H5
I2C
J5
BICK
CSN
CAD0
CCLK
SCL
VSS4
DVDD
CDTI
SDA
GPO2
J6
H6
H7
J7
H8
J9
I/O
I
O
I
I/O
I
I
I
I
I
I/O
O
Function
MIC Detection Pin (Internal pull down by 500kΩ)
MIC Power Supply Pin
10bit SAR ADC Analog Input 3 Pin
10bit SAR ADC Analog Input 2 Pin
10bit SAR ADC Analog Input 1 Pin
10bit SAR ADC Power Supply Pin, 2.2 ∼ 3.6V
Ground 3 Pin
Digital I/O Power Supply 3 Pin, 1.6 ∼ 3.6V
Serial Data Output B Pin
Sync Signal B Pin
Serial Data Clock B Pin
Serial Data Input B Pin
Audio Serial Data Input Pin
General Purpose Output 1 Pin
Control Data Output Pin (I2C pin = “L”: 4-wire Serial Mode)
Hi-Z (I2C pin = “H”: I2C Bus Mode)
Audio Serial Data Output Pin
Power-Down Mode Pin
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
“L” time of 150ns or more after power-up is needed to reset the AK4671.
Input / Output Channel Clock Pin
External Master Clock Input Pin
Master Clock Output Pin
Control Mode Select Pin
“H”: I2C Bus, “L”: 4-wire Serial
Audio Serial Data Clock Pin
Chip Select Pin (I2C pin = “L”: 4-wire Serial Mode)
Chip Address 0 Select Pin (I2C pin = “H”: I2C Bus Mode)
Control Data Clock Pin (I2C pin = “L”: 4-wire Serial Mode)
Control Data Clock Pin (I2C pin = “H”: I2C Bus Mode)
Ground 4 Pin
Digital Power Supply Pin, 1.6 ∼ 3.6V
Control Data Input Pin (I2C pin = “L”: 4-wire Serial Mode)
Control Data Input Pin (I2C pin = “H”: I2C Bus Mode)
General Purpose Output 2 Pin
MS0666-E-02
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-4-
[AK4671]
No. Pin Name
J8 SDTIA
G8 BICKA
H9 SYNCA
G9 SDTOA
F8 TVDD2
F9 VSS2
E8 PVDD
I/O
I
I/O
I/O
O
-
Function
Serial Data Input A Pin
Serial Data Clock A Pin
Sync Signal A Pin
Serial Data Output A Pin
Digital I/O Power Supply 2 Pin, 1.6 ∼ 3.6V
Ground 2 Pin
PLLBT Power Supply Pin, 2.2 ∼ 3.6V
Output Pin for Loop Filter of PLLBT Circuit
E9 VCOCBT
O
This pin should be connected to VSS2 pin with one resistor and capacitor in series.
Output Pin for Loop Filter of PLL Circuit
D8 VCOC
O
This pin should be connected to VSS1 pin with one resistor and capacitor in series.
Common Voltage Output Pin, 0.5 x AVDD
D9 VCOM
O
Bias voltage of ADC inputs and DAC outputs.
Mute Time Constant Control Pin
C8 MUTET
O
Connected to VSS1 pin with a capacitor for mute time constant.
C9 ROUT2
O
Rch Headphone-Amp Output Pin
B9 LOUT2
O
Lch Headphone-Amp Output Pin
Test Pin
A9 TEST
This pin should be open.
A8 AVDD
Analog Power Supply Pin, 2.2 ∼ 3.6V
B8 VSS1
Ground 1 Pin
Rch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output)
ROUT1
O
B7
Receiver-Amp Negative Output Pin (RCV bit = “1”: Receiver Output)
RCN
O
Lch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output)
LOUT1
O
A7
Receiver-Amp Positive Output Pin (RCV bit = “1”: Receiver Output)
RCP
O
Rch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output)
ROUT3
O
A6
Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
LON
O
Lch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output)
LOUT3
O
B6
Positive
Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
LOP
O
RIN4
I
Rch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input)
A5
I
Negative Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input)
IN4−
LIN4
I
Lch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input)
B5
IN4+
I
Positive Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input)
RIN3
I
Rch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)
B4
I
Negative Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)
IN3−
LIN3
I
Lch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)
A4
IN3+
I
Positive Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)
RIN2
I
Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
B3
I
Negative Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
IN2−
LIN2
I
Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
A3
IN2+
I
Positive Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
RIN1
I
Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
B2
I
Negative Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
IN1−
LIN1
I
Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
A2
IN1+
I
Positive Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
No Connect Pin
C3 NC
No internal bonding. This pin should be open or connected to the ground.
Note 1. All input pins except analog input pins (MDT, LIN1/IN1+, RIN1/IN1−, LIN2/IN2+, RIN2/IN2−, LIN3/IN3+,
RIN3/IN3−, LIN4/IN4+, RIN4/IN4−, SAIN1, SAIN2, SAIN3) should not be left floating.
I/O pins except SDA pin (LRCK, BICK, SYNCA, BICKA, SYNCB, BICKB) should be processed appropriately.
Please refer the “Master Mode/Slave Mode” (P.45) and “PCM I/F Master Mode/Slave Mode” (P.105). SDA pin
should be pulled-up by a resistor externally and be connected to (DVDD+0.3)V or less voltage.
MS0666-E-02
2010/06
-5-
[AK4671]
■ Handling of Unused Pin on the System
The unused I/O pins on the system should be processed appropriately as below.
Classification
Analog
Pin Name
MPWR, MDT, VCOC, ROUT3/LON, LOUT3/LOP,
ROUT2, LOUT2, MUTET, ROUT1/RCN,
LOUT1/RCP, RIN4/IN4−, LIN4/IN4+, RIN3/IN3−,
LIN3/IN3+, RIN2/IN2−, LIN2/IN2+, RIN1/IN1−,
LIN1/IN1+, VCOCBT, SAIN1, SAIN2, SAIN3
MCKO, SDTOA, SDTOB, GPO1, GPO2, CDTO
MCKI, SDTIA, SDTIB
Digital
BICKA, SYNCA, BICKB, SYNCB
MS0666-E-02
Setting
These pins should be open.
These pins should be open.
These pins should be connected to VSS4.
When all pins are unused, these pins should
be connected to VSS4 and PMPCM bit
must be always “0”.
When either PCM I/F A(BICKA/ SYNCA)
or PCM I/F B(BICKB/SYNCB) is used,
unused pins are connected to pull-down/up
resistor of about 100kΩ.
2010/06
-6-
[AK4671]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=VSS4=0V; Note 2, Note 3)
Parameter
Symbol
min
Power Supplies:
Analog
AVDD
−0.3
PLLBT
PVDD
−0.3
10bit SAR ADC
SAVDD
−0.3
Digital
DVDD
−0.3
Digital I/O 2
TVDD2
−0.3
Digital I/O 3
TVDD3
−0.3
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage 1 (Note 4)
VINA1
−0.3
Analog Input Voltage 2 (Note 5)
VINA2
−0.3
Digital Input Voltage 1 (Note 6)
VIND1
−0.3
Digital Input Voltage 2 (Note 7)
VIND2
−0.3
Digital Input Voltage 3 (Note 8)
VIND3
−0.3
Ambient Temperature (powered applied)
Ta
−30
Storage Temperature
Tstg
−65
max
4.0
4.0
4.0
4.0
4.0
4.0
±10
AVDD+0.3
SAVDD+0.3
DVDD+0.3
TVDD2+0.3
TVDD3+0.3
85
150
Units
V
V
V
V
V
V
mA
V
V
V
V
V
°C
°C
Note 2. All voltages with respect to ground.
Note 3. VSS1, VSS2, VSS3 and VSS4 must be connected to the same analog ground plane.
Note 4. RIN4/IN4−, LIN4/IN4+, RIN3/IN3−, LIN3/IN3+, RIN2/IN2−, LIN2/IN2+, RIN1/IN1−, LIN1/IN1+ pins
Note 5. SAIN1, SAIN2, SAIN3 pins
Note 6. PDN, I2C, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins
Pull-up resistors at SDA and SCL pins should be connected to (DVDD+0.3)V or less voltage.
Note 7. BICKA, SYNCA, SDTIA pins
Note 8. BICKB, SYNCB, SDTIB pins
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=VSS3=VSS4=0V; Note 2)
Parameter
Symbol
min
typ
Power Supplies Analog
AVDD
2.2
3.3
(Note 9) PLLBT
PVDD
2.2
3.3
10bit SAR ADC
SAVDD
2.2
3.3
Digital
DVDD
1.6
3.3
Digital I/O 2
TVDD2
1.6
3.3
Digital I/O 3
TVDD3
1.6
3.3
Difference
0
AVDD−PVDD
−0.1
max
3.6
3.6
3.6
3.6
3.6
3.6
+0.1
Units
V
V
V
V
V
V
V
Note 2. All voltages with respect to ground.
Note 9. The power-up sequence between AVDD, PVDD, SAVDD, DVDD, TVDD2 and TVDD3 is not critical.
The PDN pin should be held to “L” when power-up. The PDN pin should be set to “H” after all power supplies are
powered-up. The AK4671 should be operated by the recommended power-up/down sequence shown in “System
Design (Grounding and Power Supply Decoupling)” to avoid pop noise at receiver output, headphone output and
line output.
When the power is OFF partially except for DVDD, all power management bits (PMVCM, PMMP, PMMICL,
PMMICR, PMADL, PMADR, PMDAL, PMDAR, PMPLL, PMLOOPL, PMLOOPR, PMAINL1, PMAINR1,
PMAINL2, PMAINR2, PMAINL3, PMAINR3, PMAINL4, PMAINR4, PMLO1, PMRO1, PMLO2, PMRO2,
PMLO2S, PMRO2S, PMLO3, PMRO3, PMSRA, PMSRB, PMPCM, PMSAD) should be “0” or the PDN pin
should be “L”. DVDD should not be powered OFF while AVDD, PVDD, SAVDD, TVDD2 or TVDD3 is
powered ON. When only DVDD is OFF, the current of 10mA to 100mA around may occur.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0666-E-02
2010/06
-7-
[AK4671]
ANALOG CHARACTERISTICS (CODEC)
(Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=3.3V; VSS1=VSS2=VSS3=VSS4=0V;
Signal Frequency=1kHz; 16bit Data; fs=44.1kHz, BICK=64fs; Measurement frequency=20Hz ∼ 20kHz; unless
otherwise specified)
Parameter
min
typ
max
Units
MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins; PMAINL1/R1/L2/R2/L3/R3/L4/R4 bits = “0”
Input Resistance
MGNL/R0 bit = “0”
28
42
56
kΩ
MGNL/R0 bit = “1”
20
30
40
kΩ
Gain (Note 10)
Max (MGNL/R3-0 bits = “FH”)
+30
dB
Min (MGNL/R3-0 bits = “1H”)
dB
−12
MIC Power Supply: MPWR pin
Output Voltage (Note 11)
2.47
2.64
2.81
V
Load Resistance
0.5
kΩ
Load Capacitance
30
pF
MIC Detection: MDT pin
0.247
0.165
mV
Comparator Voltage Level (Note 12)
750
250
500
Internal pull down Resistance
kΩ
Stereo ADC Analog Input Characteristics:
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins → Stereo ADC → IVOL, IVOL=0dB, ALC=OFF
Resolution
16
Bits
(Note 14)
0.150
0.176
0.203
Vpp
Input Voltage (Note 13)
1.68
1.98
2.28
Vpp
(Note 15)
(Note 14)
72
82
dB
S/(N+D) (−1dBFS)
87
dB
(Note 15)
(Note 14)
75
85
dB
D-Range (−60dBFS, A-weighted)
95
dB
(Note 15)
(Note 14)
75
85
dB
S/N (A-weighted)
95
dB
(Note 15)
(Note 14)
75
90
dB
Interchannel Isolation
100
dB
(Note 15)
(Note 14)
0.1
0.8
dB
Interchannel Gain Mismatch
0.1
0.8
dB
(Note 15)
Note 10. In case of full-differential input, MGAIN=0dB (min) and AVDD=2.4V (min).
Note 11. Output voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ).
Note 12. Comparator Voltage Level is proportional to AVDD voltage. Vth = 0.05 x AVDD(min), 0.075 x AVDD(max).
Note 13. Input voltage is proportional to AVDD voltage. Vin = 0.053 x AVDD (typ)@MGNL3-0=MGNR3-0 bits =
“CH” (+21dB), Vin = 0.6 x AVDD(typ)@MGNL3-0=MGNR3-0 bits = “5H” (0dB).
Note 14. MGNL3-0=MGNR3-0 bits = “CH” (+21dB).
Note 15. MGNL3-0=MGNR3-0 bits = “5H” (0dB).
MS0666-E-02
2010/06
-8-
[AK4671]
Parameter
min
typ
max
Units
Stereo DAC Characteristics:
Resolution
16
Bits
Stereo Line Output Characteristics:
Stereo DAC → LOUT1/ROUT1/LOUT3/ROUT3 pins, ALC=OFF, IVOL=0dB, OVOL=0dB, L1VL=L3VL=0dB,
RCV bit = “0”, RL=10kΩ; unless otherwise specified.
Output Voltage (Note 16)
1.78
1.98
2.18
Vpp
S/(N+D) (0dBFS)
75
85
dB
S/N (A-weighted)
82
92
dB
Interchannel Isolation
85
100
dB
Interchannel Gain Mismatch
0.1
0.8
dB
Load Resistance
10
kΩ
Load Capacitance
30
pF
Mono Receiver-Amp Output Characteristics:
Stereo DAC → RCP/RCN pins, ALC=OFF, IVOL=0dB, OVOL=0dB, L1VL=0dB, RCV bit = “1”, RL=32Ω, BTL;
unless otherwise specified.
Output Voltage (Note 17)
1.76
1.96
2.16
Vpp
−6dBFS, RL=32Ω (Po=15mW)
2.77
Vpp
−3dBFS, RL=32Ω (Po=30mW)
S/(N+D)
40
60
dB
−6dBFS, RL=32Ω (Po=15mW)
20
dB
−3dBFS, RL=32Ω (Po=30mW)
S/N (A-weighted)
82
92
dB
Load Resistance
32
Ω
Load Capacitance (Note 18)
30
pF
Headphone-Amp Characteristics: DAC → LOUT2/ROUT2 pins, ALC=OFF, IVOL=0dB, OVOL=0dB, HPG=0dB,
RL=16Ω
Output Voltage (Note 19)
0.89
0.99
1.09
Vpp
−6dBFS (Po=7.6mW)
0dBFS (Po=30mW)
1.98
Vpp
S/(N+D)
40
60
dB
−6dBFS (Po=7.6mW)
0dBFS (Po=30mW)
40
dB
S/N (A-weighted)
80
90
dB
Interchannel Isolation
65
75
dB
Interchannel Gain Mismatch
0.1
0.8
dB
Load Resistance
16
Ω
C1 in Figure 2
30
pF
Load Capacitance
300
pF
C2 in Figure 2
Note 16. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
Note 17. Output voltage is proportional to AVDD voltage. Vout = (RCP) − (RCN) = 0.59 x AVDD (typ)@−6dBFS.
Note 18. Load Capacitance for VSS1.
Note 19. Output voltage is proportional to AVDD voltage. Vout = 0.3 x AVDD (typ)@−6dBFS.
MS0666-E-02
2010/06
-9-
[AK4671]
HP-Amp
LOUT2 pin
ROUT2 pin
C1
Measurement Point
100μ
F
0.22μF
C2
16Ω
10Ω
Figure 2. Headphone-Amp output circuit
Parameter
min
typ
max
Mono Line Output Characteristics: Stereo DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, OVOL=0dB,
L3VL=0dB, LODIF bit = “1”, RL=10kΩ for each pin (Full-differential)
Output Voltage (Note 20)
3.52
3.96
4.36
S/(N+D) (0dBFS)
75
85
S/N (A-weighted)
85
95
Load Resistance (LOP/LON pins, respectively)
10
Load Capacitance (LOP/LON pins, respectively)
30
(Note 21)
Single-ended Line Input: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins;
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
Maximum Input Voltage (Note 22)
1.98
Gain
InputÆLOUT1/ROUT1/LOUT2/ROUT2/LOUT3/ROUT3 (LODIF=RCV bits = “0”)
0
+1
−1
Input Æ RCP/RCN/LOP/LON (LODIF=RCV bits = “1”)
+6
Full-differential Line Input: IN1+/−, IN2+/−, IN3+/−, IN4+/− pins;
(MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
Maximum Input Voltage (Note 23)
1.98
Gain
InputÆLOUT1/ROUT1/LOUT2/ROUT2/LOUT3/ROUT3 (LODIF=RCV bits = “0”)
0
+1
−1
Input Æ RCP/RCN/LOP/LON (LODIF=RCV bits = “1”, Note 24)
+6
Power Supply Current:
Power Up (PDN pin = “H”, All Circuits Power-up)
(Note 25)
21
AVDD+PVDD+DVDD
23
30
(Note 26)
+TVDD2+TVDD3+SAVDD
8
12
(Note 27)
Power Down (PDN pin = “L”) (Note 28)
AVDD+PVDD+DVDD
1
30
+TVDD2+TVDD3+SAVDD
Units
Vpp
dB
dB
kΩ
pF
Vpp
dB
dB
Vpp
dB
dB
mA
mA
mA
μA
Note 20. Output voltage is proportional to AVDD voltage. Vout = (LOP) − (LON) = 1.2 x AVDD (typ).
Note 21. Load Capacitance for VSS1.
Note 22. Maximum Input voltage which analog output does not clip is proportional to AVDD voltage. Vin = 0.6 x AVDD
(typ).
Note 23. Maximum Input voltage which analog output does not clip is proportional to AVDD voltage. Vin = (IN4+) −
(IN4−) = 0.6 x AVDD (typ).
Note 24. Vout = (RCP) − (RCN) at RCV bit = “1”, Vout = (LOP) − (LON) at LODIF bit = “1”.
Note 25. EXT Slave Mode and LP bit = “0”, fs=44.1kHz, PMMICL = PMMICR = PMADL = PMADR = PMDAL =
PMDAR = PMLO1 = PMRO1 = PMLO2 = PMRO2 = PMLO2S = PMRO2S = PMLO3 = PMRO3 =PMSAD =
MS0666-E-02
2010/06
- 10 -
[AK4671]
PMVCM = MUTEN bits = “1”, PMPLL = MCKO = PMMP = M/S = PMSRA = PMSRB = PMPCM bits = “0”.
AVDD=13.2mA (typ), PVDD=0mA (typ), DVDD=6.7mA (typ), TVDD2=0mA (typ), TVDD3=0mA (typ),
SAVDD=0.8mA (typ).
Note 26. PLL Master Mode and LP bit = “0”, fs=44.1kHz, PMADL = PMMICL= PMMICR= PMADR = PMDAL =
PMDAR = PMLO1 = PMRO1 = PMLO2 = PMRO2 = PMLO2S = PMRO2S = PMLO3 = PMRO3 =PMSAD =
PMVCM = PMPLL = M/S = PMMP = MUTEN bits = “1”, MCKO = PMSRA = PMSRB = PMPCM bits = “0”,
PLL Reference Clock = MCKI = 11.2896MHz.
AVDD=14.7mA (typ), PVDD=0mA (typ), DVDD=7.0mA (typ), TVDD2=0mA (typ), TVDD3=0mA (typ),
SAVDD=0.8mA (typ).
Note 27. In case of LP bit = “1”, fs=8kHz, EXT Slave Mode and PMVCM = PMMP = PMMICL = PMADL = PMDAR =
RCV = PMLO1 = PMRO1 = PMSRA = PMSRB = PMPCM bits = “1”.
AVDD=5.2mA (typ), PVDD=0.6mA (typ), DVDD=2.2mA (typ), TVDD2=0mA (typ), TVDD3=0mA (typ),
SAVDD=0mA (typ).
Note 28. All digital input pins are fixed to each supply pin (DVDD, TVDD2 or TVDD3) or VSS4.
SRC CHARACTERISTICS
(Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=3.3V; VSS1=VSS2=VSS3=VSS4=0V;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 3.4kHz; unless otherwise specified)
Parameter
Symbol
min
typ
max
SRC Characteristics (Down Sampling: SRC-A): SDTI Æ SRC-A Æ SDTOA/SDTOB
Resolution
16
Input Sample Rate
FSI (fs)
8
48
Output Sample Rate
FSO (fs2)
8
THD+N (Input = 1kHz, −1dBFS, Note 29)
FSO/FSI = 8kHz/44.1kHz
−94
Dynamic Range (Input = 1kHz, −60dBFS, Note 29)
FSO/FSI = 8kHz/44.1kHz
97
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
1
SRC Characteristics (Up Sampling: SRC-B): SDTIA/SDTIB Æ SRC-B Æ SDTO
Resolution
16
Input Sample Rate
FSI (fs2)
8
Output Sample Rate
FSO (fs)
8
48
THD+N (Input = 1kHz, −1dBFS, Note 29)
FSO/FSI = 44.1kHz/8kHz
−95
Dynamic Range (Input = 1kHz, −60dBFS, Note 29)
FSO/FSI = 44.1kHz/8kHz
100
Ratio between Input and Output Sample Rate
FSO/FSI
1
6
Units
Bits
kHz
kHz
dB
dB
Bits
kHz
kHz
dB
dB
-
Note 29. Measured by Audio Precision System Two Cascade.
Note 30. fs is the sampling frequency for Stereo CODEC. fs2 is for PCM I/F.
MS0666-E-02
2010/06
- 11 -
[AK4671]
ANALOG CHARACTERISTICS (10bit SAR ADC)
(Ta=25°C; AVDD=PVDD=SAVDD=DVDD =TVDD2 =TVDD3=3.3V; VSS1=VSS2=VSS3=VSS4=0V; unless
otherwise specified)
Parameter
min
typ
max
Units
10bit SAR ADC Characteristics
Resolution
10
Bits
No Missing Codes
9
10
Bits
Integral Linearity Error
LSB
±2
DNL
LSB
±1
Analog Input Voltage Range
0
SAVDD
V
Offset Error
LSB
±3
Gain Error
LSB
±2
Accuracy (Note 31)
%
±1
Note 31. Accuracy is the difference between the output code when 1.1V is input to SAIN1, SAIN2 or SAIN3 pin and the
“ideal” code at 1.1V.
FILTER CHARACTERISTICS (CODEC)
(Ta=25°C; AVDD=PVDD =SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2 =TVDD3=1.6 ∼ 3.6V; fs=44.1kHz; Programmable
Filter=OFF)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband (Note 32)
PB
0
17.3
kHz
±0.16dB
19.4
kHz
−0.66dB
19.9
kHz
−1.1dB
22.1
kHz
−6.9dB
Stopband
SB
25.9
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
69
dB
Group Delay (Note 33)
GD
19
1/fs
Group Delay Distortion
0
ΔGD
μs
DAC Digital Filter (LPF):
Passband (Note 32)
PB
0
17.4
kHz
±0.1dB
20.0
kHz
−1.0dB
21.1
kHz
−3.0dB
Stopband
SB
25.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 33)
GD
19
1/fs
DAC Digital Filter (LPF) + SCF:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±1.4
Note 32. The passband and stopband frequencies scale with fs (system sampling rate).
For example, DAC is PB=0.454 x fs (@−0.7dB). Each response refers to that of 1kHz.
Note 33. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data of both channels from the input register to the output register of the ADC.
For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of
analog signal.
MS0666-E-02
2010/06
- 12 -
[AK4671]
FILTER CHARACTERISTICS (SRC)
(Ta=25°C; AVDD=PVDD = SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2 =TVDD3=1.6 ∼ 3.6V; fs2=8kHz; Programmable
Filter=OFF)
Parameter
Symbol
min
typ
max
Units
Down Sampling (SRC-A): fs=8kHz
Passband
PB
0
3.0
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
5
ms
Down Sampling (SRC-A): fs=11.025kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
4
ms
Down Sampling (SRC-A): fs=12kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
4
ms
Down Sampling (SRC-A): fs=16kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
3
ms
Down Sampling (SRC-A): fs=22.05kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
3
ms
Down Sampling (SRC-A): fs=24kHz
Passband
PB
0
3.1
kHz
±0.15dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.15
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
3
ms
Note 34. The calculated delay time caused by digital filtering. This time is from setting the 16-bit data from the input
register to the output register.
MS0666-E-02
2010/06
- 13 -
[AK4671]
Parameter
Symbol
min
typ
max
Units
Down Sampling (SRC-A): fs=32kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
3
ms
Down Sampling (SRC-A): fs=44.1kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
3
ms
Down Sampling (SRC-A): fs=48kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
69
dB
Group Delay (Note 34)
GD
3
ms
Note 34. The calculated delay time caused by digital filtering. This time is from setting the 16-bit data from the input
register to the output register.
MS0666-E-02
2010/06
- 14 -
[AK4671]
Parameter
Symbol
min
typ
max
Units
Up Sampling (SRC-B): fs=8kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 34)
GD
2
ms
Up Sampling (SRC-B): fs=11.025kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 34)
GD
2
ms
Up Sampling (SRC-B): fs=12kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 34)
GD
2
ms
Up Sampling (SRC-B): fs=16kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 34)
GD
2
ms
Up Sampling (SRC-B): fs=22.05kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 34)
GD
2
ms
Up Sampling (SRC-B): fs=24kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 34)
GD
2
ms
Note 34. The calculated delay time caused by digital filtering. This time is from setting the 16-bit data from the input
register to the output register.
MS0666-E-02
2010/06
- 15 -
[AK4671]
Parameter
Symbol
min
typ
max
Units
Up Sampling (SRC-B): fs=32kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 34)
GD
2
ms
Up Sampling (SRC-B): fs=44.1kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 34)
GD
2
ms
Up Sampling (SRC-B): fs=48kHz
Passband
PB
0
3.1
kHz
±0.1dB
Stopband
SB
4.7
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
68
dB
Group Delay (Note 34)
GD
2
ms
Note 34. The calculated delay time caused by digital filtering. This time is from setting the 16-bit data from the input
register to the output register.
MS0666-E-02
2010/06
- 16 -
[AK4671]
DC CHARACTERISTICS
(Ta=25°C; AVDD=PVDD =SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2 =TVDD3=1.6 ∼ 3.6V)
Parameter
Symbol
min
Typ
High-Level Input Voltage 1
2.2V≤DVDD≤3.6V
VIH1
70%DVDD
(Note 35)
1.6V≤DVDD<2.2V
VIH1
80%DVDD
Low-Level Input Voltage 1
2.2V≤DVDD≤3.6V
VIL1
(Note 35)
1.6V≤DVDD<2.2V
VIL1
High-Level Input Voltage 2
2.2V≤TVDD2≤3.6V
VIH2
70%TVDD2
(Note 36)
1.6V≤TVDD2<2.2V
VIH2
80%TVDD2
Low-Level Input Voltage 2
2.2V≤TVDD2≤3.6V
VIL2
(Note 36)
1.6V≤TVDD2<2.2V
VIL2
High-Level Input Voltage 3
2.2V≤TVDD3≤3.6V
VIH3
70%TVDD3
(Note 37)
1.6V≤TVDD3<2.2V
VIH3
80%TVDD3
Low-Level Input Voltage 3
2.2V≤TVDD3≤3.6V
VIL3
(Note 37)
1.6V≤TVDD3<2.2V
VIL3
High-Level Output Voltage
(Note 38) (Iout=−200μA) VOH1
DVDD−0.2
VOH2
(Note 39) (Iout=−200μA)
TVDD2−0.2
(Note 40) (Iout=−200μA) VOH3
TVDD3−0.2
Low-Level Output Voltage
(Except SDA pin: Iout=200μA) VOL1
(SDA pin, 2.0V≤DVDD≤3.6V: Iout=3mA) VOL2
(SDA pin, 1.6V≤DVDD<2.0V: Iout=3mA) VOL2
Input Leakage Current
(Note 41)
Iind
(Note 42)
Iina
-
max
30%DVDD
20%DVDD
30%TVDD2
20%TVDD2
30%TVDD3
20%TVDD3
Units
V
V
V
V
V
V
V
V
V
V
V
V
-
V
V
V
0.2
0.4
20%DVDD
V
V
V
±2
±2
μA
μA
Note 35. CSN/CAD0, CCLK/SCL, CDTI/SDA, I2C, PDN, BICK, LRCK, SDTI, MCKI pins.
Note 36. BICKA, SYNCA, SDTIA pins.
Note 37. BICKB, SYNCB, SDTIB pins.
Note 38. MCKO, BICK, LRCK, SDTO, CDTO, GPO1, GPO2 pins.
Note 39. BICKA, SYNCA, SDTOA pins.
Note 40. BICKB, SYNCB, SDTOB pins.
Note 41. SYNCB, BICKB, SDTIB, SDTI, LRCK, MCKI, BICK, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTIA,BICKA,
SYNCA pins.
I/O pins (SYNCB, BICKB, LRCK, BICK, SDA, BICKA, SYNCA) are at the time of Input state.
Note 42. SAIN1, SAIN2, SAIN3 pins.
MS0666-E-02
2010/06
- 17 -
[AK4671]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=PVDD =SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2 =TVDD3=1.6 ∼ 3.6V; CL=20pF (except SDA pin) or
400pF (SDA pin); unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.256
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
33
%
LRCK Output Timing
Frequency
fs
8
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK
ns
Except DSP Mode: Duty Cycle
Duty
50
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
ns
BCKO bit = “1”
tBCK
1/(64fs)
ns
Duty Cycle
dBCK
50
%
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
MCKO Output Timing
Frequency
fMCK
0.256
12.288
MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
33
%
LRCK Input Timing
Frequency
fs
8
48
kHz
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
1/fs − tBCK
ns
Except DSP Mode: Duty Cycle
Duty
45
55
%
BICK Input Timing
Period
tBCK
1/(64fs)
1/(32fs)
ns
Pulse Width Low
tBCKL
0.4 x tBCK
ns
Pulse Width High
tBCKH
0.4 x tBCK
ns
MS0666-E-02
2010/06
- 18 -
[AK4671]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
384fs
fCLK
512fs
fCLK
768fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs/384fs
fs
512fs/768fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
384fs
fCLK
512fs
fCLK
768fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS0666-E-02
min
typ
max
Units
8
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
1/(64fs)
130
130
-
1/(32fs)
-
ns
ns
ns
8
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
2.048
3.072
4.096
6.144
8.192
0.4/fCLK
0.4/fCLK
-
12.288
18.432
13.312
19.968
13.312
-
MHz
MHz
MHz
MHz
MHz
ns
ns
8
8
8
tBCK−60
45
-
48
26
13
1/fs − tBCK
55
kHz
kHz
kHz
ns
%
312.5
130
130
-
-
ns
ns
ns
2.048
3.072
4.096
6.144
8.192
0.4/fCLK
0.4/fCLK
-
12.288
18.432
13.312
19.968
13.312
-
MHz
MHz
MHz
MHz
MHz
ns
ns
8
-
tBCK
50
48
-
kHz
ns
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2010/06
- 19 -
[AK4671]
Parameter
Symbol
Audio Interface Timing (DSP Mode)
Master Mode
tDBF
LRCK “↑” to BICK “↑” (Note 43)
tDBF
LRCK “↑” to BICK “↓” (Note 44)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK “↑” to BICK “↑” (Note 43)
tLRB
LRCK “↑” to BICK “↓” (Note 44)
tBLR
BICK “↑” to LRCK “↑” (Note 43)
tBLR
BICK “↓” to LRCK “↑” (Note 44)
tBSD
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Audio Interface Timing (Right/Left justified & I2S)
Master Mode
tMBLR
BICK “↓” to LRCK Edge (Note 45)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK Edge to BICK “↑” (Note 45)
tBLR
BICK “↑” to LRCK Edge (Note 45)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
min
typ
max
Units
0.5 x tBCK − 40
0.5 x tBCK − 40
−70
−70
50
50
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK + 40
70
70
-
ns
ns
ns
ns
ns
ns
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
50
50
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
−40
−70
-
40
70
ns
ns
−70
50
50
-
70
-
ns
ns
ns
50
50
-
-
80
ns
ns
ns
50
50
-
80
-
ns
ns
ns
Note 43. MSBS, BCKP bits = “00” or “11”.
Note 44. MSBS, BCKP bits = “01” or “10”.
Note 45. BICK rising edge must not occur at the same time as LRCK edge.
MS0666-E-02
2010/06
- 20 -
[AK4671]
Parameter
Symbol
min
PCM Interface Timing (BICKA, SYNCA, SDTIA, SDTOA pins; Slave Mode):
SYNCA Timing
Frequency
fs2
Serial Interface Timing at Short/long Frame Sync
BICKA Frequency
fBCK2
128
BICKA Period
tBCK2
488
BICKA Pulse Width Low
tBCKL2
200
Pulse Width High
tBCKH2
200
tSYB2
50
SYNCA Edge to BICKA “↓” (Note 46)
tSYB2
50
SYNCA Edge to BICKA “↑” (Note 47)
tBSY2
50
BICKA “↓” to SYNCA Edge (Note 46)
tBSY2
50
BICKA “↑” to SYNCA Edge (Note 47)
SYNCA to SDTOA (MSB) (Except Short Frame)
tSYD2
tBSD2
BICKA “↑” to SDTOA (BCKPA bit = “0”)
tBSD2
BICKA “↓” to SDTOA (BCKPA bit = “1”)
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDS2
50
SYNCA Pulse Width Low
tSYL2
0.8 x tBCK2
Pulse Width High
tSYH2
0.8 x tBCK2
Serial Interface Timing at MSB justified and I2S
BICKA Frequency
fBCK2
256
BICKA Period
tBCK2
488
BICKA Pulse Width Low
tBCKL2
200
Pulse Width High
tBCKH2
200
tSYB2
50
SYNCA Edge to BICKA “↑”
tBSY2
50
BICKA “↑” to SYNCA Edge
SYNCA to SDTOA (MSB) (Except I2S mode)
tSYD2
tBSD2
BICKA “↓” to SDTOA
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDS2
50
SYNCA Duty Cycle
dSYC2
45
typ
max
Units
8
-
kHz
-
2048
80
80
80
-
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
2048
80
80
55
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Note 46. MSBSA, BCKPA bits = “00” or “11”.
Note 47. MSBSA, BCKPA bits = “01” or “10”.
MS0666-E-02
2010/06
- 21 -
[AK4671]
Parameter
Symbol
min
PCM Interface Timing (BICKA, SYNCA, SDTIA, SDTOA pins; Master Mode):
SYNCA Timing
Frequency
fs2
BICKA Timing
Period (BCKO2 bit = “0”)
tBCK2
(BCKO2 bit = “1”)
tBCK2
Duty Cycle
dBCK2
Serial Interface Timing at Short/long Frame Sync
0.5 x tBCK2 − 40
tSYB2
SYNCA Edge to BICKA “↓” (Note 46)
0.5 x tBCK2 − 40
tSYB2
SYNCA Edge to BICKA “↑” (Note 47)
tBSD2
BICKA “↑” to SDTOA (BCKPA bit = “0”)
−70
tBSD2
BICKA “↓” to SDTOA (BCKPA bit = “1”)
−70
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDS2
50
SYNCA Pulse Width High
tSYH2
Serial Interface Timing at MSB justified and I2S
tMBSY2
BICKA “↓” to SYNCA Edge
−40
SYNCA to SDTOA (MSB) (Except I2S mode)
tSYD2
−70
tBSD2
BICKA “↓” to SDTOA
−70
SDTIA Hold Time
tSDH2
50
SDTIA Setup Time
tSDS2
50
SYNCA Duty Cycle
dSYC2
-
typ
max
Units
8
-
kHz
1/(16fs2)
1/(32fs2)
50
-
ns
ns
%
0.5 x tBCK2
0.5 x tBCK2 + 40
0.5 x tBCK2
0.5 x tBCK2 + 40
tBCK2
70
70
-
ns
ns
ns
ns
ns
ns
ns
50
40
70
70
-
ns
ns
ns
ns
ns
%
Note 46. MSBSA, BCKPA bits = “00” or “11”.
Note 47. MSBSA, BCKPA bits = “01” or “10”.
MS0666-E-02
2010/06
- 22 -
[AK4671]
Parameter
Symbol
min
PCM Interface Timing (BICKB, SYNCB, SDTIB, SDTOB pins; Slave Mode):
SYNCB Timing
Frequency
fs2
Serial Interface Timing at Short/long Frame Sync
BICKB Frequency
fBCK3
128
BICKB Period
tBCK3
488
BICKB Pulse Width Low
tBCKL3
200
Pulse Width High
tBCKH3
200
tSYB3
50
SYNCB Edge to BICKB “↓” (Note 48)
tSYB3
50
SYNCB Edge to BICKB “↑” (Note 49)
tBSY3
50
BICKB “↓” to SYNCB Edge (Note 48)
tBSY3
50
BICKB “↑” to SYNCB Edge (Note 49)
SYNCB to SDTOB (MSB) (Except Short Frame)
tSYD3
tBSD3
BICKB “↑” to SDTOB (BCKPB bit = “0”)
tBSD3
BICKB “↓” to SDTOB (BCKPB bit = “1”)
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDS3
50
SYNCB Pulse Width Low
tSYL3
0.8 x tBCK3
Pulse Width High
tSYH3
0.8 x tBCK3
Serial Interface Timing at MSB justified and I2S
BICKB Frequency
fBCK3
256
BICKB Period
tBCK3
488
BICKB Pulse Width Low
tBCKL3
200
Pulse Width High
tBCKH3
200
tSYB3
50
SYNCB Edge to BICKB “↑”
tBSY3
50
BICKB “↑” to SYNCB Edge
SYNCB to SDTOB (MSB) (Except I2S mode)
tSYD3
tBSD3
BICKB “↓” to SDTOB
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDS3
50
SYNCB Duty Cycle
dSYC3
45
typ
max
Units
8
-
kHz
-
2048
80
80
80
-
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
2048
80
80
55
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Note 48. MSBSB, BCKPB bits = “00” or “11”.
Note 49. MSBSB, BCKPB bits = “01” or “10”.
MS0666-E-02
2010/06
- 23 -
[AK4671]
Parameter
Symbol
min
PCM Interface Timing (BICKB, SYNCB, SDTIB, SDTOB pins; Master Mode):
SYNCB Timing
Frequency
fs2
BICKB Timing
Period (BCKO2 bit = “0”)
tBCK3
(BCKO2 bit = “1”)
tBCK3
Duty Cycle
dBCK3
Serial Interface Timing at Short/long Frame Sync
0.5 x tBCK3 − 40
tSYB3
SYNCB Edge to BICKB “↓” (Note 48)
0.5 x tBCK3 − 40
tSYB3
SYNCB Edge to BICKB “↑” (Note 49)
tBSD3
BICKB “↑” to SDTOB (BCKPB bit = “0”)
−70
tBSD3
BICKB “↓” to SDTOB (BCKPB bit = “1”)
−70
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDS3
50
SYNCB Pulse Width High
tSYH3
Serial Interface Timing at MSB justified and I2S
tMBSY3
BICKB “↓” to SYNCB Edge
−40
SYNCB to SDTOB (MSB) (Except I2S mode)
tSYD3
−70
tBSD3
BICKB “↓” to SDTOB
−70
SDTIB Hold Time
tSDH3
50
SDTIB Setup Time
tSDS3
50
SYNCB Duty Cycle
dSYC3
-
typ
max
Units
8
-
kHz
1/(16fs2)
1/(32fs2)
50
-
ns
ns
%
0.5 x tBCK3
0.5 x tBCK3 + 40
0.5 x tBCK3
0.5 x tBCK3 + 40
tBCK3
70
70
-
ns
ns
ns
ns
ns
ns
ns
50
40
70
70
-
ns
ns
ns
ns
ns
%
Note 48. MSBSB, BCKPB bits = “00” or “11”.
Note 49. MSBSB, BCKPB bits = “01” or “10”.
MS0666-E-02
2010/06
- 24 -
[AK4671]
Parameter
Control Interface Timing (4-wire Serial mode)
CCLK Period (Note 51)
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN Edge to CCLK “↑” (Note 52)
CCLK “↑” to CSN Edge (Note 52)
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I2C Bus mode): (Note 50)
SCL Clock Frequency (Note 53)
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 54)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 55)
PMADL or PMADR “↑” to SDTO valid (Note 56)
PMSRA “↑” to SDTOA valid (Note 57)
PMSRB “↑” to SDTO valid (Note 58)
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
50
50
-
-
33000
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
30
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
tPDV
tPDV2
tPDV3
150
-
1059
21
135
-
ns
1/fs
1/fs2
1/fs
Note 50. I2C-bus is a trademark of NXP B.V.
Note 51. CCLK should be input succeedingly until 10bit data of SAR ADC is read out at 4-wire serial mode (Figure 97).
Note 52. CCLK rising edge must not occur at the same time as CSN edge.
Note 53. In case that SAR ADC data is read out via I2C bus, SCL should be input succeedingly corresponding 2 byte data
including ACK (Figure 104).
Note 54. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 55. The AK4671 can be reset by bringing PDN pin = “L” to “H” only upon power up.
Note 56. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1” at PMSRB bit = “1”.
Note 57. The signal path is SDTI → SRC-A → SDTOA and PLLBT is locked.
Note 58. The signal path is SDTIA → SRC-B → SDTO.
MS0666-E-02
2010/06
- 25 -
[AK4671]
■ Timing Diagram
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%DVDD
BICK
tBCKH
tBCKL
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
1/fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 3. Clock Timing (PLL/EXT Master mode)
Note 59. MCKO is not available at EXT Master mode.
tLRCKH
LRCK
50%DVDD
tDBF
BICK
(BCKP = "0")
50%DVDD
BICK
(BCKP = "1")
50%DVDD
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH1
SDTI
VIL1
Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”)
MS0666-E-02
2010/06
- 26 -
[AK4671]
tLRCKH
LRCK
50%DVDD
tDBF
BICK
(BCKP = "1")
50%DVDD
BICK
(BCKP = "0")
50%DVDD
tBSD
SDTO
50%DVDD
MSB
tSDS
tSDH
VIH1
SDTI
VIL1
Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”)
50%DVDD
LRCK
tMBLR
BICK
50%DVDD
tLRD
tBSD
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode)
MS0666-E-02
2010/06
- 27 -
[AK4671]
1/fs
VIH1
LRCK
VIL1
tLRCKH
tBLR
tBCK
VIH1
BICK
(BCKP = "0")
VIL1
tBCKH
tBCKL
VIH1
BICK
(BCKP = "1")
VIL1
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “0”)
1/fs
VIH1
LRCK
VIL1
tLRCKH
tBLR
tBCK
VIH1
BICK
(BCKP = "1")
VIL1
tBCKH
tBCKL
VIH1
BICK
(BCKP = "0")
VIL1
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”)
MS0666-E-02
2010/06
- 28 -
[AK4671]
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
VIH1
LRCK
VIL1
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
VIH1
BICK
VIL1
tBCKH
tBCKL
1/fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 9. Clock Timing (PLL Slave mode; Except DSP mode)
tLRCKH
VIH1
LRCK
VIL1
tLRB
VIH1
BICK
VIL1
(BCKP = "0")
VIH1
BICK
(BCKP = "1")
VIL1
tBSD
SDTO
MSB
tSDS
50%DVDD
tSDH
VIH1
SDTI
MSB
VIL1
Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “0”)
MS0666-E-02
2010/06
- 29 -
[AK4671]
tLRCKH
VIH1
LRCK
VIL1
tLRB
VIH1
BICK
VIL1
(BCKP = "1")
VIH1
BICK
(BCKP = "0")
VIL1
tBSD
SDTO
50%DVDD
MSB
tSDS
tSDH
VIH1
SDTI
MSB
VIL1
Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS = “1”)
1/fCLK
VIH1
MCKI
VIL1
tCLKH
tCLKL
1/fs
VIH1
LRCK
VIL1
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH1
BICK
VIL1
tBCKH
tBCKL
Figure 12. Clock Timing (EXT Slave mode)
MS0666-E-02
2010/06
- 30 -
[AK4671]
VIH1
LRCK
VIL1
tLRB
tBLR
VIH1
BICK
VIL1
tBSD
tLRD
SDTO
50%DVDD
MSB
tSDH
tSDS
VIH1
SDTI
VIL1
Figure 13. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode)
1/fs2
VIH2
SYNCA
VIL2
tSYH2
tSYL2
dSYC2 = tSYH2 x fs2 x 100
tSYL2 x fs2 x 100
tBC K2 = 1/fBC K2
VIH 2
VIL2
BIC KA
tBC KH 2
tBC KL2
Figure 14. Clock Timing of PCM I/F A (Slave mode)
MS0666-E-02
2010/06
- 31 -
[AK4671]
VIH2
SYNCA
VIL2
tBSY2
tSYB2
VIH2
BICKA
VIL2
(BCKPA = “0”)
VIH2
BICKA
VIL2
(BCKPA = “1”)
tSYD2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 15. PCM I/F A Timing at short and long frame sync (Slave mode; MSBSA = “0”)
VIH2
SYNCA
VIL2
tBSY2
tSYB2
VIH2
BICKA
VIL2
(BCKPA = “1”)
VIH2
BICKA
(BCKPA = “0”)
VIL2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 16. PCM I/F A Timing at short and long frame sync (Slave mode; MSBSA = “1”)
MS0666-E-02
2010/06
- 32 -
[AK4671]
VIH2
SYNCA
VIL2
tBSY2
tSYB2
VIH2
BICKA
VIL2
tSYD2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 17. PCM I/F A Timing at MSB justified and I2S (Slave mode)
1/fs2
50%TVDD2
SYNCA
tSYH2
tSYL2
dSYC2 = tSYL2 x fs2 x 100
tBC K2 = 1/fBC K2
50% T VD D 2
BIC KA
tBC KH 2
tBC KL2
dBC K2 = tBC KL2 / tBC K2 x 100
Figure 18. Clock Timing of PCM I/F A (Master mode)
MS0666-E-02
2010/06
- 33 -
[AK4671]
SYNCA
50%TVDD2
tSYB2
BICKA
(BCKPA = “0”)
50%TVDD2
BICKA
50%TVDD2
(BCKPA = “1”)
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 19. PCM I/F A Timing at short and long frame sync (Master mode; MSBSA = “0”)
SYNCA
50%TVDD2
tSYB2
50%TVDD2
BICKA
(BCKPA = “1”)
50%TVDD2
BICKA
(BCKPA = “0”)
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 20. PCM I/F A Timing at short and long frame sync (Master mode; MSBSA = “1”)
MS0666-E-02
2010/06
- 34 -
[AK4671]
50%TVDD2
SYNCA
tMBSY2
50%TVDD2
BICKA
tSYD2
tBSD2
SDTOA
50%TVDD2
tSDS2
tSDH2
VIH2
SDTIA
VIL2
Figure 21. PCM I/F A Timing at MSB justified and I2S (Master mode)
1/fs2
VIH3
SYNCB
VIL3
tSYH3
tSYL3
dSYC3 = tSYH3 x fs2 x 100
tSYL3 x fs2 x 100
tBC K3 = 1/fBC K3
VIH 3
VIL3
BIC KB
tBC KH 3
tBC KL3
Figure 22. Clock Timing of PCM I/F B (Slave mode)
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[AK4671]
VIH3
SYNCB
VIL3
tBSY3
tSYB3
VIH3
BICKB
VIL3
(BCKPB = “0”)
VIH3
BICKB
VIL3
(BCKPB = “1”)
tSYD3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 23. PCM I/F B Timing at short and long frame sync (Slave mode; MSBSB = “0”)
VIH3
SYNCB
VIL3
tBSY3
tSYB3
VIH3
BICKB
VIL3
(BCKPB = “1”)
VIH3
BICKB
(BCKPB = “0”)
VIL3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 24. PCM I/F B Timing at short and long frame sync (Slave mode; MSBSB = “1”)
MS0666-E-02
2010/06
- 36 -
[AK4671]
VIH3
SYNCB
VIL3
tBSY3
tSYB3
VIH3
BICKB
VIL3
tSYD3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 25. PCM I/F B Timing at MSB justified and I2S (Slave mode)
1/fs2
50%TVDD3
SYNCB
tSYH3
tSYL3
dSYC3 = tSYL3 x fs2 x 100
tBC K3 = 1/fBC K3
50% T VD D 3
BIC KB
tBC KH 3
tBC KL3
dBC K3 = tBC KL3 / tBC K3 x 100
Figure 26. Clock Timing of PCM I/F B (Master mode)
MS0666-E-02
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[AK4671]
SYNCB
50%TVDD3
tSYB3
50%TVDD3
BICKB
(BCKPB = “0”)
50%TVDD3
BICKB
(BCKPB = “1”)
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 27. PCM I/F B Timing at short and long frame sync (Master mode; MSBSB = “0”)
SYNCB
50%TVDD3
tSYB3
50%TVDD3
BICKB
(BCKPB = “1”)
50%TVDD3
BICKB
(BCKPB = “0”)
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 28. PCM I/F B Timing at short and long frame sync (Master mode; MSBSB = “1”)
MS0666-E-02
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[AK4671]
50%TVDD3
SYNCB
tMBSY3
50%TVDD3
BICKB
tSYD3
tBSD3
SDTOB
50%TVDD3
tSDS3
tSDH3
VIH3
SDTIB
VIL3
Figure 29. PCM I/F B Timing at MSB justified and I2S (Master mode)
VIH1
CSN
VIL1
tCSH
tCCKL
tCSS
tCCKH
VIH1
CCLK
VIL1
tCCK
tCDH
tCDS
VIH1
CDTI
CDTO
C1
C0
R/W
VIL1
Hi-Z
Figure 30. WRITE Command Input Timing
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[AK4671]
tCSW
VIH1
CSN
VIL1
tCSH
tCSS
VIH1
CCLK
VIL1
VIH1
CDTI
D2
D1
D0
VIL1
Hi-Z
CDTO
Figure 31. WRITE Data Input Timing
VIH1
CSN
VIL1
VIH1
CCLK
VIL1
VIH1
CDTI
A1
A0
VIL1
tDCD
CDTO
Hi-Z
D7
D6
50%DVDD
Figure 32. READ Data Output Timing 1
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[AK4671]
tCSW
VIH1
CSN
VIL1
tCSH
VIH1
CCLK
VIL1
VIH1
CDTI
VIL1
tCCZ
CDTO
D2
D1
D0
Hi-Z
50%DVDD
Figure 33. READ Data Output Timing 2
VIH1
SDA
VIL1
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH1
SCL
VIL1
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
Start
tSU:STO
Stop
Figure 34. I2C Bus Mode Timing
MS0666-E-02
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[AK4671]
PMADL bit
or
PMADR bit
tPDV
SDTO
50%DVDD
Figure 35. Power Down & Reset Timing 1
tPD
PDN
VIL1
Figure 36. Power Down & Reset Timing 2
PMSRA bit
tPDV2
SDTOA
50%TVDD2
Figure 37. Power Down & Reset Timing 3
PMSRB bit
tPDV3
SDTO
50%DVDD
Figure 38. Power Down & Reset Timing 4
MS0666-E-02
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[AK4671]
OPERATION OVERVIEW
■ System Clock (Audio I/F)
There are the following five clock modes to interface with external devices. (Table 1 and Table 2)
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode (Note 60)
1
1
See Table 4
Figure 39
PLL Slave Mode 1
Figure 40
1
0
See Table 4
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
Figure 41
1
0
See Table 4
Figure 42
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
0
0
x
Figure 43
EXT Master Mode
0
1
x
Figure 44
Note 60. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
MCKO pin
L
Selected by
PS1-0 bits
L
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL3-0 bits
Selected by
PLL3-0 bits
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
L
GND
EXT Slave Mode
0
L
Selected by
FS1-0 bits
EXT Master Mode
0
L
Selected by
FS1-0 bits
BICK pin
Output
(Selected by
BCKO bit)
LRCK pin
Input
(≥ 32fs)
Input
(1fs)
Input
(Selected by
PLL3-0 bits)
Input
(≥ 32fs)
Output
(Selected by
BCKO bit)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Table 2. Clock pins state in Clock Mode
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4671 is power-down mode (PDN pin = “L”) and exits reset state, the AK4671 is slave mode. After exiting reset state,
the AK4671 goes to master mode by changing M/S bit = “1”.
When the AK4671 is used by master mode, LRCK and BICK pins are a Hi-Z state until M/S bit becomes “1”. LRCK and
BICK pins of the AK4671 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the
floating state.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Slave Mode
MS0666-E-02
(default)
2010/06
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[AK4671]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4671 is supplied to a stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. When AIN3 bit = “1”, the PLL is not
available.
1) Setting of PLL Mode
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input
Frequency
0
0
0
0
0
LRCK pin
1fs
2
0
0
1
0
BICK pin
32fs
3
0
0
1
1
BICK pin
64fs
4
5
6
7
8
12
13
14
15
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
Others
R and C of
VCOC pin
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
10n
10k
4.7n
10k
10n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
10k
4.7n
10k
10n
10k
10n
10k
220n
10k
220n
MCKI pin
11.2896MHz
MCKI pin
12.288MHz
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
19.2MHz
MCKI pin
13.5MHz
MCKI pin
27MHz
MCKI pin
13MHz
MCKI pin
26MHz
Others
N/A
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
PLL Lock
Time
(max)
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
(default)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
5
0
1
0
1
11.025kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
15
1
1
1
1
44.1kHz
(default)
Others
Others
N/A
(N/A: Not available)
Table 5. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
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[AK4671]
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-2 bits (Table 6).
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency Range
x
x
0
0
0
8kHz ≤ fs ≤ 12kHz
x
x
1
0
1
12kHz < fs ≤ 24kHz
x
x
x
2
1
(default)
24kHz < fs ≤ 48kHz
Others
Others
N/A
(x: Don’t care, N/A: Not available)
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pin at MCKO bit
is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, the MCKO pin changes to “L”
(Table 7).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
BICK pin
MCKO bit = “0”
MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
“L” Output
PLL Unlock (except above case)
“L” Output
Invalid
Invalid
PLL Lock
“L” Output
See Table 9
See Table 10
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
LRCK pin
“L” Output
Invalid
1fs Output
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ
“1”. After that, the clock selected by Table 9 is output from the MCKO pin when PLL is locked. ADC and DAC output
invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL and DACH
bits.
MCKO pin
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
“L” Output
Invalid
PLL Unlock
“L” Output
Invalid
PLL Lock
“L” Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
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[AK4671]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz)
is input to the MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO
output frequency is selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. The BICK output frequency
is selected between 32fs or 64fs, by BCKO bit (Table 10).
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
DSP or μP
AK4671
MCKI
256fs/128fs/64fs/32fs
MCKO
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 39. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BICK Output
Frequency
0
32fs
(default)
1
64fs
Table 10. BICK Output Frequency at Master Mode
BCKO bit
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[AK4671]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the
AK4671 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 4).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK does not
matter. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (Table 5).
In case that the CODEC is used without Audio I/F (like phone call), the CODEC can be operated by MCKI only. In this
case, BICK and LRCK can be stopped.
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
AK4671
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 40. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
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2010/06
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[AK4671]
b) PLL reference clock: BICK or LRCK pin
Sampling frequency corresponds to 8kHz to 48kHz by changing FS3-0 bits (Table 6).
AK4671
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 41. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4671
DSP or μP
MCKO
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 42. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1”,
PMDAL bit = “1” or PMDAR bit = “1”). If MCKI is not provided, the AK4671 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and
DAC should be in the power-down mode (PMADL=PMADR=PMDAL=PMDAR bits = “0”).
MS0666-E-02
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[AK4671]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4671 becomes EXT mode. Master clock is input from the MCKI pin, the internal PLL
circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate the
AK4671 are MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI)
should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is
selected by FS2-0 bits (Table 11).
In case that the CODEC is used without Audio I/F (like phone call), the CODEC can be operated by MCKI only. In this
case, BICK and LRCK can be stopped.
Mode
0
1
4
5
6
7
Others
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
0
256fs
8kHz ∼ 48kHz
x
0
0
1
1024fs
8kHz ∼ 13kHz
x
1
0
0
384fs
8kHz ∼ 48kHz
x
1
0
1
768fs
8kHz ∼ 26kHz
x
1
1
0
512fs
8kHz ∼ 26kHz
x
1
1
1
256fs
(default)
8kHz ∼ 48kHz
Others
N/A
N/A
(x: Don’t care, N/A: Not available)
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
FS3 bit
FS2 bit
FS1 bit
FS0 bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through
LOUT/ROUT pins at fs=8kHz is shown in Table 12.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs, 384fs
83dB
512fs, 768fs
93dB
1024fs
93dB
Table 12. Relationship between MCKI and S/N of LOUT1/ROUT1 pins
MCKI
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1”,
PMDAL bit = “1” or PMDAR bit = “1”). If MCKI is not provided, the AK4671 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and
DAC should be in the power-down mode (PMADL=PMADR=PMDAL=PMDAR bits = “0”).
AK4671
DSP or μP
MCKO
MCKI
BICK
LRCK
256fs, 384fs, 512fs,
768fs or 1024fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 43. EXT Slave Mode
MS0666-E-02
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[AK4671]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4671 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 384fs, 512fs, 768fs or
1024fs). The input frequency of MCKI is selected by FS2-0 bits (Table 13).
Mode
0
1
4
5
6
7
Others
MCKI Input
Sampling Frequency
Frequency
Range
x
0
0
0
256fs
8kHz ∼ 48kHz
x
0
0
1
1024fs
8kHz ∼ 13kHz
x
1
0
0
384fs
8kHz ∼ 48kHz
x
1
0
1
768fs
8kHz ∼ 26kHz
x
1
1
0
512fs
8kHz ∼ 26kHz
x
1
1
1
256fs
(default)
8kHz ∼ 48kHz
Others
N/A
N/A
(x: Don’t care, N/A: Not available)
Table 13. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
FS3 bit
FS2 bit
FS1 bit
FS0 bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be reduced by using higher frequency of the master clock. The S/N of the DAC output through
LOUT/ROUT pins at fs=8kHz is shown in Table 14.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs, 384fs
83dB
512fs, 768fs
93dB
1024fs
93dB
Table 14. Relationship between MCKI and S/N of LOUT1/ROUT1 pins
MCKI
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1”,
PMDAL bit = “1” or PMDAR bit = “1”). If MCKI is not provided, the AK4671 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and
DAC should be in the power-down mode (PMADL=PMADR=PMDAL=PMDAR bits = “0”).
AK4671
DSP or μP
MCKO
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
32fs or 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 44. EXT Master Mode
BICK Output
Frequency
0
32fs
(default)
1
64fs
Table 15. BICK Output Frequency at Master Mode
BCKO bit
MS0666-E-02
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[AK4671]
■ System Reset
When power-up, the AK4671 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAL
and PMDAR bits are “0”. The initialization cycle time is [email protected]=44.1kHz. During the initialization cycle, the
ADC digital data outputs of both channels are forced to a 2’s complement, “0”. The ADC output reflects the analog input
signal after the initialization cycle is complete. When PMDAL or PMDAR is “1”, the ADC does not require an
initialization cycle.
■ Audio Interface Format
Four types of data formats are available and can be selected by setting the DIF1-0 bits (Table 16). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the AK4671 in master mode, but must be input to the AK4671 in slave mode.
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO (ADC)
SDTI (DAC)
DSP Mode
DSP Mode
MSB justified
LSB justified
MSB justified
MSB justified
I2S compatible
I2S compatible
Table 16. Audio Interface Format
BICK
≥ 32fs
≥ 32fs
≥ 32fs
≥ 32fs
Figure
Table 17
Figure 49
Figure 50
Figure 51
(default)
In modes 1, 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge
(“↑”).
In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 17).
DIF1
0
DIF0
MSBS
BCKP
0
0
0
1
1
0
1
1
0
Audio Interface Format
MSB of SDTO is output by the rising edge (“↑”) of the
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by the falling edge (“↓”) of the
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next rising edge (“↑”) of the
falling edge (“↓”) of the first BICK after the rising edge
(“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next falling edge (“↓”) of the
rising edge (“↑”) of the first BICK after the rising edge
(“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
Table 17. Audio Interface Format in Mode 0
Figure
Figure 45
(default)
Figure 46
Figure 47
Figure 48
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0666-E-02
2010/06
- 51 -
[AK4671]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
47
48
49
50
26
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
2
1
0
15 14
1
0
2
1
0
Rch
Lch
SDTI(i)
2
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 45. Mode 0 Timing (BCKP = “0”, MSBS = “0”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
15 14
Rch
2
1
0
2
1
0
15 14
2
1
0
2
1
0
Rch
Lch
SDTI(i)
15 14
15 14
1/fs
15:MSB, 0:LSB
Figure 46. Mode 0 Timing (BCKP = “1”, MSBS = “0”)
MS0666-E-02
2010/06
- 52 -
[AK4671]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
26
27
26
29
30
31
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
46
34
47
48
49
50
26
27
26
62
63
30
31
BICK(64fs)
Lch
SDTO(o)
Rch
15 14
2
1
0
15 14
Lch
SDTI(i)
2
1
0
2
1
0
Rch
15 14
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 47. Mode 0 Timing (BCKP = “0”, MSBS = “1”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
2
9
10
11
12
13
14
15
16
17
24
18
25
29
0
BICK(32fs)
Lch
SDTO(o)
0
SDTI(i)
0
Rch
15 14
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Lch
15
1
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
Rch
15 14
0
15 14
14
2
15
16
17
18
30
31
15 14
32
33
34
46
47
48
49
50
62
63
BICK(64fs)
Lch
SDTO(o)
15 14
Rch
2
1
0
Lch
SDTI(i)
15 14
15 14
2
1
0
2
1
0
Rch
2
1
0
15 14
1/fs
15:MSB, 0:LSB
Figure 48. Mode 0 Timing (BCKP = “1”, MSBS = “1”)
MS0666-E-02
2010/06
- 53 -
[AK4671]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
1 0
15 14 13
15 14 13
15 14
Don't Care
1 0
1 0
Don't Care
15
15 14
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 49. Mode 1 Timing
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14 13
1 0
SDTI(i)
15 14 13
1 0
Don't Care
15 14 13
1 0
15 14 13
1 0
15
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 50. Mode 2 Timing
MS0666-E-02
2010/06
- 54 -
[AK4671]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
SDTI(i)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
2 1 0
SDTI(i)
15 14
2 1 0
Don't Care
15 14
2 1 0
15 14
2 1 0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 51. Mode 3 Timing
MS0666-E-02
2010/06
- 55 -
[AK4671]
■ MIC/LINE Input Selector
The AK4671 has input selector. When MDIF1, MDIF2, MDIF3 and MDIF4 bits are “0”, INL1-0 and INR1-0 bits select
LIN1/LIN2/LIN3/LIN4 and RIN1/RIN2/RIN3/RIN4, respectively. When MDIF1, MDIF2, MDIF3 and MDIF4 bits are
“1”, LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 pins become IN1+/−, IN2+/−, IN3+/− and IN4+/− pins,
respectively. In this case, full-differential input is available (Figure 53).
MDIF1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
MDIF2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
MDIF3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
0
0
MDIF4
INL1
INL0
INR1
INR0
Lch
Rch
0
0
0
0
0
LIN1
RIN1
0
0
0
0
1
LIN1
RIN2
0
0
0
1
0
LIN1
RIN3
0
0
0
1
1
LIN1
RIN4
0
0
1
0
0
LIN2
RIN1
0
0
1
0
1
LIN2
RIN2
0
0
1
1
0
LIN2
RIN3
0
0
1
1
1
LIN2
RIN4
0
1
0
0
0
LIN3
RIN1
0
1
0
0
1
LIN3
RIN2
0
1
0
1
0
LIN3
RIN3
0
1
0
1
1
LIN3
RIN4
0
1
1
0
0
LIN4
RIN1
0
1
1
0
1
LIN4
RIN2
0
1
1
1
0
LIN4
RIN3
0
1
1
1
1
LIN4
RIN4
1
0
0
1
1
LIN1
IN4+/−
1
0
1
1
1
LIN2
IN4+/−
1
1
0
1
1
LIN3
IN4+/−
0
1
0
0
0
RIN1
IN3+/−
0
1
0
0
1
RIN2
IN3+/−
0
1
0
1
1
RIN4
IN3+/−
1
1
0
1
1
IN3+/−
IN4+/−
0
0
0
0
1
LIN1
IN2+/−
0
1
0
0
1
LIN3
IN2+/−
0
1
1
0
1
LIN4
IN2+/−
0
1
0
0
1
IN3+/−
IN2+/−
0
0
0
0
1
RIN2
IN1+/−
0
0
0
1
0
RIN3
IN1+/−
0
0
0
1
1
RIN4
IN1+/−
1
0
0
1
1
IN1+/−
IN4+/−
0
0
0
0
1
IN1+/−
IN2+/−
Others
N/A
Table 18. MIC-Amp Input Signal (N/A: Not available)
MS0666-E-02
(default)
2010/06
- 56 -
[AK4671]
AK4671
INL1-0 bits
LIN1/IN1+ pin
ADC Lch
RIN1/IN1− pin
MDIF1 bit MIC-Amp Lch
MDIF3 bit
INR1-0 bits
LIN2/IN2+ pin
ADC Rch
RIN2/IN2− pin
MDIF2 bit MIC-Amp Rch
MDIF4 bit
LIN3/IN3+ pin
RIN3/IN3− pin
LIN4/IN4+ pin
PMLOOPR bit
PMLOOPL bit
PMAINR4 bit
PMAINL4 bit
PMAINR3 bit
PMAINL3 bit
PMAINR2 bit
PMAINL2 bit
PMAINR1 bit
PMAINL1 bit
RIN4/IN4− pin
Lineout
Figure 52. Mic/Line Input Selector
AK4671
MPWR pin
1k
MIC-Amp
IN1+ pin
IN1− pin
1k
Figure 53. Connection Example for Full-differential Mic Input (MDIF1/2/3/4 bits = “1”)
AK4671
MIC-Amp
IN1+ pin
IN1− pin
Figure 54. Connection Example for Full-differential Mic Input (MDIF1/2/3/4 bits = “1”)
MS0666-E-02
2010/06
- 57 -
[AK4671]
■ MIC Gain Amplifier
The AK4671 has a gain amplifier for microphone input. The gain of MIC-Amp Lch and Rch is independently selected by
the MGNL3-0 and MGNR3-0 bits (Table 19). The typical input impedance is 42kΩ(typ)@MGNL/R0 bits = “0” or
30kΩ(typ)@MGNL/R0 bits = “1”.
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MGNL3
MGNR3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MGNL2
MGNL1
MGNL0
Input Gain
MGNR2
MGNR1
MGNR0
0
0
0
N/A
0
0
1
−12dB
0
1
0
−9dB
0
1
1
−6dB
1
0
0
−3dB
1
0
1
0dB
1
1
0
+3dB
1
1
1
+6dB
0
0
0
+9dB
0
0
1
+12dB
0
1
0
+15dB
0
1
1
+18dB
1
0
0
+21dB
1
0
1
+24dB
1
1
0
+27dB
1
1
1
+30dB
Table 19. Mic Input Gain (N/A: Not available)
MS0666-E-02
Input Resistance
N/A
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
42kΩ
30kΩ
(default)
2010/06
- 58 -
[AK4671]
■ MIC Power
When PMMP bit = “1”, the MPWR pin supplies power for the microphone. This output voltage is typically 0.8 x AVDD
and the load resistance is minimum 0.5kΩ. In case of using two sets of stereo mic, the load resistance is minimum 2kΩ for
each channel. Any capacitor must not be connected directly to the MPWR pin (Figure 55).
PMMP bit
MPWR pin
0
Hi-Z
1
Output
Table 20. MIC Power
(default)
MIC Power
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
MPWR pin
Microphone
LIN1 pin
Microphone
RIN1 pin
Microphone
LIN2 pin
Microphone
RIN2 pin
Figure 55. MIC Block Circuit
MS0666-E-02
2010/06
- 59 -
[AK4671]
■ MIC Detection
The AK4671 has the detecting function of microphone. The external circuit is showed in Figure 56.
The followings show the example of external microphone detection sequence:
(1) PMMP bit should be set to “1” after CPU detects the jack insertion of microphone or headphone.
(2) The MPWR pin drives external microphone.
(3) The GPO2 pin (at GPOM2 bit = “1”) and DTMIC bit are set as Table 21. In case of Headset (with Mic), the input
voltage of MDT pin is higher than 0.075 x AVDD because of the relationship between the bias resistance at the
MPWR pin (typ. 2.2kΩ) and the microphone impedance. In case of Headphone (No Mic), the input voltage of MDT
pin is 0V because the pin of headphone jack connected to the MDT pin is assigned as ground.
Input Level of MDT pin
≥ 0.075 x AVDD
< 0.050 x AVDD
GPO2 pin
DTMIC bit
H
1
L
0
Table 21. Microphone Detection Result
MPWR
Result
Mic (Headset)
No Mic (Headphone)
PMMP bit
AK4671
LIN1
LIN2
Headset
G
M
R
MDT
L
DTMIC bit
typ.
500k
or
Headphone
G
R
0.075 x AVDD
L
Figure 56. Microphone Power Supply and Mic Detection
MS0666-E-02
2010/06
- 60 -
[AK4671]
■ Digital Block
Digital block is composed as Figure 57. Each block can be powered-down by power management bits (PMADL,
PMADR, PMDAL, PMDAR, PMSRA, PMSRB and PMPCM bits). When blocks from HPF to MIX are powered-down,
both MIX and SVOLA blocks should not be selected by SDOL/R bits and PFMXL/R bits.
PMADL or PMADR
HPF
A/D
HPFAD
PFSEL
PFSEL=0
PMADL
or
PMADR
PFSEL=1
PMDAL
or
PMDAR
or
PMSRA
HPF
HPF
LPF
LPF
Stereo
Separation
5-band
Notch
FIL3, EQ0,
GN1-0
EQ1-5
ALC
ALC, IVL/R
MIX
ADM
SDOL/R1-0 SDOD
SDTO Lch
SDTO Rch
SVAL/R2-0
SVOLA
DAM, MIXD
D/A
PMDAL
or PMDAR
OVL/R
EQ
SRMXL/R1-0
M DATT 5-band
I SMUTE
EQ
X
PMDAL or PMDAR or PMSRA
S
E
L
SDTI Lch
SDTI Rch
SDIM1-0
PFMXL/R1-0
SRA1-0, MIXD
PMPCM
PMSRA
SDOA
SRC-A
SDOAD
SDTOA
SVOLB
SVB2-0
PMSRB
SRC-B
BVMX1-0
DATT-B
SDTIA
BVL7-0
SBMX1-0
DATT-C
CVL7-0
BIV2-0
BIVOL
SDOBD
SDTOB
SDTIB
Figure 57. Path Select of Digital Block
MS0666-E-02
2010/06
- 61 -
[AK4671]
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
ADC: Include the Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”.
DAC: Include the Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”.
HPF: High Pass Filter. Applicable to use as Wind-Noise Reduction Filter. (See “Digital Programmable Filter”.)
LPF: Low Pass Filter (See “Digital Programmable Filter”.)
Stereo Separation: Stereo Separation Emphasis Filter & Gain Compensation. (See “Digital Programmable Filter”.)
Gain Compensation is composed with EQ0 and Gain blocks. This block adjusts the frequency response after Stereo
Separation Emphasis.
5-Band Notch: Applicable to use as Equalizer or Notch Filter. (See “Digital Programmable Filter”.)
ALC: Input Digital Volume with ALC function. (See “Input Digital Volume” and “ALC Operation”.)
SVOLA: Side Tone Volume at Internal MIC/SPK or External Headset Phone Call. (See “Side Tone Volume”.)
5-Band EQ: Equalizer for playback path. (See “5-band Equalizer”.)
DATT: Digital Volume for playback path. (See “Digital Output Volume”.)
SMUTE: Soft mute. (See “Soft Mute”.)
DATT-B: Digital Volume for Recording of Received Voice. (See “Digital Volume for Recording of Received
Voice”)
DATT-C: Digital Volume of Received Voice. (See “Digital Volume for Received Voice”)
SVOLA: Side Tone Volume at B/T Headset Phone Call. (See “Side Tone Volume for B/T Phone Call”.)
Mode
Recording Mode
PMADL
1
1
0
1
1
0
0
Recording &
Playback Mode
Playback Mode
ADC
PMADR
PMDAL
PMDAR
1
0
0
0
0
0
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
Table 22. Recode/Playback Mode
2nd Order
1st Order
HPF
LPF
Stereo
Separation
Gain
Compensation
PFSEL
0
0
0
0
0
0
1
Figure
Figure 58
Figure 59
Figure 60
5 Band
Notch
ALC
(Volume)
Figure 58. Path at Recording Mode
ADC
DAC
2nd Order
1st Order
HPF
LPF
DEM
SMUTE
DATT
Stereo
Separation
Gain
Compensation
5 Band
Notch
ALC
(Volume)
5 Band
EQ
Figure 59. Path at Recording & Playback Mode
ADC
DAC
1st Order
“0” Data
HPF
DEM
SMUTE
DATT
5 Band
EQ
ALC
(Volume)
5 Band
EQ
Gain
Compensation
Stereo
Separation
1st Order
1st Order
LPF
HPF
Figure 60. Path at Playback Mode
MS0666-E-02
2010/06
- 62 -
[AK4671]
■ Digital Programmable Filter
(1) High Pass Filter (HPF)
Normally, this HPF is used for a Wind-Noise Reduction Filter. This is composed of 2 steps of 1st order HPF. The
coefficient of both HPF is the same and set by F1A13-0 bits and F1B13-0 bits. HPFAD bit controls ON/OFF of the 1st
step HPF and HPF bit controls ON/OFF of the 2nd step HPF. When the HPF is OFF, the audio data passes this block by
0dB gain. The coefficient should be set when HPFAD=HPF bits = “0” or PMADL=PMADR=PMDAL=PMDAR bits =
“0”.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 61)
HPF: F1A[13:0] bits =A, F1B[13:0] bits =B
(MSB=F1A13, F1B13; LSB=F1A0, F1B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1 − z −1
H(z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
(2) Low Pass Filter (LPF)
This is composed with 1st order LPF. F2A13-0 bits and F2B13-0 bits set the coefficient of LPF. LPF bit controls ON/OFF
of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient should be set when LPF
bit = “0” or PMADL=PMADR=PMDAL=PMDAR bits = “0”.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 61)
LPF: F2A[13:0] bits =A, F2B[13:0] bits =B
(MSB=F2A13, F1B13; LSB=F2A0, F2B0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
The cut-off frequency should be set as below.
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
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[AK4671]
(3) Stereo Separation Emphasis Filter (FIL3)
FIL3 is used to emphasize the stereo separation of stereo mic recording data or playback data. F3A13-0 and F3B13-0 bits
set the filter coefficient of FIL3. FIL3 becomes High Pass Filter (HPF) at F3AS bit = “0”, and Low Pass Filter (LPF) at
F3AS bit = “1”. FIL3 bit controls ON/OFF of FIL3. When Stereo Separation Emphasis Filter is OFF, the audio data
passes this block by 0dB gain. The coefficient should be set when FIL3 bit = “0” or PMADL = PMADR = PMDAL =
PMDAR bits = “0”.
1) When FIL3 is set to “HPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB ≥ K ≥ −10dB)
Register setting (Note 61)
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB=F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A = 10K/20 x
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1 − z −1
H(z) = A
1 + Bz −1
2) When FIL3 is set to “LPF”
fs: Sampling frequency
fc: Cut-off frequency
K: Filter gain [dB] (0dB ≥ K ≥ −10dB)
Register setting (Note 61)
FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F3A13, F3B13; LSB= F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
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[AK4671]
(4) Gain Compensation (EQ0)
Gain Compensation is used to compensate the frequency response and the gain that is changed by Stereo Separation
Emphasis Filter. Gain Compensation is composed with Equalizer (EQ0) and the Gain (0dB/+12dB/+24dB). E0A15-0,
E0B13-0 and E0C15-0 bits set the coefficient of EQ0. GN1-0 bits set the gain (Table 23). EQ0 bit controls ON/OFF of
EQ0. When EQ is OFF and the gain is 0dB, the audio data passes this block by 0dB gain. The coefficient should be set
when EQ0 bit = “0” or PMADL=PMADR=PMDAL=PMDAR bits = “0”.
fs: Sampling frequency
fc1: Pole frequency
fc2: Zero-point frequency
K: Filter gain [dB] (Maximum +12dB)
Register setting (Note 61)
E0A[15:0] bits =A, E0B[13:0] bits =B, E0C[15:0] bits =C
(MSB=E0A15, E0B13, E0C15; LSB=E0A0, E0B0, E0C0)
A = 10K/20 x
1 − 1 / tan (πfc1/fs)
1 + 1 / tan (πfc2/fs)
,
1 + 1 / tan (πfc1/fs)
B=
,
C =10K/20 x
1 + 1 / tan (πfc1/fs)
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
Transfer function
A + Cz −1
H(z) =
1 + Bz −1
Gain[dB]
K
fc1
fc2
Frequency
Figure 61. EQ0 Frequency Response
GN1
GN0
Gain
0
0
0dB
(default)
0
1
+12dB
1
x
+24dB
Table 23. Gain select of gain block (x: Don’t care)
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[AK4671]
(5) 5-band Notch
This block can be used as Equalizer or Notch Filter. 5-band Equalizer (EQ1, EQ2, EQ3, EQ4 and EQ5) is ON/OFF
independently by EQ1, EQ2, EQ3, EQ4 and EQ5 bits. When Equalizer is OFF, the audio data passes this block by 0dB
gain. E1A15-0, E1B15-0 and E1C15-0 bits set the coefficient of EQ1. E2A15-0, E2B15-0 and E2C15-0 bits set the
coefficient of EQ2. E3A15-0, E3B15-0 and E3C15-0 bits set the coefficient of EQ3. E4A15-0, E4B15-0 and E4C15-0
bits set the coefficient of EQ4. E5A15-0, E5B15-0 and E5C15-0 bits set the coefficient of EQ5. The EQx (x=1∼5)
coefficient should be set when EQx bit = “0” or PMADL=PMADR=PMDAL=PMDAR bits = “0”.
fs: Sampling frequency
fo1 ~ fo5: Center frequency
fb1 ~ fb5: Band width where the gain is 3dB different from center frequency
K1 ~ K5 : Gain (−1 ≤ Kn ≤ 3)
Register setting (Note 61)
EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1
EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2
EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3
EQ4: E4A[15:0] bits =A4, E4B[15:0] bits =B4, E4C[15:0] bits =C4
EQ5: E5A[15:0] bits =A5, E5B[15:0] bits =B5, E5C[15:0] bits =C5
(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15,
E5A15, E5B15, E5C15; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0,
E4C0, E5A0, E5B0, E5C0)
1 − tan (πfbn/fs)
2
tan (πfbn/fs)
An = Kn x
, Bn = cos(2π fon/fs) x
1 + tan (πfbn/fs)
,
1 + tan (πfbn/fs)
Cn =
1 + tan (πfbn/fs)
(n = 1, 2, 3, 4, 5)
Transfer function
H(z) = 1 + h1(z) + h2(z) + h3(z) + h4(z) + h5(z)
1 − z −2
hn (z) = An
1− Bnz −1− Cnz −2
(n = 1, 2, 3, 4, 5)
The center frequency should be set as below.
fon / fs < 0.497
Note 61. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s
complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X should be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sine bit.
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[AK4671]
■ ALC Operation
The ALC (Automatic Level Control) is executed by ALC block when ALC bit is “1”. ALC circuit operates at playback
path for Playback mode and operates at recording path for Recording mode as shown in Figure 60.
1.
ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 24), the IVL
and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 25).
When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation
at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing
timeout period of both ALC limiter and recovery operation (Table 26). IVL and IVR values are attenuated 1 step
immediately (period: 1/fs) by ALC limiter operation when output level is over FS (Digital Full Scale). When output level
is not over FS, the IVL and IVR values are changed at the individual zero crossing points of Lch and Rch or at the zero
crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by
ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level (Table 24)
or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTH1-0 bits.
LMTH1
0
0
1
1
LMTH0
0
1
0
1
ALC Limier Detection Level
ALC Recovery Waiting Counter Reset Level
−2.5dBFS > ALC Output ≥ −4.1dBFS
ALC Output ≥ −2.5dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
ALC Output ≥ −4.1dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
ALC Output ≥ −6.0dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
ALC Output ≥ −8.5dBFS
Table 24. ALC Limiter Detection Level / Recovery Counter Reset Level
LMAT1
LMAT0
0
0
1
1
0
1
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
ALC Limiter ATT Step
ALC Output
ALC Output
ALC Output
≥ LMTH
≥ FS
≥ FS + 6dB
1
1
1
2
2
2
2
4
4
1
2
4
Table 25. ALC Limiter ATT Step
ALC Output
≥ FS + 12dB
1
2
8
8
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 26. ALC Zero Crossing Timeout Period
MS0666-E-02
(default)
(default)
(default)
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[AK4671]
2.
ALC Recovery Operation
The ALC recovery operation waits for the WTM2-0 bits (Table 27) to be set after completing the ALC limiter operation.
If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 24) during the wait time, the ALC
recovery operation is executed. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 28) up
to the set reference level (Table 29) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 26).
Then the IVL and IVR are set to the same value for both channels. The ALC recovery operation is executed in a period set
by WTM2-0 bits. When zero cross is detected at both channels during the wait period set by WTM2-0 bits, the ALC
recovery operation waits until WTM2-0 period and the next recovery operation is executed. If ZTM1-0 is longer than
WTM2-0 and no zero crossing occurs, the ALC recovery operation is executed in a period set by ZTM1-0 bits.
For example, when the current IVL and IVR values are 30H and RGAIN1-0 bits are set to “01”, IVL and IVR values are
changed to 32H by the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When
the IVL and IVR values exceed the reference level (REF7-0 bits), the IVL and IVR values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation
becomes faster than a normal recovery operation (Fast Recovery Operation). When large noise is input to microphone
instantaneously, the quality of small signal level in the large noise can be improved by this fast recovery operation. The
speed of fast recovery operation is set by RFST1-0 bits (Table 30).
WTM2
WTM1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
0
128/fs
16ms
8ms
2.9ms
1
256/fs
32ms
16ms
5.8ms
0
512/fs
64ms
32ms
11.6ms
1
1024/fs
128ms
64ms
23.2ms
0
2048/fs
256ms
128ms
46.4ms
1
4096/fs
512ms
256ms
92.9ms
0
8192/fs
1024ms
512ms
185.8ms
1
16384/fs
2048ms
1024ms
371.5ms
Table 27. ALC Recovery Operation Waiting Period
WTM0
RGAIN1
0
0
1
1
RGAIN0
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 28. ALC Recovery GAIN Step
MS0666-E-02
(default)
(default)
2010/06
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[AK4671]
REF7-0 bits
GAIN (dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
(default)
E1H
+30.0
:
:
0.375dB
92H
+0.375
91H
0.0
90H
−0.375
:
:
2H
−53.625
1H
−54.0
0H
MUTE
Table 29. Reference Level at ALC Recovery Operation
RFST1 bit
RFST0 bit
Recovery Speed
0
0
4 times
(default)
0
1
8 times
1
0
16times
1
1
N/A
Table 30. Fast Recovery Speed Setting (N/A: Not available)
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[AK4671]
3.
Example of ALC Operation
Table 31 and Table 32 show the examples of the ALC setting for mic recording and playback, respectively.
Register Name
Comment
LMTH1-0
ZELMN
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
* ZTM1-0 bits should be equal to or
shorter than WTM2-0 bits.
Recovery waiting period
Maximum gain at recovery operation
ZTM1-0
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Gain of IVOL
Data
01
0
fs=8kHz
Operation
−4.1dBFS
Enable
Data
01
0
fs=44.1kHz
Operation
−4.1dBFS
Enable
01
32ms
11
23.2ms
001
E1H
32ms
+30dB
100
E1H
46.4ms
+30dB
E1H
+30dB
E1H
+30dB
00
00
00
1
1 step
1 step
4 times
Enable
Limiter ATT step
00
1 step
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 31. Example of the ALC setting (Recording Path)
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
longer data as ZTM1-0 bits
Maximum gain at recovery operation
001
32ms
100
46.4ms
A1H
+6dB
A1H
+6dB
Gain of IVOL
91H
0dB
91H
0dB
00
00
00
1
1 step
1 step
4 times
Enable
WTM2-0
REF5-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Data
01
0
01
Limiter ATT step
00
1 step
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 32. Example of the ALC setting (Playback Path)
MS0666-E-02
Data
01
0
11
2010/06
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[AK4671]
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0
Example:
Limiter = Zero crossing Enable
Recovery Cycle = [email protected]
Zero Crossing Timeout Period = [email protected]
Limiter and Recovery Step = 1
Fast Recovery Speed = 4 step
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
Manual Mode
WR (IVL7-0)
(1) Addr=12H, Data=E1H
WR (IVR7-0)
(2) Addr=13H, Data=E1H
WR (REF7-0)
* The value of IVOL should be
(3) Addr=14H, Data=E1H
the same or smaller than REF’s
WR (ZTM1-0, WTM2-0, RFST1-0)
(4) Addr=16H, Data=05H
WR (LMTH1-0, RGAIN1-0, LMAT1-0, ZELMN)
(5) Addr=17H, Data=01H
WR (ALC = “1”)
(6) Addr=18H, Data=03H
ALC Operation
Note : WR : Write
Figure 62. Registers set-up sequence at ALC operation
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[AK4671]
■ Input Digital Volume (Manual Mode)
The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below.
1.
2.
3.
After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH1-0 and etc)
When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed.
For example, in case of changing the sampling frequency.
When IVOL is used as a manual volume.
IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 33). When IVOLC bit is “0”, IVL7-0 and IVR7-0 bits
control Lch and Rch volume values independently. When IVOLC bit is “1”, IVL7-0 bits controls both channels. The
IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 or
IVR7-0 bits are written during PMADL=PMADR bits = “0”, IVOL operation starts with the written values at the end of
the ADC initialization cycle after PMADL or PMADR bit is changed to “1”.
(default)
IVL7-0 bits
GAIN (dB)
IVR7-0 bits
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
92H
+0.375
91H
0.0
90H
−0.375
:
:
03H
−53.25
02H
−53.625
01H
−54
00H
MUTE
Table 33. Input Digital Volume Setting
Step
0.375dB
■ Side Tone Volume (SVOLA)
The AK4671 has the channel independent side tone volume (5 levels, 6dB step). The volume can be set by the
SVAL/R2-0 bits. The volume is included at mixing path from ALC to 5-band EQ. The output data of ALC is changed
from 0 to –24dB.
SVL2-0
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 34. Side Tone Volume A Code Table (N/A: Not available)
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[AK4671]
■ 5-Band Equalizer
The AK4671 has 5-Band Equalizer before DAC of Stereo CODEC.
The center frequencies and cut/boost amount are the followings.
• Center frequency: 100Hz, 250Hz, 1kHz, 3.5kHz and 10kHz (Note 62, Note 63, Note 64)
• Cut/Boost amount: –10.5dB ∼ +12dB, 1.5dB step
Note 62. These are the frequencies when the sampling frequency is 44.1kHz. These frequencies are proportional to the
sampling frequency.
Note 63. 100Hz is not center frequency but the frequency component lower than 100Hz is controlled.
Note 64. 10kHz is not center frequency but the frequency component higher than 10kHz is controlled.
EQ bit controls ON/OFF of this Equalizer and these Boost amount are set by EQA3-0, EQB3-0, EQC3-0, EQD3-0 and
EQE3-0 bits, respectively, as shown in Table 35.
EQA3-0:
EQB3-0:
EQC3-0:
EQD3-0:
EQE3-0:
Select the boost level of 100Hz
Select the boost level of 250Hz
Select the boost level of 1kHz
Select the boost level of 3.5kHz
Select the boost level of 10kHz
EQx3-0
Boost amount
0H
+12.0dB
1H
+10.5dB
2H
+9.0dB
3H
+7.5dB
:
:
8H
0dB
(default)
:
:
DH
−7.5dB
EH
−9.0dB
FH
−10.5dB
Table 35. Boost amount of 5-Band Equalizer
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2010/06
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[AK4671]
■ Digital Output Volume
The AK4671 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the OVL7-0 and
OVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or
MUTE. When the OVOLC bit = “1”, the OVL7-0 bits control both Lch and Rch attenuation levels. When the OVOLC bit
= “0”, the OVL7-0 bits control Lch level and OVR7-0 bits control Rch level. This volume has a soft transition function.
The OVTM bit sets the transition time between set values of OVL/R7-0 bits as either 1061/fs or 256/fs (Table 37). When
OVTM bit = “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs ([email protected]=44.1kHz)
from 00H (+12dB) to FFH (MUTE).
(default)
OVTM bit
0
1
OVL/R7-0
Gain
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
:
:
18H
0dB
:
:
FDH
−114.5dB
FEH
−115.0dB
FFH
MUTE (−∞)
Table 36. Digital Volume Code Table
Step
0.5dB
Transition time between DVL/R7-0 bits = 00H and FFH
Setting
fs=8kHz
fs=44.1kHz
1061/fs
133ms
24ms
256/fs
32ms
6ms
Table 37. Transition Time Setting of Digital Output Volume
MS0666-E-02
(default)
2010/06
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[AK4671]
■ Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit is changed to “1”, the output signal is
attenuated to −∞ (“0”) during the cycle set by the OVTM bit. When the SMUTE bit is returned to “0”, the mute is
cancelled and the output attenuation gradually changes to the value set by the OVL/R7-0 bits during the cycle set of the
OVTM bit. If the soft mute is cancelled within the cycle set by the OVTM bit after starting the operation, the attenuation
is discontinued and returned to the value set by the OVL/R7-0 bits. The soft mute is effective for changing the signal
source without stopping the signal transmission (Figure 63).
S M U T E bit
O VTM bit
O VL/R 7-0 bits
O VTM bit
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 63. Soft Mute Function
(1) The output signal is attenuated until −∞ (“0”) in the cycle set by the OVTM bit.
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within the cycle set by the OVTM bit, the attenuation is discounted and returned to the
value set by the OVL/R7-0 bits.
MS0666-E-02
2010/06
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[AK4671]
■ Digital Volume for Recording of Received Voice (DATT-B)
The AK4671 has a digital output volume (DATT-B: 256 levels, 0.5dB step, Mute) for recording of received voice. The
volume can be set by the BVL7-0 bits. The volume is included in front of an SRC-B block. The input data of SRC-B is
changed from +12 to –115dB or MUTE. This volume has a soft transit function. The transition time between set values of
BVL7-0 bits is 256/fs2. It takes 256/fs2 ([email protected]=8kHz) from 00H (+12dB) to FFH (MUTE).
(default)
BVL7-0
Gain
Step
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
:
:
0.5dB
18H
0dB
:
:
FDH
−114.5dB
FEH
−115.0dB
FFH
MUTE (−∞)
Table 38. Digital Volume B Code Table
■ Digital Volume for Received Voice (DATT-C)
The AK4671 has a digital output volume (DATT-C: 256 levels, 0.5dB step, Mute) for received voice. The volume can be
set by the CVL7-0 bits. The volume is included in front of SDTOB output. The input data of SRC-C is changed from +12
to –115dB or MUTE. This volume has a soft transition function. The transition time between set values of CVL7-0 bits is
256/fs2. It takes 256/fs2 ([email protected]=8kHz) from 00H (+12dB) to FFH (MUTE).
(default)
CVL7-0
Gain
Step
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
:
:
0.5dB
18H
0dB
:
:
FDH
−114.5dB
FEH
−115.0dB
FFH
MUTE (−∞)
Table 39. Digital Volume C Code Table
■ Side Tone Volume for B/T Phone Call (SVOLB)
The AK4671 has the side tone volume (5 levels, 6dB step) for B/T phone call. The volume can be set by the SVL2-0 bits.
The volume is included at mixing path from SRC-A to DATT-C. The output data of SRC-A is changed from 0 to –24dB.
SVB2-0
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 40. Side Tone Volume B Code Table (N/A: Not available)
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■ Digital Volume for B/T MIC Input (BIVOL)
The AK4671 has the digital volume (5 levels, 6dB step) for B/T mic input. The volume can be set by the BIV2-0 bits. The
volume is included at SDTIB input. The input data is changed from 0 to –24dB.
BIV2-0
Gain
0H
0dB
(default)
1H
−6dB
2H
−12dB
3H
−18dB
4H
−24dB
Others
N/A
Table 41. SDTIB Volume Code Table (N/A: Not available)
■ Path & Mixing Setting of Digital Block (Figure 57)
PMADL and PMADR bits set both ADC power management and output data selection. In case of mono operation, the
same data is output to both channel slots.
PMADL
0
0
1
1
PMADR
ADC Lch data
ADC Rch data
0
All “0”
All “0”
1
Rch Input Signal
Rch Input Signal
0
Lch Input Signal
Lch Input Signal
1
Lch Input Signal
Rch Input Signal
Table 42. ADC Mono/Stereo Select
(default)
PFSEL bit select the input data of programmable filter.
PFSEL
Programmable Filter Input
0
ADC Output (selected by Table 42)
(default)
1
SDTI Input (selected by Table 48)
Table 43. Programmable Filter Input Signal Select
When ADM bit is “1”, ALC output data is output to both channels of SDTO and SVOLA as (L+R)/2, respectively.
ADM
Lch
Rch
0
L
R
(default)
1
(L+R)/2
(L+R)/2
Table 44. ALC Output Mono Mixing
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SDOL1-0 and SDOR1-0 bits set the data mixing for each channel of SDTO from the data selected by Table 44 and SRC-B
output data.
SDOL1
0
0
1
1
SDOL0
SDTO Lch
0
Lch Signal selected by Table 44
1
SRC-B
0
(Lch Signal selected by Table 44) + (SRC-B)
1
N/A
Table 45. SDTO Lch Output Mixing (N/A: Not available)
SDOR1
0
0
1
1
SDOR0
SDTO Rch
0
Rch Signal selected by Table 44
1
SRC-B
0
(Rch Signal selected by Table 44) + (SRC-B)
1
N/A
Table 46. SDTO Rch Output Mixing (N/A: Not available)
(default)
(default)
When SDOD bit is “1”, SDTO output data can be disabled (fixed to “L”). Input data of SVOLA is not disabled.
SDOD
0
1
SDTO
Enable (Output) (default)
Disable (“L”)
Table 47. SDTO Disable
SDIM1-0 bits select stereo or mono of SDTI input data. In case of mono mode, the same data is input to both channels.
SDIM1
SDIM0
Lch
Rch
0
0
L
R
(default)
0
1
L
L
1
0
R
R
1
1
N/A
Table 48. SDTI Stereo/Mono Select (N/A: Not available)
PFMXL1-0 and PFMXR1-0 bits set the data mixing for each channel of 5-band EQ from the data selected by Table 48
and SVOLA output data.
PFMXL1
0
0
1
1
PFMXL0
5-band EQ Lch Input
0
Lch Signal selected by Table 48
1
SVOLA Lch
0
(Lch Signal selected by Table 48) + (SVOLA Lch)
1
N/A
Table 49. 5-band EQ Lch Input Mixing 1 (N/A: Not available)
PFMXR1
0
0
1
1
PFMXR0
5-band EQ Rch Input
0
Rch Signal selected by Table 48
1
SVOLA Rch
0
(Rch Signal selected by Table 48) + (SVOLA Rch)
1
N/A
Table 50. 5-band EQ Rch Input Mixing 1 (N/A: Not available)
MS0666-E-02
(default)
(default)
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[AK4671]
SRMXL1-0 and SRMXR1-0 bits set the data mixing for each channel of 5-band EQ from the data selected by Table
49/Table 50 and SVOLA output data.
SRMXL1 SRMXL0
5-band EQ Lch Input
0
0
Signal selected by Table 49
(default)
0
1
SRC-B
1
0
(Signal selected by Table 49) + (SRC-B)
1
1
N/A
Table 51. 5-band EQ Lch Input Mixing 2 (N/A: Not available)
SRMXR1 SRMXR0
5-band EQ Rch Input
0
0
Signal selected by Table 50
(default)
0
1
SRC-B
1
0
(Signal selected by Table 50) + (SRC-B)
1
1
N/A
Table 52. 5-band EQ Rch Input Mixing 2 (N/A: Not available)
DAM and MIXD bits set the data mixing for DAC input.
DAM
0
1
1
MIXD
Lch
Rch
x
L
R
(default)
0
L+R
L+R
1
(L+R)/2
(L+R)/2
Table 53. DAC Mono Mixing (x: Don’t care)
SRA1-0 and MIXD bits set the data mixing for SRC-A input.
SRA1
SRA0
MIXD
SRC-A
0
0
x
L
(default)
0
1
x
R
1
0
0
L+R
1
0
1
(L+R)/2
1
1
x
N/A
Table 54. SRC-A Input Mixing (x: Don’t care, N/A: Not available)
SDOA bit selects the output data of SDTOA.
SDOA
0
1
SDTOA
SRC-A
(default)
SDTIB
Table 55. SDTOA Output Select
When SDOAD bit is “1”, SDTOA output data can be disabled (fixed to “L”). Input data of SVOLB is not disabled.
SDOAD
SDTOA
0
Enable (Output) (default)
1
Disable (“L”)
Table 56. SDTOA Disable
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SBMX1-0 bits set the data mixing from SDTIA input and SVOLB output. The mixed data is output to SDTOB via
DATT-C.
SBMX1
0
0
1
1
SBMX0
DATT-C Input
0
SDTIA
(default)
1
SVOLB
0
(SDTIA) + (SVOLB)
1
N/A
Table 57. SDTOB Mixing (N/A: Not available)
When SDOBD bit is “1”, SDTOB output data can be disabled (fixed to “L”).
SDOBD
SDTOB
0
Enable (Output) (default)
1
Disable (“L”)
Table 58. SDTOB Disable
BVMX1-0 bits set the data mixing for SRC-B from SDTIA input (DATT-B output) and SDTIB input (BIVOL output).
BVMX1
BVMX0
SRC-B Input
0
0
SDTIA
(default)
0
1
SDTIB
1
0
(SDTIA) + (SDTIB)
1
1
N/A
Table 59. SRC-B Input Mixing (N/A: Not available)
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■ Analog Mixing: Single-ended Input (LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins)
AK4671 supports analog mixing function from each line input to each line output (Figure 64).
When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. When
PMAINL1=PMAINR1=PMAINL2=PMAINR2=PMAINL3=PMAINR3=PMAINL4=PMAINR4=PMMICL=PMMICR
bits = “1”, the input resistance of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins becomes 25kΩ (typ) at
MGNL/R0 bits = “0” and 20kΩ (typ) at MGNL/R0 bits = “1”, respectively.
L1G1-0, L2G1-0, L3G1-0, L4G1-0 and LPG1-0 bits adjust the gain for each path (Table 60, Table 61, Table 62, Table 63,
Table 64).
AK4671
INL4-0 bits
LIN1/IN1+ pin
ADC Lch
RIN1/IN1− pin
MDIF1 bit MIC-Amp Lch
MDIF3 bit
INR4-0 bits
LIN2/IN2+ pin
ADC Rch
RIN2/IN2− pin
MDIF2 bit MIC-Amp Rch
MDIF4 bit
LIN3/IN3+ pin
RIN3/IN3− pin
LIN4/IN4+ pin
Figure 56, 57, 59, 60
LOUT1 pin
Figure 62, 63
ROUT1 pin
LOUT2 pin
ROUT2 pin
PMLOOPR bit
PMLOOPL bit
PMAINR4 bit
PMAINL4 bit
PMAINR3 bit
PMAINL3 bit
PMAINR2 bit
PMAINL2 bit
PMAINL1 bit
PMAINR1 bit
RIN4/IN4− pin
Figure 66, 67, 69, 70
LOUT3 pin
ROUT3 pin
Figure 64. Analog Mixing Circuit
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L1G1 bit
L1G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 60. LIN1/RIN1 (or IN1+/−) Mixing Gain (typ) (N/A: Not available)
L2G1 bit
L2G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 61. LIN2/RIN2 (or IN2+/−) Mixing Gain (typ) (N/A: Not available)
L3G1 bit
L3G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 62. LIN3/RIN3 (or IN3+/−) Mixing Gain (typ) (N/A: Not available)
L4G1 bit
L4G0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 63. LIN4/RIN4 (or IN4+/−) Mixing Gain (typ) (N/A: Not available)
LPG1 bit
LPG0 bit
Gain
0
0
0dB
(default)
0
1
+6dB
1
0
−6dB
1
1
N/A
Table 64. MIC-Amp Mixing Gain (typ) (N/A: Not available)
■ Analog Mixing: Full-differential Input (IN1+/IN1−/IN2+/IN2−/IN3+/IN3−/IN4+/IN4− pins)
When MDIF1, MDIF2, MDIF3 and MDIF4 bits are “1”, LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 pins
become IN1+/−, IN2+/−, IN3+/− and IN4+/− pins, respectively, and analog mixing is availble.
When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. When
PMAINL1=PMAINR1=PMAINL2=PMAINR2=PMAINL3=PMAINR3=PMAINL4=PMAINR4=PMMICL=PMMICR
bits = “1”, the input resistance of IN1+/−, IN2+/−, IN3+/− and IN4+/− pins becomes 25kΩ (typ) at MGNL/R0 bits = “0”
and 20kΩ (typ) at MGNL/R0 bits = “1”, respectively.
L1G1-0, L2G1-0, L3G1-0, L4G1-0 and LPG1-0 bits adjust the gain for each path (Table 60, Table 61, Table 62, Table 63,
Table 64).
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[AK4671]
■ Stereo Line Output (LOUT1/ROUT1 pins)
When DACL and DACR bits are “1”, Lch/Rch signal of DAC is output from the LOUT1/ROUT1 pins which is
single-ended. When DACL and DACR bits are “0”, output signal is muted and LOUT1/ROUT1 pins output VCOM
voltage. The load impedance is 10kΩ (min.). When the PMLO1=PMRO1=LOPS1 bits = “0”, LOUT1/ROUT1 enters
power-down mode and the output is pulled-down to VSS1 by 100kΩ(typ). When the LOPS1 bit is “1”, LOUT1/ROUT1
enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO1 and PMRO1 bits at LOPS1
bit = “1”. In this case, output signal line should be pulled-down to VSS1 by 20kΩ after AC coupled as Figure 65. Rise/Fall
time is 300ms(max) at C=1μF and AVDD=3.3V. When PMLO1=PMRO1 bits = “1” and LOPS1 bit = “0”,
LOUT1/ROUT1 is in normal operation.
L1VL3-0 bits control the volume of LOUT1/ROUT1.
When LOM bit = “1”, DAC output signal is output to LOUT1 and ROUT1 pins as (L+R) mono signal.
When LOOPM bit = “1”, the MIC-Amp signal is output to LOUT1 and ROUT1 pins as (L+R) mono signal.
LOPS1
0
1
LOPS1
0
1
PMLO1
Mode
LOUT1 pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 65. Stereo Line Output Mode Select (LOUT1)
PMRO1
Mode
ROUT1 pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 66. Stereo Line Output Mode Select (ROUT1)
(default)
(default)
L1VL2-0
Attenuation
6H
+6dB
5H
0dB
(default)
4H
−6dB
3H
−12dB
2H
−18dB
1H
−24dB
0H
MUTE
Table 67. Stereo Line Output Volume Setting
LOUT1
ROUT1
1μF
220Ω
20kΩ
Figure 65. External Circuit for Stereo Line Output (in case of using Pop Noise Reduction Circuit)
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<Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)>
(2 )
(5 )
P M L O 1 b it
P M R O 1 b it
(1 )
(3 )
(4 )
(6 )
L O P S 1 b it
L O U T 1 p in
R O U T 1 p in
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 66. Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)
(1) Set LOPS1 bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO1=PMRO1 bits = “1”. Stereo line output exits the power-down mode.
LOUT1 and ROUT1 pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and
AVDD=3.3V.
(3) Set LOPS1 bit = “0” after LOUT1 and ROUT1 pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS1 bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO1=PMRO1 bits = “0”. Stereo line output enters power-down mode.
LOUT1 and ROUT1 pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V.
(6) Set LOPS1 bit = “0” after LOUT1 and ROUT1 pins fall down. Stereo line output exits the power-save mode.
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[AK4671]
<Analog Mixing Circuit for LOUT1/ROUT1>
DACL, DACR, LOM, LINL1, RINR1, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, LOOPL, LOOPR and LOOPM
bits control each path switch.
LINL1 bit
LIN1 pin
+6/0/−6dB
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINL2 bit
LINL3 bit
LINL4 bit
M
LOOPL bit
+6/0/−6dB
I
X
LOUT1 pin
L1VL2-0 bits
LOOPR bit x LOOPM bit
MIC-Amp Lch
DACL bit
DATT
Stereo DAC Lch
0dB
DACR bit x LOM bit
RINR1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
RIN4 pin
+6/0/−6dB
RINR2 bit
RINR3 bit
RINR4 bit
M
LOOPL bit x LOOPM bit
I
X
ROUT1 pin
L1VL2-0 bits
LOOPR bit
+6/0/−6dB
DACL bit x LOM bit
MIC-Amp Rch
DACR bit
DATT
Stereo DAC Rch
0dB
Figure 67. LOUT1/ROUT1 Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
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[AK4671]
LINL1 bit
+6/0/−6dB
IN1+/− pins
LINL2 bit
LINL3 bit
+6/0/−6dB
IN3+/− pins
LINL4 bit
M
LOOPL bit
+6/0/−6dB
I
X
LOUT1 pin
L1VL2-0 bits
LOOPR bit x LOOPM bit
MIC-Amp Lch
DACL bit
DATT
Stereo DAC Lch
0dB
DACR bit x LOM bit
RINR1 bit
RINR2 bit
+6/0/−6dB
IN2+/− pins
RINR3 bit
RINR4 bit
M
+6/0/−6dB
IN4+/− pins
LOOPL bit x LOOPM bit
I
X
ROUT1 pin
L1VL2-0 bits
LOOPR bit
+6/0/−6dB
DACL bit x LOM bit
MIC-Amp Rch
DACR bit
DATT
Stereo DAC Rch
0dB
Figure 68. LOUT1/ROUT1 Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
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[AK4671]
■ Receiver-Amp (RCP/RCN pins)
When RCV bit = “1”, LOUT1/ROUT1 pins become RCP/RCN pins, respectively. Lch/Rch signal of DAC or
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the RCP/RCN pins which is BTL as (L+R) signal. The
load impedance is 32Ω (min). When the PMLO1 = PMRO1 bits = “0”, the mono receiver output enters power-down
mode and the output is Hi-Z. When the PMLO1 = PMRO1 bits = “1” and LOPS1 bit = “1”, mono receiver output enters
power-save mode. Pop noise at power-up/down can be reduced by changing PMLO1 and PMRO1 bits at LOPS1 bit =
“0”. When PMLO1 = PMRO1 bits = “1” and LOPS1 bit = “0”, mono receiver output enters in normal operation.
L1VL3-0 bits control the volume of mono receiver output.
L1VL2-0
Attenuation
6H
+12dB
5H
+6dB
(default)
4H
0dB
3H
−6dB
2H
−12dB
1H
−18dB
0H
MUTE
Table 68. Mono Receiver Output Volume Setting
PMLO1/RO1
0
1
LOPS1
Mode
RCP
RCN
x
Power-down
Hi-Z
Hi-Z
1
Power-save
Hi-Z
VCOM
0
Normal Operation
Normal Operation Normal Operation
Table 69. Receiver-Amp Mode Setting (x: Don’t care)
(default)
PMLO1 bit
PMRO1 bit
LOPS1 bit
RCP pin
RCN pin
Hi-Z
Hi-Z
Hi-Z
VCOM
VCOM
>1ms
>0
Hi-Z
Figure 69. Power-up/Power-down Timing for Receiver-Amp
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[AK4671]
<Analog Mixing Circuit for Receiver Output>
DACL, DACR, LINL1, RINR1, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, LOOPL and LOOPR bits control each
path switch.
When MDIF1/2/3/4 bits = “1”, RINR1/2/3/4 bits should be “0”.
LINL1 bit
LIN1 pin
+6/0/−6dB
LINL2 bit
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LINL3 bit
LINL4 bit
LIN4 pin
+6/0/−6dB
LOOPL bit
+6/0/−6dB
MIC-Amp Lch
RINR1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
M
RINR2 bit
I
X
RCP/RCN pins
L1VL2-0 bits
RINR3 bit
RINR4 bit
RIN4 pin
+6/0/−6dB
LOOPR bit
+6/0/−6dB
MIC-Amp Rch
DATT
Stereo DAC Lch
DACL bit
0dB
DACR bit
DATT
Stereo DAC Rch
0dB
Figure 70. Receiver Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
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[AK4671]
LINL1 bit
+6/0/−6dB
IN1+/− pins
LINL2 bit
+6/0/−6dB
IN2+/− pins
LINL3 bit
IN3+/− pins
+6/0/−6dB
IN4+/− pins
+6/0/−6dB
LINL4 bit
LOOPL bit
RCP/RCN pins
+6/0/−6dB
MIC-Amp Lch
L1VL2-0 bits
LOOPR bit
M
+6/0/−6dB
I
MIC-Amp Rch
DACL bit
DATT
Stereo DAC Lch
0dB
DATT
Stereo DAC Rch
0dB
X
DACR bit
Figure 71. Receiver Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
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[AK4671]
■ Headphone Output (LOUT2/ROUT2 pins)
Power supply voltage for the LOUT2/ROUT2 is supplied from the AVDD pin and centered on the 0.5 x AVDD (typ)
voltage. The load resistance is 16Ω (min). HPG3-0 bits control the output volume (Table 70).
When LOM2 bit = “1”, DAC output signal is output to LOUT2 and ROUT2 pins as (L+R) mono signal.
When LOOPM2 bit = “1”, the MIC-Amp signal is output to LOUT2 and ROUT2 pins as (L+R) mono signal.
HPG3-0
Attenuation
DH
+6dB
CH
+3dB
BH
0dB
(default)
AH
−3dB
:
:
:
:
2H
−27dB
1H
−30dB
0H
MUTE
Table 70. LOUT2/ROUT2 Output Volume
When the MUTEN bit is “0”, the common voltage of LOUT2/ROUT2 falls and the outputs (LOUT2 and ROUT2 pins)
change to “L” (VSS1). When the MUTEN bit is “1”, the common voltage rises to VCOM voltage. A capacitor between
the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to AVDD voltage
and the capacitor at MUTET pin.
[Example]: A capacitor between the MUTET pin and ground = 1.0μF, AVDD=3.3V:
Rise/fall time constant: τ = 100ms(typ), 250ms(max)
Time until the common goes to VSS1 when MUTEN bit = “1” Æ “0”: 500ms(max)
When PMLO2, PMRO2, PMLO2S and PMRO2S bits are “0”, the LOUT2/ROUT2 is powered-down, and the outputs
(LOUT2 and ROUT2 pins) go to “L” (VSS1).
PMLO2 bit, PMRO2 bit,
PMLO2S bit, PMRO2S bit
MUTEN bit
LOUT2 pin,
ROUT2 pin
(1) (2)
(3)
(4)
Figure 72. Power-up/Power-down Timing for LOUT2/ROUT2
(1) LOUT2/ROUT2 power-up (PMLO2, PMRO2, PMLO2S, PMRO2S bit = “1”). The outputs are still VSS1.
(2) LOUT2/ROUT2 common voltage rises up (MUTEN bit = “1”).
(3) LOUT2/ROUT2 common voltage falls down (MUTEN bit = “0”).
(4) LOUT2/ROUT2 power-down (PMLO2, PMRO2, PMLO2S, PMRO2S bit = “0”). The outputs are VSS1. If the power
supply is switched off or LOUT2/ROUT2 is powered-down before the common voltage goes to VSS1, some POP
noise occurs.
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[AK4671]
<Analog Mixing Circuit for LOUT2/ROUT2>
DACHL, DACHR, LOM2, LINH1, RINH1, LINH2, RINH2, LINH3, RINH3, LINH4, RINH4, LOOPHL, LOOPHR and
LOOPM2 bits control each path switch.
LINH1 bit
LIN1 pin
+6/0/−6dB
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINH2 bit
LINH3 bit
LINH4 bit
M
LOOPHL bit
+6/0/−6dB
I
X
LOUT2 pin
HPG3-0 bits
LOOPHR bit x LOOPM2 bit
MIC-Amp Lch
DACHL bit
DATT
Stereo DAC Lch
0dB
DACHR bit x LOM2 bit
RINH1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
RINH2 bit
RINH3 bit
RINH4 bit
RIN4 pin
M
+6/0/−6dB
LOOPHL bit x LOOPM2 bit
I
X
ROUT2 pin
HPG3-0 bits
LOOPHR bit
+6/0/−6dB
DACHL bit x LOM2 bit
MIC-Amp Rch
DACHR bit
DATT
Stereo DAC Rch
0dB
Figure 73. LOUT2/ROUT2 Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
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LINH1 bit
+6/0/−6dB
IN1+/− pins
LINH2 bit
LINH3 bit
+6/0/−6dB
IN3+/− pins
LINH4 bit
M
LOOPHL bit
+6/0/−6dB
I
X
LOUT2 pin
HPG3-0 bits
LOOPHR bit x LOOPM2 bit
MIC-Amp Lch
DACHL bit
DATT
Stereo DAC Lch
0dB
DACHR bit x LOM2 bit
RINH1 bit
RINH2 bit
+6/0/−6dB
IN2+/− pins
RINH3 bit
RINH4 bit
M
+6/0/−6dB
IN4+/− pins
LOOPHL bit x LOOPM2 bit
I
X
ROUT2 pin
HPG3-0 bits
LOOPHR bit
+6/0/−6dB
DACHL bit x LOM2 bit
MIC-Amp Rch
DACHR bit
DATT
Stereo DAC Rch
0dB
Figure 74. LOUT2/ROUT2 Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
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[AK4671]
■ Stereo Line Output 3 (LOUT3/ROUT3 pins)
When DACSL and DACSR bits are “1”, Lch/Rch signal of DAC is output from the LOUT3/ROUT3 pins which is
single-ended. When DACSL and DACSR bits are “0”, output signal is muted and LOUT3/ROUT3 pins output VCOM
voltage. The load impedance is 10kΩ (min.). When the PMLO3=PMRO3=LOPS3 bits = “0”, LOUT3/ROUT3 enters
power-down mode and the output is pulled-down to VSS1 by 100kΩ(typ). When the LOPS3 bit is “1”, LOUT3/ROUT3
enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO3 and PMRO3 bits at LOPS3
bit = “1”. In this case, output signal line should be pulled-down to VSS1 by 20kΩ after AC coupled as Figure 75. Rise/Fall
time is 300ms(max) at C=1μF and AVDD=3.3V. When PMLO3=PMRO3 bits = “1” and LOPS3 bit = “0”,
LOUT3/ROUT3 is in normal operation.
L3VL3-0 bits control the volume of LOUT3/ROUT3.
When LOM3 bit = “1”, DAC output signal is output to LOUT3 and ROUT3 pins as (L+R) mono signal.
When LOOPM3 bit = “1”, the MIC-Amp signal is output to LOUT3 and ROUT3 pins as (L+R) mono signal.
LOPS3
0
1
LOPS3
0
1
PMLO3
Mode
LOUT3 pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 71. Stereo Line Output Mode Select (LOUT3)
PMRO3
Mode
ROUT3 pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 72. Stereo Line Output Mode Select (ROUT3)
(default)
(default)
L3VL1
L3VL0
Attenuation
1
1
+3dB
1
0
0dB
(default)
0
1
−3dB
0
0
−6dB
Table 73. Stereo Line Output Volume Setting
LOUT3
ROUT3
1μF
220Ω
20kΩ
Figure 75. External Circuit for Stereo Line Output (in case of using Pop Noise Reduction Circuit)
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<Stereo Line Output 3 Control Sequence (in case of using Pop Noise Reduction Circuit)>
(2 )
(5 )
P M L O 3 b it
P M R O 3 b it
(1 )
(3 )
(4 )
(6 )
L O P S 3 b it
L O U T 3 , R O U T 3 p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 76. Stereo Line Output 3 Control Sequence (in case of using Pop Noise Reduction Circuit)
(1) Set LOPS3 bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO3=PMRO3 bits = “1”. Stereo line output exits the power-down mode.
LOUT3 and ROUT3 pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and
AVDD=3.3V.
(3) Set LOPS3 bit = “0” after LOUT3 and ROUT3 pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS3 bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO3=PMRO3 bits = “0”. Stereo line output enters power-down mode.
LOUT3 and ROUT3 pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V.
(6) Set LOPS3 bit = “0” after LOUT3 and ROUT3 pins fall down. Stereo line output exits the power-save mode.
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<Analog Mixing Circuit for LOUT3/ROUT3>
DACSL, DACSR, LOM3, LINS1, RINS1, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4, LOOPSL, LOOPSR and
LOM3 bits control each path switch.
LINS1 bit
LIN1 pin
+6/0/−6dB
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LIN4 pin
+6/0/−6dB
LINS2 bit
LINS3 bit
LINS4 bit
M
LOOPSL bit
+6/0/−6dB
I
X
LOUT3 pin
L3VL1-0 bits
LOOPSR bit x LOOPM3 bit
MIC-Amp Lch
DACSL bit
DATT
Stereo DAC Lch
0dB
DACSR bit x LOM3 bit
RINS1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
RIN3 pin
+6/0/−6dB
RIN4 pin
+6/0/−6dB
RINS2 bit
RINS3 bit
RINS4 bit
M
LOOPSL bit x LOOPM3 bit
I
X
ROUT3 pin
L3VL1-0 bits
LOOPSR bit
+6/0/−6dB
DACSL bit x LOM3 bit
MIC-Amp Rch
DACSR bit
DATT
Stereo DAC Rch
0dB
Figure 77. LOUT3/ROUT3 Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
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LINS1 bit
+6/0/−6dB
IN1+/− pins
LINS2 bit
LINS3 bit
+6/0/−6dB
IN3+/− pins
LINS4 bit
M
LOOPSL bit
+6/0/−6dB
I
X
LOUT3 pin
L3VL1-0 bits
LOOPSR bit x LOOPM3 bit
MIC-Amp Lch
DACSL bit
DATT
Stereo DAC Lch
0dB
DACSR bit x LOM3 bit
RINS1 bit
RINS2 bit
+6/0/−6dB
IN2+/− pins
RINS3 bit
RINS4 bit
M
+6/0/−6dB
IN4+/− pins
LOOPSL bit x LOOPM3 bit
I
X
ROUT3 pin
L3VL1-0 bits
LOOPSR bit
+6/0/−6dB
DACSL bit x LOM3 bit
MIC-Amp Rch
DACSR bit
DATT
Stereo DAC Rch
0dB
Figure 78. LOUT3/ROUT3 Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
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[AK4671]
■ Full-differential Mono Line Output (LOP/LON pins)
When LODIF bit = “1”, LOUT3/ROUT3 pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins which is full-differential as (L+R)
signal. The load impedance is 10kΩ (min) for LOP and LON pins, respectively. When the PMLO3 = PMRO3 bits = “0”,
the mono line output enters power-down mode and the output is pulled-down to VSS1. When the PMLO3 = PMRO3 bits
= “1” and LOPS3 bit = “1”, mono line output enters power-save mode. Pop noise at power-up/down can be reduced by
changing PMLO3 and PMRO3 bits at LOPS3 bit = “0”. When PMLO3 = PMRO3 bits = “1” and LOPS3 bit = “0”, mono
line output enters in normal operation. L3VL1-0 bits set the volume of mono line output.
L3VL1-0
Attenuation
3H
+9dB
2H
+6dB
(default)
1H
+3dB
0H
0dB
Table 74. Mono Line Output Gain Setting
LOPS3
PMLO3/RO3
Mode
LOUT3 pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 75. Mono Line Output Mode Setting
0
1
(default)
<Full-differential Mono Line Output Control Sequence (in case of using Pop Noise Reduction
Circuit)>
(2 )
(5 )
P M L O 3 b it
P M R O 3 b it
(1 )
(3 )
(4 )
(6 )
L O P S 3 b it
L O P , L O N p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 79. Mono Line Output 3 Control Sequence (in case of using Pop Noise Reduction Circuit)
(1) Set LOPS3 bit = “1”. Mono line output enters the power-save mode.
(2) Set PMLO3 = PMRO3 bits = “1”. Mono line output exits the power-down mode.
LOP and LON pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF and AVDD=3.3V.
(3) Set LOPS3 bit = “0” after LOP and LON pins rise up. Mono line output exits the power-save mode.
Mono line output is enabled.
(4) Set LOPS3 bit = “1”. Mono line output enters power-save mode.
(5) Set PMLO3 = PMRO3 bits = “0”. Mono line output enters power-down mode.
LOP and LON pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V.
(6) Set LOPS3 bit = “0” after LOP and LON pins fall down. Mono line output exits the power-save mode.
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<Analog Mixing Circuit for Mono Line Output>
DACSL, DACSR, LINS1, RINS1, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4, LOOPSL and LOOPSR bits control
each path switch.
When MDIF1/2/3/4 bits = “1”, RINS1/2/3/4 bits should be “0”.
LINS1 bit
LIN1 pin
+6/0/−6dB
LINS2 bit
LIN2 pin
+6/0/−6dB
LIN3 pin
+6/0/−6dB
LINS3 bit
LINS4 bit
LIN4 pin
+6/0/−6dB
LOOPSL bit
+6/0/−6dB
MIC-Amp Lch
RINS1 bit
RIN1 pin
+6/0/−6dB
RIN2 pin
+6/0/−6dB
M
RINS2 bit
I
X
LOP/LON pins
L3VL1-0 bits
RINS3 bit
RIN3 pin
+6/0/−6dB
RINS4 bit
RIN4 pin
+6/0/−6dB
LOOPSR bit
+6/0/−6dB
MIC-Amp Rch
DATT
Stereo DAC Lch
DACSL bit
0dB
DACSR bit
DATT
Stereo DAC Rch
0dB
Figure 80. Mono Line Output Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “0”)
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LINS1 bit
IN1+/− pins
+6/0/−6dB
LINS2 bit
IN2+/− pins
+6/0/−6dB
LINS3 bit
IN3+/− pins
+6/0/−6dB
IN4+/− pins
+6/0/−6dB
LINS4 bit
LOOPSL bit
LOP/LON pins
+6/0/−6dB
MIC-Amp Lch
L3VL1-0 bits
LOOPSR bit
M
+6/0/−6dB
I
MIC-Amp Rch
DACSL bit
DATT
Stereo DAC Lch
0dB
DATT
Stereo DAC Rch
0dB
X
DACSR bit
Figure 81. Mono Line Output Mixing Circuit (MDIF1=MDIF2=MDIF3=MDIF4 bits = “1”)
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■ System Clock (PCM I/F)
A reference clock of PLLBT is selected among the input clocks to SYNCA, BICKA, SYNCB or BICKB pin. The
required clock to PCM I/F is generated by an internal PLLBT circuit. PLLBT circuit is powered up by PMPCM bit. Input
frequency is selected by PLLBT3-0 bits (Table 76). BCKO2 bit select the output clock frequency of BICKA or BICKB
pin (Table 77). AK4671 does not support master mode for both PCM I/F A and B nor slave mode for both PCM I/F A and
B. Whether PCM I/F A or B should be set as slave mode. When PMPCM bit is “0”, SYNCA, BICKA, SYNCB and
BICKB pins are Hi-Z. Table 78 indicates the output data of SDTOA and SDTOB pins in case of PMPCM bit = “0” and
during lock time in Table 76, respectively. Table 79 indicates the output clock at master mode during lock time in Table
76.
Mode
PLLBT3
PLLBT2
PLLBT1
PLLBT0
Reference Clock
Input Pin
Frequency
R, C at
VCOCBT pin
R
SYNCA
1fs2
6.8k
BICKA
16fs2
10k
BICKA
32fs2
10k
BICKA
64fs2
10k
SYNCB
1fs2
6.8k
BICKB
16fs2
10k
BICKB
32fs2
10k
BICKB
64fs2
10k
BICKA
48fs2
10k
BICKB
48fs2
10k
N/A
Table 76. PLLBT Reference Clock (N/A: Not available)
Note 65. Mode 1 is available at only FMTA1 bit = “0”.
Note 66. Mode 5 is available at only FMTB1 bit = “0”.
0
1
2
3
4
5
6
7
11
15
Others
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
1
1
C
220n
4.7n
4.7n
4.7n
220n
4.7n
4.7n
4.7n
4.7n
4.7n
Lock Time
(max)
260ms
40ms
40ms
40ms
260ms
40ms
40ms
40ms
40ms
40ms
(default)
BICKA/BICKB
Output Frequency
0
16fs2
(default)
1
32fs2
Table 77. BICKA/B Output Frequency
BCKO2 bit
Mode
16bit Linear
8bit A-Law
8bit μ-Law
After PMPCM bit = “0” → “1”
& Before SYNCA/SYNCB Input
L
L
L
H
L
H
Table 78. SDTOA, SDTOB pins Output Data
PMPCM bit = “0”
PMPCM bit = “1”
During Locktime
0000H
11010101b
11111111b
Format
SYNCA, SYNCB
BICKA, BICKB
Except for I2S
L
L
I2S
H
L
Table 79. Output Clock during Lock Time
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a) PLLBT reference clock: SYNCA or BICKA pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCA or BICKA. Generated clocks are output via
SYNCB and BICKB pins.
AK4671
SYNCA
BICKA
Phone Module
1fs2
≥ 16fs2
SYNC
BICK
SDTOA
SDTI
SDTIA
SDTO
Bluetooth Module
SYNCB
BICKB
1fs2
16fs2 or 32fs2
SYNC
BICK
SDTOB
SDTI
SDTIB
SDTO
Figure 82. PCM I/F (PLLBT Reference Clock: SYNCA or BICKA pin)
b) PLLBT reference clock: SYNCB or BICKB pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCB or BICKB. Generated clocks are output via
SYNCA and BICKA pins.
AK4671
SYNCA
BICKA
Phone Module
1fs2
16fs2 or 32fs2
SYNC
BICK
SDTOA
SDTI
SDTIA
SDTO
Bluetooth Module
SYNCB
BICKB
1fs2
≥ 16fs2
SYNC
BICK
SDTOB
SDTI
SDTIB
SDTO
Figure 83. PCM I/F (PLLBT Reference Clock: SYNCB or BICKB pin)
PLLBT should always be powered-up (PMPCM bit = “1”) whenever SRC-A or SRC-B is in operation (PMSRA bit = “1”
or PMSRB bit = “1”). If PLLBT is powered-down, the AK4671 may draw excess current and it is not possible to operate
properly because utilizes dynamic refreshed logic internally. If PLLBT is powered-down, SRC-A, SRC-B and SRC-C
should be in the power-down mode (PMSRA=PMSRB bits = “0”).
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■ PCM I/F Master Mode/Slave Mode
The PLLBT2 bit selects either master or slave mode (Table 80). When either PCM I/F A or PCM I/F B is set in slave
mode, the other is set in master mode. (For example, when PCM I/F B is set in slave mode, PCM I/F A is set in master
mode.) When the AK4671 is power-down mode (PDN pin = “L”) or PMPCM bit = “0”, each clock pins (SYNCA,
BICKA, SYNCB, BICKB) of PCM I/F become a Hi-Z (Table 81).
PLLBT3-0 bits should be set when PMPCM bit = “0” to avoid shorting out of the slave mode clock pins and master mode
clock output.
After setting the PDN pin = “H”, the PCM I/F clock pins are the Hi-Z state until PMPCM bit becomes “1”. The PCM I/F
clock pins of master mode should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the
floating state.
PLLBT2 bit
0
1
PCM I/F A
Slave Mode
Master Mode
PDN pin
L
H
SYNCA, BICKA pins
PCM I/F B
SYNCB, BICKB pins
Input
Master Mode
Output
Output
Slave Mode
Input
Table 80. Select PCM I/F Master/Slave Mode
PMPCM bit
0
1
(default)
SYNCA, BICKA pin
SYNCB, BICKB pin
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I/O Select by PLLBT2 bit I/O Select by PLLBT2 bit
(Table 80)
(Table 80)
Table 81. PCM I/F Clock I/O State
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■ PCM I/F A & B Format
AK4671 supports dual PCM I/F (PCM I/F A & PCM I/F B) that supports 3 kind of I/F (16bit Linear, 8bit A-Law and 8bit
μ-Law) independently (Table 82 and Table 83).
Mode
0
1
2
3
LAWA1
LAWA0
Format
0
0
16bit Linear
0
1
N/A
1
0
8bit A-Law
1
1
8bit μ-Law
Table 82. PCM I/F A Mode (N/A: Not available)
Mode
0
1
2
3
LAWB1
LAWB0
Format
0
0
16bit Linear
0
1
N/A
1
0
8bit A-Law
1
1
8bit μ-Law
Table 83. PCM I/F B Mode (N/A: Not available)
(default)
(default)
Four types of data formats are available and are selected by setting the FMTA1-0 and FMTB1-0 bits independently (Table
84 and Table 85). In 16bit Linear mode, the serial data is MSB first, 2’s complement format. In 8bit A-Law and μ-Law
Mode, the serial data is MSB first. PCM I/F formats can be used in both master and slave modes. SYNCA/B and
BICKA/B are output from the AK4671 in master mode, but must be input to the AK4671 in slave mode.
Mode
0
1
2
3
FMTA1
0
0
1
1
FMTA0
0
1
0
1
Format
BICKA
Short Frame Sync
≥ 16fs2
Long Frame Sync
≥ 16fs2
MSB justified
≥ 32fs2
I2S
≥ 32fs2
Table 84. PCM I/F A Format
Figure
See Table 86
See Table 88
Figure 92
Figure 93
Mode
0
1
2
3
FMTB1
0
0
1
1
FMTB0
0
1
0
1
Format
BICKB
Short Frame Sync
≥ 16fs2
Long Frame Sync
≥ 16fs2
MSB justified
≥ 32fs2
I2S
≥ 32fs2
Table 85. PCM I/F B Format
Figure
See Table 87
See Table 89
Figure 92
Figure 93
(default)
(default)
In modes 2 and 3, the SDTOA/B is clocked out on the falling edge (“↓”) of BICKA/B and the SDTIA/B is latched on the
rising edge (“↑”).
In Modes 0 and 1, PCM I/F A timing is changed by BCKPA and MSBSA bits, and PCM I/F B timing is changed by
BCKPB and MSBSB bits.
When BCKPA bit = “0”, the SDTOA is clocked out on the rising edge (“↑”) of BICKA and the SDTIA is latched on the
falling edge (“↓”). When BCKPA bit = “1”, the SDTOA is clocked out on the falling edge (“↓”) of BICKA and the
SDTIA is latched on the rising edge (“↑”).
MSBSA bit can shift the MSB position of SDTOA and SDTIA by half period of BICKA.
When BCKPB bit = “0”, the SDTOB is clocked out on the rising edge (“↑”) of BICKB and the SDTIB is latched on the
falling edge (“↓”). When BCKPB bit = “1”, the SDTOB is clocked out on the falling edge (“↓”) of BICKB and the
SDTIB is latched on the rising edge (“↑”).
MSBSB bit can shift the MSB position of SDTOB and SDTIB by half period of BICKB.
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MSBSA
BCKPA
0
0
0
1
1
0
1
1
MSBSB
BCKPB
0
0
0
1
1
0
1
1
MSBSA
BCKPA
0
0
0
1
1
0
1
1
MSBSB
BCKPB
0
0
0
1
1
0
1
1
Data Interface Format
MSB of SDTOA is output by next rising edge (“↑”) of the falling edge (“↓”) of BICKA
after the rising edge (“↑”) of SYNCA. MSB of SDTIA is latched by the falling edge (“↓”) of
the BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by next falling edge (“↓”) of the rising edge (“↑”) of BICKA
after the rising edge (“↑”) of SYNCA. MSB of SDTIA is latched by the rising edge (“↑”) of
the BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the 2nd rising edge (“↑”) of BICKA after the rising edge (“↑”)
of SYNCA. MSB of SDTIA is latched by the falling edge (“↓”) of the BICKA just after the
output timing of SDTOA’s MSB.
MSB of SDTOA is output by the 2nd falling edge (“↓”) of BICKA after the rising edge
(“↑”) of SYNCA. MSB of SDTIA is latched by the rising edge (“↑”) of the BICKA just
after the output timing of SDTOA’s MSB.
Table 86. PCM I/F A Format in Mode 0
Data Interface Format
MSB of SDTOB is output by next rising edge (“↑”) of the falling edge (“↓”) of BICKB after
the rising edge (“↑”) of SYNCB. MSB of SDTIB is latched by the falling edge (“↓”) of the
BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by next falling edge (“↓”) of the rising edge (“↑”) of BICKB after
the rising edge (“↑”) of SYNCB. MSB of SDTIB is latched by the rising edge (“↑”) of the
BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the 2nd rising edge (“↑”) of BICKB after the rising edge (“↑”)
of SYNCB. MSB of SDTIB is latched by the falling edge (“↓”) of the BICKB just after the
output timing of SDTOB’s MSB.
MSB of SDTOB is output by the 2nd falling edge (“↓”) of BICKB after the rising edge
(“↑”) of SYNCB. MSB of SDTIB is latched by the rising edge (“↑”) of the BICKB just after
the output timing of SDTOB’s MSB.
Table 87. PCM I/F B Format in Mode 0
Data Interface Format
MSB of SDTOA is output by the rising edge (“↑”) of SYNCA. MSB of SDTIA is latched by
the falling edge (“↓”) of the BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the rising edge (“↑”) of SYNCA. MSB of SDTIA is latched by
the rising edge (“↑”) of the BICKA just after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the rising edge (“↑”) of the first BICKA after the rising edge
(“↑”) of SYNCA. MSB of SDTIA is latched by the falling edge (“↓”) of the BICKA just
after the output timing of SDTOA’s MSB.
MSB of SDTOA is output by the falling edge (“↓”) of the first BICKA after the rising edge
(“↑”) of SYNCA. MSB of SDTIA is latched by the rising edge (“↑”) of the BICKA just
after the output timing of SDTOA’s MSB.
Table 88. PCM I/F A Format in Mode 1
Data Interface Format
MSB of SDTOB is output by the rising edge (“↑”) of SYNCB. MSB of SDTIB is latched by
the falling edge (“↓”) of the BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the rising edge (“↑”) of SYNCB. MSB of SDTIB is latched by
the rising edge (“↑”) of the BICKB just after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the rising edge (“↑”) of the first BICKB after the rising edge
(“↑”) of SYNCB. MSB of SDTIB is latched by the falling edge (“↓”) of the BICKB just
after the output timing of SDTOB’s MSB.
MSB of SDTOB is output by the falling edge (“↓”) of the first BICKB after the rising edge
(“↑”) of SYNCB. MSB of SDTIB is latched by the rising edge (“↑”) of the BICKB just after
the output timing of SDTOB’s MSB.
Table 89. PCM I/F B Format in Mode 1
MS0666-E-02
Figure
Figure 84
Figure 85
Figure 86
Figure 87
Figure
Figure 84
Figure 85
Figure 86
Figure 87
Figure
Figure 88
Figure 89
Figure 90
Figure 91
Figure
Figure 88
Figure 89
Figure 90
Figure 91
2010/06
- 104 -
[AK4671]
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
Don’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
Don’t Care
D7
D6
Don’t Care D7
D6
Figure 84. Timing of Short Frame Sync (MSBSA bit = “0”, BCKPA bit = “0”)
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
D on’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D on’t Care
D7
D6
D7
D6
Figure 85. Timing of Short Frame Sync (MSBSA bit = “0”, BCKPA bit = “1”)
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
D on’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D on’t Care
D7
D6
D7
D6
Figure 86. Timing of Short Frame Sync (MSBSA bit = “1”, BCKPA bit = “0”)
MS0666-E-02
2010/06
- 105 -
[AK4671]
1/fs2
SYNCA
BICKA
(16bit Linear)
SDTOA
SDTIA
D on’t Care
(8bit A-Law/μ-Law)
SDTOA
SDTIA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
Don’t Care
D on’t Care
Don’t Care
D7
D6
D7
D6
Figure 87. Timing of Short Frame Sync (MSBSA bit = “1”, BCKPA bit = “1”)
1/fs2
SYNCA
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D5
D7
D6
D5
Figure 88. Timing of Long Frame Sync (MSBSA bit = “0”, BCKPA bit = “0”)
1/fs2
SYNCA
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D5
D7
D6
D5
Figure 89. Timing of Long Frame Sync (MSBSA bit = “0”, BCKPA bit = “1”)
MS0666-E-02
2010/06
- 106 -
[AK4671]
1/fs2
SYNCA
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D5
Don’t Care D7
D6
D5
Figure 90. Timing of Long Frame Sync (MSBSA bit = “1”, BCKPA bit = “0”)
1/fs2
SYNCA
(Slave)
BICKA
(16bit Linear)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
Don’t Care D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13
SDTOA
SDTIA
(8bit A-Law/μ-Law)
SDTOA
SDTIA
Don’t Care
D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care D7
D6
D5
D4
D3
D2
D1
D0
Don’t Care
D7
D6
D5
Don’t Care D7
D6
D5
Figure 91. Timing of Long Frame Sync (MSBSA bit = “1”, BCKPA bit = “1”)
MS0666-E-02
2010/06
- 107 -
[AK4671]
SYNCA
BICKA
(32fs2)
SDTOA(o)
SDTIA(i)
BICKA
(64fs2)
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
15 14 13
7 6 5 4 3 2 1 0
15 14 13
7 6 5 4 3 2 1 0
0 1 2 3
15 16 17 18
SDTOA(o)
15 14 13
1 0
SDTIA(i)
15 14 13
1 0
9 10 11 12 13 14 15 0 1
15
Don't Care
31 0 1 2 3
Don't Care
15 16 17 18
15
31 0 1
15
Don't Care
Don't Care
15
15:MSB, 0:LSB
Figure 92. Timing of MSB justified
SYNCA
BICKA
(32fs2)
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
SDTOA(o)
15 14
8 7 6 5 4 3 2 1 0
SDTIA(i)
15 14
8 7 6 5 4 3 2 1 0
BICKA
(64fs2)
0 1 2 3
15 16 17 18
SDTOA(o)
15 14
2 1 0
SDTIA(i)
15 14
2 1 0
31 0 1 2 3
Don't Care
9 10 11 12 13 14 15 0 1
Don't Care
15 16 17 18
31 0 1
Don't Care
15:MSB, 0:LSB
Figure 93. Timing of I2S
MS0666-E-02
2010/06
- 108 -
[AK4671]
■ Phone Path
MIC-Amp
& ALC
A/D
HPF
MIC
HPF
LPF
Stereo
Separation
5-band
Notch
ALC
MIX
SDTO Lch
SDTO Rch
Audio
I/F
SVOLA
D/A
M DATT 5-band
I SMUTE
EQ
X
S
E
L
CPU
SDTI Lch
SDTI Rch
Receiver
Headphone
Speaker
SRC-A
PCM
I/F A
SVOLB
SRC-B
TX
SDTOA
RX
SDTIA
DATT-B
DATT-C
BIVOL
SDTOB
SDTIB
Baseband
PCM
I/F B
B/T
Phone Call TX
Phone Call TX Recording
Phone Call Side Tone
Phone Call RX
Phone Call RX Recording
Figure 94. Internal MIC/SPK or External MIC/HP Phone Call & Recoring
MS0666-E-02
2010/06
- 109 -
[AK4671]
MIC-Amp
& ALC
A/D
HPF
MIC
HPF
LPF
Stereo
Separation
5-band
Notch
ALC
MIX
SDTO Lch
SDTO Rch
Audio
I/F
SVOLA
D/A
M DATT 5-band
I SMUTE
EQ
X
S
E
L
CPU
SDTI Lch
SDTI Rch
Receiver
Headphone
Speaker
SRC-A
PCM
I/F A
SVOLB
SRC-B
TX
SDTOA
RX
SDTIA
DATT-B
DATT-C
BIVOL
SDTOB
SDTIB
Baseband
PCM
I/F B
B/T
Phone Call TX
Phone Call TX Recording
Phone Call Side Tone
Phone Call RX
Phone Call RX Recording
Figure 95. B/T Headset Phone Call & Recording
MS0666-E-02
2010/06
- 110 -
[AK4671]
■ General Purpose Output
AK4671 supports General Purpose Output Pin (GPO) to control the external component.
In the case of GPOM1 bit = “0”, GPO1 pin goes to “H” at GPOE1 bit = “1”.
GPOE1 bit
GPO1 pin
0
L
(default)
1
H
Table 90. General Purpose Output 1 Pin Control (at GPOM1 bit = “0”)
In the case of GPOM1 bit = “1”, GPO1 pin goes to “H” if the input level of the channel selected by A0 bit (SAIN1 or
SAIN2 pin) is higher than the reference voltage that is input to the SAIN3 pin. In the case of GPOM1 bit = “1”, the
reference voltage input to SAIN3 pin should be lower than 0.5 x SAVDD.
SAIN1/2 pin
GPO1 pin
< SAIN3 pin
L
(default)
H
≥ SAIN3 pin
Table 91. General Purpose Output 1 Pin Control (at GPOM1 bit = “1”)
In the case of GPOM2 bit = “0”, GPO2 pin goes to “H” at GPOE2 bit = “0”.
GPOE2 bit
GPO2 pin
0
L
(default)
1
H
Table 92. General Purpose Output 2 Pin Control (at GPOM2 bit = “0”)
In the case of GPOM2 bit = “1”, GPO2 pin outputs the mic detection result. (Table 21)
Input Level of MDT pin
≥ 0.075 x AVDD
< 0.050 x AVDD
GPO2 pin
DTMIC bit
H
1
L
0
Table 21. Microphone Detection Result
MS0666-E-02
Result
Mic (Headset)
No Mic (Headphone)
2010/06
- 111 -
[AK4671]
■ SAR 10bit ADC
The AK4671 incorporates a 10-bit successive approximation resistor A/D converter for DC measurement.
The A/D converter output is a straight binary format as shown in Table 93:
Input Voltage
(AVDD−1.5LSB) ~ AVDD
(AVDD−2.5LSB) ~ (AVDD−1.5LSB)
:
0.5LSB ~ 1.5LSB
0 ~ 0.5LSB
Table 93. Output Code
Output Code
3FFH
3FEH
:
001H
000H
When PMSAD bit is set to “1”, 10bit ADC is powered-up. When the control register is read, A/D conversion is executed
and data is output. In case of 4-wire serial control mode, 10bit A/D data is output from 9th to 18th CCLK clock when 4th
bit is set to “1” just after R/W bit.
10bit ADC supports 3 kinds of analog input. A1-0 bits select the measurement modes.
Mode
0
1
2
3
A1
A0
Input Channel
0
0
SAIN1
(default)
0
1
SAIN2
1
0
SAIN3
1
1
N/A
Table 94. SAR ADC Measurement Mode (N/A: Not available)
MS0666-E-02
2010/06
- 112 -
[AK4671]
<SAR ADC Execute Sequence (in case that the interrupt function is not used.)>
[4-wire Serial Mode]
(1) Select the measurement mode by A1-0 bits and set PMSAD bit = “1” to power-up SAR ADC.
(2) Input “1” at the 4th bit just after R/W bit so that A/D conversion is executed and 10bit A/D data is output from 9th to
18th CCLK clock.
[I2C Mode]
(1) Select the measurement mode by A1-0 bits and set PMSAD bit = “1” to power-up SAR ADC.
(2) Read Addr=5BH so that A/D conversion is executed and MSB 8bit data is output.
(3) Continuously read Addr=5CH then LSB 2bit data is output.
<SAR ADC Execute Sequence (in case that the interrupt function is used.)>
[4-wire Serial Mode]
(1) GPOM1 bit should be set to “1”. The GPO1 pin can be used as the interrupt output pin.
(2) Select the measurement mode by A0 bit.
(3) The GPO1 pin goes to “H” when the input DC voltage of SAIN1 or SAIN2 pin (selected by A0 bit) is higher than the
input voltage of SAIN3 pin.
(4) After CPU detects GPO1 pin = “H”, set GPOM1 bit = “0” and PMSAD bit = “1” to power-up SAR ADC.
(5) Input “1” at the 4th bit just after R/W bit so that A/D conversion is executed and 10bit A/D data is output from 9th to
18th CCLK clock.
[I2C Mode]
(1) GPOM1 bit should be set to “1”. The GPO1 pin can be used as the interrupt output pin.
(2) Select the measurement mode by A0 bit.
(3) The GPO1 pin goes to “H” when the input DC voltage of SAIN1 or SAIN2 pin (selected by A0 bit) is higher than the
input voltage of SAIN3 pin.
(4) After CPU detects GPO1 pin = “H”, set GPOM1 bit = “0” and PMSAD bit = “1” to power-up SAR ADC.
(5) Read Addr=5BH so that A/D conversion is executed and MSB 8bit data is output.
(6) Continuously read Addr=5CH then LSB 2bit data is output.
MS0666-E-02
2010/06
- 113 -
[AK4671]
■ Serial Control Interface
(1) 4-wire Serial Control Mode (I2C pin = “L”)
Internal registers may be written by using the 4-wire µP interface pins (CSN, CCLK, CDTI and CDTO).
In case except for 10bit SAR ADC data read, the data on this interface consists of a 3-bit Chip address (fixed to “100”),
Read/Write (1bit), Register address (MSB first, 7bits) and Control data (MSB first, 8bits).
In case of 10bit SAR ADC data read, the data on this interface consists of a 3-bit Chip address (fixed to “101”),
Read/Write (1bit: fixed to “0”) and SAR ADC Data (MSB first, 10bits).
Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. Address and data
are latched on the 24th CCLK rising edge (“↑”) after CSN falling edge (“↓”) for write operations and CDTO bit goes to
Hi-Z after CSN rising edge (“↑”). CSN should be set to “H” once after 24th CCLK for each address. The clock speed of
CCLK is 5MHz (max). The value of internal registers is initialized at PDN pin = “L”.
CSN
0
CCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
17
18
19
20
21
22
23
Clock,
"H" or "L"
Clock,
"H" or "L"
"H" or "L"
CDTI
"H" or "L"
C2 C1 R/W C0
WRITE
0
0
0
0
0
A6
A5
A4
A3
A2
A1
A0 D7 D6 D5
D4 D3 D2 D1 D0
0
0
0
0
0
A6
A5
A4
A3
A2
A1
A0 D7 D6
D4 D3 D2 D1 D0
Hi-Z
CDTO
"H" or "L"
READ
(except for
10bit SAR ADC Data)
CDTI
"H" or "L"
C2 C1 R/W C0
Hi-Z
CDTO
D7 D6
D5
D5 D4 D3 D2 D1 D0
Hi-Z
C2-C0: Chip Address (Fixed to “100”)
R/W: READ/WRITE (0: READ, 1: WRITE)
A6-A0: Register Address
D7-D0: Control Data
Figure 96. Serial Control I/F Timing (Except for 10bit SAR ADC Data)
CSN
0
CCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
CDTI
CDTO
18
19
20
21
22
23
Clock,
"H" or "L"
"H" or "L"
"H" or "L"
READ
(10bit SAR ADC Data)
17
Clock,
"H" or "L"
C2 C1 R/W C0
Hi-Z
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
D9 D8 D7
D6 D5 D4 D3 D2
D1 D0
0
0
0
0
0
0
Hi-Z
C2-C0: Chip Address (Fixed to “101”)
R/W: READ/WRITE (Fixed to “0”: READ Only)
D9-D0: SAR ADC Data
Figure 97. Serial Control I/F Timing (10bit SAR ADC Data)
MS0666-E-02
2010/06
- 114 -
[AK4671]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4671 supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected
to (DVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 98 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 105). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit).
This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits
(Figure 99). If the slave address matches that of the AK4671, the AK4671 generates an acknowledge and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 106). A R/W bit value of “1” indicates that the read operation is to be executed. A “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4671. The format is MSB first, and the most significant
1-bit is fixed to “0” (Figure 100). The data after the second byte contains control data. The format is MSB first, 8bits
(Figure 101). The AK4671 generates an acknowledge after each byte is received. A data transfer is always terminated by
a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a
STOP condition (Figure 105).
The AK4671 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4671
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 5AH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 107) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
A
C
K
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 98. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
1
CAD0
R/W
A1
A0
D1
D0
(The CAD0 should match with CAD0 pin.)
Figure 99. The First Byte
0
A6
A5
A4
A3
A2
Figure 100. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 101. Byte Structure after the second byte
MS0666-E-02
2010/06
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[AK4671]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4671. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 7-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 5AH prior to generating a stop condition, the address
counter will “roll over” to 00H and the data of 00H will be read out.
The AK4671 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ (except for 10bit SAR ADC Data)
The AK4671 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4671 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but instead generates a stop condition, the AK4671
ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
P
MA
AC
SK
T
E
R
MN
AA
SC
T
EK
R
Figure 102. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit “1”. The AK4671 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but instead generates a stop condition, the AK4671 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S K
T
E
R
A
C
K
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 103. RANDOM ADDRESS READ (Except for 10bit SAR ADC Data)
When SAR ADC data is read, 5BH should be set as register address and 2 byte data should be read by RANDOM
ADDRESS READ, then stop condition should be input. A/D readout format is MSB first, 2 byte width. Upper 10bits are
valid on 2byte (16-bit), and lower 6bits are filled with zero.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(5BH)
A
C
K
S
T
O
P
R/W="1"
A
C
K
Data(D9-2)
A
C
K
Data(D1-0)
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 104. RANDOM ADDRESS READ (10bit SAR ADC Data)
MS0666-E-02
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[AK4671]
SDA
SCL
S
P
start condition
stop condition
Figure 105. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 106. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 107. Bit Transfer on the I2C-Bus
MS0666-E-02
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[AK4671]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Register Name
AD/DA Power Management
PLL Mode Select 0
PLL Mode Select 1
Format Select
MIC Signal Select
MIC Amp Gain
Mixing Power Management 0
Mixing Power Management
Output Volume Control
LOUT1 Signal Select
ROUT1 Signal Select
LOUT2 Signal Select
ROUT2 Signal Select
LOUT3 Signal Select
ROUT3 Signal Select
LOUT1 Power Management
LOUT2 Power Management
LOUT3 Power Management
Lch Input Volume Control
Rch Input Volume Control
ALC Reference Select
Digital Mixing Control
ALC Timer Select
ALC Mode Control
Mode Control 1
Mode Control 2
Lch Output Volume Control
Rch Output Volume Control
Side Tone A Control
Digital Filter Select
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
FIL2 Co-efficient 0
FIL2 Co-efficient 1
FIL2 Co-efficient 2
FIL2 Co-efficient 3
D7
PMDAR
FS3
BTCLK
0
MDIF4
D6
PMDAL
FS2
LP
0
MDIF3
D5
PMADR
FS1
BCKO
0
MDIF2
D4
PMADL
FS0
PS1
SDOD
MDIF1
MGNR3
MGNR2
MGNR1
MGNR0
MGNL3
MGNL2
MGNL1
MGNL0
0
0
0
0
0
DTMIC
PMLOOPR
PMLOOPL
PMAINR4
PMAINL4
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMAINR1
PMAINL1
HPG3
L1G1
L2G1
L3G1
L4G1
LPG1
0
0
0
L3VL1
IVL7
IVR7
REF7
HPG2
L1G0
L2G0
L3G0
L4G0
LPG0
0
0
HPG1
LOOPL
LOOPR
HPG0
LINL4
RINR4
LINH4
RINH4
LINS4
RINS4
LOOPM
IVL4
IVR4
REF4
0
LINL3
RINR3
LINH3
RINH3
LINS3
RINS3
LOM
LOM2
LOM3
IVL3
IVR3
REF3
L1VL2
LINL2
RINR2
LINH2
RINH2
LINS2
RINS2
LOPS1
MUTEN
LOPS3
IVL2
IVR2
REF2
L1VL1
LINL1
RINR1
LINH1
RINH1
LINS1
RINS1
PMRO1
PMRO2
PMRO3
IVL1
IVR1
REF1
L1VL0
DACL
DACR
DACHL
DACHR
DACSL
DACSR
PMLO1
PMLO2
PMLO3
IVL0
IVR0
REF0
LOOPHL
LOOPHR
LOOPSL
LOOPSR
RCV
D2
PMMICL
PLL3
PS0
MSBS
INR1
PLL2
MCKO
BCKP
INR0
D1
PMMP
PLL1
M/S
DIF1
INL1
D0
PMVCM
PLL0
PMPLL
DIF0
INL0
PMRO2S
PMLO2S
L3VL0
IVL6
IVR6
REF6
LODIF
IVL5
IVR5
REF5
SRMXR1
SRMXR0
SRMXL1
SRMXL0
PFMXR1
PFMXR0
PFMXL1
PFMXL0
0
0
DAM
SRA1
OVL7
OVR7
0
GN1
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
F1A7
F1AS
F1B7
0
F2A7
0
F2B7
0
RFST1
ZELMN
MIXD
SRA0
OVL6
OVR6
0
GN0
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
F1A6
0
F1B6
0
F2A6
0
F2B6
0
RFST0
LMAT1
SDIM1
BIV2
OVL5
OVR5
SVAR2
LPF
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
F1A5
F1A13
F1B5
F1B13
F2A5
F2A13
F2B5
F2B13
WTM2
LMAT0
SDIM0
BIV1
OVL4
OVR4
SVAR1
HPF
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
F1A4
F1A12
F1B4
F1B12
F2A4
F2A12
F2B4
F2B12
WTM1
RGAIN1
EQ
BIV0
OVL3
OVR3
SVAR0
EQ0
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
F1A3
F1A11
F1B3
F1B11
F2A3
F2A11
F2B3
F2B11
WTM0
RGAIN0
ADM
SMUTE
OVL2
OVR2
SVAL2
FIL3
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
F1A2
F1A10
F1B2
F1B10
F2A2
F2A10
F2B2
F2B10
ZTM1
LMTH1
IVOLC
OVTM
OVL1
OVR1
SVAL1
0
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
F1A1
F1A9
F1B1
F1B9
F2A1
F2A9
F2B1
F2B9
ZTM0
LMTH0
ALC
OVOLC
OVL0
OVR0
SVAL0
PFSEL
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
F1A0
F1A8
F1B0
F1B8
F2A0
F2A8
F2B0
F2B8
MS0666-E-02
LOOPM2
LOOPM3
D3
PMMICR
2010/06
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[AK4671]
Addr
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
Register Name
Digital Filter Select 2
Reserved
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
EQ Control 10kHz
PCM I/F Control 0
PCM I/F Control 1
PCM I/F Control 2
Digital Volume B Control
Digital Volume C Control
Side Tone Volume Control
Digital Mixing Control
SAR ADC Control
D7
0
0
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
EQB3
EQD3
0
GPOM2
SDOAD
SDOBD
BVL7
CVL7
0
SDOR1
0
D6
0
0
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
EQB2
EQD2
0
GPOE2
BCKO2
PLLBT3
BVL6
CVL6
0
SDOR0
0
D5
0
0
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
EQB1
EQD1
0
PLLBT2
MSBSA
MSBSB
BVL5
CVL5
0
SDOL1
0
D4
EQ5
0
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
EQB0
EQD0
0
PLLBT1
BCKPA
BCKPB
BVL4
CVL4
0
SDOL0
GPOM1
D3
EQ4
0
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
EQA3
EQC3
EQE3
PLLBT0
LAWA1
LAWB1
BVL3
CVL3
SDOA
BVMX1
GPOE1
D2
EQ3
0
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
EQA2
EQC2
EQE2
PMPCM
LAWA0
LAWB0
BVL2
CVL2
SVB2
BVMX0
A1
D1
EQ2
0
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
EQA1
EQC1
EQE1
PMSRB
FMTA1
FMTB1
BVL1
CVL1
SVB1
SBMX1
A0
D0
EQ1
0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
EQA0
EQC0
EQE0
PMSRA
FMTA0
FMTB0
BVL0
CVL0
SVB0
SBMX0
PMSAD
Note 67. PDN pin = “L” resets the registers to their default values.
Note 68. The bits defined as 0 must contain a “0” value.
Note 69. Addresses 1EH to 2FH and 32H to 4FH cannot be read.
MS0666-E-02
2010/06
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[AK4671]
■ Register Definitions
Addr
00H
Register Name
AD/DA Power Management
R/W
(default)
D7
PMDAR
R/W
0
D6
PMDAL
R/W
0
D5
PMADR
R/W
0
D4
PMADL
R/W
0
D3
D2
PMMICR
PMMICL
R/W
0
R/W
0
D1
PMMP
R/W
0
D0
PMVCM
R/W
0
PMVCM: VCOM Power Management
0: Power down (default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits are “0”.
PMMP: MPWR pin Power Management
0: Power down: Hi-Z (default)
1: Power up
PMMICL: MIC-Amp Lch Power Management
0: Power down (default)
1: Power up
PMMICR: MIC-Amp Rch Power Management
0: Power down (default)
1: Power up
PMADL: ADC Lch Power Management
0: Power down (default)
1: Power up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
PMADR: ADC Rch Power Management
0: Power down (default)
1: Power up
PMDAL: DAC Lch Power Management
0: Power down (default)
1: Power up
PMDAR: DAC Rch Power Management
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless of setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0”, all blocks are powered-down. The register values remain unchanged. Power
supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA), PDN pin should be “L”.
When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks
must always be present.
MS0666-E-02
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[AK4671]
Addr
01H
Register Name
PLL Mode Select 0
R/W
Default
D7
FS3
R/W
1
D6
FS2
R/W
1
D5
FS1
R/W
1
D4
FS0
R/W
1
D3
PLL3
R/W
0
D2
PLL2
R/W
1
D1
PLL1
R/W
1
D0
PLL0
R/W
0
PLL3-0: PLL Reference Clock Select (Table 4)
Default: “0110”(MCKI pin, 12MHz)
FS3-0: Sampling Frequency Select (Table 5 and Table 6) and MCKI Frequency Select (Table 11)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
Addr
02H
Register Name
PLL Mode Select 1
R/W
Default
D7
BTCLK
R/W
0
D6
LP
R/W
0
D5
BCKO
R/W
0
D4
PS1
R/W
0
D3
PS0
R/W
0
D2
MCKO
R/W
0
D1
M/S
R/W
0
D0
PMPLL
R/W
0
PMPLL: PLL Power Management
0: EXT Mode and Power Down (default)
1: PLL Mode and Power up
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
PS1-0: MCKO Output Frequency Select (Table 9)
default: “00”(256fs)
BCKO: BICK Output Frequency Select at Master Mode (Table 10)
LP: Low Power Mode
0: Normal Mode (default)
1: Low Power Mode: available at fs=22.05kHz or less.
BTCLK: Clock Mode of Audio CODEC
0: Synchronized to Audio I/F (default)
1: Synchronized to PCM I/F
BTCLK bit is enabled at only PMPLL bit = “0”. When BTCLK bit is “1”, Audio CODEC and the digital block
(shown in Figure 57) operate by the clock generated by PLLBT.
MS0666-E-02
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[AK4671]
Addr
03H
Register Name
Format Select
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
SDOD
R/W
0
D3
MSBS
R/W
0
D2
BCKP
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
DIF1-0: Audio Interface Format (Table 16)
Default: “10” (Left jutified)
BCKP: BICK Polarity at DSP Mode (Table 17)
“0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (default)
“1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”).
MSBS: LRCK Phase at DSP Mode (Table 17)
“0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (default)
“1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change.
SDOD: SDTO Disable (Table 47)
“0”: Enable (default)
“1”: Disable (“L”)
Addr
04H
Register Name
MIC Signal Select
R/W
Default
D7
MDIF4
R/W
0
D6
MDIF3
R/W
0
D5
MDIF2
R/W
0
D4
MDIF1
R/W
0
D3
INR1
R/W
0
D2
INR0
R/W
0
D1
INL1
R/W
0
D0
INL0
R/W
0
INL1-0: MIC-Amp Lch Input Source Select (Table 18)
Default: “00” (LIN1)
INR1-0: MIC-Amp Rch Input Source Select (Table 18)
Default: “00” (RIN1)
MDIF1: Line1 Input Type Select
0: Single-ended input (LIN1/RIN1 pins: default)
1: Full-differential input (IN1+/IN1− pins)
MDIF2: Line2 Input Type Select
0: Single-ended input (LIN2/RIN2 pins: default)
1: Full-differential input (IN2+/IN2− pins)
MDIF3: Line3 Input Type Select
0: Single-ended input (LIN3/RIN3 pins: default)
1: Full-differential input (IN3+/IN3− pins)
MDIF4: Line4 Input Type Select
0: Single-ended input (LIN4/RIN4 pins: default)
1: Full-differential input (IN4+/IN4− pins)
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[AK4671]
Addr
05H
Register Name
MIC Amp Gain
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
MGNR3
MGNR2
MGNR1
MGNR0
MGNL3
MGNL2
MGNL1
MGNL0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
DTMIC
RD
0
MGNL3-0: MIC-Amp Lch Gain Control (Table 19)
Default: “0101” (0dB)
MGNR3-0: MIC-Amp Rch Gain Control (Table 19)
Default: “0101” (0dB)
Addr
06H
Register Name
Mixing Power Management 0
R/W
Default
D7
0
RD
0
D6
0
RD
0
D1
D0
PMLOOPR
PMLOOPL
R/W
0
R/W
0
PMLOOPL: MIC-Amp Lch Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMLOOPR: MIC-Amp Rch Mixing Circuit Power Management
0: Power down (default)
1: Power up
DTMIC: Microphone Detection Result (Read Only: Table 21)
0: Microphone is not detected. (default)
1: Microphone is detected.
MS0666-E-02
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[AK4671]
Addr
07H
Register Name
Mixing Power Management 1
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
PMAINR4
PMAINL4
PMAINR3
PMAINL3
PMAINR2
PMAINL2
PMAINR1
PMAINL1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D5
HPG1
R/W
1
D4
HPG0
R/W
1
D3
0
RD
0
PMAINL1: LIN1 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINR1: RIN1 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINL2: LIN2 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINR2: RIN2 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINL3: LIN3 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINR3: RIN3 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINL4: LIN4 Mixing Circuit Power Management
0: Power down (default)
1: Power up
PMAINR4: RIN4 Mixing Circuit Power Management
0: Power down (default)
1: Power up
Addr
08H
Register Name
Output Volume Control
R/W
Default
D7
HPG3
R/W
1
D6
HPG2
R/W
0
D2
L1VL2
R/W
1
D1
L1VL1
R/W
0
D0
L1VL0
R/W
1
L1VL2-0: LOUT1/ROUT1 Output Volume Control (Table 67)
Default: “5H” (0dB)
HPG3-0: LOUT2/ROUT2 Output Volume Control (Table 70)
Default: “BH” (0dB)
MS0666-E-02
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Addr
09H
Register Name
LOUT1 Signal Select
R/W
Default
D7
L1G1
R/W
0
D6
L1G0
R/W
0
D5
LOOPL
R/W
0
D4
LINL4
R/W
0
D3
LINL3
R/W
0
D2
LINL2
R/W
0
D1
LINL1
R/W
0
D0
DACL
R/W
0
DACL: Switch Control from DAC Lch to LOUT1
0: OFF (default)
1: ON
When PMLO1 bit is “1”, DACL bit is enabled. When PMLO1 bit is “0”, the LOUT1 pin goes to VSS1.
LINL1: Switch Control from LIN1 to LOUT1
0: OFF (default)
1: ON
LINL2: Switch Control from LIN2 to LOUT1
0: OFF (default)
1: ON
LINL3: Switch Control from LIN3 to LOUT1
0: OFF (default)
1: ON
LINL4: Switch Control from LIN4 to LOUT1
0: OFF (default)
1: ON
LOOPL: Switch Control from MIC-Amp Lch to LOUT1
0: OFF (default)
1: ON
L1G1-0: LIN1/RIN1 Mixing Gain Control (Table 60)
Default: “00” (0dB)
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[AK4671]
Addr
0AH
Register Name
ROUT1 Signal Select
R/W
Default
D7
L2G1
R/W
0
D6
L2G0
R/W
0
D5
LOOPR
R/W
0
D4
RINR4
R/W
0
D3
RINR3
R/W
0
D2
RINR2
R/W
0
D1
RINR1
R/W
0
D0
DACR
R/W
0
DACR: Switch Control from DAC Rch to ROUT1
0: OFF (default)
1: ON
When PMRO1 bit is “1”, DACR bit is enabled. When PMRO1 bit is “0”, the ROUT1 pin goes to VSS1.
RINR1: Switch Control from RIN1 to ROUT1
0: OFF (default)
1: ON
RINR2: Switch Control from RIN2 to ROUT1
0: OFF (default)
1: ON
RINR3: Switch Control from RIN3 to ROUT1
0: OFF (default)
1: ON
RINR4: Switch Control from RIN4 to ROUT1
0: OFF (default)
1: ON
LOOPR: Switch Control from MIC-Amp Rch to ROUT1
0: OFF (default)
1: ON
L2G1-0: LIN2/RIN2 Mixing Gain Control (Table 61)
Default: “00” (0dB)
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Addr
0BH
Register Name
LOUT2 Signal Select
R/W
Default
D7
L3G1
R/W
0
D6
L3G0
R/W
0
D5
LOOPHL
R/W
0
D4
LINH4
R/W
0
D3
LINH3
R/W
0
D2
LINH2
R/W
0
D1
LINH1
R/W
0
D0
DACHL
R/W
0
DACHL: Switch Control from DAC Lch to LOUT2
0: OFF (default)
1: ON
LINH1: Switch Control from LIN1 to LOUT2
0: OFF (default)
1: ON
LINH2: Switch Control from LIN2 to LOUT2
0: OFF (default)
1: ON
LINH3: Switch Control from LIN3 to LOUT2
0: OFF (default)
1: ON
LINH4: Switch Control from LIN4 to LOUT2
0: OFF (default)
1: ON
LOOPHL: Switch Control from MIC-Amp Lch to LOUT2
0: OFF (default)
1: ON
L3G1-0: LIN3/RIN3 Mixing Gain Control (Table 62)
Default: “00” (0dB)
MS0666-E-02
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[AK4671]
Addr
0CH
Register Name
ROUT2 Signal Select
R/W
Default
D7
L4G1
R/W
0
D6
L4G0
R/W
0
D5
LOOPHR
R/W
0
D4
RINH4
R/W
0
D3
RINH3
R/W
0
D2
RINH2
R/W
0
D1
RINH1
R/W
0
D0
DACHR
R/W
0
DACHR: Switch Control from DAC Rch to ROUT2
0: OFF (default)
1: ON
RINH1: Switch Control from RIN1 to ROUT2
0: OFF (default)
1: ON
RINH2: Switch Control from RIN2 to ROUT2
0: OFF (default)
1: ON
RINH3: Switch Control from RIN3 to ROUT2
0: OFF (default)
1: ON
RINH4: Switch Control from RIN4 to ROUT2
0: OFF (default)
1: ON
LOOPHR: Switch Control from MIC-Amp Rch to ROUT2
0: OFF (default)
1: ON
L4G1-0: LIN4/RIN4 Mixing Gain Control (Table 63)
Default: “00” (0dB)
MS0666-E-02
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[AK4671]
Addr
0DH
Register Name
LOUT3 Signal Select
R/W
Default
D7
LPG1
R/W
0
D6
LPG0
R/W
0
D5
LOOPSL
R/W
0
D4
LINS4
R/W
0
D3
LINS3
R/W
0
D2
LINS2
R/W
0
D1
LINS1
R/W
0
D0
DACSL
R/W
0
DACSL: Switch Control from DAC Lch to LOUT3
0: OFF (default)
1: ON
When PMLO3 bit is “1”, DACSL bit is enabled. When PMLO3 bit is “0”, the LOUT3 pin goes to VSS1.
LINS1: Switch Control from LIN1 to LOUT3
0: OFF (default)
1: ON
LINS2: Switch Control from LIN2 to LOUT3
0: OFF (default)
1: ON
LINS3: Switch Control from LIN3 to LOUT3
0: OFF (default)
1: ON
LINS4: Switch Control from LIN4 to LOUT3
0: OFF (default)
1: ON
LOOPSL: Switch Control from MIC-Amp Lch to LOUT3
0: OFF (default)
1: ON
LPG1-0: MIC-Amp Mixing Gain Control (Table 64)
Default: “00” (0dB)
MS0666-E-02
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[AK4671]
Addr
0EH
Register Name
ROUT3 Signal Select
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
LOOPSR
R/W
0
D4
RINS4
R/W
0
D3
RINS3
R/W
0
D2
RINS2
R/W
0
D1
RINS1
R/W
0
D0
DACSR
R/W
0
DACSR: Switch Control from DAC Rch to ROUT3
0: OFF (default)
1: ON
When PMRO3 bit is “1”, DACR bit is enabled. When PMRO3 bit is “0”, the ROUT3 pin goes to VSS1.
RINS1: Switch Control from RIN1 to ROUT3
0: OFF (default)
1: ON
RINS2: Switch Control from RIN2 to ROUT3
0: OFF (default)
1: ON
RINS3: Switch Control from RIN3 to ROUT3
0: OFF (default)
1: ON
RINS4: Switch Control from RIN4 to ROUT3
0: OFF (default)
1: ON
LOOPSR: Switch Control from MIC-Amp Rch to ROUT3
0: OFF (default)
1: ON
MS0666-E-02
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[AK4671]
Addr
0FH
Register Name
LOUT1 Power Management
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
RCV
R/W
0
D4
LOOPM
R/W
0
D3
LOM
R/W
0
D2
LOPS1
R/W
0
D1
PMRO1
R/W
0
D0
PMLO1
R/W
0
PMLO1: LOUT1 Power Management
0: Power down (default)
1: Power up
PMRO1: ROUT1 Power Management
0: Power down (default)
1: Power up
LOPS1: LOUT1/ROUT1 Power Save Mode
0: Normal Operation (default)
1: Power Save Mode
LOM: Mono Mixing from DAC to LOUT1/ROUT1
0: Stereo Mixing (default)
1: Mono Mixing
LOOPM: Mono Mixing from MIC-Amp to LOUT1/ROUT1
0: Stereo Mixing (default)
1: Mono Mixing
RCV: Receiver Select
0: Stereo Line Output (LOUT1/ROUT1 pins) (default)
1: Mono Receiver Output (RCP/RCN pins)
MS0666-E-02
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[AK4671]
Addr
10H
Register Name
LOUT2 Power Management
R/W
Default
D7
0
RD
0
D6
D5
D4
PMRO2S
PMLO2S
LOOPM2
R/W
0
R/W
0
R/W
0
D3
LOM2
R/W
0
D2
MUTEN
R/W
0
D1
PMRO2
R/W
0
D0
PMLO2
R/W
0
PMLO2: LOUT2 Power Management
0: Power down (default)
1: Power up
PMRO2: ROUT2 Power Management
0: Power down (default)
1: Power up
MUTEN: LOUT2/ROUT2 Mute Control
0: Mute (default)
1: Normal operation
LOM2: Mono Mixing from DAC to LOUT2/ROUT2
0: Stereo Mixing (default)
1: Mono Mixing
LOOPM2: Mono Mixing from MIC-Amp to LOUT2/ROUT2
0: Stereo Mixing (default)
1: Mono Mixing
PMLO2S: LOUT2 MIX-Amp Power Management
0: Power down (default)
1: Power up
PMRO2S: ROUT2 MIX-Amp Power Management
0: Power down (default)
1: Power up
MS0666-E-02
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[AK4671]
Addr
11H
Register Name
LOUT3 Power Management
R/W
Default
D7
L3VL1
R/W
1
D6
L3VL0
R/W
0
D5
D4
LODIF
LOOPM3
R/W
0
R/W
0
D3
LOM3
R/W
0
D2
LOPS3
R/W
0
D1
PMRO3
R/W
0
D0
PMLO3
R/W
0
PMLO3: LOUT3 Power Management
0: Power down (default)
1: Power up
PMRO3: ROUT3 Power Management
0: Power down (default)
1: Power up
LOPS3: LOUT3/ROUT3 Power Save Mode
0: Normal Operation (default)
1: Power Save Mode
LOM3: Mono Mixing from DAC to LOUT3/ROUT3
0: Stereo Mixing (default)
1: Mono Mixing
LOOPM3: Mono Mixing from MIC-Amp to LOUT3/ROUT3
0: Stereo Mixing (default)
1: Mono Mixing
LODIF: Lineout Select
0: Single-ended Stereo Line Output (LOUT3/ROUT3 pins) (default)
1: Full-differential Mono Line Output (LOP/LON pins)
L3VL1-0: LOUT3/ROUT3 Output Gain Control (Table 73)
Default: “10” (0dB)
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[AK4671]
Addr
12H
13H
Register Name
Lch Input Volume Control
Rch Input Volume Control
R/W
Default
D7
IVL7
IVR7
R/W
1
D6
IVL6
IVR6
R/W
0
D5
IVL5
IVR5
R/W
0
D4
IVL4
IVR4
R/W
1
D3
IVL3
IVR3
R/W
0
D2
IVL2
IVR2
R/W
0
D1
IVL1
IVR1
R/W
0
D0
IVL0
IVR0
R/W
1
D3
REF3
R/W
0
D2
REF2
R/W
0
D1
REF1
R/W
0
D0
REF0
R/W
1
IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 33)
Default: “91H” (0dB)
Addr
14H
Register Name
ALC Reference Select
R/W
Default
D7
REF7
R/W
1
D6
REF6
R/W
1
D5
REF5
R/W
1
D4
REF4
R/W
0
REF7-0: Reference Value at ALC Recovery Operation (Recording); 0.375dB step, 242 Level (Table 29)
Default: “E1H” (+30.0dB)
Addr
15H
Register Name
Digital Mixing Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
SRMXR1
SRMXR0
SRMXL1
SRMXL0
PFMXR1
PFMXR0
PFMXL1
PFMXL0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D5
RFST0
R/W
0
D4
WTM2
R/W
0
D3
WTM1
R/W
0
D2
WTM0
R/W
0
D1
ZTM1
R/W
0
D0
ZTM0
R/W
0
PFMXL1-0: 5-band EQ Lch Input Mixing 1 (Table 49)
Default: “00” (SDTI)
PFMXR1-0: 5-band EQ Rch Input Mixing 1 (Table 50)
Default: “00” (SDTI)
SRMXL1-0: 5-band EQ Lch Input Mixing 2 (Table 51)
Default: “00” (SDTI)
SRMXR1-0: 5-band EQ Rch Input Mixing 2 (Table 52)
Default: “00” (SDTI)
Addr
16H
Register Name
ALC Timer Select
R/W
Default
D7
0
RD
0
D6
RFST1
R/W
0
ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 26)
Default: “00” (128/fs)
WTM2-0: ALC Recovery Waiting Period (Table 27)
Default: “000” (128/fs)
RFST1-0: ALC First recovery Speed (Table 30)
Default: “00” (4times)
MS0666-E-02
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[AK4671]
Addr
17H
Register Name
ALC Mode Control
R/W
Default
D7
0
RD
0
D6
ZELMN
R/W
0
D5
LMAT1
R/W
0
D4
LMAT0
R/W
0
D3
RGAIN1
R/W
0
D2
RGAIN0
R/W
0
D1
LMTH1
R/W
0
D0
LMTH0
R/W
0
D2
ADM
R/W
0
D1
IVOLC
R/W
1
D0
ALC
R/W
0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 24)
Default: “00”
RGAIN1-0: ALC Recovery GAIN Step (Table 28)
Default: “00”
LMAT1-0: ALC Limiter ATT Step (Table 25)
Default: “00”
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (default)
1: Disable
Addr
18H
Register Name
Mode Control 1
R/W
Default
D7
DAM
R/W
0
D6
MIXD
R/W
0
D5
SDIM1
R/W
0
D4
SDIM0
R/W
0
D3
EQ
R/W
0
ALC: ALC Enable
0: ALC Disable (default)
1: ALC Enable
IVOLC: Input Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0
bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits
control Rch level, respectively.
ADM: Mono Recording (Table 44)
0: Stereo (default)
1: Mono: (L+R)/2
EQ: Select 5-Band Equalizer
0: OFF (default)
1: ON
SDIM1-0: SDTI Input Signal Select (Table 48)
Default: “00” (L=Lch, R=Rch)
MIXD: DAC and SRC-A Mono Mixing (Table 53 and Table 54)
0: L+R (default)
1: (L+R)/2
DAM: DAC Mono Mixing (Table 53)
0: Stereo (default)
1: Mono: (L+R) or (L+R)/2 is selected by MIXD bit.
MS0666-E-02
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[AK4671]
Addr
19H
Register Name
Mode Control 2
R/W
Default
D7
SRA1
R/W
0
D6
SRA0
R/W
0
D5
BIV2
R/W
0
D4
BIV1
R/W
0
D3
BIV0
R/W
0
D2
SMUTE
R/W
0
D1
OVTM
R/W
0
D0
OVOLC
R/W
1
OVOLC: Output Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When OVOLC bit = “1”, OVL7-0 bits control both Lch and Rch volume level, while register values of
OVL7-0 bits are not written to OVR7-0 bits. When OVOLC bit = “0”, OVL7-0 bits control Lch level and
OVR7-0 bits control Rch level, respectively.
OVTM: Digital Volume Transition Time Setting
0: 1061/fs (default)
1: 256/fs
This is the transition time between OVL/R7-0 bits = 00H and FFH.
SMUTE: Soft Mute Control
0: Normal Operation (default)
1: DAC outputs soft-muted
BIV2-0: SDTIB Input Volume Control (Table 41)
Default: “0H” (0dB)
SRA1-0: SRC-A Input Signal Select (Table 54)
Default: “00” (Lch)
Addr
1AH
1BH
Register Name
Lch Output Volume Control
Rch Output Volume Control
R/W
Default
D7
OVL7
OVR7
R/W
0
D6
OVL6
OVR6
R/W
0
D5
OVL5
OVR5
R/W
0
D4
OVL4
OVR4
R/W
1
D3
OVL3
OVR3
R/W
1
D2
OVL2
OVR2
R/W
0
D1
OVL1
OVR1
R/W
0
D0
OVL0
OVR0
R/W
0
D5
SVAR2
R/W
0
D4
SVAR1
R/W
0
D3
SVAR0
R/W
0
D2
SVAL2
R/W
0
D1
SVAL1
R/W
0
D0
SVAL0
R/W
0
OVL7-0, OVR7-0: Output Digital Volume (Table 36)
Default: “18H” (0dB)
Addr
1CH
Register Name
Side Tone A Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
SVAL2-0, SVAR2-0: Side Tone Volume A (SVOLA) (Table 34)
Default: “000” (0dB)
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Addr
1DH
Register Name
Digital Filter Select
R/W
Default
D7
GN1
R/W
0
D6
GN0
R/W
0
D5
LPF
R/W
0
D4
HPF
R/W
0
D3
EQ0
R/W
0
D2
FIL3
R/W
0
D1
HPFAD
R/W
1
D0
PFSEL
R/W
0
PFSEL: Signal Select of Programmable Filter Block (Table 43)
0: ADC Output Data (default)
1: SDTI Input Data
HPFAD: HPF Control of ADC
0: OFF
1: ON (default)
When HPFAD bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPFAD bit is “0”,
HPFAD block is through (0dB).
GN1-0: Gain Select at GAIN block (Table 23)
Default: “00” (0dB)
FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is “0”, FIL3 block
is OFF (MUTE).
EQ0: EQ0 (Gain Compensation Filter) Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ0 bit is “1”, the settings of E0A15-0, E0B13-0 and E0C15-0 bits are enabled. When EQ0 bit is “0”,
EQ0 block is through (0dB).
HPF: HPF Coefficient Setting Enable
0: Disable (default)
1: Enable
When HPF bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPF bit is “0”, HPF block
is through (0dB).
LPF: LPF Coefficient Setting Enable
0: Disable (default)
1: Enable
When LPF bit is “1”, the settings of F2A13-0 and F2B13-0 bits are enabled. When LPF bit is “0”, LPF block
is through (0dB).
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Addr
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
R/W
Default
D7
F3A7
F3AS
F3B7
0
E0A7
E0A15
E0B7
0
E0C7
E0C15
W
0
D6
F3A6
0
F3B6
0
E0A6
E0A14
E0B6
0
E0C6
E0C14
W
0
D5
F3A5
F3A13
F3B5
F3B13
E0A5
E0A13
E0B5
E0B13
E0C5
E0C13
W
0
D4
F3A4
F3A12
F3B4
F3B12
E0A4
E0A12
E0B4
E0B12
E0C4
E0C12
W
0
D3
F3A3
F3A11
F3B3
F3B11
E0A3
E0A11
E0B3
E0B11
E0C3
E0C11
W
0
D2
F3A2
F3A10
F3B2
F3B10
E0A2
E0A10
E0B2
E0B10
E0C2
E0C10
W
0
D1
F3A1
F3A9
F3B1
F3B9
E0A1
E0A9
E0B1
E0B9
E0C1
E0C9
W
0
D0
F3A0
F3A8
F3B0
F3B8
E0A0
E0A8
E0B0
E0B8
E0C0
E0C8
W
0
F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2)
Default: “0000H”
F3AS: FIL3 (Stereo Separation Emphasis Filter) Select
0: HPF (default)
1: LPF
E0A15-0, E0B13-0, E0C15-C0: EQ0 (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1)
Default: “0000H”
Addr
28H
29H
2AH
2BH
Register Name
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
R/W
Default
D7
F1A7
0
F1B7
0
W
D6
F1A6
0
F1B6
0
W
D5
F1A5
F1A13
F1B5
F1B13
W
D4
F1A4
F1A12
F1B4
F1B12
W
D3
F1A3
F1A11
F1B3
F1B11
W
D2
F1A2
F1A10
F1B2
F1B10
W
D1
F1A1
F1A9
F1B1
F1B9
W
D0
F1A0
F1A8
F1B0
F1B8
W
F1A13-0 bits = “1FA9H”, F1B13-0 bits = “20ADH”
F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2)
Default: F1A13-0 bits = “1FA9H”, F1B13-0 bits = “20ADH” ([email protected]=44.1kHz)
Addr
2CH
2DH
2EH
2FH
Register Name
FIL2 Co-efficient 0
FIL2 Co-efficient 1
FIL2 Co-efficient 2
FIL2 Co-efficient 3
R/W
Default
D7
F2A7
0
F2B7
0
W
0
D6
F2A6
0
F2B6
0
W
0
D5
F2A5
F2A13
F2B5
F2B13
W
0
D4
F2A4
F2A12
F2B4
F2B12
W
0
D3
F2A3
F2A11
F2B3
F2B11
W
0
D2
F2A2
F2A10
F2B2
F2B10
W
0
D1
F2A1
F2A9
F2B1
F2B9
W
0
D0
F2A0
F2A8
F2B0
F2B8
W
0
F2A13-0, F2B13-B0: FIL2 (LPF) Coefficient (14bit x 2)
Default: “0000H”
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Addr
30H
Register Name
Digital Filter Select 2
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
EQ5
R/W
0
D3
EQ4
R/W
0
D2
EQ3
R/W
0
D1
EQ2
R/W
0
D0
EQ1
R/W
0
EQ1: Equalizer 1 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ1 bit is “1”, the settings of E1A15-0, E1B15-0 and E1C15-0 bits are enabled. When EQ1 bit is “0”,
EQ1 block is through (0dB).
EQ2: Equalizer 2 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ2 bit is “1”, the settings of E2A15-0, E2B15-0 and E2C15-0 bits are enabled. When EQ2 bit is “0”,
EQ2 block is through (0dB).
EQ3: Equalizer 3 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ3 bit is “1”, the settings of E3A15-0, E3B15-0 and E3C15-0 bits are enabled. When EQ3 bit is “0”,
EQ3 block is through (0dB).
EQ4: Equalizer 4 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ4 bit is “1”, the settings of E4A15-0, E4B15-0 and E4C15-0 bits are enabled. When EQ4 bit is “0”,
EQ4 block is through (0dB).
EQ5: Equalizer 5 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ5 bit is “1”, the settings of E5A15-0, E5B15-0 and E5C15-0 bits are enabled. When EQ5 bit is “0”,
EQ5 block is through (0dB).
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Addr
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
R/W
Default
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
W
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
W
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
W
0
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
W
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
W
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
W
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
W
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
W
0
E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3)
Default: “0000H”
E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3)
Default: “0000H”
E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3)
Default: “0000H”
E4A15-0, E4B15-0, E4C15-0: Equalizer 4 Coefficient (16bit x3)
Default: “0000H”
E5A15-0, E5B15-0, E5C15-0: Equalizer 5 Coefficient (16bit x3)
Default: “0000H”
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Addr
50H
51H
Register Name
EQ Control 250Hz/100Hz
EQ Control 3.5kHz/1kHz
R/W
Default
Addr
52H
Register Name
EQ Control 10kHz
R/W
Default
D7
EQB3
EQD3
R/W
1
D6
EQB2
EQD2
R/W
0
D5
EQB1
EQD1
R/W
0
D4
EQB0
EQD0
R/W
0
D3
EQA3
EQC3
R/W
1
D2
EQA2
EQC2
R/W
0
D1
EQA1
EQC1
R/W
0
D0
EQA0
EQC0
R/W
0
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
EQE3
R/W
1
D2
EQE2
R/W
0
D1
EQE1
R/W
0
D0
EQE0
R/W
0
D3
PLLBT0
R/W
0
D2
PMPCM
R/W
0
D1
PMSRB
R/W
0
D0
PMSRA
R/W
0
EQA3-0: Select the boost level of 100Hz
EQB3-0: Select the boost level of 250Hz
EQC3-0: Select the boost level of 1kHz
EQD3-0: Select the boost level of 3.5kHz
EQE3-0: Select the boost level of 10kHz
See Table 35.
Addr
53H
Register Name
PCM I/F Control 0
R/W
Default
D7
GPOM2
R/W
0
D6
GPOE2
R/W
0
D5
PLLBT2
R/W
0
D4
PLLBT1
R/W
0
PMSRA: SRC-A Power Management
0: Power down (default)
1: Power up
PMSRB: SRC-B Power Management
0: Power down (default)
1: Power up
PMPCM: PCM I/F Power Management
0: Power down (default)
1: Power up
PLLBT2-0: PLLBT Reference Clock Select (Table 76)
PLLBT3 bit is D6 of Addr=55H.
Default: “0000”: SYNCA
GPOE2: General Purpose Output 2 Enable at GPOM2 bit = “1”
“0”: GPO2 pin = “L” (default)
“1”: GPO2 pin = “H”
GPOM2: General Purpose Output 2 Operation Mode (Table 92)
“0”: Controlled by GPOE2 bit (default)
“1”: MIC Detection Interrupt
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Addr
54H
Register Name
PCM I/F Control 2
R/W
Default
D7
SDOAD
R/W
0
D6
BCKO2
R/W
0
D5
MSBSA
R/W
0
D4
BCKPA
R/W
0
D3
LAWA1
R/W
0
D2
LAWA0
R/W
0
D1
FMTA1
R/W
0
D0
FMTA0
R/W
0
FMTA1-0: PCM I/F A Format (Table 84)
Default: “00” (Mode 0)
LAWA1-0: PCM I/F A Mode (Table 82)
Default: “00” (Mode 0)
BCKPA: BICKA Polarity of PCM I/F A (Table 86)
“0”: SDTOA is output by the rising edge (“↑”) of BICKA and SDTIA is latched by the falling edge (“↓”). (default)
“1”: SDTOA is output by the falling edge (“↓”) of BICKA and SDTIA is latched by the rising edge (“↑”).
MSBSA: SYNCA Phase of PCM I/F A (Table 86)
“0”: The rising edge (“↑”) of SYNCA is half clock of BICKA before the channel change. (default)
“1”: The rising edge (“↑”) of SYNCA is one clock of BICKA before the channel change.
BCKO2: BICKA/B Output Frequency Select at Master Mode (Table 77)
0: 16fs2 (default)
1: 32fs2
SDOAD: SDTOA Disable (Table 56)
“0”: Enable (default)
“1”: Disable (“L”)
Addr
55H
Register Name
PCM I/F Control 3
R/W
Default
D7
SDOBD
R/W
0
D6
PLLBT3
R/W
0
D5
MSBSB
R/W
0
D4
BCKPB
R/W
0
D3
LAWB1
R/W
0
D2
LAWB0
R/W
0
D1
FMTB1
R/W
0
D0
FMTB0
R/W
0
FMTB1-0: PCM I/F B Format (Table 85)
Default: “00” (Mode 0)
LAWB1-0: PCM I/F B Mode (Table 83)
Default: “00” (Mode 0)
BCKPB: BICKB Polarity of PCM I/F B (Table 87)
“0”: SDTOB is output by the rising edge (“↑”) of BICKB and SDTIB is latched by the falling edge (“↓”). (default)
“1”: SDTOB is output by the falling edge (“↓”) of BICKB and SDTIB is latched by the rising edge (“↑”).
MSBSB: SYNCB Phase of PCM I/F B (Table 87)
“0”: The rising edge (“↑”) of SYNCB is half clock of BICKB before the channel change. (default)
“1”: The rising edge (“↑”) of SYNCB is one clock of BICKB before the channel change.
PLLBT3: PLLBT Reference Clock Select (Table 76)
PLLBT2-0 bits is D5-3 of Addr=53H.
Default: “0000”: SYNCA
SDOBD: SDTOB Disable (Table 58)
“0”: Enable (default)
“1”: Disable (“L”)
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Addr
56H
Register Name
Digital Volume B Control
R/W
Default
D7
BVL7
R/W
0
D6
BVL6
R/W
0
D5
BVL5
R/W
0
D4
BVL4
R/W
1
D3
BVL3
R/W
1
D2
BVL2
R/W
0
D1
BVL1
R/W
0
D0
BVL0
R/W
0
D6
CVL6
R/W
0
D5
CVL5
R/W
0
D4
CVL4
R/W
1
D3
CVL3
R/W
1
D2
CVL2
R/W
0
D1
CVL1
R/W
0
D0
CVL0
R/W
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
SDOA
R/W
0
D2
SVB2
R/W
0
D1
SVB1
R/W
0
D0
SVB0
R/W
0
D5
SDOL1
R/W
0
D4
SDOL0
R/W
0
D3
BVMX1
R/W
0
D2
BVMX0
R/W
0
D1
SBMX1
R/W
0
D0
SBMX0
R/W
0
BVL7-0: Digital Volume B (Table 38)
Default: “18H” (0dB)
Addr
57H
Register Name
Digital Volume C Control
R/W
Default
D7
CVL7
R/W
0
CVL7-0: Digital Volume C (Table 39)
Default: “18H” (0dB)
Addr
58H
Register Name
Side Tone Volume Control
R/W
Default
D7
0
RD
0
SVB2-0: Side Tone Volume (Table 40)
Default: “0H” (0dB)
SDOA: SDTOA Output Signal Select (Table 55)
“0”: SRC-A (default)
“1”: SDTI-B
Addr
59H
Register Name
Digital Mixing Control
R/W
Default
D7
SDOR1
R/W
0
D6
SDOR0
R/W
0
SBMX1-0: SDTOB Output Signal Select (Table 57)
Default: “00” (SDTIA)
BVMX1-0: SRC-B Input Signal Select (Table 59)
Default: “00” (SDTIA)
SDOL1-0: SDTO Lch Output Mixing (Table 45)
Default: “00” (Lch Signal Selected by Table 44)
SDOR1-0: SDTO Rch Output Mixing (Table 46)
Default: “00” (Rch Signal Selected by Table 44)
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[AK4671]
Addr
5AH
Register Name
SAR ADC Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
GPOM1
R/W
0
D3
GPOE1
R/W
0
D2
A1
R/W
0
D1
A0
R/W
0
D0
PMSAD
R/W
0
PMSAD: 10bit ADC Power Management
“0”: Power down (default)
“1”: Power up
A1-0: SAR ADC Measurement Mode (Table 94)
Default: “00” (AIN1)
GPOE1: General Purpose Output 1 Enable at GPOM1 bit = “1”
“0”: GPO pin = “L” (default)
“1”: GPO pin = “H”
GPOM1: General Purpose Output 1 Operation Mode
“0”: Controlled by GPOE bit (default)
“1”: Controlled by A0 bit
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[AK4671]
SYSTEM DESIGN
Figure 108 shows the system connection diagram for the AK4671. The evaluation board [AKD4671] demonstrates the
optimum layout, power supply arrangements and measurement results.
Headphone
Digital
Ground
Digital
(Base Band)
1.6 ∼ 3.6V
10u
0.1u
TEST
LOUT2
AVDD
VSS1
RCP
ROUT2
MUTET
C
VCOM VCOCBT
VCOC
PVDD
0.1u
0.1u
Base Band
R
0.1u
2.2u
1u
Rp
Cp
Analog
2.2 ∼ 3.6V
Analog
Ground
VSS2
TVDD2
SDTOA
BICKA
SYNCA
GPO2
CDTI
SDTIA
RCN
VSS4
DVDD
ROUT3
LOUT3
CCLK
CSN
RIN4
LIN4
I2C
BICK
LIN3
RIN3
MCKI
MCKO
Digital
(μP & CPU)
1.6 ∼ 3.6V
Receiver
Ext SPK-Amp
0.1u
μP
Stereo
Speaker
AK4671EG
Top View
Line In
CPU
NC
Internal MIC
IN1+
IN1−
SAIN2
SAVDD
TVDD3
SDTOB
MDT
MPWR
SAIN3
SAIN1
VSS3
SYNCB
PDN
LRCK
BICKB
SDTO
CDTO
SDTIB
SDTI
GPO1
Bluetooth
Module
0.1u
0.1u
1k
IN2−
1k
IN2+
2.2k
External MIC
Digital
(Bluetooth)
1.6 ∼ 3.6V
DC Measurement
Notes:
- VSS1, VSS2, VSS3 and VSS4 of the AK4671 should be distributed separately from the ground of external
controllers.
- All digital input pins should not be left floating.
- When the AK4671 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC pin is not needed.
- When the AK4671 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC pin is shown in Table
4.
- When the AK4671 is used by master mode, LRCK and BICK pins are a Hi-Z state until M/S bit becomes “1”.
LRCK and BICK pins of the AK4671 should be pulled-down or pulled-up by the resistor (about 100kΩ)
externally to avoid the floating state.
- A resistor and capacitor of the VCOCBT pin is shown in Table 76.
- After setting PDN pin = “H”, the PCM I/F clock pins of AK4671 are a Hi-Z state until PMPCM bit becomes
“1”. The PCM I/F clock pins of master mode should be pulled-down or pulled-up by the resistor (about 100kΩ)
externally to avoid the floating state.
Figure 108. Typical Connection Diagram
(Internal Full-differentila Mic, External pseudo differential Mic, Recevier Output, 4-wire serial mode)
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1. Grounding and Power Supply Decoupling
The AK4671 requires careful attention to power supply and grounding arrangements. AVDD, PVDD, SAVDD, DVDD,
TVDD2 and TVDD3 are usually supplied from the system’s analog supply. If AVDD, PVDD, SAVDD, DVDD, TVDD2
and TVDD3 are supplied separately, the power-up sequence is not critical. The PDN pin should be held to “L” when
power-up. The PDN pin should be set to “H” after all power supplies are powered-up.
In case that the pop noise should be avoided at receiver output, headphone output and line output, the AK4671 should be
operated by the following recommended power-up/down sequence.
1) Power-up
- The PDN pin should be held to “L” when power-up. The AK4671 should be reset by bringing the PDN pin “L” for
150ns or more.
- In case that the power supplies are separated in two or more groups, the power supply including DVDD should be
powered ON at first.
2) Power-down
- Each power supplies should be powered OFF after the PDN pin is set to “L”.
- In case that the power supplies are separated in two or more groups, the power supply including DVDD should be
powered OFF at last.
VSS1, VSS2, VSS3 and VSS4 of the AK4671 should be connected to the analog ground plane. System analog ground
and digital ground should be connected together near to where the supplies are brought onto the printed circuit board.
Decoupling capacitors should be as near to the AK4671 as possible, with the small value ceramic capacitor being the
nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached
to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the
AK4671.
3. Analog Inputs
The Mic, Line and MIN inputs are single-ended. The input signal range scales with nominally at 0.6 x AVDD Vpp (typ)
at MGNL=MGNR=0dB and single-ended input, centered around the internal common voltage (0.5 x AVDD). The input
signal should be AC coupled using a capacitor. The cut-off frequency is fc = 1/(2πRC). The AK4671 can accept input
voltages from VSS1 to AVDD.
4. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and
a negative full scale for 8000H(@16bit). The ideal output is VCOM voltage for 0000H(@16bit). VCOM voltage is 0.5 x
AVDD (typ).
When LOUT1, ROUT1, LOUT2, ROUT2, LOUT3/LOP and ROUT3/LON pins are single-ended output, these pins
should be AC coupled using a capacitor. When RCP, RCN pins are full-differential output, these pins should be
connected directly to a receiver. (RCP, RCN pins should be not AC coupled using a capacitor.)
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CONTROL SEQUENCE (AUDIO)
„ Clock Set up
When ADC or DAC is powered-up, the clocks must be supplied.
1. PLL Master Mode.
Example:
Power Supply
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:00H, D0)
(4)
(1) Power Supply & PDN pin = “L” Æ “H”
MCKO bit
(Addr:02H, D2)
PMPLL bit
(2)Addr:02H, Data:22H
Addr:03H, Data:02H
Addr:01H, Data:F4H
(Addr:02H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:01H
(Addr:02H, D1)
40msec(max)
(6)
BICK pin
LRCK pin
Output
(4)Addr:02H, Data:27H
Output
MCKO, BICK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 109. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
(5) PLL lock time is 40ms(max.) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(6) The AK4671 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation
starts.
(7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”.
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2. PLL Slave Mode (MCKI pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
(2)Addr:03H, Data:02H
Addr:01H, Data:F4H
PMVCM bit
(Addr:00H, D0)
(4)
MCKO bit
(Addr:02H, D2)
(3)Addr:00H, Data:01H
PMPLL bit
(Addr:02H, D0)
(5)
MCKI pin
(4)Addr:02H, Data:25H
Input
40msec(max)
(7)
MCKO pin
MCKO output start
Output
(6)
(8)
BICK pin
LRCK pin
Input
BICK and LRCK input start
Figure 110. Clock Set Up Sequence (2)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 40ms(max.).
(6) The normal clock is output from MCKO during this period.
(7) The invalid frequency is output from MCKO after PLL is locked.
(8) BICK and LRCK clocks should be synchronized with MCKO clock.
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3. PLL Slave Mode (LRCK or BICK pin)
Example:
Power Supply
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(3)
PMVCM bit
(Addr:00H, D0)
PMPLL bit
(2) Addr:03H, Data:02H
Addr:01H, Data:83H
(Addr:02H, D0)
LRCK pin
BICK pin
Input
(3) Addr:00H, Data:01H
(4)
Internal Clock
(5)
(4) Addr:02H, Data:01H
Figure 111. Clock Set Up Sequence (3)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) DIF1-0, FS3-2 and PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is
supplied. PLL lock time is 160ms(max.) when LRCK is a PLL reference clock. And PLL lock time is
2ms(max.) when BICK is a PLL reference clock.
(5) Normal operation stats after that the PLL is locked.
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4. EXT Slave Mode
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(2) Addr:03H, Data:02H
Addr:01H, Data:00H
(3)
PMVCM bit
(Addr:00H, D0)
(4)
MCKI pin
Input
(3) Addr:00H, Data:01H
(4)
LRCK pin
BICK pin
Input
MCKI, BICK and LRCK input
Figure 112. Clock Set Up Sequence (4)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) DIF1-0 and FS1-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) Normal operation starts after the MCKI, LRCK and BICK are supplied.
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5. EXT Master Mode
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
(1) Power Supply & PDN pin = “L” Æ “H”
Power Supply
(1)
PDN pin
(2) MCKI input
(4)
PMVCM bit
(Addr:00H, D0)
(3) Addr:03H, Data:02H
Addr:01H, Data:00H
Addr:02H, Data:02H
(2)
MCKI pin
Input
(3)
M/S bit
BICK and LRCK output
(Addr:02H, D1)
LRCK pin
BICK pin
Output
(4) Addr:00H, Data:01H
Figure 113. Clock Set Up Sequence (5)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) MCKI should be input.
(3) After DIF1-0 and FS2-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output.
(4) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
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[AK4671]
■ MIC Input Recording (Stereo)
Example:
FS3-0 bits
0000
(Addr:01H, D7-4)
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Pre MIC AMP: +15dB
MIC Power: On
ALC setting: Refer to Table 62
ALC: Enable
1111
(1)
MIC Control
55H
(Addr:05H, D7-0)
AAH
(2)
ALC Control 1
(1) Addr:01H, Data:F4H
00H
(Addr:16H)
05H
(2) Addr:05H, Data: AAH
(3)
ALC Control 2
E1H
(Addr:14H)
E1H
(3) Addr:16H, Data:05H
(4)
ALC Control 3
15H
(Addr:17H)
01H
(4) Addr:14H, Data:E1H
(5)
ALC Control 4
02H
(Addr:18H)
03H
02H
ALC State
(5) Addr:17H, Data:01H
(9)
(6)
ALC Disable
ALC Enable
ALC Disable
(6) Addr:18H, Data:03H
(7) Addr:00H, Data:3FH
PMMP bit
(Addr:00H, D1)
Recording
PMMICL/R bits
PMADL/R bits
1059 / fs
(Addr:00H, D5-2)
ADC Internal
State
(8)
(7)
Power Down
(8) Addr:00H, Data:01H
Initialize Normal State Power Down
(9) Addr:18H, Data:02H
Figure 114. Stereo MIC Input Sequence
(MIC Recording: LIN1/RIN1 → MICL/R → ADCL/R → ALC → Audio I/F → SDTO)
<Example>
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to “Figure
62”.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4671 is PLL mode, MIC and ADC should be powered-up in
consideration of PLL lock time after a sampling frequency is changed.
(2) Set up Gain for MIC-Amp (Addr: 05H)
(3) Set up Timer Select for ALC (Addr: 16H)
(4) Set up REF value for ALC (Addr: 14H)
(5) Set up LMTH1-0, RGAIN1-0 and LMAT1-0 bits (Addr: 17H)
(6) Set up ALC bit (Addr: 18H)
(7) Power Up MIC and ADC: PMMP = PMMICL = PMMICR = PMADL = PMADR bits = “0” → “1”
The initialization cycle time of ADC is [email protected]=44.1kHz.
After the ALC bit is set to “1” and ADC block is powered-up, the ALC operation starts from IVOL default value (0dB).
The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog input pin
going to the common voltage and the time constant of the offset cancel digital HPF. This time can be shorter by using
the following sequence:
At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to power-up
the ADC should be longer than 4 times of the time constant that is determined by the AC coupling capacitor at analog
input pin and the internal input resistance.
(8) Power Down MIC and ADC: PMMP = PMMICL = PMMICR = PMADL = PMADR bits = “1” → “0”
When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is disabled
because the ADC block is powered-down. If the registers for the ALC operation are also changed when the sampling
frequency is changed, it should be done after the AK4671 goes to the manual mode (ALC bit = “0”) or ADC block is
powered-down (PMADL = PMADR bits = “0”). IVOL gain is not reset when PMADL = PMADR bits = “0”, and then
IVOL operation starts from the setting value when PMADL or PMADR bit is changed to “1”.
(9) ALC Disable: ALC bit = “1” → “0”
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■ Headphone-Amp Output
FS3-0 bits
(Addr:01H, D7-4)
0000
1111
E x a m p le :
(1)
HPG3-0 bits
(Addr:08H, D7-4)
1011
P L L M a s ter M o d e
A u d i o I/F F o r m a t: M S B ju s tif i e d ( A D C & D A C )
S a m p l in g F r e q u e n c y : 4 4 . 1 k H z
O V O L C b it = “ 1 ” ( d e f a u lt)
D ig i t a l V o l u m e L e v e l : − 8 d B
H P V o lu m e L e v e l: − 3 d B
5 b a n d E Q : E n a b le
1010
(2)
( 1 ) A d d r :0 1 H , D a t a :F 4 H
DACHL/R bits
(12)
(Addr:0B&0CH, D0)
EQ bit
(Addr:18H, D3)
0
1
0
(3)
( 2 ) A d d r :0 8 H , D a t a A 5 H
A d d r :0 B H & 0 C H , D a t a 0 1 H
( 3 ) A d d r :1 8 H , D a t a 0 A H
(11)
( 4 ) A d d r :1 A H & 1 B H , D a ta 2 8 H
OVL/R7-0 bits
(Addr:1AH&1BH, D7-0)
18H
28H
( 5 ) A d d r :0 0 H , D a t a C 1 H
(4)
PMDAL/R bits
(Addr:00H, D7-6)
( 6 ) A d d r :1 0 H , D a t a 6 3 H
(5)
(10)
( 7 ) A d d r :1 0 H , D a t a 6 7 H
PML/RO2S bits
P la y b a c k
(Addr:10H, D6-5)
(6)
(9)
PML/RO2 bits
(Addr:10H, D1-0)
MUTEN bit
( 8 ) A d d r :1 0 H , D a t a 6 3 H
( 9 ) A d d r :1 0 H , D a t a 0 0 H
(7)
(8)
( 1 0 ) A d d r : 0 0 H , D a ta 0 1 H
(Addr:10H, D2)
LOUT2 pin
ROUT2 pin
( 1 1 ) A d d r : 1 8 H , D a ta 0 2 H
Normal Output
( 1 2 ) A d d r : 0 B H & 0 C H , D a ta 0 0 H
Figure 115. Headphone-Amp Output Sequence
(Headphone Playback: SDTI → Audio I/F → EQ → DATT → DACL/R → LOUT2/ROUT2)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4671 is PLL mode, DAC and Headphone-Amp should
be powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “SDTI Æ DAC Æ HP-Amp”: DACHL = DACHR bits = “0” → “1”
Set up analog volume for HP-Amp (Addr: 08H, HPG3-0 bits)
(3) Enable 5-band Equalizer: EQ bit = “0” Æ “1” (Boost amount is selected by Addr = 50H-52H.)
(4) Set up the output digital volume (Addr: 1AH and 1BH)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(5) Power up DAC: PMDAL = PMDAR bits = “0” → “1”
(6) Power up Headphone-Amp and MIX-Amp: PMLO2 = PMRO2 = PMLO2S = PMRO2S bits = “0” → “1”
Output voltages of Headphone-Amp are still VSS1.
(7) Rise up the common voltage of Headphone-Amp: MUTEN bit = “0” → “1”
The rise time depends on AVDD and the capacitor value connected with the MUTET pin. When AVDD=3.3V
and the capacitor value is 1.0μF, the time constant is τr = 250ms(max.).
(8) Fall down the common voltage of Headphone-Amp: MUTEN bit = “1” → “0”
The fall time depends on AVDD and the capacitor value connected with the MUTET pin. When AVDD=3.3V
and the capacitor value is 1.0μF, the time constant is τ f = 250ms(max.).
If the power supply is powered-off or Headphone-Amp is powered-down before the common voltage goes to
VSS2, the pop noise occurs. It takes twice of τf that the common voltage goes to VSS2.
(9) Power down Headphone-Amp and MIX-Amp: PMLO2 = PMRO2 = PMLO2S = PMRO2S bits = “1” → “0”
(10) Power down DAC: PMDAL = PMDAR bits = “1” → “0”
(11) Disable 5-band Equalizer: EQ bit = “1” Æ “0”
(12) Disable the path of “DAC → Headphone-Amp”: DACHL = DACHR bits = “1” → “0”
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■ Stereo Line Output
Example:
FS3-0 bits
(Addr:01H, D7-4)
0000
PLL, Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
OVOLC bit = “1”(default)
Digital Volume Level: −8dB
LINEOUT Volume Level: −3dB
1111
(1)
L3VL1-0 bits
(Addr:11H, D7-D6)
10
01
(1) Addr:01H, Data:F4H
(2)
(2) Addr:11H, Data:40H
Addr:1DH, Data:01H
Addr:15H, Data:05H
Addr:0DH&0EH, Data:01H
PFSEL bis
(Addr:1DH, D0)
PFMXL/R1-0 bits 0000
0101
(Addr:15H, D3-0)
(3) Addr:1AH&1BH, Data:28H
DACSL/R bits
(9)
(Addr:0DH&0EH, D0)
OVL/R7-0 bits
(Addr:1AH&1BH, D7-0)
18H
(4) Addr:11H, Data:44H
(5) Addr:00H, Data:C1H
Addr:11H, Data:47H
28H
(3)
(6) Addr:11H, Data:43H
LOPS3 bit
(Addr:11H, D2)
(6)
(4)
(7)
(10)
PMDAL/R bits
(7) Addr:11H, Data:47H
(Addr:00H, D7-6)
(8)
(5)
(8) Addr:00H, Data:01H
Addr:11H, Data:44H
PML/RO3 bits
(Addr:11H, D1-0)
LOUT3 pin
ROUT3 pin
Playback
>300 ms
>300 ms
(9) Addr:0DH&0E, Data:00H
Normal Output
(10) Addr:11H, Data:40H
Figure 116. Stereo Lineout Sequence
(Speaker Playback: SDTI → Audio I/F → SVOLA → DATT → DACL/R → LOUT3/ROUT3 → External SPK-Amp)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4671 is PLL mode, DAC and Stereo Line-Amp
should be powered-up in consideration of PLL lock time after the sampling frequency is changed.
(2) Set up the path of “SDTI Æ DAC Æ Stereo Line-Amp”: PFSEL = “0” Æ “1”, PFMXL1-0 = PFMXR1-0 bits =
“0000” Æ “0101”, DACSL = DACSR bits = “0” Æ “1”
Set up analog volume for Stereo Line-Amp (Addr: 11H, L3VL1-0 bits)
(3) Set up the output digital volume (Addr: 1AH and 1BH)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(4) Enter power-save mode of Stereo Line-Amp: LOPS3 bit = “0” Æ “1”
(5) Power-up DAC and Stereo Line-Amp: PMDAL = PMDAR = PMLO3 = PMRO3 bits = “0” → “1”
LOUT3 and ROUT3 pins rise up to VCOM voltage after PMLO3 and PMRO3 bits are changed to “1”. Rise
time is 300ms(max.) at C=1μF and AVDD=3.3V.
(6) Exit power-save mode of Stereo Line-Amp: LOPS3 bit = “1” Æ “0”
LOPS3 bit should be set to “0” after LOUT3 and ROUT3 pins rise up. Stereo Line-Amp goes to normal
operation by setting LOPS3 bit to “0”.
(7) Enter power-save mode of Stereo Line-Amp: LOPS3 bit: “0” Æ “1”
(8) Power-down DAC and Stereo Line-Amp: PMDAL = PMDAR = PMLO3 = PMRO3 bits = “1” → “0”
LOUT3 and ROUT3 pins fall down to VSS1. Fall time is 300ms(max.) at C=1μF and AVDD=3.3V.
(9) Disable the path of “DAC Æ Stereo Line-Amp”: DACSL = DACSR bits = “1” Æ “0”
(10) Exit power-save mode of Stereo Line-Amp: LOPS3 bit = “1” Æ “0”
LOPS3 bit should be set to “0” after LOUT3 and ROUT3 pins fall down.
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■ Stop of Clock
Master clock can be stopped when ADC and DAC are not used.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:02H, D0)
(1)
MCKO bit
"1" or "0"
(1) Addr:02H, Data:02H
(Addr:02H, D2)
(2)
External MCKI
Input
(2) Stop an external MCKI
Figure 117. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO clock: MCKO bit = “1” → “0”
(2) Stop an external MCKI clock.
2. PLL Slave (MCKI pin)
Example
(1)
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
PMPLL bit
(Addr:02H, D0)
(1)
MCKO bit
(1) Addr:02H, Data:00H
(Addr:02H, D2)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 118. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
3. PLL Slave Mode (LRCK or BICK pin)
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:02H, D0)
(2)
External BICK
Input
(1) Addr:02H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 119. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
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4. EXT Slave Mode
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format:MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
Sampling Frequency:44.1kHz
(1)
(1) Stop the external clocks
Figure 120. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
5. EXT Master Mode
(1)
External MCKI
Input
Example
BICK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Audio I/F Format:MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
Sampling Frequency:44.1kHz
(1) Stop the external MCKI
Figure 121. Clock Stopping Sequence (5)
<Example>
(1) Stop MCKI clock. BICK and LRCK are fixed to “H” or “L”.
■ Power down
Power supply current can be shut down (typ. 20μA) by stopping clocks and setting PMVCM bit = “0” after all blocks
except for VCOM are powered-down. Power supply current can be also shut down (typ. 1μA) by stopping clocks and
setting the PDN pin = “L”. When the PDN pin = “L”, the registers are initialized.
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CONTROL SEQUENCE (PCM)
■ Clock Set up
When ADC or DAC is powered-up, the clocks must be supplied.
1. PCM I/F A Slave Mode
Example:
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCA
SYNCA frequency: 1fs2
Sampling Frequency: 8kHz
Power Supply
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
PMVCM bit
(2) Addr:02H, Data:C0H
Addr:03H, Data:12H
Addr:54H, Data:00H
Addr:53H, Data:00H
Addr:55H, Data:00H
(Addr:00H, D0)
PMPCM bit
(Addr:53H, D2)
SYNCA pin
BICKA pin
Input
(3) Addr:00H, Data:01H
(4)
Internal Clock
(5)
(4) Addr:53H, Data:04H
Figure 122. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) BTCLK, LP, SDOD, FMTA1-0, LAWA1-0, BCKPA, MSBSA, PLLBT3-0 bits should be set during this
period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) PLLBT starts after the PMPCM bit changes from “0” to “1” and PLLBT reference clock (SYNCA or BICKA
pin) is supplied. PLLBT lock time is 260ms(max.) when SYNCA is a PLLBT reference clock. And PLLBT
lock time is 40ms(max.) when BICKA is a PLLBT reference clock.
(5) Normal operation stats after that the PLLBT is locked.
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2. PCM I/F A Master Mode
Example:
Power Supply
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCB
SYNCB frequency: 1fs2
Sampling Frequency: 8kHz
(1)
PDN pin
(2)
(3)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
PMVCM bit
(Addr:00H, D0)
PMPCM bit
(2) Addr:02H, Data:C0H
Addr:03H, Data:12H
Addr:54H, Data:00H
Addr:53H, Data:00H
Addr:55H, Data:00H
(Addr:53H, D2)
SYNCB pin
BICKB pin
Input
(4)
Internal Clock
(5)
(3) Addr:00H, Data:01H
(6)
SYNCA pin
BICKA pin
Output
(4) Addr:53H, Data:04H
Figure 123. Clock Set Up Sequence (2)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) BTCLK, LP, SDOD, FMTA1-0, LAWA1-0, BCKPA, MSBSA, PLLBT3-0 bits should be set during this
period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) PLLBT starts after the PMPCM bit changes from “0” to “1” and PLLBT reference clock (SYNCB or BICKB
pin) is supplied. PLLBT lock time is 260ms(max.) when SYNCB is a PLLBT reference clock. And PLLBT
lock time is 40ms(max.) when BICKB is a PLLBT reference clock.
(5) Normal operation stats after that the PLLBT is locked.
(6) The invalid frequency is output from SYNCA and BICKA after PLLBT is locked.
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■ MIC Input Phone Call (Mono)
MIC Control 1
(Addr:04H, D7-0)
14H
00H
Example:
PCM I/F A: Slave Mode
PCM I/F A Format: Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Pre MIC AMP: +15dB
MIC Power: On
Digital Volume Level: +17.25dB
ADC HPF: Enable
5 band EQ: Enable
(1)
MIC Control 2
(Addr:05H, D3-0)
HPFAD bit
(Addr:1DH, D1)
0101
1010
0
1
(2)
HPF bit
(Addr:1DH, D4)
(1) Addr:04H, Data:14H
Addr:05H, Data: AAH
(8)
0
1
00
01
(2) Addr:1DH, Data:12H
PFMXL1-0 bits
(Addr:15H, D1-0)
(3) Addr:15H, Data:01H
(3)
EQ bit
(Addr:18H, D3)
0
0
1
IVL7-0 bits
(Addr:12H, D7-0)
(4) Addr:18H, Data:0AH
(9)
(4)
91H
(5) Addr:12H, Data:BFH
BFH
(5)
(6) Addr:00H, Data:17H
Addr:53H, Data:05H
PMMP bit
(Addr:00H, D1)
Phone Call
PMMICL bit
PMADL bit
(Addr:00H, D4&D2)
(7) Addr:00H, Data:01H
Addr:53H, Data:04H
PMSRA bit
(Addr:53H, D0)
1059 / fs
(7)
(6)
ADC Internal
State
Power Down
Initialize Normal State
(8) Addr:1DH, Data:00H
Power Down
(9) Addr:18H, Data:02H
Figure 124. Mono MIC Input Sequence
(Phone Call Tx: IN1+/IN1- → MICL → ADCL → HPF→ IVL → EQ → SRC-A → PCM I/F A → SDTOA)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence. Also, MIC, ADC and SRC-A should be
powered-up in consideration of PLLBT lock time.
(1) Set up Signal Select for MIC Input (Addr: 04H) and Gain for MIC-Amp (Addr: 05H)
(2) Enable ADC High Pass Filter: HPFAD bit = “0” Æ “1”
Enable the coefficient of High Pass Filter: HPF bit = “0” Æ “1” (Coefficient of wind-noise reduction filter is set by
Addr = 28H- 2BH.)
This sequence is an example of HPF setting at fs2=8kHz. The coefficient should be set when HPFAD = HPF bits = “0”
or PMADL = PMADR = PMDAL = PMDAR bits = “0”.
(3) Set up the path of “ADC Æ 5-band EQ”: PFMXL1-0 bits = “00” Æ “01”
(4) Enable 5-band Equalizer: EQ bit = “0” Æ “1” (Boost amount is selected by Addr = 50H-52H.)
(5) Set up input volume (Addr: 12H)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(6) Power Up MIC, ADC and SRC-A: PMMP = PMMICL = PMADL = PMSRA bits = “0” → “1”
The initialization cycle time of ADC is [email protected]=8kHz.
The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog input pin
going to the common voltage and the time constant of the offset cancel digital HPF. This time can be shorter by using
the following sequence:
At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to power-up
the ADC should be longer than 4 times of the time constant that is determined by the AC coupling capacitor at analog
input pin and the internal input resistance.
(7) Power Down MIC, ADC and SRC-A: PMMP = PMMICL = PMADL = PMSRA bits = “1” → “0”
IVOL gain is not reset when PMADL = PMADR bits = “0”, and then IVOL operation starts from the setting value when
PMADL or PMADR bit is changed to “1”.
(8) Disable ADC High Pass Filter : HPFAD bit = “1” Æ “0”
Disable the coefficient of High Pass Filter: HPF bit = “1” Æ “0”
(9) Disable 5-band Equalizer: EQ bit = “1” Æ “0”
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■ Receiver-Amp Output
Example:
L1VL2-0 bits
(Addr:08H, D2-0)
101
PCM I/F A: Slave Mode
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Digital Volume Level: −8dB
RCV Volume Level: 0dB
5 band EQ: Enable
100
(1)
SRMXR1-0 bits
(Addr:15H, D7-6)
00
(1) Addr:08H, Data:B4H
Addr:15H, Data:40H
Addr:0AH, Data:01H
Addr:0FH, Data:20H
01
DACR bit
(10)
(Addr:0AH, D0)
(2) Addr:18H, Data:0AH
RCV bit
(Addr:0FH, D5)
EQ bit
(Addr:18H, D3)
OVR7-0 bits
(Addr:1BH, D7-0)
(3) Addr:1BH, Data:28H
0
1
0
(2)
(4) Addr:0FH, Data:24H
(9)
18H
(5) Addr:53H, Data:06H
Addr:00H, Data:81H
Addr:0FH, Data:27H
28H
(3)
(6) Addr:0FH, Data:23H
LOPS1 bit
(Addr:0FH, D2)
(6)
(4)
(7)
(11)
PMSRB bit
(7) Addr:0FH, Data:27H
(Addr:53H, D1)
PMDAR bit
(Addr:00H, D7)
(5)
(8)
PML/RO1 bits
(Addr:0FH, D1-0)
Phone Call
(8) Addr:53H, Data:04H
Addr:00H, Data:01H
Addr:0FH, Data:24H
(9) Addr:18H, Data:02H
>1 ms
(10) Addr:0AH, Data:00H
RCP pin
RCN pin
Normal Output
(11) Addr:0FH, Data:20H
Figure 125. Receiver-Amp Output Sequence
(Phone Call Rx: SDTIA → PCM I/F A → SRC-B → EQ → DATT → DACR → RCP/RCN)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence. Also, SRC-B, DAC and Receiver-Amp
should be powered-up in consideration of PLLBT lock time.
(1) Set up the path of “SDTIA Æ DAC Æ Receiver-Amp”: SRMXR1-0 bits = “00” Æ “01”, DACR bit = “0” Æ
“1”, RCV bit = “0” Æ “1”
Set up analog volume for Receiver-Amp (Addr: 08H, L1VL2-0 bits)
(2) Enable 5-band Equalizer: EQ bit = “0” Æ “1” (Boost amount is selected by Addr = 50H-52H.)
(3) Set up the output digital volume (Addr: 1BH)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(4) Enter power-save mode of Receiver-Amp: LOPS1 bit = “0” Æ “1”
(5) Power-up SRC-B, DAC and Receiver-Amp: PMSRB bit = PMDAR = PMLO1 = PMRO1 bits = “0” → “1”
RCN pin rise up to VCOM voltage after PMLO1 and PMRO1 bits are changed to “1”.
(6) Exit power-save mode of Receiver-Amp: LOPS1 bit = “1” Æ “0”
LOPS1 bit should be set to “0” after PCN pin rise up. Receiver-Amp goes to normal operation by setting
LOPS1 bit to “0”.
(7) Enter power-save mode of Receiver-Amp: LOPS1 bit: “0” Æ “1”
(8) Power-down SRC-B, DAC and Receiver-Amp: PMSRB bit = PMDAR = PMLO1 = PMRO1 bits = “1” → “0”
Receiver-Amp becomes to power-down mode.
(9) Disable 5-band Equalizer: EQ bit = “1” Æ “0”
(10) Disable the path of “DAC Æ Receiver-Amp”: DACR bit = “1” Æ “0”
(11) Exit power-save mode of Receiver-Amp: LOPS1 bit = “1” Æ “0”
LOPS1 bit should be set to “0” after Receiver-Amp power-down.
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■ Mono Line Output
Example:
L3VL1-0 bits
(Addr:11H, D7-D6)
10
PCM I/F A: Slave Mode
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
Sampling Frequency: 8kHz
Digital Volume Level: −8dB
LINEOUT Volume Level: −3dB
5 band EQ: Enable
01
(1) Addr:11H, Data:40H
Addr:15H, Data:40H
Addr:0EH, Data:01H
(1)
SRMXR1-0 bits
(Addr:15H, D7-6)
00
01
(2) Addr:18H, Data:0AH
DACSR bit
(10)
(Addr:0EH, D0)
EQ bit
(Addr:18H, D3)
OVR7-0 bits
(Addr:1BH, D7-0)
(3) Addr:1BH, Data:28H
0
1
0
(2)
(4) Addr:11H, Data:44H
(9)
18H
(5) Addr:53H, Data:06H
Addr:00H, Data:81H
Addr:11H, Data:46H
28H
(3)
(6) Addr:11H, Data:42H
LOPS3 bit
(Addr:11H, D2)
(4)
(6)
(7)
(11)
PMSRB bit
(7) Addr:11H, Data:46H
(Addr:53H, D1)
PMDAR bit
(Addr:00H, D7)
(8)
(5)
PMRO3 bit
(Addr:11H, D1)
(8) Addr:53H, Data:04H
Addr:00H, Data:01H
Addr:11H, Data:44H
(9) Addr:18H, Data:02H
>300 ms
>300 ms
ROUT3 pin
Playback
(10) Addr:0EH, Data:00H
Normal Output
(11) Addr:11H, Data:40H
Figure 126. Mono Lineout Sequence
(Speaker Playback: SDTIA → PCM I/F A → SRC-B → EQ → DATT → DACR → ROUT3 → External SPK-Amp)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence. Also, SRC-B, DAC and Mono Line-Amp
should be powered-up in consideration of PLLBT lock time.
(1) Set up the path of “SDTIA Æ DAC Æ Mono Line-Amp”: SRMXR1-0 bits = “00” Æ “01”, DACSR bit = “0” Æ “1”
Set up analog volume for Mono Line-Amp (Addr: 11H, L3VL1-0 bits)
(2) Enable 5-band Equalizer: EQ bit = “0” Æ “1” (Boost amount is selected by Addr = 50H-52H.)
(3) Set up the output digital volume (Addr: 1BH)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(4) Enter power-save mode of Mono Line-Amp: LOPS3 bit = “0” Æ “1”
(5) Power-up SRC-B, DAC and Mono Line-Amp: PMSRB = PMDAR = PMRO3 bits = “0” → “1”
ROUT3 pin rise up to VCOM voltage after PMRO3 bit is changed to “1”. Rise time is 300ms(max.) at C=1μF
and AVDD=3.3V.
(6) Exit power-save mode of Mono Line-Amp: LOPS3 bit = “1” Æ “0”
LOPS3 bit should be set to “0” after ROUT3 pin rise up. Mono Line-Amp goes to normal operation by setting
LOPS3 bit to “0”.
(7) Enter power-save mode of Mono Line-Amp: LOPS3 bit: “0” Æ “1”
(8) Power-down SRC-B, DAC and Mono Line-Amp: PMSRB = PMDAR = PMRO3 bits = “1” → “0”
ROUT3 pin fall down to VSS1. Fall time is 300ms(max.) at C=1μF and AVDD=3.3V.
(9) Disable 5-band Equalizer: EQ bit = “1” Æ “0”
(10) Disable the path of “DAC Æ Mono Line-Amp”: DACSR bit = “1” Æ “0”
(11) Exit power-save mode of Mono Line-Amp: LOPS3 bit = “1” Æ “0”
LOPS3 bit should be set to “0” after ROUT3 pin fall down.
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■ Stop of Clock
Master clock can be stopped when ADC and DAC are not used.
1. PCM I/F A Slave Mode
Example
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCA
SYNCA frequency: 1fs2
Sampling Frequency: 8kHz
(1)
PMPCM bit
(Addr:53H, D2)
(2)
External SYNCA
Input
(1) Addr:53H, Data:00H
(2)
External BICKA
Input
(2) Stop the external clocks
Figure 127. Clock Stopping Sequence (1)
<Example>
(1) Power down PLLBT: PMPCM bit = “1” → “0”
(2) Stop the external SYNCA and BICKA clocks
2. PCM I/F A Master Mode
(1 )
PMPCM bit
(Ad d r:5 3 H , D 2 )
Example
(2 )
External SYNCB
PCM I/F A Format : Linear, Short Frame (ADC & DAC)
PLLBT Reference clock: SYNCB
SYNCB frequency: 1fs2
Sampling Frequency: 8kHz
Input
(2 )
External BICKB
Input
SYNCA
Output
"H" or "L"
BICKA
Output
"H" or "L"
(1) Addr:53H, Data:00H
(2) Stop the external clocks
Figure 128. Clock Stopping Sequence (2)
< Example >
(1) Power down PLLBT: PMPCM bit = “1” → “0”
(2) Stop the external SYNCB and BICKB clocks. SYNCA and BICKA are fixed to “H” or “L”.
■ Power down
Power supply current can be shut down (typ. 20μA) by stopping clocks and setting PMVCM bit = “0” after all blocks
except for VCOM are powered-down. Power supply current can be also shut down (typ. 1μA) by stopping clocks and
setting the PDN pin = “L”. When the PDN pin = “L”, the registers are initialized.
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[AK4671]
PACKAGE
5.0 ± 0.1
φ 0.05
A
57 - φ 0.3 ± 0.05
M S AB
9 8 7 65
4 3 2 1
4.0
5.0 ± 0.1
A
B
C
D
E
B
F
G
H
J
0.5
0.5
1.0MAX
0.25 ± 0.05
S
0.08 S
■ Material & Lead finish
Package molding compound:
Interposer material:
Solder ball material:
Epoxy, Halogen (bromine and chlorine) free
BT resin
SnAgCu
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MARKING
4671
XXXX
1
A
XXXX: Date code (4 digit)
Pin #A1 indication
REVISION HISTORY
Date (YY/MM/DD)
07/10/15
08/12/04
Revision
00
01
10/06/04
02
Reason
First Edition
Specification
Change
Error Correct
Page
Contents
163
Package molding compound was changed.
6
Unused pin: BICKA, SYNCA, BICKB, SYNCB
“Connect to VSS4”
Î “When all pins are unused, these pins should be
connected to VSS4 and PMPCM bit must be
always “0”.
When either PCM I/F A(BICKA/ SYNCA) or PCM
I/F B(BICKB/SYNCB) is used, unused pins are
connected to pull-down/up resistor of about
100kΩ.”
Table 86:
MSBSA, BCKPA=“00”
[MSB of SDTOA is output by the falling edge (“↓”)
of SYNCA.]
Î [MSB of SDTOA is output by next rising edge
(“↑”) of the falling edge (“↓”) of BICKA after the
rising edge (“↑”) of SYNCA.]
MSBSA, BCKPA=“01”
[MSB of SDTOA is output by the falling edge (“↓”)
of SYNCA.]
Î [MSB of SDTOA is output by next falling edge
(“↓”) of the rising edge (“↑”) of BICKA after the
rising edge (“↑”) of SYNCA.]
MSBSA, BCKPA=“10”
[MSB of SDTOA is output by the rising edge (“↑”)
of the first BICKA after the rising edge(“↑”) of
SYNCA.]
Î [MSB of SDTOA is output by the 2nd rising edge
(“↑”) of BICKA after the rising edge (“↑”) of
SYNCA.]
104
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Date (YY/MM/DD)
10/06/04
Revision
02
Reason
Page
Error Correct 104
105 ~
107
Contents
Table 86:
MSBSA, BCKPA=“11”
[MSB of SDTOA is output by the falling edge (“↓”)
of the first BICKA after the rising edge(“↑”) of
SYNCA.]
Î [MSB of SDTOA is output by the 2nd falling edge
(“↓”) of BICKA after the rising edge (“↑”) of
SYNCA.]
Table 87:
MSBSB, BCKPB=“00”
[MSB of SDTOB is output by the falling edge (“↓”)
of SYNCB.]
Î [MSB of SDTOB is output by next rising edge
(“↑”) of the falling edge (“↓”) of BICKB after the
rising edge (“↑”) of SYNCB.]
MSBSB, BCKPB=“01”
[MSB of SDTOB is output by the falling edge (“↓”)
of SYNCB.]
Î [MSB of SDTOB is output by next falling edge
(“↓”) of the rising edge (“↑”) of BICKB after the
rising edge (“↑”) of SYNCB.]
MSBSB, BCKPB=“10”
[MSB of SDTOB is output by the rising edge (“↑”)
of the first BICKB after the rising edge(“↑”) of
SYNCB.]
Î [MSB of SDTOB is output by the 2nd rising edge
(“↑”) of BICKB after the rising edge (“↑”) of
SYNCB.]
MSBSB, BCKPB=“11”
[MSB of SDTOB is output by the falling edge (“↓”)
of the first BICKB after the rising edge(“↑”) of
SYNCB.]
Î [MSB of SDTOB is output by the 2nd falling edge
(“↓”) of BICKB after the rising edge (“↑”) of
SYNCB.]
Figure 84-91: Arrow of SYNCA and BICKA was added.
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[AK4671]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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