AKM AK4953A

[AK4953A]
AK4953A
24bit Stereo CODEC with MIC/HP/SPK-AMP
GENERAL DESCRIPTION
The AK4953A is a low power consumption 24bit stereo CODEC with a microphone, headphone and
speaker amplifiers. The input circuits include a microphone amplifier and an ALC (Automatic Level
Control) circuit, and the output circuits include a cap-less headphone amplifier and a speaker amplifier. It
is suitable for portable application with recording/playback function. The integrated charge pump circuit
generates a negative voltage and removes the output AC coupling capacitors. The speaker amplifier has
a wide operating voltage range, which is from 0.9V to 5.5V, enabling a direct drive to batteries. The
AK4953A is available in a small 36pin QFN (5x5mm 0.4mm pitch), utilizing less board space than
competitive offerings.
FEATURES
1. Recording Function
• Stereo Single-ended input with three Selectors
• MIC Amplifier (+29dB/+26dB/+23dB/+20dB/+16dB/+12dB/0dB)
• Digital ALC (Automatic Level Control)
(Setting Range: +36dB ∼ −54dB, 0.375dB Step)
• ADC Performance: S/(N+D): 82dB, DR, S/N: 88dB (MIC-Amp=+20dB)
S/(N+D): 85dB, DR, S/N: 96dB (MIC-Amp=0dB)
• Wind-noise Reduction Filter
• 5 Band Notch Filter
• Digital MIC Interface
2. Playback Function
• Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
• Digital ALC (Automatic Level Control)
(Setting Range: +36dB ~ −54dB, 0.375dB Step)
• Digital Volume Control (+12dB ~ −115dB, 0.5dB Step, Mute)
• Capacitor-less Stereo Headphone Amplifier
- HP-Amp Performance: S/(N+D): [email protected], S/N: 96dB
- Output Power: [email protected]
- Pop Noise Free at Power-ON/OFF
• Mono Speaker-Amplifier
- SPK-Amp Performance: S/(N+D): [email protected], S/N: 95dB
- BTL Output
- Output Power: [email protected] (SVDD=3.3V)
[email protected] (SVDD=1.5V)
• Beep Generator
3. Power Management
4. Master Clock:
(1) PLL Mode
• Frequencies: 11.2896MHz, 12MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)
32fs or 64fs (BICK pin)
(2) External Clock Mode
• Frequencies: 256fs, 384fs, 512fs or 1024fs (MCKI pin)
MS1252-E-00
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[AK4953A]
5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs
• PLL Slave Mode (BICK pin): 7.35kHz ∼ 96kHz
• PLL Slave Mode (MCKI pin): 7.35kHz, 8kHz, 11.025kHz, 12kHz, 14.7kHz, 16kHz,
22.05kHz, 24kHz, 29.4kHz, 32kHz, 44.1kHz, 48kHz,
64kHz, 88.2kHz, 96kHz
• PLL Master Mode: 7.35kHz, 8kHz, 11.025kHz, 12kHz, 14.7kHz, 16kHz, 22.05kHz,
24kHz, 29.4kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz,
96kHz
• EXT Master/Slave Mode: 7.35kHz ~ 96kHz (256fs), 7.35kHz ~ 48kHz (384fs),
7.35kHz ~ 48kHz (512fs), 7.35kHz ~ 12kHz (1024fs)
6. μP I/F: 3-wire Serial, I2C Bus (Ver 1.0, 400kHz Fast-Mode)
7. Master/Slave mode
8. Audio Interface Format: MSB First, 2’s complement
• ADC: 24bit MSB justified, 16/24bit I2S
• DAC: 24bit MSB justified, 16bit LSB justified, 24bit LSB justified, 16/24bit I2S
9. Ta = −30 ∼ 85°C (SPK-Amp = OFF)
Ta = −30 ∼ 70°C (SPK-Amp = ON)
10. Power Supply:
• Analog Power Supply (AVDD): 2.85 ~ 3.5V
• Digital Power Supply (DVDD): 1.6 ~ 2.0V
• Digital I/O Power Supply (TVDD): DVDD ~ 3.5V
• Speaker Power Supply (SVDD): 0.9 ~ 5.5V
11. Package: 36pin QFN (5 x 5mm, 0.4mm pitch)
■ Block Diagram
AVDD
VSS1 REGFIL VCOM
DVDD TVDD VSS2
PMMP
MPWR2
MPWR1
PMVCM
MIC Power
Supply
LDO
+2.5V
I2C
Analog Block
PMADL
Control
Register
Charge pump
RIN1/DMCLK
LIN2
PMADR
PDN
PMADL or PMADR
ADC
External
MIC
SDTI
HPF1
RIN2
PMPFIL
MIC-Amp
HPF2
LIN3
Line In
CCLK/SCL
CDTIO/CAD0
LIN1/DDAT
Internal
MIC
CSN/SDA
BICK
LPF
RIN3
Audio
I/F
4-band EQ
LRCK
SDTI
PMBP
SVDD
PMSPK
Generator
1-band EQ
SPP
SPN
Speaker
SDTO
ALC
Beep
VSS4
Class-AB
SPK-AMP
SDTO
PMHPL
HPL
Cap-less
Headphone
PMDAC
DVL/R DEM
DAC
SMUTE
HPR
MCKO
PMPLL
PLL
MCKI
PMHPR
CP
PMHPL or PMHPR
Charge
Pump
AVDD
CN
PVEE VSS3
Figure 1. Block Diagram
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[AK4953A]
■ Ordering Guide
−30 ∼ +85°C
36pin QFN (0.4mm pitch)
Evaluation board for AK4953A
AK4953AEN
AKD4953A
CN
CP
VSS3
PVEE
HPR
HPL
DVDD
SPP
SPN
27
26
25
24
23
22
21
20
19
■ Pin Layout
AVDD
28
18
VSS4
VSS1
29
17
SVDD
REGFIL
30
16
I2C
VCOM
31
15
MCKO
LIN3
32
14
MCKI
RIN3
33
13
VSS2
LIN2
34
12
TVDD
RIN2
35
11
SDTO
MPWR2
36
10
BICK
AK4953A
6
7
8
9
CDTIO/CAD0
SDTI
LRCK
4
PDN
CCLK/SCL
3
RIN1/DMCLK
5
2
LIN1/DMDAT
CSN/SDA
1
MPWR1
Top View
MS1252-E-00
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-3-
[AK4953A]
■ Comparison with AK4645
Function
Resolution
AVDD
DVDD
HVDD
SVDD
TVDD
ADC DR, S/N
DAC S/N
Input level
Output level (Headphone)
ADC Input Selector
MIC Power Output Voltage
MIC-Amp
Digital MIC I/F
HPF(HPF1) after ADC
Notch Filter
Stereo Emphasis
Output Volume
AK4645
16bit
2.6V ∼ 3.6V
2.6V ∼ 3.6V
2.6V ∼ 5.25V
1.6V ~ 3.6V
86dB @ MGAIN = +20dB
95dB @ MGAIN = 0dB
92dB
typ. 0.6 x AVDD @ MIC Gain=0dB
typ. 0.6 x AVDD @LOVL=0dB
4 Stereo
0.8 x AVDD
0dB/+20dB/+26dB/+32dB
AK4953A
24bit
2.85V ∼ 3.5V
1.6V ~ 2.0V
0.9V ∼ 5.5V
DVDD ∼ 3.5V
88dB @ MGAIN = +20dB
96dB @ MGAIN = 0dB
96dB
typ. 2.4Vpp @ MIC Gain=0dB
typ. 1.75Vpp @ DVOL=0dB
3 Stereo
typ 2.3V (2 Line Outputs)
0dB/+12dB/+16dB/+20dB/+23dB/
+26dB/+29dB
No
Yes
Fixed (fc = 0.9Hz)
4 frequencies
(fc = 3.4Hz/13.6Hz/108.8Hz/217.6Hz
@ fs=44.1kHz)
No
5 Step (4 Step + 1 Step)
Yes
No
+36dB ∼ -54dB, 0.375dB Step (Note 1) +36dB ∼ -54dB, 0.375dB Step (Note 1)
& +12dB ∼ -115dB, 0.5dB Step
& +12dB ∼ -115dB, 0.5dB Step
No
Yes
11.2896MHz, 12MHz, 12.288MHz,
11.2896MHz, 12MHz, 13.5MHz,
13.5MHz, 24MHz, 27MHz
24MHz, 27MHz
256fs, 512fs, 1024fs
256fs, 384fs, 512fs, 1024fs
Speaker-Amp
Master Clock Reference for
PLL Mode
External Clock Mode
Master Clock
Power Supply Current
typ. 7.3mA
typ. 3.3mA
(Stereo Recording)
typ. 3.6mA
(Headphone Playback) typ. 10.6mA
32QFN (4 x 4mm, 0.4mm pitch)
36QFN (5 x 5mm, 0.4mm pitch)
Package
Note 1. ALC and Volume circuits are shared by input and output. Therefore, it is impossible to use ALC and Volume
control function at the same time for both recording and playback mode.
■ Compatibility with AK4953
1. Function
Function
Headphone Hi-Z Mode
AK4953
No
AK4953A
Yes
AK4953
0 (Pull-down by 10Ω)
AK4953A
0: Pull-down by 10Ω (Default)
1: Hi-Z
2. Register
Addr
05H
Bit
D2
MS1252-E-00
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-4-
[AK4953A]
PIN/FUNCTION
No.
1
Pin Name
MPWR1
LIN1
DMDAT
RIN1
DMCLK
I/O
O
I
I
I
O
Function
MIC Power Supply Pin for Microphone 1
Lch Analog Input 1 Pin
(DMIC bit = “0”)
2
Digital Microphone Data Input Pin
(DMIC bit = “1”)
Rch Analog Input 1 Pin
(DMIC bit = “0”)
3
Digital Microphone Clock pin
(DMIC bit = “1”)
Power-down & Reset
4
PDN
I
When “L”, the AK4953A is in power-down mode and is held in reset.
The AK4953A must be always reset upon power-up.
CSN
I
Chip Select Pin
(I2C pin = “L”)
5
SDA
I/O Control Data Input/Output Pin
(I2C pin = “H”)
CCLK
I
Control Data Clock Pin
(I2C pin = “L”)
6
SCL
I
Control Data Clock Pin
(I2C pin = “H”)
CDTIO
I/O Control Data Input/Output Pin
(I2C pin = “L”)
7
CAD0
I
Chip Address Select Pin
(I2C pin = “H”)
8
SDTI
I
Audio Serial Data Input Pin
9
LRCK
I/O Input/Output Channel Clock Pin
10 BICK
I/O Audio Serial Data Clock Pin
11 SDTO
O
Audio Serial Data Output Pin
12 TVDD
Digital I/O Power Supply Pin, 1.6 ~ 3.5V
13 VSS2
Ground 2 Pin
14 MCKI
I
External Master Clock Input Pin
15 MCKO
O
Master Clock Output Pin
16 I2C
I
Control Mode Select Pin “H”: I2C Bus, “L”: 3-wire Serial
17 SVDD
Speaker-Amp Power Supply Pin, 0.9 ~ 5.5V
18 VSS4
Ground 4 Pin
19 SPN
O
Speaker-Amp Negative Output Pin
20 SPP
O
Speaker-Amp Positive Output Pin
21 DVDD
Digital Power Supply Pin, 1.6 ~ 2.0V
22 HPL
O
Lch Headphone-Amp Output Pin
23 HPR
O
Rch Headphone-Amp Output Pin
Charge-Pump Circuit Negative Voltage Output Pin
24 PVEE
O
This pin must be connected to VSS3 with 2.2μF±50% capacitor in series.
25 VSS3
Ground 3 Pin
Positive Charge-Pump Capacitor Terminal Pin
26 CP
O
This pin must be connected to CN pin with 2.2μF±50% capacitor in series.
Negative Charge-Pump Capacitor Terminal Pin
27 CN
I
This pin must be connected to CP pin with 2.2μF±50% capacitor in series.
28 AVDD
Analog Power Supply Pin, 2.85 ~ 3.5V
29 VSS1
Ground 1 Pin
Regulator Ripple Filter Pin
30 REGFIL
O
This pin must be connected to VSS1 with 2.2μF±50% capacitor in series.
Common Voltage Output Pin
31 VCOM
O
Bias voltage of ADC inputs and DAC outputs.
This pin must be connected to VSS1 with 2.2μF±50% capacitor in series.
32 LIN3
I
Lch Analog Input 3 Pin
33 RIN3
I
Rch Analog Input 3 Pin
34 LIN2
I
Lch Analog Input 2 pin
35 RIN2
I
Rch Analog Input 2 Pin
36 MPWR2
O
MIC Power Supply Pin for Microphone 2
Note 2. All input pins except analog input pins (LIN1, RIN1, LIN2, RIN2, LIN3, RIN3) must not be left floating.
MS1252-E-00
2010/10
-5-
[AK4953A]
■ Handling of Unused Pin
The unused I/O pins must be processed appropriately as below.
Classification
Pin Name
MPWR1, MPWR2, SPN, SPP, HPL, HPR, CP, CN,
Analog
PVEE, LIN1/DMDAT, RIN1/DMCLK, LIN2,
RIN2, LIN3, RIN3
MCKO
Digital
MCKI
Setting
These pins must be open.
This pin must be open.
This pin must be connected to VSS2.
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=VSS4=0V; Note 3)
Parameter
Symbol
min
max
Units
Power Supplies: Analog
AVDD
6.0
V
−0.3
Digital
DVDD
2.5
V
−0.3
Digital I/O
TVDD
6.0
V
−0.3
Speaker-Amp
SVDD
6.0
V
−0.3
Input Current, Any Pin Except Supplies
IIN
mA
±10
Analog Input Voltage (Note 5)
VINA
AVDD+0.3
V
−0.3
Digital Input Voltage (Note 6)
VIND
TVDD+0.3
V
−0.3
Ambient Temperature (powered applied)
Ta
85
−30
°C
Storage Temperature
Tstg
150
−65
°C
Pd1
660
mW
Ta = 85°C (Note 8)
Maximum Power
Dissipation (Note 7)
Pd2
900
mW
Ta = 70°C (Note 9)
Note 3. All voltages are with respect to ground.
Note 4. VSS1, VSS2, VSS3 and VSS4 must be connected to the same analog ground plane.
Note 5. LIN1, RIN1, LIN2, RIN2, LIN3, RIN3 pins
Note 6. PDN, CSN, CCLK, CDTIO, SDTI, LRCK, BICK and MCKI pins
Pull-up resistors at SDA and SCL pins should be connected to (TVDD+0.3)V or less voltage.
Note 7. In case that PCB wiring density is 100% over. This power is the AK4953A internal dissipation that does not
include power dissipation of externally connected speakers.
Note 8. The Speaker Amplifier is not available.
Note 9. The Speaker Amplifier is available.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
MS1252-E-00
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[AK4953A]
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=VSS3=VSS4=0V; Note 3)
Parameter
Symbol
min
typ
max
Units
Power Supplies
Analog
AVDD
2.85
3.3
3.5
V
(Note 10) Digital
DVDD
1.6
1.8
2.0
V
Digital I/O
TVDD
DVDD
3.3
3.5
V
SPK-Amp
SVDD
0.9
3.3
5.5
V
Note 3. All voltages are with respect to ground.
Note 10. The power-up sequence between AVDD, DVDD, TVDD and SVDD is not critical. The PDN pin must be “L”
upon power up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit
error.
* When SVDD is powered ON and the PDN pin is “L”, AVDD, DVDD or TVDD can be powered
ON/OFF. When TVDD is powered ON and the PDN pin is “L”, AVDD, DVDD or SVDD can be
powered ON/OFF. When the AK4953A is changed from power down state to power ON, the
PDN pin must be “H” after all power supplies are ON.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1252-E-00
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-7-
[AK4953A]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=TVDD=SVDD=3.3V, DVDD=1.8V; VSS1=VSS2=VSS3=VSS4=0V; fs=44.1kHz, BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
min
typ
max
Units
Parameter
MIC Amplifier: LIN1, RIN1, LIN2, RIN2, LIN3, RIN3 pins
Input Resistance
20
30
40
kΩ
Gain
MGAIN2-0 bits = “000”
-1
0
+1
dB
+11
MGAIN2-0 bits = “001”
+12
+13
dB
+15
MGAIN2-0 bits = “010”
+16
+17
dB
+19
MGAIN2-0 bits = “011”
+20
+21
dB
MGAIN2-0 bits = “100”
+22
+23
+24
dB
MGAIN2-0 bits = “101”
+25
+26
+27
dB
MGAIN2-0 bits = “110”
+28
+29
+30
dB
MIC Power Supply: MPWR1, MPWR2 pins
Output Voltage
2.1
2.3
2.5
V
Output Noise Level (A-weighted)
-108
dBV
PSRR (f = 1kHz) (Note 11)
100
dB
Load Resistance
1.0
kΩ
Load Capacitance
30
pF
ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 pins → ADC → Programmable Filter
(IVOL=0dB, EQ=ALC=OFF) → SDTO
Resolution
24
Bits
(Note 12)
0.21
0.24
0.27
Vpp
Input Voltage
2.16
2.4
2.64
Vpp
(Note 13)
fs=44.1kHz
(Note 12)
72
82
dBFS
BW=20kHz (Note 13)
85
dBFS
S/(N+D) (-1dBFS)
(Note 12)
79
dBFS
fs=96kHz
BW=40kHz (Note 13)
80
dBFS
(Note 12)
78
88
dB
D-Range (−60dBFS, A-weighted)
96
dB
(Note 13)
(Note 12)
78
88
dB
S/N (A-weighted)
96
dB
(Note 13)
(Note 12)
75
90
dB
Interchannel Isolation
100
dB
(Note 13)
(Note 12)
0
0.8
dB
Interchannel Gain Mismatch
0
0.8
dB
(Note 13)
Note 11. PSR is applied to AVDD with 500mpVpp sine wave.
Note 12. MGAIN2-0 bits = “011” (+20dB)
Note 13. MGAIN2-0 bits = “000” (0dB)
MS1252-E-00
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[AK4953A]
min
typ
max
Units
Parameter
DAC Characteristics:
Resolution
24
Bits
Headphone-Amp Characteristics: DAC → HPL, HPR pins, ALC=OFF, OVOL=DVOL= 0dB, RL=16Ω
(0dBFS)
1.75
Vpp
Output Voltage (0dBFS)
(-3dBFS)
1.11
1.24
1.37
Vpp
fs=44.1kHz, BW=20kHz
80
dB
(0dBFS)
(Note 14)
S/(N+D)
fs=44.1kHz, BW=20kHz
70
80
dB
(-3dBFS)
fs=96kHz, BW=40kHz
77
dB
S/N (A-weighted)
86
96
dB
Interchannel Isolation
75
90
dB
Interchannel Gain Mismatch
0
0.8
dB
Output Offset Voltage
-1
0
+1
mV
PSRR (f = 1kHz) (Note 15)
80
dB
Load Resistance
16
Ω
Load Capacitance
300
pF
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, OVOL=DVOL= 0dB, RL=8Ω, BTL
Output Voltage (Note 16)
3.18
Vpp
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
3.20
4.00
4.80
Vpp
SPKG1-0 bits = “01”, −0.5dBFS (Po=250mW)
1.79
Vrms
SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW)
SPKG1-0 bits = “00”, −1.5dBFS (Po=100mW)
0.9
Vrms
(Note 17)
S/(N+D)
70
dB
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
40
70
dB
SPKG1-0 bits = “01”, −0.5dBFS (Po=250mW)
20
dB
SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW)
SPKG1-0 bits = “00”, −1.5dBFS (Po=100mW)
20
dB
(Note 17)
S/N (A-weighted)
85
95
dB
Output Offset Voltage
-30
0
+30
mV
PSRR (f = 1kHz) (Note 18)
50
dB
Load Resistance
6.8
8
Ω
Load Capacitance
30
pF
Note 14. When CPCK bit = “1”.
Note 15. PSR is applied to AVDD or DVDD with 500mpVpp sine wave.
Note 16. The output level is calculated by assuming that output signals are not clipped. In the actual case, the output signal
is clipped when DAC outputs 0dBFS signal. Therefore, DAC output level should be set to lower level by setting
digital volume so that Speaker-Amp output level is not clipped.
Note 17. When SVDD = 1.5V.
Note 18. PSR is applied to AVDD or SVDD with 500mpVpp sine wave.
MS1252-E-00
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-9-
[AK4953A]
min
typ
max
Units
Parameter
Power Supplies:
Power Up (PDN pin = “H”)
MIC + ADC + DAC + Headphone out
AVDD+DVDD+TVDD (Note 19)
8.9
13.4
mA
AVDD+DVDD+TVDD (Note 20)
6.1
mA
SVDD (No Load)
11
17
μA
MIC + ADC + DAC + Speaker out
AVDD+DVDD+TVDD (Note 21)
7.8
11.7
mA
AVDD+DVDD+TVDD (Note 22)
5.1
mA
SVDD (No Load)
1.3
2.0
mA
MIC + ADC (Note 23)
AVDD+DVDD+TVDD
3.3
mA
DAC + Headphone out (Note 24)
AVDD+DVDD+TVDD
3.6
mA
Power Down (PDN pin = “L”) (Note 25)
AVDD+DVDD+TVDD+SVDD
1
10
μA
SVDD (Note 26)
0
10
μA
Note 19. When PLL Master Mode (MCKI=12MHz), and PMADL=PMADR=PMDAC=PMPFIL=PMHPL=PMHPR=
PMVCM=PMPLL=MCKO=PMBP=PMMP=M/S bits = “1”. In this case, the MPWR1 (MPWR2) pin outputs
0mA. AVDD= 4.6 mA (typ), DVDD= 2.2 mA (typ), TVDD= 2.1 mA (typ).
Note 20. When EXT Slave Mode (PMPLL=M/S=MCKO bits =“0”), PMADL=PMADR=PMDAC=PMHPL=PMHPR=
PMVCM=PMBP=PMMP bits = “1”, and PMPFIL bit = “0”. In this case, the MPWR1 (MPWR2) pin outputs
0mA. AVDD= 4.2 mA (typ), DVDD= 1.8 mA(typ), TVDD= 0.1 mA (typ).
Note 21. When PLL Master Mode (MCKI=12MHz), and PMADL=PMADR=PMDAC=PMPFIL=PMSPK=PMVCM=
PMPLL=MCKO=PMBP=PMMP=M/S bits = “1”. In this case, the MPWR1 (MPWR2) pin outputs 0mA.
AVDD= 3.9 mA (typ), DVDD= 1.8 mA (typ), TVDD= 2.1 mA (typ).
Note 22. When EXT Slave Mode (PMPLL=M/S=MCKO bits =“0”), PMADL=PMADR=PMDAC=PMSPK=PMVCM=
PMBP=PMMP bits = “1”, and PMPFIL bit = “0”. In this case, the MPWR1 (MPWR2) pin outputs 0mA.
AVDD= 3.6 mA (typ), DVDD= 1.4 mA(typ), TVDD= 0.1 mA (typ).
Note 23. When EXT Slave Mode (PMPLL=M/S=MCKO bits =“0”), PMADL=PMADR=PMVCM bits = “1”, and
PMPFIL bit = “0”. AVDD= 2.2 mA (typ), DVDD= 1.0 mA(typ), TVDD= 0.1 mA (typ).
Note 24. When EXT Slave Mode (PMPLL=M/S=MCKO bits =“0”), PMDAC=PMHPL=PMHPR=PMVCM bits = “1”,
and PMPFIL bit = “0”. AVDD= 2.5 mA (typ), DVDD= 1.1 mA(typ), TVDD= 0 mA (typ).
Note 25. All digital input pins are fixed to TVDD or VSS2.
Note 26. When AVDD, DVDD, and TVDD are powered OFF.
MS1252-E-00
2010/10
- 10 -
[AK4953A]
■ Power Consumption on Each Operation Mode
Conditions: Ta=25°C; AVDD=TVDD=SVDD=3.3V, DVDD=1.8V; VSS1=VSS2=VSS3=VSS4=0V; fs=44.1kHz,
External Slave Mode, BICK=64fs; 1kHz, 0dBFS input; Headphone & Speaker = No output.
01H
PMHPR
Total Power
[mW]
PMHPL
SVDD
[mA]
PMADR
TVDD
[mA]
PMADL
DVDD
[mA]
PMDAC
All Power-down
LIN1/RIN1 → ADC
LIN1 (Mono) → ADC
DAC → HP
DAC → SPK
LIN1/RIN1 → ADC
& DAC → HP
LIN1/RIN1 → ADC
& DAC → SPK
AVDD
[mA]
PMSPK
Mode
PMVCM
00H
Power Management Bit
0
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
2.2
1.5
2.5
1.8
0
1.0
1.0
1.1
0.7
0
0.1
0.1
0
0
0
0
0
0
1.3
0
9.4
7.1
10.2
11.5
1
0
1
1
1
1
1
3.9
1.8
0.1
0
16.4
1
1
1
1
1
0
0
3.1
1.4
0.1
1.3
17.4
Table 1. Power Consumption on Each Operation Mode (typ)
MS1252-E-00
2010/10
- 11 -
[AK4953A]
ADC FILTER CHARACTERISTICS (fs=44.1kHz)
(Ta =25°C; AVDD=2.85~3.5V, DVDD=1.6∼2.0V, TVDD=DVDD~3.5V, SVDD=0.9 ∼ 5.5V)
Parameter
Symbol
min
typ
max
ADC Digital Filter (Decimation LPF):
Passband (Note 27)
PB
0
17.3
±0.16dB
19.4
−0.66dB
19.9
−1.1dB
22.1
−6.9dB
Stopband
SB
26.1
Passband Ripple
PR
±0.16
Stopband Attenuation
SA
73
Group Delay (Note 28)
GD
16
Group Delay Distortion
0
ΔGD
ADC Digital Filter (HPF): HPFC1-0 bits = “00”
Frequency Response
FR
3.4
−3.0dB
10
−0.5dB
22
−0.1dB
Units
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
Hz
Hz
Hz
ADC FILTER CHARACTERISTICS (fs=96kHz)
(Ta =25°C; AVDD=2.85~3.5V, DVDD=1.6∼2.0V, TVDD=DVDD ~ 3.5V, SVDD=0.9 ∼ 5.5V)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband (Note 27)
PB
0
37.7
kHz
±0.16dB
42.2
kHz
−0.66dB
43.3
kHz
−1.1dB
48.0
kHz
−6.9dB
Stopband
SB
56.8
kHz
Passband Ripple
PR
dB
±0.16
Stopband Attenuation
SA
73
dB
Group Delay (Note 28)
GD
16
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF): HPFC1-0 bits = “00”
Frequency Response
FR
7.4
Hz
−3.0dB
21.8
Hz
−0.5dB
47.9
Hz
−0.1dB
Note 27. The passband and stopband frequencies scale with fs (system sampling rate). Each response refers to that of
1kHz.
Note 28. A calculating delay time which induced by digital filtering. This time is from the input of an analog signal to the
setting of 24-bit data of both channels to the ADC output register. For the signal through the programmable
filters (First HPF + First LPF + 4-band Equalizer + ALC + Equalizer), the group delay is increased 4/fs from the
value above if there is no phase change by the IIR filter.
MS1252-E-00
2010/10
- 12 -
[AK4953A]
DAC FILTER CHARACTERISTICS (fs=44.1kHz)
(Ta =25°C; AVDD=2.85 ~ 3.5V, DVDD =1.6 ∼ 2.0V, TVDD=DVDD ~ 3.5V, SVDD=0.9 ∼ 5.5V; DEM=OFF)
Parameter
Symbol
min
typ
max
Units
DAC Digital Filter (LPF):
Passband (Note 29)
PB
0
20.0
kHz
±0.05dB
22.05
kHz
−6.0dB
Stopband
SB
24.1
kHz
Passband Ripple
PR
dB
±0.05
Stopband Attenuation
SA
54
dB
Group Delay (Note 30)
GD
22
1/fs
DAC Digital Filter (LPF) + SCF:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±1.0
DAC FILTER CHARACTERISTICS (fs=96kHz)
(Ta =25°C; AVDD=2.85 ~ 3.5V, DVDD =1.6 ∼ 2.0V, TVDD=DVDD ~ 3.5V, SVDD=0.9 ∼ 5.5V; DEM=OFF)
Parameter
Symbol
min
typ
max
Units
DAC Digital Filter (LPF):
Passband (Note 29)
PB
0
43.5
kHz
±0.05dB
48.0
kHz
−6.0dB
Stopband
SB
52.5
kHz
Passband Ripple
PR
dB
±0.05
Stopband Attenuation
SA
54
dB
Group Delay (Note 30)
GD
22
1/fs
DAC Digital Filter (LPF) + SCF:
FR
dB
Frequency Response: 0 ∼ 40.0kHz
±1.0
Note 29. The passband and stopband frequencies scale with fs (system sampling rate). Each response refers to that of
1kHz.
Note 30. A calculating delay time which induced by digital filtering. This time is from setting the 24bit data of both
channels to input register to the output of analog signal. For the signal through the programmable filters (First
HPF + First LPF + 4-band Equalizer + ALC + Equalizer), the group delay is increased 7/fs from the value above
if there is no phase change by the IIR filter.
MS1252-E-00
2010/10
- 13 -
[AK4953A]
DC CHARACTERISTICS
(Ta =25°C; AVDD=2.85 ~ 3.5V, DVDD =1.6 ∼ 2.0V, TVDD=DVDD ~ 3.5V, SVDD=0.9 ∼ 5.5V)
Parameter
Symbol
min
typ
max
Units
Audio Interface & Serial µP Interface
(CDTIO/CAD0, CSN/SDA, CCLK/SCL, I2C, PDN, BICK, LRCK, SDTI, MCKI pins )
High-Level Input Voltage
(TVDD ≥ 2.2V)
VIH
70%TVDD
V
(TVDD < 2.2V)
80%TVDD
V
Low-Level Input Voltage
(TVDD ≥ 2.2V)
VIL
30%TVDD
V
(TVDD < 2.2V)
20%TVDD
V
Audio Interface & Serial µP Interface (CDTIO, SDA, MCKO, BICK, LRCK, SDTO pins Output)
High-Level Output Voltage
(Iout = −80μA)
VOH
V
TVDD−0.2
Low-Level Output Voltage
(Except SDA pin : Iout = 80μA) VOL1
0.2
V
0.4
V
(SDA pin, 2.0V ≤ TVDD ≤ 3.5V: Iout = 3mA) VOL2
20%TVDD
V
(SDA pin, 1.6V ≤ TVDD < 2.0V: Iout = 3mA) VOL2
Input Leakage Current
Iin
±10
μA
Digital MIC Interface (DMDAT pin Input ; DMIC bit = “1”)
High-Level Input Voltage
VIH3
65%AVDD
V
Low-Level Input Voltage
VIL3
35%AVDD
V
Digital MIC Interface (DMCLK pin Output ; DMIC bit = “1”)
High-Level Output Voltage
(Iout=−80μA)
VOH3
AVDD-0.4
V
VOL3
0.4
V
Low-Level Output Voltage
(Iout= 80μA)
Input Leakage Current
Iin
±10
μA
MS1252-E-00
2010/10
- 14 -
[AK4953A]
SWITCHING CHARACTERISTICS
(Ta =25°C; AVDD=2.85 ~ 3.5V, DVDD =1.6 ∼ 2.0V, TVDD=DVDD ~ 3.5V, SVDD=0.9 ∼ 5.5V; CL=20pF)
Parameter
Symbol
min
typ
max
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
24.576
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
256fs at fs=32kHz, 29.4kHz
dMCK
33
LRCK Output Timing
Frequency
fs
7.35
96
Duty Cycle
Duty
50
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
BCKO bit = “1”
tBCK
1/(64fs)
Duty Cycle
dBCK
50
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
24.576
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
256fs at fs=32kHz, 29.4kHz
dMCK
33
LRCK Input Timing
Frequency
fs
7.35
96
Duty
Duty
45
55
BICK Input Timing
Period
tBCK
1/(64fs)
1/(32fs)
Pulse Width Low
tBCKL
0.4 x tBCK
Pulse Width High
tBCKH
0.4 x tBCK
-
MS1252-E-00
Units
MHz
ns
ns
MHz
%
%
kHz
%
ns
ns
%
MHz
ns
ns
MHz
%
%
kHz
%
ns
ns
ns
2010/10
- 15 -
[AK4953A]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
Duty
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
384fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs
fs
384fs
fs
512fs
fs
1024fs
fs
Duty
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
384fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
MS1252-E-00
min
typ
max
Units
7.35
45
-
96
55
kHz
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
1.8816
2.8224
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
24.576
18.432
24.576
12.288
-
MHz
MHz
MHz
MHz
ns
ns
7.35
7.35
7.35
7.35
45
-
96
48
48
12
55
kHz
kHz
kHz
kHz
%
156.25
65
65
-
-
ns
ns
ns
1.8816
2.8224
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
24.576
18.432
24.576
12.288
-
MHz
MHz
MHz
MHz
ns
ns
7.35
-
50
96
-
kHz
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2010/10
- 16 -
[AK4953A]
Parameter
Symbol
min
Audio Interface Timing
Master Mode
tMBLR
−20
BICK “↓” to LRCK Edge (Note 31)
tLRD
LRCK Edge to SDTO (MSB)
−35
(Except I2S mode)
tBSD
BICK “↓” to SDTO
−35
SDTI Hold Time
tSDH
25
SDTI Setup Time
tSDS
20
Slave Mode
tLRB
25
LRCK Edge to BICK “↑” (Note 31)
tBLR
25
BICK “↑” to LRCK Edge (Note 31)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
25
SDTI Setup Time
tSDS
20
Control Interface Timing (3-wire Mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTIO Setup Time
tCDS
40
CDTIO Hold Time
tCDH
40
CSN “H” Time
tCSW
150
tCSS
50
CSN Edge to CCLK “↑” (Note 32)
tCSH
50
CCLK “↑” to CSN Edge (Note 32)
tDCD
CCLK “↓” to CDTIO (at Read Command)
tCCZ
CSN “↑” to CDTIO (Hi-Z) (at Read Command)(Note 34)
Control Interface Timing (I2C Bus Mode):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 35)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Capacitive Load on Bus
Cb
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Note 31. BICK rising edge must not occur at the same time as LRCK edge.
Note 32. CCLK rising edge must not occur at the same time as CSN edge.
Note 33. I2C-bus is a trademark of NXP B.V.
Note 34. RL=1kΩ/10% change (pull-up or TVDD)
Note 35. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS1252-E-00
typ
max
Units
-
20
35
ns
ns
-
35
-
ns
ns
ns
-
45
ns
ns
ns
-
45
-
ns
ns
ns
-
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
2010/10
- 17 -
[AK4953A]
Parameter
Symbol
min
Digital Audio Interface Timing; fs = 7.35kHz ~ 48kHz, CL=100pF
DMCLK Output Timing
Period
tSCK
Rising Time
tSRise
Falling Time
tSFall
Duty Cycle
dSCK
40
Audio Interface Timing
DMDAT Setup Time
tSDS
50
DMDAT Hold Time
tSDH
0
Power-down & Reset Timing
PDN Pulse Width
(Note 36)
tPD
150
PMADL or PMADR “↑” to SDTO valid (Note 37)
ADRST1-0 bits = “00”
tPDV
ADRST1-0 bits = “01”
tPDV
ADRST1-0 bits = “10”, “11”
tPDV
Note 36. The AK4953A can be reset by the PDN pin = “L”.
Note 37. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
typ
max
Units
1/(64fs)
50
10
10
60
ns
ns
ns
%
-
-
ns
ns
-
-
ns
1059
267
2115
-
1/fs
1/fs
1/fs
■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%TVDD
LRCK
tLRCKH
tLRCKL
1/fMCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%TVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Note 38. MCKO is not available at EXT Master mode.
Figure 2. Clock Timing (PLL/EXT Master mode)
MS1252-E-00
2010/10
- 18 -
[AK4953A]
50%TVDD
LRCK
tMBLR
tBCKL
BICK
50%TVDD
tLRD
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 3. Audio Interface Timing (PLL/EXT Master mode)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
50%TVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 4. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin)
MS1252-E-00
2010/10
- 19 -
[AK4953A]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tLRCKL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 5. Clock Timing (EXT Slave mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
tLRD
SDTO
MSB
50%TVDD
tSDH
tSDS
VIH
SDTI
VIL
Figure 6. Audio Interface Timing (PLL/EXT Slave mode)
MS1252-E-00
2010/10
- 20 -
[AK4953A]
VIH
CSN
VIL
tCSH
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
CDTIO
A6
A5
R/W
VIH
VIL
Figure 7. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
CDTIO
VIL
D2
D1
VIH
D0
VIL
Figure 8. WRITE Data Input Timing
VIH
CSN
VIL
CCLK
Clock, H or L
D3
VIL
tCCZ
tDCD
CDTIO
VIH
D2
D1
D0
Hi-Z
50%
DVDD
Figure 9. Read Data Output Timing
MS1252-E-00
2010/10
- 21 -
[AK4953A]
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
Start
tSU:STO
Start
Stop
Figure 10. I2C Bus Mode Timing
tSCK
65%AVDD
DMCLK
50%AVDD
35%AVDD
tSCKL
tSRise
tSFall
dSCK = 100 x tSCKL / tSCK
Figure 11. DMCLK Clock Timing
65%AVDD
DMCLK
35%AVDD
tSDS
tSDH
VIH3
DMDAT
VIL3
Figure 30. Audio Interface Timing (DCLKP bit = “1”)
65%AVDD
DMCLK
35%AVDD
tSDS
tSDH
VIH3
DMDAT
VIL3
Figure 31. Audio Interface Timing (DCLKP bit = “0”)
MS1252-E-00
2010/10
- 22 -
[AK4953A]
PMADL bit
or
PMADR bit
tPDV
SDTO
50%TVDD
Figure 12. Power Down & Reset Timing 1
tPD
PDN
VIL
Figure 13. Power Down & Reset Timing 2
MS1252-E-00
2010/10
- 23 -
[AK4953A]
OPERATION OVERVIEW
■ System Clock
There are the following five clock modes to interface with external devices (Table 2, Table 3).
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode (Note 39)
1
1
Table 5
Figure 14
PLL Slave Mode 1
Table 5
Figure 15
1
0
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
Table 5
Figure 16
(PLL Reference Clock: LRCK or BICK
1
0
pin)
EXT Slave Mode
0
0
x
Figure 17
EXT Master Mode
0
1
x
Figure 18
Note 39. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from the MCKO pin.
Table 2. Clock Mode Setting (x: Don’t care)
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
MCKO bit
0
1
0
1
MCKO pin
L
Selected by
PS1-0 bits
L
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL3-0 bits
Selected by
PLL3-0 bits
BICK pin
Output
(Selected by
BCKO bit)
LRCK pin
Input
(≥ 32fs)
Input
(1fs)
Output
(1fs)
Input
Input
(Selected by
(1fs)
PLL3-0 bits)
Input
Input
Selected by
EXT Slave Mode
0
L
(1fs)
FS3-0 bits
(≥ 32fs)
Output
Selected by
Output
EXT Master Mode
0
L
(Selected by
FS3-0 bits
(1fs)
BCKO bit)
Note 40. When PMVCM bit = M/S bit = “1” and MCKI is input, LRCK and BICK are output, even if PMDAC bit =
PMADL bit = PMADR bit = “0”.
Table 3. Clock pins state in Clock Mode
PLL Slave Mode
(PLL Reference Clock: BICK pin)
0
L
GND
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4953A is in power-down mode (PDN pin = “L”) and when exits reset state, the AK44953 is in slave mode. After
exiting reset state, the AK4953A goes to master mode by changing M/S bit = “1”.
When the AK4953A is in master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The
LRCK and BICK pins of the AK4953A must be pulled-down or pulled-up by the resistor (about 100kΩ) externally to
avoid the floating state.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 4. Select Master/Slave Mode
MS1252-E-00
(default)
2010/10
- 24 -
[AK4953A]
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) circuit generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock times, when the AK4953A is supplied stable clocks or the sampling frequency is
changed after PLL is powered-up (PMPLL bit = “0” → “1”), are shown in Table 5.
1) PLL Mode Setting
PLL3 PLL2 PLL1 PLL0
PLL Reference
Input
PLL Lock Time
Mode
bit
bit
bit
bit
Clock Input Pin
Frequency
(max)
2 ms
2
0
0
1
0
BICK pin
32fs
3
0
0
1
1
BICK pin
64fs
2 ms
4
0
1
0
0
MCKI pin
11.2896MHz
10 ms
6
0
1
1
0
MCKI pin
12MHz
10 ms
7
0
1
1
1
MCKI pin
24MHz
10 ms
12
1
1
0
0
MCKI pin
13.5MHz
10 ms
13
1
1
0
1
MCKI pin
27MHz
10 ms
Others
Others
N/A
Note 41. PLL3-0 bits = “0000”(Default: N/A). When PLL mode is used, PLL3-0 bits must be set before PMPLL bit = “0”
Æ “1”.
Table 5. PLL Mode Setting (*fs: Sampling Frequency, N/A: Not Available)
2) Setting of sampling frequency in PLL Mode
When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in Table 6.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
DS bit Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
0
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
8
1
0
0
0
32kHz
9
1
0
0
1
48kHz
10
1
0
1
0
64kHz
1
11
1
0
1
1
96kHz
12
1
1
0
0
29.4kHz
0
13
1
1
0
1
44.1kHz
15
1
1
1
1
1
88.2kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1”
(Reference Clock = MCKI pin), (N/A: Not Available)
When PLL2 bit is “0” (PLL reference clock input is BICK pin), the sampling frequency is selected by FS1-0 bits (Table
7).
Sampling Frequency
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
DS bit
Range
0
x
x
0
0
7.35kHz ≤ fs ≤ 12kHz (default)
0
1
x
x
0
1
12kHz < fs ≤ 24kHz
2
x
x
1
0
24kHz < fs ≤ 48kHz
3
x
x
1
1
1
48kHz < fs ≤ 96kHz
Others
Others
N/A
Table 7. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2
(PLL Reference Clock: BICK pin), (x: Don’t care, N/A: Not Available)
MS1252-E-00
2010/10
- 25 -
[AK4953A]
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the LRCK pin goes to “L” and the BICK pin goes to “H”, and irregular frequency clock is output from the
MCKO pin when MCKO bit is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”,
the MCKO pin outputs “L” (Table 8).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
MCKO pin
BICK pin
LRCK pin
MCKO bit = “0” MCKO bit = “1”
After PMPLL bit “0” → “1”
“L” Output
Invalid
“H” Output
“L” Output
PLL Unlock (except the case above)
“L” Output
Invalid
Invalid
Invalid
PLL Lock
“L” Output
Table 10
Table 11
1fs Output
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0” →
“1”. Then, the clock selected by Table 10 is output from the MCKO pin when PLL is locked. ADC and DAC output
invalid data when the PLL is unlocked. DAC should be powered up by PMDAC bit “0” → “1” after PLL is locked.
MCKO pin
MCKO bit = “0”
MCKO bit = “1”
After PMPLL bit “0” → “1”
“L” Output
Invalid
PLL Unlock (except the case above)
“L” Output
Invalid
PLL Lock
“L” Output
Table 10
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
PLL State
MS1252-E-00
2010/10
- 26 -
[AK4953A]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the internal PLL
circuit generates MCKO, BICK and LRCK clocks. The MCKO output frequency is selected by PS1-0 bits (Table 10) and
the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit (Table
11).
11.2896MHz,12MHz, 13.5MHz,
24MHz, 27MHz
AK4953A
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 14. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 10. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BCKO bit
BICK Output Frequency
0
32fs
(default)
1
64fs
Table 11. BICK Output Frequency at Master Mode
MS1252-E-00
2010/10
- 27 -
[AK4953A]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pins. The required clock for
the AK4953A is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5).
a) PLL reference clock: MCKI pin
The BICK and LRCK inputs must be synchronized with MCKO output. The phase between MCKO and LRCK is not
important. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 10) and the output is enabled by MCKO
bit. Sampling frequency can be selected by FS3-0 bits and DS bit. (Table 6)
11.2896MHz, 12MHz, 13.5MHz,
24MHz, 27MHz
AK4953A
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 15. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
b) PLL reference clock: BICK pin
The sampling frequency corresponds to a range from 7.35kHz to 96kHz by changing FS3-0 bits and DS bit (Table 7).
AK4953A
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 16. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
MS1252-E-00
2010/10
- 28 -
[AK4953A]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4953A becomes EXT mode. Master clock can be input to the internal ADC and DAC
directly from the MCKI pin without internal PLL circuit operation. This mode is compatible with I/F of a normal audio
CODEC. The external clocks required to operate this mode are MCKI (256fs, 384fs, 512fs or 1024fs), LRCK (fs) and
BICK (≥32fs). The master clock (MCKI) must be synchronized with LRCK. The phase between these clocks is not
important. The input frequency of MCKI is selected by FS3-2 bits (Table 12).
Sampling Frequency
Range
0
0
0
7.35kHz ≤ fs ≤ 12kHz (default)
0
1
0
1
12kHz < fs ≤ 24kHz
0
0
256fs
2
1
0
24kHz < fs ≤ 48kHz
3
1
1
1
48kHz < fs ≤ 96kHz
4
0
0
7.35kHz ≤ fs ≤ 12kHz
0
1
0
384fs
5
0
1
12kHz < fs ≤ 24kHz
6
1
0
24kHz < fs ≤ 48kHz
8
0
0
7.35kHz ≤ fs ≤ 12kHz
1
0
0
512fs
9
0
1
12kHz < fs ≤ 24kHz
10
1
0
24kHz < fs ≤ 48kHz
12
1
1
0
0
0
1024fs
7.35kHz ≤ fs ≤ 12kHz
Others
Others
N/A
N/A
Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”), (N/A: Not Available)
Mode
MCKI Input
Frequency
FS3 bit FS2 bit FS1 bit FS0 bit DS bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through HPL/HPR pins is shown in Table 13.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83 dB
384fs
83 dB
512fs
95 dB
1024fs
96 dB
Table 13. Relationship between MCKI and S/N of HPL/HPR pins
MCKI
AK4953A
DSP or μP
MCKO
MCKI
BICK
LRCK
256fs, 384fs,
512fs or 1024fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 17. EXT Slave Mode
MS1252-E-00
2010/10
- 29 -
[AK4953A]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4953A becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock can be input to
the internal ADC and DAC directly from the MCKI pin without the internal PLL circuit operation. The external clock
required to operate the AK4953A is MCKI (256fs, 384fs, 512fs or 1024fs). The input frequency of MCKI is selected by
FS3-2 bits (Table 14).
Sampling Frequency
Range
0
0
0
7.35kHz ≤ fs ≤ 12kHz (default)
0
1
0
1
12kHz < fs ≤ 24kHz
0
0
256fs
2
1
0
24kHz < fs ≤ 48kHz
3
1
1
1
48kHz < fs ≤ 96kHz
4
0
0
7.35kHz ≤ fs ≤ 12kHz
0
1
0
384fs
5
0
1
12kHz < fs ≤ 24kHz
6
1
0
24kHz < fs ≤ 48kHz
8
0
0
7.35kHz ≤ fs ≤ 12kHz
1
0
0
512fs
9
0
1
12kHz < fs ≤ 24kHz
10
1
0
24kHz < fs ≤ 48kHz
12
1
1
0
0
0
1024fs
7.35kHz ≤ fs ≤ 12kHz
Others
Others
N/A
N/A
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (N/A: Not Available)
Mode
MCKI Input
Frequency
FS3 bit FS2 bit FS1 bit FS0 bit DS bit
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through HPL/HPR pins is shown in Table 15.
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83 dB
384fs
83 dB
512fs
95 dB
1024fs
96 dB
Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
AK4953A
DSP or μP
MCKO
MCKI
BICK
LRCK
256fs, 384fs,
512fs or 1024fs
32fs or 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 18. EXT Master Mode
BCKO bit
BICK Output Frequency
0
32fs
(default)
1
64fs
Table 16. BICK Output Frequency at Master Mode
MS1252-E-00
2010/10
- 30 -
[AK4953A]
■ System Reset
Upon power-up, the AK4953A must be reset by bringing the PDN pin = “L”. This reset is released when a dummy
command is input after the PDN pin = “H”. This ensures that all internal registers reset to their initial value. Dummy
command is executed by writing all “0” to the register address 00H. It is recommended to set the PDN pin = “L” before
power up the AK4953A.
CSN
0
CCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
“H” or “L”
CDTIO “H” or “L”
“H” or “L”
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
R/W:
A6-A0:
D7-D0:
“H” or “L”
READ/WRITE (“1”: WRITE)
Register Address (00H)
Control data (Input), (00H)
Figure 19. Dummy Command in 3-wired Serial Mode
S
T
A
R
T
SDA
S
S
T
O
P
R/W="0"
Slave
Address
Sub
Address(00H)
Data(00H)
N
A
C
K
N
A
C
K
P
N
A
C
K
Figure 20. Dummy Command in I2C-bus Mode
The ADC enters an initialization cycle when the PMADL or PMADR bit is changed from “0” to “1”. The initialization
cycle time is set by ADRST1-0 bits (Table 17). During the initialization cycle, the ADC digital data outputs of both
channels are forced to a 2's complement, “0”. The ADC output reflects the analog input signal after the initialization cycle
is complete. When using a digital microphone, the initialization cycle is the same as ADC’s.
Note 42. The initial data of ADC has offset data that depends on the condition of the microphone and the cut-off
frequency of HPF. If this offset is not small, make initialization cycle longer by setting ADRST1-0 bits or do not
use the initial data of ADC.
ADRST1
bit
0
0
1
1
ADRST0
bit
0
1
0
1
Init Cycle
Cycle
fs = 8kHz
fs = 16kHz fs = 44.1kHz
1059/fs
132.4ms
66.2ms
24ms
267/fs
33.4ms
16.7ms
N/A
2115/fs
264.4ms
132.2ms
48ms
2115/fs
264.4ms
132.2ms
48ms
Table 17. ADC Initialization Cycle (N/A: Not Available)
MS1252-E-00
fs = 96kHz
11ms
N/A
22ms
22ms
(default)
2010/10
- 31 -
[AK4953A]
■ Audio Interface Format
Four types of data formats are available and selected by setting the DIF1-0 bits (Table 18). In all modes, the serial data is
MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK
are output from the AK4953A in master mode, but must be input to the AK4953A in slave mode. The SDTO is clocked
out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”) of BICK.
Mode
0
1
2
DIF1 bit
0
0
1
3
DIF0 bit
0
1
0
1
SDTO (ADC)
24bit MSB justified
24bit MSB justified
24bit MSB justified
SDTI (DAC)
24bit LSB justified
16bit LSB justified
24bit MSB justified
2
1
BICK
≥ 48fs
≥ 32fs
≥ 48fs
=32fs or
≥ 48fs
2
I S Compatible
I S Compatible
Figure
Figure 21
Figure 22
Figure 23
(default)
Figure 24
Table 18. Audio Interface Format
If 24-bit (16-bit) data, the output of ADC, is converted to 8-bit data by removing LSB 16-bit (8-bit), “−1” at 24-bit (16bit)
data is converted to “−1” at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted
to “−65536” at 24-bit (“−256” at 16-bit) data which is a large offset. This offset can be removed by adding the offset of
“32768” at 24-bit (“128” at 16-bit) to 24-bit (16-bit) data before converting to 8-bit data.
LRCK
0
1
2
8
9
10
20
21
31
0
1
2
8
9
10
20
21
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
16 15 14
Don’t Care
0
23 22
23:MSB, 0:LSB
23 22
12 11
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
12 11
1
0
Rch Data
Figure 21. Mode 0 Timing
LRCK
0
1
2
3
7
8
9
10
12
13
14
15
0
1
2
3
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
23 22 21
15 14 13 12 11 10
9
8
23 22 21
15 14 13 12 11 10
9
8
23
SDTI(i)
15 14 13
7
1
0
15 14 13
7
1
0
15
0
1
2
3
15
6
16
5
17
4
18
3
23
2
24
31
30
0
1
2
3
15
6
16
5
17
4
18
3
23
2
24
25
31
30
1
BICK(64fs)
SDTO(o)
23 22 21
SDTI(i)
Don’t Care
8
7
6
5
15
14 13 8
23 22 21
0
2
1
0
Don’t Care
8
7
6
5
15
14 13 8
23
0
2
1
0
24bit: 23:MSB, 0:LSB
16bit: 15: MSB, 0:LSB
Lch Data
Rch Data
Figure 22. Mode 1 Timing
MS1252-E-00
2010/10
- 32 -
[AK4953A]
LRCK
0
1
2
18
19
20
21
22
23
24
25
0
1
2
18
19
20
21
22
23
24
25
0
1
BCLK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
23
Rch Data
Figure 23. Mode 2 Timing
LRCK
0
1
2
3
7
8
9
10
12
13
14
15
0
1
2
3
8
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
8
23 22
16 15 14 13 12 11
10 9
8
23 22
16 15 14 13 12 11
10 9
8
SDTI(i)
8
23 22
16 15 14 13 12 11
10 9
8
23 22
16 15 14 13 12 11
10 9
8
0
1
2
3
19
20
21
22
23
24
25
0
1
2
3
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 24. Mode 3 Timing
■ Mono/Stereo Mode
PMADL, PMADR, PMDML and PMDMR bits set mono/stereo ADC operation. When changing ADC operation and
analog/digital microphone, PMADL, PMADR, PMDML and PMDMR bits must be set “0” at first. When DMIC bit =
“1”, PMADL and PMADR bit settings are ignored. When DMIC bit = “0”, PMDML and PMDMR bit settings are
ignored.
PMADL bit
0
0
1
1
PMADR bit
ADC Lch data
ADC Rch data
0
All “0”
All “0”
1
Rch Input Signal
Rch Input Signal
0
Lch Input Signal
Lch Input Signal
1
Lch Input Signal
Rch Input Signal
Table 19. Mono/Stereo ADC operation (Analog MIC)
PMDML bit
0
0
1
1
PMDMR bit
ADC Lch data
ADC Rch data
0
All “0”
All “0”
1
Rch Input Signal
Rch Input Signal
0
Lch Input Signal
Lch Input Signal
1
Lch Input Signal
Rch Input Signal
Table 20. Mono/Stereo ADC operation (Digital MIC)
MS1252-E-00
(default)
(default)
2010/10
- 33 -
[AK4953A]
■ MIC/LINE Input Selector
The AK4953A has an input selector. INL1-0 and INR1-0 bits select LIN1/LIN2 /LIN3 and RIN1/RIN2/RIN3,
respectively. When DMIC bit = “1”, digital microphone input is selected regardless of INL and INR bits.
DMIC bit
0
1
INL1 bit
0
0
0
0
0
0
1
1
1
INL0 bit INR1 bit INR0 bit
Lch
Rch
0
0
0
LIN1
RIN1
0
0
1
LIN1
RIN2
0
1
0
LIN1
RIN3
1
0
0
LIN2
RIN1
1
0
1
LIN2
RIN2
1
1
0
LIN2
RIN3
0
0
0
LIN3
RIN1
0
0
1
LIN3
RIN2
0
1
0
LIN3
RIN3
Others
N/A
N/A
x
x
x
x
Digital Microphone
Table 21. MIC/Line In Path Select (x: Don’t care, N/A: Not available)
(default)
■ MIC Gain Amplifier
The AK4953A has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN3-0 bits
(Table 22). The typical input impedance is 30kΩ.
MGAIN2 bit
0
0
0
0
1
1
1
MGAIN1 bit
MGAIN0 bit
Input Gain
0
0
0dB
0
1
+12dB
1
0
+16dB
1
1
+20dB
0
0
+23dB
0
1
+26dB
1
0
+29dB
Others
N/A
Table 22. Input Gain (N/A: Not available)
MS1252-E-00
(default)
2010/10
- 34 -
[AK4953A]
■ MIC Power
When PMMP bit = “1”, the MPWR1 or MPWR2 pin supplies power for the microphones. This output voltage is typically
2.3V and the load resistance is minimum 1kΩ. In case of using two sets of stereo microphones, the load resistance is
minimum 2kΩ for each channel. Any capacitor must not be connected directly to the MPWR1 and MPWR2 pins (Figure
25).
PMMP bit
0
1
MPSEL bit
Output
x
Hi-Z
0
MPWR1 pin
1
MPWR2 pin
Table 23. MIC Power
(default)
MIC Power
MPWR1 pin
≥ 2k Ω
≥ 2kΩ
“MPSEL”
≥ 2k Ω
≥ 2k Ω
MPWR2 pin
Microphone
LIN1 pin
Microphone
RIN1 pin
Microphone
LIN2 pin
Microphone
RIN2 pin
Figure 25. MIC Block Circuit
MS1252-E-00
2010/10
- 35 -
[AK4953A]
■ Digital MIC
1. Connection to Digital Microphones
The AK4953A can be connected to a digital microphone by setting DMIC bit = “1”, and it supports sampling frequency
up to 48kHz. When DMIC bit is set to “1”, the LIN1 and RIN1 pins become DMDAT (digital microphone data input) and
DMCLK (digital microphone clock supply) pins respectively. The same voltage as AVDD must be provided to the digital
microphone. The Figure 26 and Figure 27 show mono/stereo connection examples. The DMCLK signal is output from the
AK4953A, and the digital microphone outputs 1bit data, which generated by ΔΣModulator using, from DMDAT.
PMDML/R bits control power up/down of the digital block (Decimation Filter and Digital Filter). PMADL/PMADR bits
settings do not affect the digital microphone power management. The DCLKE bit controls ON/OFF of the output clock
from the DMCLK pin. When the AK4953A is powered down (PDN pin= “L”), the DMCLK and DMDAT pins are
floating state. Pull-down resistors must be connected to the DMCLK and DMDAT pins externally to avoid this floating
state.
AVDD
AK4953A
VDD
DMCLK(64fs)
AMP
MCKI
PLL
100kΩ
ΔΣ
Modulator
Decimation
Filter
DMDAT
Lch
HPF1
Programmable
Filter
SDTO
ALC
R
VDD
AMP
ΔΣ
Modulator
Rch
Figure 26. Connection Example of Stereo Digital MIC
AVDD
AK4953A
VDD
DMCLK(64fs)
AMP
ΔΣ
PLL
MCKI
100kΩ
Modulator
DMDAT
Decimation
Filter
HPF1
Programmable
Filter
ALC
SDTO
R
Figure 27. Connection Example of Mono Digital MIC
MS1252-E-00
2010/10
- 36 -
[AK4953A]
2. Interface
The input data channel of the DMDAT pin is set by DCLKP bit. When DCLKP bit = “1, Lch data is input to the
decimation filter if DMCLK = “H”, and Rch data is input if DMCLK = “L”. When DCLKP bit = “0”, Rch data is input to
the decimation filter if DMCLK = “H”, and Lch data is input if DMCLK = “L”. The DMCLK pin outputs “L” when
DCLKE bit = “0”, and only supports 64fs. In this case, necessary clocks must be supplied to the AK4953A for ADC
operation. The output data through “the Decimation and Digital Filters” is 24bit full scale when the 1bit data density is
0%~100%.
DCLKP bit
0
1
DMCLK = “H”
DMCLK = “L”
Rch
Lch
Lch
Rch
Table 24. Data In/Output Timing with Digital MIC
(default)
DMCLK(64fs)
DMDAT (Lch)
Valid
Data
Valid
Data
Valid
Data
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 28. Data In/Output Timing with Digital MIC (DCLKP bit = “1”)
DMCLK(64fs)
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 29. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)
MS1252-E-00
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- 37 -
[AK4953A]
■ Digital Block
The digital block consists of the blocks shown in Figure 30. Recording path and playback path is selected by setting
ADCPF bit, PFDAC bit and PFSDO bit. (Figure 31 ~ Figure 34, Table 25)
PMADL/R bit or
PMDML/R bit
SDTI
ADC
1st Order
HPFAD bit
HPF1
ADCPF bit
“1”
“0”
PMPFIL bit
HPF bit
LPF bit
1st Order
HPF2
1st Order
LPF
4 Band
EQ5-2 bit
EQ
ALC1/2 bits
ALC
(Volume)
1 Band
EQ1 bit
“0”
EQ
“1”
“1”
PFSDO bit
“0”
PFDAC bit
PMDAC bit
DVL/R
SMUTE
SDTO
DAC
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
ADC: Includes the Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”.
HPF1: Includes the Digital Filter (HPF) for ADC as shown in “FILTER CHRACTERISTICS”.
DAC: Includes the Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”.
HPF2: High Pass Filter. Applicable for use as Wind-Noise Reduction Filter. (See “Digital Programmable Filter
Circuit”)
LPF: Low Pass Filter (See “Digital Programmable Filter Circuit”)
4 Band EQ: Applicable for use as Equalizer or Notch Filter. (See “Digital Programmable Filter Circuit”)
Volume: Input Digital Volume with ALC function. (See “Input Digital Volume” and “ALC Operation”)
1 Band EQ: Applicable for use as Equalizer or Notch Filter. (See “Digital Programmable Filter Circuit”)
DVL/R, SMUTE: Digital volume with soft mute function for playback path (See “Output Digital Volume2” )
Figure 30. Digital Block Path Select
MS1252-E-00
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- 38 -
[AK4953A]
ADCPF bit
PFDAC bit
Mode
Recording Mode 1
1
0
Playback Mode 1
0
1
Recording Mode 2 & Playback Mode 2
x
0
(Programmable Filter Bypass Mode: PMPFIL bit = “0”)
Loopback Mode
1
1
Table 25. Recording Playback Mode (x: Don’t care)
1
0
Figure
Figure 31
Figure 32
0
Figure 33
1
Figure 34
PFSDO bit
LPF bit, HPF bit, EQ0 bit, EQ1 bit, EQ2 bit, EQ3 bit, EQ4 bit, EQ5 bit, ACL1 bit and ALC2 bit must be “0” when
changing those modes.
ADC
DAC
1st Order
1st Order
1st Order
4 Band
HPF1
HPF2
LPF
EQ
SMUTE
1 Band
ALC
EQ
(Volume)
DVL/R
Figure 31. Path at Recording Mode 1 (default)
1st Order
ADC
HPF1
DAC
SMUTE
DVL/R
1 Band
ALC
EQ
(Volume)
4 Band
1st Order
1st Order
EQ
LPF
HPF2
Figure 32. Path at Playback Mode 1
1st Order
ADC
HPF1
DAC
SMUTE
DVL/R
Figure 33. Path at Recording Mode 2 & Playback Mode 2
ADC
DAC
1st Order
1st Order
1st Order
4 Band
HPF1
HPF2
LPF
EQ
SMUTE
ALC
(Volume)
1 Band
EQ
DVL/R
Figure 34. Path at Loopback Mode
■ Digital HPF1
A digital High Pass Filter (HPF) is integrated for DC offset cancellation of the ADC input. The cut-off frequencies of the
HPF1 are set by HPFC1-0 bits (Table 26). It is proportional to the sampling frequency (fs) and default is 3.4Hz (@fs =
44.1kHz). HPFAD bit controls the ON/OFF of the HPF1 (HPF ON is recommended).
HPFC1 bit
HPFC0 bit
0
0
1
1
0
1
0
1
fc
fs=96kHz
fs=44.1kHz
fs=22.05kHz
7.4Hz
3.4Hz
1.7Hz
29.6Hz
13.6Hz
6.8Hz
236.8Hz
108.8Hz
54.4Hz
473.6Hz
217.6Hz
108.8Hz
Table 26. HPF1 Cut-off Frequency
MS1252-E-00
fs=8kHz
0.62Hz
2.47Hz
19.7Hz
39.5Hz
(default)
2010/10
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[AK4953A]
■ Digital Programmable Filter Circuit
(1) High Pass Filter (HPF2)
Normally, this HPF is used for Wind-Noise Reduction. This is composed 1st order HPF. The coefficient of HPF is set by
F1A13-0 bits and F1B13-0 bits. HPF bit controls ON/OFF of the HPF2. When the HPF2 is OFF, the audio data passes
this block by 0dB gain. The coefficient must be set when HPF bit = “0” or PMPFIL bit = “0”. The HPF2 starts operation
4/fs(max) after when HPF bit=PMPFIL bit= “1” is set.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 43)
HPF: F1A[13:0] bits =A, F1B[13:0] bits =B
(MSB=F1A13, F1B13; LSB=F1A0, F1B0)
1 − 1 / tan (πfc/fs)
1 / tan (πfc/fs)
A=
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
Transfer function
1 − z −1
H(z) = A
1 + Bz −1
The cut-off frequency must be set as below.
fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz)
(2) Low Pass Filter (LPF)
This is composed with 1st order LPF. F2A13-0 bits and F2B13-0 bits set the coefficient of LPF. LPF bit controls ON/OFF
of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when LPF bit
= “0” or PMPFIL bit = “0”. The LPF starts operation 4/fs(max) after when LPF bit =PMPFIL bit= “1” is set.
fs: Sampling frequency
fc: Cut-off frequency
Register setting (Note 43)
LPF: F2A[13:0] bits =A, F2B[13:0] bits =B
(MSB=F2A13, F2B13; LSB=F2A0, F2B0)
1 − 1 / tan (πfc/fs)
1
A=
,
1 + 1 / tan (πfc/fs)
B=
1 + 1 / tan (πfc/fs)
Transfer function
1 + z −1
H(z) = A
1 + Bz −1
The cut-off frequency must be set as below.
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
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[AK4953A]
(3) 4-band Equalizer & 1-band Equalizer after ALC
This block can be used as Equalizer or Notch Filter. 4-band Equalizer (EQ2, EQ3, EQ4 and EQ5) is switched ON/OFF
independently by EQ2, EQ3, EQ4 and EQ5 bits. The equalizer after ALC (EQ1) is controlled by EQ1 bit. When Equalizer
is OFF, the audio data passes this block by 0dB gain. E1A15-0, E1B15-0 and E1C15-0 bits set the coefficient of EQ1.
E2A15-0, E2B15-0 and E2C15-0 bits set the coefficient of EQ2. E3A15-0, E3B15-0 and E3C15-0 bits set the coefficient
of EQ3. E4A15-0, E4B15-0 and E4C15-0 bits set the coefficient of EQ4. E5A15-0, E5B15-0 and E5C15-0 bits set the
coefficient of EQ5. The EQx (x=1∼5) coefficient must be set when EQx bit = “0” or PMPFIL bit = “0”. EQ1-5 start
operation 4/fs(max) after when EQx (x=1~5) = PMPFIL bit = “1”is set.
fs: Sampling frequency
fo1 ~ fo5: Center frequency
fb1 ~ fb5: Band width where the gain is 3dB different from center frequency
K1 ~ K5: Gain (−1 ≤ Kn ≤ 3)
Register setting (Note 43)
EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1
EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2
EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3
EQ4: E4A[15:0] bits =A4, E4B[15:0] bits =B4, E4C[15:0] bits =C4
EQ5: E5A[15:0] bits =A5, E5B[15:0] bits =B5, E5C[15:0] bits =C5
(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15,
E5A15, E5B15, E5C15 ; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0,
E4C0, E5A0, E5B0, E5C0)
An = Kn x
tan (πfbn/fs)
2
, Bn = cos(2π fon/fs) x
1 + tan (πfbn/fs)
1 + tan (πfbn/fs)
,
Cn =
1 − tan (πfbn/fs)
1 + tan (πfbn/fs)
(n = 1, 2, 3, 4, 5)
Transfer function
H(z) = {1 + h2(z) + h3(z) + h4(z) + h5(z) } x h1(z)
1 − z −2
hn (z) = An
1− Bnz −1− Cnz −2
(n = 1, 2, 3, 4, 5)
The center frequency must be set as below.
fon / fs < 0.497
When gain of K is set to “-1”, this equalizer becomes a notch filter. When EQ2 ∼EQ5 is used as a notch filter, central
frequency of a real notch filter deviates from the above-mentioned calculation, if its central frequency of each band is near.
The control soft that is attached to the evaluation board has functions that revises a gap of frequency and calculates the
coefficient. When its central frequency of each band is near, the central frequency should be revised and confirm the
frequency response.
Note 43. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s
complement)]
X = (Real number of filter coefficient calculated by the equations above) x 213
X must be rounded to integer, and then should be translated to binary code (2’s complement).
MSB of each filter coefficient setting register is sine bit.
MS1252-E-00
2010/10
- 41 -
[AK4953A]
■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block when ALC bit is “1”. When ADCPF bit is “1”, ALC
circuit operates at recording path. When ADCPF bit is “0”, ALC circuit operates at playback path. ALC1 bit controls
ON/OFF of ALC operation at recording path, and ALC2 bit controls of ON/OFF of ALC operation at playback path.
Note 44. In this section, VOL means IVL and IVR for recording path, OVL and OVR for playback path.
Note 45. In this section, ALC bit means ALC1 bit for recording path, ALC2 bit for playback path.
Note 46. In this section, REF means IREF for recording path, OREF for playback path.
1.
ALC Limiter Operation
During ALC limiter operation, when either L or R channel output level exceeds the ALC limiter detection level (Table
27), the VOL value (same value for both L and R) is attenuated automatically by the amount defined by the ALC limiter
ATT step (Table 28). The VOL is then set to the same value for both channels.
When ZELMN bit = “0” (zero cross detection is enabled), the VOL value is changed by ALC limiter operation at the
individual zero crossing points of L channel and R channel, or at the zero crossing timeout. ZTM1-0 bits set the zero
crossing timeout period of both ALC limiter and recovery operation (Table 29). When ALC output level exceeds
full-scale at LFST bit = “1”, VOL values are immediately (Period: 1/fs) changed in 1step(L/R common). When ALC
output level is less than full-scale, VOL values are changed at the individual zero crossing point of each channels or at the
zero crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled), VOL value is immediately (period: 1/fs) changed by ALC
limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input signal
level exceeds ALC limiter detection level.
LMTH1 bit LMTH0 bit ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level
0
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
0
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
1
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 27. ALC Limiter Detection Level / Recovery Counter Reset Level
(default)
ALC Limiter ATT Step
LMAT1 bit LMAT0 bit ALC Output
≥ LMTH
0
0
1
1
0
1
0
1
ALC Output
≥ FS
ALC Output
≥ FS + 6dB
1
1
2
2
2
4
1
2
Table 28. ALC Limiter ATT Step
MS1252-E-00
1
2
4
4
ALC Output
≥ FS + 12dB
1
2
8
8
(default)
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[AK4953A]
ZTM1
bit
0
0
1
1
2.
ZTM0
bit
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 29. ALC Zero Crossing Timeout Period
96kHz
1.3ms
2.7ms
5.3ms
10.7ms
(default)
ALC Recovery Operation
ALC recovery operation wait for the WTM2-0 bits (Table 30) to be set after completing ALC limiter operation. If the
input signal does not exceed “ALC recovery waiting counter reset level” (Table 27) during the wait time, ALC recovery
operation is executed. The VOL value is automatically incremented by RGAIN1-0 bits (Table 31) up to the set reference
level (Table 32) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 29). The ALC recovery
operation is executed in a period set by WTM2-0 bits. If the setting of ZTM1-0 is longer than WTM2-0 and no zero
crossing occurs, the ALC recovery operation is executed at a period set by ZTM1-0 bits.
For example, when the current VOL value is 30H and RGAIN1-0 bits are set to “01”, VOL is changed to 32H by auto
limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the VOL value exceeds the
reference level (REF7-0), the VOL values are not increased.
When
“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”
during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When
“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,
the waiting timer of ALC recovery operation starts.
ALC operations correspond to the impulse noise. When the impulse noise is input, the ALC recovery operation becomes
faster than a normal recovery operation. When large noise is input to a microphone instantaneously, the quality of small
level in the large noise can be improved by this fast recovery operation. The speed of first recovery operation is set by
RFST1-0 bits (Table 34).
WTM2
bit
0
0
0
0
1
1
1
1
WTM1
bit
0
0
1
1
0
0
1
1
WTM0
bit
0
1
0
1
0
1
0
1
ALC Recovery Operation Waiting Period
8kHz
16kHz
44.1kHz
96kHz
128/fs
16ms
8ms
2.9ms
1.3ms
256/fs
32ms
16ms
5.8ms
2.7ms
512/fs
64ms
32ms
11.6ms
5.3ms
1024/fs
128ms
64ms
23.2ms
10.7ms
2048/fs
256ms
128ms
46.4ms
21.3ms
4096/fs
512ms
256ms
92.9ms
42.7ms
8192/fs
1024ms
512ms
185.8ms
85.3ms
16384/fs
2048ms
1024ms
371.5ms
170.7ms
Table 30. ALC Recovery Operation Waiting Period
RGAIN1 bit
0
0
1
1
RGAIN0 bit
GAIN STEP
0
1 step
0.375dB
1
2 step
0.750dB
0
3 step
1.125dB
1
4 step
1.500dB
Table 31. ALC Recovery GAIN Step
MS1252-E-00
(default)
(default)
2010/10
- 43 -
[AK4953A]
IREF7-0bits
GAIN (0dB)
Step
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E1H
+30.0
(default)
0.375dB
:
:
92H
+0.375
91H
0.0
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 32. Reference Level at ALC Recovery Operation for Recoding
OREF5-0bits
GAIN (0dB)
Step
3CH
+36.0
3BH
+34.5
3AH
+33.0
:
:
28H
+6.0
(default)
1.5dB
:
:
25H
+1.5
24H
0.0
23H
-1.5
:
:
2H
-51.0
1H
-52.5
0H
-54.0
Table 33. Reference Level at ALC Recovery Operation for Playback
RFST1 bit
RFST0 bit
Recovery Speed
0
0
Quad Speed
(default)
0
1
8times
1
0
16times
1
1
N/A
Table 34. First Recovery Speed Setting (N/A: Not available)
MS1252-E-00
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[AK4953A]
3.
The Volume at ALC Operation
The volume value during ALC operation is reflected in VOL7-0 bits. It is enable to check the current volume value by
reading the register value of VOL7-0 bits.
VOL7-0bits
GAIN (0dB)
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
C5H
+19.5
:
:
92H
+0.375
91H
0.0
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 35. Value of VOL7-0 bits
4.
Example of ALC Setting
Table 36 and Table 37 show the examples of the ALC setting for recording and playback path.
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits must be the same value
or larger value than ZTM1-0 bits
Maximum gain at recovery operation
WTM2-0
IREF7-0
IVL7-0,
IVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC1
Gain of IVOL
Data
01
0
01
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
Data
01
0
11
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
001
32ms
100
46.4ms
E1H
+30dB
E1H
+30dB
E1H
+30dB
E1H
+30dB
00
1
00
00
1
1 step
ON
1 step
4 times
Enable
Limiter ATT step
00
1 step
Fast Limiter Operation
1
ON
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 36. Example of the ALC Setting (Recording)
MS1252-E-00
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[AK4953A]
Register Name
Comment
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits must be the same value
or larger value than ZTM1-0 bits
Maximum gain at recovery operation
WTM2-0
OREF5-0
OVL7-0,
OVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC2
5.
Data
01
0
01
Gain of VOL
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
Data
01
0
11
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
001
32ms
100
46.4ms
28H
+6dB
28H
+6dB
91H
0dB
91H
0dB
00
1
00
00
1
1 step
ON
1 step
4 times
Enable
Limiter ATT step
00
1 step
Fast Limiter Operation
1
ON
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 37. Example of the ALC Setting (Playback)
Example of registers set-up sequence of ALC Operation
The following registers must not be changed during ALC operation. These bits must be changed after ALC operation is
finished by ALC1 bit=ALC2 bit = “0”. All ALC outputs are “0” until manual mode starts when ALC1 bit =ALC2 bit =
“0”.
LMTH1-0, LMAT1-0, ZTM1-0, WTM2-0, RGAIN 1-0, IREF7-0, ZELMN, RFST1-0, LFST bits
Example:
Limiter = Zero crossing Enable
Recovery Cycle = [email protected]
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
Manual Mode
ALC1 bit = “1”
WR (ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=0AH, Data=24H
WR (IREF7-0)
(2) Addr=0CH, Data=E1H
WR (IVL/R7-0)
* The value of IVOL should be
the same or smaller than REF’s
(3) Addr=0FH&10H, Data=E1H
WR (RGAIN1-0)
(4) Addr=0DH, Data=28H
WR (LFST, ZELMN, LMAT1-0, LMTH1-0; ALC1= “1”)
(5) Addr=0BH, Data=A1H
ALC Operation
[Note] WR: Write
Figure 35. Registers Set-up Sequence at ALC1 Operation (recording path)
MS1252-E-00
2010/10
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[AK4953A]
■ Input Digital Volume (Manual Mode)
The input digital volume becomes manual mode at ALC1 bit = “0” when ADCPF bit =“1”. This mode is used in the case
shown below.
1.
2.
3.
After exiting reset state, when setting up the registers for ALC operation (ZTM1-0, LMTH and etc.)
When the registers for ALC operation (Limiter period, Recovery period and etc.) are changed.
For example; when the sampling frequency is changed.
When IVOL is used as a manual volume control.
IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 38). The IVOL value is changed at zero crossing or
timeout. The zero crossing timeout period is set by ZTM1-0 bits. Lch and Rch volumes are set individually by IVL7-0 and
IVR7-0 bits when IVOLC bit = “0”. IVL7-0 bits control both Lch and Rch volumes together when IVOLC bit = “1”.
When changing the volume, zero cross detection is executed on both Lch and Rch independently.
IVL7-0 bits
IVR7-0 bits
F1H
F0H
EFH
:
E2H
E1H
E0H
:
03H
02H
01H
00H
GAIN (dB)
Step
+36.0
+35.625
+35.25
:
+30.375
0.375dB
+30.0
+29.625
:
−53.25
−53.625
−54
MUTE
Table 38. Input Digital Volume Setting
(default)
If IVL7-0 or IVR7-0 bits are written during PMPFIL bit = “0”, IVOL operation starts with the written values after
PMPFIL bit is changed to “1”.
When writing to IVOL7-0 bits continually, take an interval of zero crossing timeout period or more. If not, the zero
crossing counters are reset at each time and the volume will not be changed. However, when writing the same register
values as the previous time, the zero crossing counters will not be reset, so that it could be written in an interval less than
zero crossing timeout.
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[AK4953A]
■ De-emphasis Filter
The AK4953A includes a digital de-emphasis filter (tc = 50/15μs) which corresponds three kinds frequency (32kHz,
44.1kHz, 48kHz) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 39).
DEM1
0
0
1
1
DEM0
Mode
0
44.1kHz
1
OFF
(default)
0
48kHz
1
32kHz
Table 39. De-emphasis Control
■ Output Digital Volume (Manual Mode)
The ALC block becomes output digital volume (manual mode) by setting ALC2 bit to “0” when PMPFIL = PMDAC bits
= “1” and ADCPF bit is “0”. The output digital volume gain is set by the OVL7-0 bit and the OVR7-0 bit (Table 40).
When the OVOLC bit = “1”, the OVL7-0 bits control both L and R channel volume levels. When the OVOLC bit = “0”,
the OVL7-0 bits control L channel volume level and the OVR7-0 bits control R channel volume level. When changing the
volumes, zero cross detection is executed on both L and R channels independently. The OVOL value is changed at zero
crossing or timeout. The zero crossing timeout period is set by ZTM1-0 bits.
OVL7-0 bits
GAIN (0dB)
Step
OVR7-0 bits
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
0.375dB
92H
+0.375
91H
0.0
90H
-0.375
:
:
2H
-53.625
1H
-54.0
0H
MUTE
Table 40. Output Digital Volume Setting
(default)
When writing to the OVL7-0 bits and OVR7-0 bit continuously, the control register should be written in an interval more
than zero crossing timeout. If not, the zero crossing counters are reset at each time and the volume will not be changed.
However, when writing the same register values as the previous time, the zero crossing counter will not be reset, so that it
could be written in an interval less than zero crossing timeout.
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[AK4953A]
■ Output Digital Volume 2
The AK4953A has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and
DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or
MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit
= “0”, the DVL7-0 bits control Lch level and DVR7-0 bits control Rch level. This volume has soft transition function.
Therefore no switching noise occurs during the transition. The DVTM1-0 bits set the transition time between set values
of DVL/R7-0 bits (from 00H to FFH) as either 256/fs, 1024/fs or 2048/fs (Table 42). When DVTM1-0 bits = “01”, a soft
transition between the set values occurs (1024 levels). It takes 1024/fs ([email protected]=44.1kHz) from 00H (+12dB) to FFH
(MUTE).
DVL7-0 bits
Gain
Step
DVR7-0 bits
00H
+12.0dB
01H
+11.5dB
02H
+11.0dB
:
:
0.5dB
18H
0dB
(default)
:
FDH
-114.5dB
FEH
-115.0dB
FFH
Mute (- ∞)
Table 41. Output Digital Volume2 Setting
Transition Time between DVL/R7-0 bits = 00H and FFH
DVTM1 DVTM0
bit
bit
Setting
fs=8kHz
fs=44.1kHz
fs=96kHz
0
0
256/fs
32ms
5.8ms
2.7ms
0
1
1024/fs
128ms
23ms
11ms
(default)
1
0
2048/fs
256ms
46ms
21ms
1
1
N/A
Table 42. Transition Time Setting of Output Digital Volume2 (N/A: Not available)
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[AK4953A]
■ Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit is set “1”, the output signal is attenuated by
-∞ (“0”) during the cycle set by DVTM1-0 bits. When the SMUTE bit is returned to “0”, the mute is cancelled and the
output attenuation gradually changes to the value set by DVL/R7-0 bits from -∞ during the cycle set by DVTM1-0 bits. If
the soft mute is cancelled within the cycle set by DVTM1-0 bits after starting the operation, the attenuation is
discontinued and returned to the level set by DVL/R7-0 bits. The soft mute is effective for changing the signal source
without stopping the signal transaction (Figure 36)
S MU TE bit
D VL /R 7 -0 bits
D VT M 1 -0
b its
(1)
D V T M1 -0
bits
(1 )
A tte nu a tion
(3 )
-∞
GD
(2 )
GD
A na lo g O u tpu t
Figure 36. Soft Mute Function
(1) The input signal is attenuated by −∞ (“0”) during the cycle set by DVTM1-0 bits.
(2) Analog output corresponding to digital input has group delay (GD).
(3) If soft mute is cancelled within the cycle set by DVTM1-0 bits after starting the operation, the attenuation is
discounted and returned to the value set by DVL/R7-0 bits within the same cycle.
MS1252-E-00
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[AK4953A]
■ BEEP Signal Generating Circuit
The AK4953A integrates a BEPP signal generating circuit. When PMSPK bit = “1”, the speaker amplifier outputs BEEP
signal by setting PMBP bit = “1”, and the Headphone amplifier outputs BEEP signal by setting PMBP bit = “1” when
PMHPL bit or PMHPR bit = “1”.
When PMDAC bit = “1” and PMHPL bit or PMHPR bit = “1”, switching noise of connection between the BEEP
generating circuit and headphone amplifier can be suppressed by soft transition. The transition time of ON/OFF switching
is set by PTS1-0 bits. Soft transition Enable/Disable is controlled by MOFF bit. When this bit is “1”, soft transition is
disabled and the headphone is switched ON/OFF immediately.
PTS1
bit
0
0
1
1
PTS0
bit
0
1
0
1
ON/OFF Time
7.35kHz ≤ fs ≤ 24kHz
24kHz < fs ≤ 48kHz
48kHz < fs ≤ 96kHz
64/fs
5.3 ~ 8.7ms
128/fs
2.7 ~ 5.3ms
256/fs
2.7 ~ 5.3ms
128/fs 10.7 ~ 17.4ms
256/fs
5.3 ~ 10.7ms
512/fs
5.3 ~ 10.7ms
256/fs 21.3 ~ 34.8ms
512/fs
10.7 ~ 21.3ms 1024/fs 10.7 ~ 21.3ms
512/fs 42.7 ~ 69.7ms 1024/fs 21.3 ~ 42.7ms 2048/fs 21.3 ~ 42.7ms
Table 43. BEEP (Headphone-Amp) ON/OFF Transition Time
(default)
After outputting the signal during the time set by BPON7-0 bits, the AK4953A stops the output signal during the time set
by BPOFF7-0 bits (Figure 37). The repeat count is set by BPTM6-0 bit, and the output level is set by BPLVL4-0 bits.
When BPCNT bit is “0”, if BPOUT bit is written “1”, the AK4953A outputs the beep for the times of repeat count. When
the output is finished, BPOUT bit is set to “0” automatically. When BPCNT bit is set to “1”, it outputs beep signals
incessantly regardless of repeat count, on-time nor off-time. The output frequency is set by BPFR1-0 bits.
< Setting parameter >
1) Output Frequency (Table 44, Table 45)
2) ON Time (Table 46, Table 47)
3) OFF Time (Table 48, Table 49)
4) Repeat Count (Table 50)
5) Output Level (Table 51)
* BPFR1-0, BPON7-0, BPOFF7-0, BPTM6-0 and BPLVL4-0 bits should be set when BPOUT
=BPCNT = “0”.
* BPCNT bit is given priority in BPOUT bit. When BPOUT bit is set to “1”, if BPCNT bit is set to
“0”, BPOUT bit is set to “0” forcibly.
* When stopping the BEEP outputs by changing BPCNT bit to “0” from “1”, writing to BPOUT and
BPCNT bits are inhibited for 10ms. When BEEP is output by setting BPCNT bit = “1”, writing to
BPOUT and BPCNT bits are inhibited for 10ms after BPOUT bit is changed to “0” or BEEP
signal outputs are finished (ON/OFF time and the number of times set by repeated time).
BEEP Output
ON Time
OFF Time
Repeat Count
Figure 37. BEEP Signal Output
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[AK4953A]
Output frequency of BEEP Generator [Hz]
fs = 44.1kHz system
BPFR1-0 bits
fs = 48kHz system
(Note 48)
(Note 47)
00
4000
4009
(default)
01
2000
2005
10
1297
1297
11
800
802
Note 47. Sampling frequency is 8kHz, 16kHz, 32kHz, 48kHz, 64kHz or 96kHz.
Note 48. Sampling frequency is 11.025kHz, 22.05kHz, 44.1kHz or 88.2kHz.
Table 44. Beep Signal Frequency (PLL Master/Slave Mode; MCKI referenced)
Output frequency of BEEP Generator [Hz]
FS1-0 bits
FS1-0 bits
FS1-0 bits
FS1-0 bits
= “00”
= “01”
= “10”
= “11”
00
fs/2.75
fs/5.5
fs/11
fs/22
(default)
01
fs/5.5
fs/11
fs/22
fs/44
10
fs/8.5
fs/17
fs/34
fs/68
11
fs/13.75
fs/27.5
fs/55
fs/110
Table 45. Beep Signal Frequency (BICK referenced PLL Slave Mode, EXT Master/Slave Mode)
BPFR1-0 bits
ON Time of BEEP Generator [msec]
Step[msec]
fs=48kHz system fs=44.1kHz system fs=48kHz system fs=44.1kHz system
(Note 48)
(Note 47)
(Note 48)
(Note 47)
0H
8.0
7.98
8.0
7.98
1H
16.0
15.96
2H
24.0
23.95
3H
32.0
31.93
:
:
:
FDH
2032
2027.3
FEH
2040
2035.3
FFH
2048
2043.4
Note 47. Sampling frequency is 8kHz, 16kHz, 32kHz, 48kHz, 64kHz or 96kHz
Note 48. Sampling frequency is 11.025kHz, 22.05kHz, 44.1kHz or 88.2kHz
Table 46. Beep Output ON-time (PLL Master/Slave Mode; MCKI referenced)
BPON7-0 bits
(default)
ON Time of BEEP Generator [msec]
Step[msec]
fs=48kHz system fs=44.1kHz system fs=48kHz system fs=44.1kHz system
(Note 48)
(Note 47)
(Note 48)
(Note 47)
0H
7.33
7.98
7.33
7.98
(default)
1H
14.67
15.96
2H
22.00
23.95
3H
29.33
31.93
:
:
:
FDH
1862.6
2027.3
FEH
1970.0
2035.3
FFH
1877.3
2043.4
Note 47. Sampling frequency is 8kHz, 16kHz, 32kHz, 48kHz, 64kHz or 96kHz
Note 48. Sampling frequency is 11.025kHz, 22.05kHz, 44.1kHz or 88.2kHz
Table 47. Beep Output ON-time (BICK referenced PLL Slave Mode, EXT Master/Slave Mode)
BPON7-0 bits
MS1252-E-00
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[AK4953A]
OFF Time of BEEP Generator [msec]
Step[msec]
fs=48kHz system fs=44.1kHz system fs=48kHz system fs =44.1kHz system
(Note 48)
(Note 47)
(Note 48)
(Note 47)
0H
8.0
7.98
8.0
7.98
1H
16.0
15.96
2H
24.0
23.95
3H
32.0
31.93
:
:
:
FDH
2032
2027.3
FEH
2040
2035.3
FFH
2048
2043.4
Note 47. Sampling frequency is 8kHz, 16kHz, 32kHz, 48kHz, 64kHz or 96kHz
Note 48. Sampling frequency is 11.025kHz, 22.05kHz, 44.1kHz or 88.2kHz
Table 48. Beep Output OFF-time (PLL Master/Slave Mode; MCKI referenced)
BPOFF7-0 bits
(default)
OFF Time of BEEP Generator [msec]
Step[msec]
BPOFF7-0 bits fs=48kHz system fs=44.1kHz system fs=48kHz system fs=44.1kHz system
(Note 48)
(Note 47)
(Note 48)
(Note 47)
0H
7.33
7.98
7.33
7.98
(default)
1H
14.67
15.96
2H
22.00
23.95
3H
29.33
31.93
:
:
:
FDH
1862.6
2027.3
FEH
1970.0
2035.3
FFH
1877.3
2043.4
Note 47. Sampling frequency is 8kHz, 16kHz, 32kHz, 48kHz, 64kHz or 96kHz
Note 48. Sampling frequency is 11.025kHz, 22.05kHz, 44.1kHz or 88.2kHz
Table 49. Beep Output OFF-time (BICK referenced PLL Slave Mode, EXT Master/Slave Mode)
BPTM6-0 bits
Repeat Count
0H
1
1H
2
2H
3
:
:
7DH
126
7EH
127
7FH
128
Table 50. Beep Output Repeat Count
(default)
BPLVL4-0 bits
Beep Output Level
STEP
0H
0dB
(default)
1H
−3dB
2H
−6dB
3dB
:
:
12H
−54dB
13H
−57dB
14H
−60dB
Note 49. Beep output amplitude in 0dB setting is 1.5Vpp from the headphone amplifier, and 2.8Vpp @8Ω (SPKG1-0
bits = “00”) from the speaker amplifier.
Table 51. Beep Output Level
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[AK4953A]
■ Charge Pump Circuit
The internal charge pump circuit generates negative voltage (PVEE) from AVDD voltage. The PVEE voltage is used for
the headphone amplifier and the speaker amplifier in low voltage mode (LSV bit = “1”). The charge pump circuit starts
operation when PMHPL or PMHPR bit = “1”, or when LSV bit = PMSPK bit = “1”. PMVCM bit must be set “1” to power
up the charge pump circuit.
The power up time of the charge pump circuit is 11ms (max). The headphone amplifier and speaker amplifier will be
powered up after the charge pump circuit is powered up (when PMHPL or PMHPR bit = “1”, or LSV bit = PMSPK bit =
“1”).
The operating frequency of the charge pump circuit is dependent on the sampling frequency. The operation mode of the
headphone amplifier can be changed by the CPCK bit. (Table 52)
CPCK bit
Mode
Power Consumption
(DAC → Headphone out)
S/(N+D)
(0dBFS)
0
Low power mode
10.2mW
72dB
1
High performance mode
12.1mW
80dB
Table 52. Operation Mode of the Charge Pump (PMHPL or PMHPR bit = “1”)
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[AK4953A]
■ Headphone Amplifier (HPL/HPR pins)
The positive voltage of the headphone amplifier uses the power supply to the DVDD pin, therefore 150mA of the
maximum power supply capacity is needed. The internal charge pump circuit generates negative voltage (PVEE) from
AVDD voltage. The headphone amplifier output is single-ended and centered around on VSS (0V). Therefore, the
capacitor for AC-coupling can be removed. The minimum load resistance is 16Ω. When HPM bit = “1”, the DAC output
signal is output to HPL and HPR pins as (L+R)/2 mono signal.
<External Circuit of Headphone-Amp>
An oscillation prevention circuit (0.22μF±20% capacitor and 100Ω±20% resistor) should be put because it has the
possibility that Headphone-Amp oscillates in type of headphone.
HP-AMP
Headphone
DAC
0.22μ
AK4953A
16Ω
100Ω
Figure 38. External Circuit of Headphone
When HPZ bit = “0” and PMHPL, PMHPR bits = “1”, headphone outputs are in normal operation.
When PMHPL and PMHPR bits = “0”, the headphone-amps are powered-down completely. At that time, the HPL and
HPR pins go to VSS voltage via the internal pulled-down resistor. The pulled-down resistor is 10Ω (typ). The HPL and
HPR pins become Hi-Z state by setting HPZ bit to “1” when PMHPL and PMHPR bit = “0”.
The power-up time of the headphone-amps is 35ms (max.), and power-down is executed immediately.
PMVCM
bit
x
x
1
1
PMHPL/R
HPZ bit
Mode
HPL/R pins
bits
0
0
Power-down & Mute
Pull-down by 10Ω (typ)
0
1
Power-down
Hi-Z
1
0
Normal Operation
Normal Operation
1
1
N/A
N/A
Table 53. Headphone Output Status (x: Don’t’ care, N/A: Not available)
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(default)
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[AK4953A]
■ Speaker Output
The DAC output signal is input to the speaker amplifier as [(L+R)/2]. The speaker amplifier is mono and BTL output. The
gain is set by SPKG1-0 bits. Output level depends on SVDD voltage and SPKG1-0 bits. The AK4953A has a low voltage
mode (LSV bit = “1”) which the speaker amplifier can be operated by SVDD= 0.9V ~ 2.0V. In low voltage mode, the
negative power which is generated by the charge pump circuit using the voltage from the AVDD pin is used. This
negative power is not used in normal voltage mode (LSV bit = “0”, SVDD=1.8V~5.5V). In low voltage mode, SPKG1-0
bits must be set to “00” and the DAC output level should be set to lower level by setting digital volume so that the speaker
amplifier outputs is suppressed to lower level and output signal is not clipped.
SPKG1-0 bits
00
01
10
11
Gain
ALC2 bit = “0”
ALC2 bit = “1”
5.3 dB
7.3 dB
7.3 dB
9.3 dB
9.3 dB
11.3 dB
11.3 dB
13.3 dB
Table 54. SPK-Amp Gain
(default)
SPK-Amp Output
(DAC Input=0dBFS, SVDD=3.3V)
SPKG1-0 bits
ALC2 bit = “0”
ALC2 bit = “1”
(LMTH1-0 bits = “00”)
00
3.37Vpp
3.17Vpp
01
4.23Vpp (Note 50)
4.00Vpp
10
5.33Vpp (Note 50)
5.04Vpp (Note 50)
11
6.71Vpp (Note 50)
6.33Vpp (Note 50)
Note 50. The output level is calculated by assuming that output signal is not clipped. In the actual case, the output signal
may be clipped when DAC outputs 0dBFS signal. The DAC output level should be set to lower level by setting
digital volume so that the speaker amplifier output level is 4.0Vpp or less and output signal is not clipped.
Table 55. SPK-Amp Output Level
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[AK4953A]
< Speaker-Amp Control Sequence >
The speaker amplifier is powered-up/down by PMSPK bit. When PMSPK bit is “0”, both SPP and SPN pins are in Hi-Z
state. When PMSPK bit is “1” and SPPSN bit is “0”, the speaker amplifier enters power-save mode. In this mode, the SPP
pin is placed in Hi-Z state and the SPN pin outputs SVDD/2 voltage.
When the PMSPK bit is “1” after the PDN pin is changed from “L” to “H”, the SPP and SPN pins rise up from
power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. Because
the SPP and SPN pins rise up at power-save-mode, this mode can reduce a pop noise. When the AK4953A is
powered-down, pop noise can also be reduced by first entering power-save-mode.
PMSPK
0
SPPSN
x
0
1
1
Mode
SPP
SPN
Power-down
Hi-Z
Hi-Z
Power-save
Hi-Z
SVDD/2
Normal Operation Normal Operation Normal Operation
Table 56 Speaker-Amp Mode Setting (x: Don’t care)
(default)
PMSPK bit
SPPSN bit
>1ms (Note 51)
SPP pin
SPN pin
Hi-Z
Hi-Z
Hi-Z
SVDD/2
SVDD/2
Hi-Z
Note 51. This time needs 15ms or more in low voltage mode (LSV bit= “1”).
Figure 39. Power-up/Power-down Timing for Speaker-Amp
■ Thermal Shutdown Function
When the internal device temperature rises up irregularly (E.g. Output pins of speaker amplifier are shortened.), the
charge pump, headphone amplifier and speaker amplifier are automatically powered down and then THDET bit becomes
“1”.
When the internal temperature goes down and the thermal shutdown is released, the charge pump, speaker and headphone
amplifiers are powered up automatically and THDET bit returns to “0”.
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[AK4953A]
■ Serial Control Interface
(1) 3-wire Serial Control Mode
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on this
interface consists of Read/Write, Register address (MSB first, 7bits) and Control or Output data (MSB first, 8bits). Each
bit is clocked in on the rising edge (“↑”) of CCLK. Data writings become available on the rising edge of CSN. When
reading the data, the CDTIO pin changes to output mode at the falling edge of 8th CCLK and outputs D7-D0. However
this reading function is available only when READ bit = “1”. When READ bit = “0”, the CDTIO pin stays as Hi-Z even
after the falling edge of 8th CCLK. The output finishes on the rising edge of CSN. The CDTIO is placed in a Hi-Z state
except when outputting data at read operation mode. Clock speed of CCLK is 5MHz (max). The value of internal registers
are initialized by the PDN pin = “L”.
Note 52. Data reading is only available on the following addresses; 00H~19H, 1CH~25H, 30H and 32H~4FH. When
reading the address 1AH, 1BH, 26H~2FH, 31H and 50H~7FH the register values are invalid.
CSN
0
CCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
“H” or “L”
CDTIO “H” or “L”
“H” or “L”
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
R/W:
A6-A0:
D7-D0:
“H” or “L”
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data (Input) at Write Command
Output data (Output) at Read Command
Figure 40. Serial Control I/F Timing
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[AK4953A]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4953A supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins must be
connected to (TVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 41 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 47). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit).
This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits
(Figure 42). If the slave address matches that of the AK4953A, the AK4953A generates an acknowledge and the
operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH)
during the acknowledge clock pulse (Figure 48). A R/W bit value of “1” indicates that the read operation is to be
executed, and “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4953A. The format is MSB first, and those most
significant 1bit is fixed to zero (Figure 43). The data after the second byte contains control data. The format is MSB first,
8bits (Figure 44). The AK4953A generates an acknowledge after each byte is received. Data transfer is always terminated
by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a
STOP condition (Figure 47).
The AK4953A can perform more than one byte write operation per sequence. After receipt of the third byte the AK4953A
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 4FH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line
can only be changed when the clock signal on the SCL line is LOW (Figure 49) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 41. Data Transfer Sequence at I2C Bus Mode
0
0
1
0
0
1
CAD0
R/W
A2
A1
A0
D2
D1
D0
Figure 42. The First Byte
0
A6
A5
A4
A3
Figure 43. The Second Byte
D7
D6
D5
D4
D3
Figure 44. The Third Byte
MS1252-E-00
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[AK4953A]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4953A. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal address counter is incremented by one, and the next data is automatically
taken into the next address. If the address exceeds 4FH prior to generating stop condition, the address counter will “roll
over” to 00H and the data of 00H will be read out.
Note 52. Data reading is only available on the following addresses; 00H~19H, 1CH~25H, 30H and 32H~4FH. When
reading the address 1AH, 1BH, 26H~2FH, 31H and 50H~7FH the register values are invalid.
The AK4953A supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4953A has an internal address counter that maintains the address of the last accessed word incremented by one.
Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4953A generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the
AK4953A ceases the transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
A
C
K
P
MN
AA
SC
T
EK
R
MA
AC
SK
T
E
R
Figure 45. Current Address Read
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit “1”. The AK4953A then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but generates a stop condition instead, the AK4953A ceases the transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 46. Random Address Read
MS1252-E-00
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[AK4953A]
SDA
SCL
S
P
start condition
stop condition
Figure 47. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 48. Acknowledge (I2C Bus)
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 49. Bit Transfer (I2C Bus)
MS1252-E-00
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[AK4953A]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Signal Select 3
Mode Control 1
Mode Control 2
Mode Control 3
Digital MIC
Timer Select
ALC Timer Select
ALC Mode Control 1
ALC Mode Control 2
ALC Mode Control 3
ALC Volume
Lch Input Volume Control
Rch Input Volume Control
Lch Output Volume Control
Rch Output Volume Control
Lch Digital Volume Control
Rch Digital Volume Control
BEEP Frequency
BEEP ON Time
BEEP OFF Time
BEEP Repeat Count
BEEP Volume Control
Reserved
Reserved
Digital Filter Select 1
Digital Filter Mode
HPF2 Co-efficient 0
HPF2 Co-efficient 1
HPF2 Co-efficient 2
HPF2 Co-efficient 3
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D7
D6
PMPFIL PMVCM
0
0
SPPSN
0
SPKG1
SPKG0
0
0
PLL3
PLL2
PS1
PS0
READ
THDET
0
0
ADRST1 ADRST 0
0
ZTM1
LFST
ALC2
IREF7
IREF6
RGAIN1 RGAIN0
VOL7
VOL6
IVL7
IVL6
IVR7
IVR6
OVL7
OVL6
OVR7
OVR6
DVL7
DVL6
DVR7
DVR6
BPCNT
0
BPON7
BPON6
BPOFF7 BPOFF6
0
BPTM6
BPOUT
0
0
0
0
0
0
0
0
0
F1A7
F1A6
0
0
F1B7
F1B6
0
0
F2A7
F2A6
0
0
F2B7
F2B6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D5
PMBP
PMHPL
DACS
0
PTS1
PLL1
CPCK
SMUTE
PMDMR
0
ZTM0
ALC1
IREF5
OREF5
VOL5
IVL5
IVR5
OVL5
OVR5
DVL5
DVR5
0
BPON5
BPOFF5
BPTM5
0
0
0
LPF
0
F1A5
F1A13
F1B5
F1B13
F2A5
F2A13
F2B5
F2B13
0
0
0
0
0
0
0
0
0
0
MS1252-E-00
D4
PMSPK
PMHPR
MPSEL
0
PTS0
PLL0
DS
DVOLC
PMDML
0
WTM2
ZELMN
IREF4
OREF4
VOL4
IVL4
IVR4
OVL4
OVR4
DVL4
DVR4
0
BPON4
BPOFF4
BPTM4
BPLVL4
0
0
HPF
0
F1A4
F1A12
F1B4
F1B12
F2A4
F2A12
F2B4
F2B12
0
0
0
0
0
0
0
0
0
0
D3
LSV
M/S
PMMP
INR1
MOFF
BCKO
FS3
OVOLC
DCLKE
0
WTM1
LMAT1
IREF3
OREF3
VOL3
IVL3
IVR3
OVL3
OVR3
DVL3
DVR3
0
BPON3
BPOFF3
BPTM3
BPLVL3
0
0
0
0
F1A3
F1A11
F1B3
F1B11
F2A3
F2A11
F2B3
F2B11
0
0
0
0
0
0
0
0
0
0
D2
PMDAC
0
MGAIN2
INL1
HPM
HPZ
FS2
IVOLC
0
0
WTM0
LMAT0
IREF2
OREF2
VOL2
IVL2
IVR2
OVL2
OVR2
DVL2
DVR2
0
BPON2
BPOFF2
BPTM2
BPLVL2
0
0
HPFC1
PFDAC
F1A2
F1A10
F1B2
F1B10
F2A2
F2A10
F2B2
F2B10
0
0
0
0
0
0
0
0
0
0
D1
PMADR
MCKO
MGAIN1
INR0
0
DIF1
FS1
DEM1
DCLKP
DVTM1
RFST1
LMTH1
IREF1
OREF1
VOL1
IVL1
IVR1
OVL1
OVR1
DVL1
DVR1
BPFR1
BPON1
BPOFF1
BPTM1
BPLVL1
0
0
HPFC0
ADCPF
F1A1
F1A9
F1B1
F1B9
F2A1
F2A9
F2B1
F2B9
0
0
0
0
0
0
0
0
0
0
D0
PMADL
PMPLL
MGAIN0
INL0
0
DIF0
FS0
DEM0
DMIC
DVTM0
RFST0
LMTH0
IREF0
OREF0
VOL0
IVL0
IVR0
OVL0
OVR0
DVL0
DVR0
BPFR0
BPON0
BPOFF0
BPTM0
BPLVL0
0
0
HPFAD
PFSDO
F1A0
F1A8
F1B0
F1B8
F2A0
F2A8
F2B0
F2B8
0
0
0
0
0
0
0
0
0
0
2010/10
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[AK4953A]
Addr
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
Digital Filter Select 2
Reserved
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
D7
0
0
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
D6
0
0
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
D5
0
0
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
D4
EQ5
0
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
D3
EQ4
0
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
D2
EQ3
0
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
D1
EQ2
0
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
D0
EQ1
0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
Note 53. PDN pin = “L” resets the registers to their default values.
Note 54. The bits defined as 0 must contain a “0” value.
Note 55. Reading address 1AH, 1BH, 26H~2FH, 31H and 50H~7FH are not possible.
Note 56. Address 0EH is a read only register. Writing access to 0EH is ignored and does not effect the operation.
MS1252-E-00
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[AK4953A]
■ Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
PMPFIL
R/W
0
D6
PMVCM
R/W
0
D5
PMBP
R/W
0
D4
PMSPK
R/W
0
D3
LSV
R/W
0
D2
PMDAC
R/W
0
D1
PMADR
R/W
0
D0
PMADL
R/W
0
PMADL: MIC-Amp Lch and ADC Lch Power Management
0: Power-down (default)
1: Power-up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz, ADRST1-0 bits = “00”) starts. After initializing, digital data of the ADC is output.
PMADR: MIC-Amp Rch, ADC Rch Power Management
0: Power down (default)
1: Power up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz, ADRST1-0 bits = “00”) starts. After initializing, digital data of the ADC is output.
PMDAC: DAC Power Management
0: Power-down (default)
1: Power-up
LSV: Low Voltage Operation Mode of the Speaker Amplifier
0: Normal mode: SVDD=1.8V ~ 5.5V (default)
1: Low voltage mode: SVDD=0.9V ~ 2.0V
PMSPK: Speaker-Amp Power Management
0: Power-down (default)
1: Power-up
PMBP: BEEP Generating Circuit Power Management
0: Power-down (default)
1: Power-up
PMVCM: VCOM, Regulator (2.5V) Power Management
0: Power-down (default)
1: Power-up
PMPFIL: Programmable Filter Block (HPF2/LPF/5 Band EQ/ALC) Power Management
0: Power down (default)
1: Power up
All blocks can be powered-down by writing “0” to the address “00H”, PMPLL, PMMP, PMHPL, PMHPR,
PMDML, PMDMR and MCKO bits. In this case, register values are maintained.
PMVCM bit must be “1” when one of bocks is powered-up. PMVCM bit can only be “0” when the address “00H”
and all power management bits (PMPLL, PMMP, PMHPL, PMHPR, PMDML, PMDMR and MCKO) are “0”.
MS1252-E-00
2010/10
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[AK4953A]
Addr
01H
Register Name
Power Management 2
R/W
Default
D7
0
R
0
D6
0
R
0
D5
PMHPL
R/W
0
D4
PMHPR
R/W
0
D3
M/S
R/W
0
D2
0
R
0
D1
MCKO
R/W
0
D0
PMPLL
R/W
0
PMPLL: PLL Power Management
0: EXT Mode and Power down (default)
1: PLL Mode and Power up
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
M/S: Master / Slave Mode Select
0: Slave Mode (default)
1: Master Mode
PMHPR: Rch Headphone Amplifier and Charge Pump Power Management
0: Power down (default)
1: Power up
PMHPL: Lch Headphone Amplifier and Charge Pump Power Management
0: Power down (default)
1: Power up
MS1252-E-00
2010/10
- 65 -
[AK4953A]
Addr
02H
Register Name
Signal Select 1
R/W
Default
D7
SPPSN
R/W
0
D6
0
R
0
D5
DACS
R/W
0
D4
MPSEL
R/W
0
D3
PMMP
R/W
0
D2
MGAIN2
R/W
0
D1
D0
MGAIN1 MGAIN0
R/W
R/W
1
1
MGAIN3-0: MIC-Amp Gain Control (Table 22)
PMMP: MPWR pin Power Management
0: Power-down: Hi-Z (default)
1: Power-up
MPSEL: MPWR Output Select
0: MPWR1 pin (default)
1: MPWR2 pin
DACS: Signal Switch Control from DAC to Speaker-Amp
0: OFF (default)
1: ON
When DACS bit is “1”, DAC output signal is input to Speaker-Amp.
SPPSN: Speaker-Amp Power-Save Mode
0: Power-Save Mode (default)
1: Normal Operation
When SPPSN bit is “0”, Speaker-Amp is in power-save mode. In this mode, the SPP pin goes to Hi-Z and
outputs SVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to “L”,
Speaker-Amp is in power-down mode since PMSPK bit is “0”.
Addr
03H
Register Name
Signal Select 2
R/W
Default
D7
SPKG1
R/W
0
D6
SPKG0
R/W
0
D5
0
R
0
D4
0
R
0
D3
INR1
R/W
0
D2
INL1
R/W
0
D1
INR0
R/W
0
D0
INL0
R/W
0
INL1-0: ADC Lch Input Source Select (Table 21)
Default: 00 (LIN1 pin)
INR1-0: ADC Rch Input Source Select (Table 21)
Default: 00 (RIN1 pin)
SPKG1-0: Speaker-Amp Output Gain Select (Table 54)
MS1252-E-00
2010/10
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[AK4953A]
Addr
04H
Register Name
Signal Select 3
R/W
Default
D7
0
R
0
D6
0
R
0
D5
PTS1
R/W
0
D4
PTS0
R/W
1
D3
MOFF
R/W
0
D2
HPM
R/W
0
D1
0
R
0
D0
0
R
0
HPM: Headphone Output Select
0: Stereo (default)
1: Mono
When HPM bit = “1”, DAC output signals are output from the headphone amplifier as (L+R)/2.
MOFF: Soft Transition Control of “BEEP → Headphone” Connection ON/OFF
0: Enable (default)
1: Disable
PTS1-0: Soft Transition Time of “BEEP → Headphone” Connection ON/OFF
Default: “01” (Table 43)
Addr
05H
Register Name
Mode Control 1
R/W
Default
D7
PLL3
D6
PLL2
D5
PLL1
D4
PLL0
D3
BCKO
D2
HPZ
D1
DIF1
D0
DIF0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
0
R/W
1
R/W
0
DIF1-0: Audio Interface Format (Table 18)
Default: “10” (MSB justified)
HPZ: Pull-down Setting of HP-Amp
0: Pull-down by a 10Ω(typ) resistor. (Default)
1: Hi-Z
When using HPZ bit, set HPZ bit to “1” before starting a speaker amplifier operation, and then write registers
according to the sequence in “■ Speaker-Amp Output”. Set HPZ bit to “0” before starting a headphone
amplifier operation, and then write registers according to the sequence in “■ Headphone-Amp Output”.
BCKO: Master Mode BICK Output Frequency Setting (Table 11)
PLL3-0: PLL Reference Clock Select (Table 5)
Default: “0000”
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Addr
06H
Register Name
Mode Control 2
R/W
Default
D7
PS1
R/W
0
D6
PS0
R/W
0
D5
CPCK
R/W
0
D4
DS
R/W
0
D3
FS3
R/W
0
D2
FS2
R/W
0
D1
FS1
R/W
0
D0
FS0
R/W
0
FS3-0: Sampling frequency (Table 6, Table 7) and MCKI frequency (Table 12, Table 14) Setting
These bits control sampling frequency in PLL mode and control MCKI input frequency in EXT mode.
DS: Double Speed Mode
0: Normal Speed: fs ≤ 48kHz (default)
1: Double Speed: 48kHz < fs ≤ 96kHz
PS1-0: MCKO Frequency Setting (Table 10)
Default: “00” (256fs)
CPCK: Operation Mode of the Charge Pump (Table 52)
0: Low Power Mode (default)
1: High Performance Mode
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Addr
07H
Register Name
Mode Control 3
R/W
Default
D7
READ
R/W
0
D6
THDET
R
0
D5
SMUTE
R/W
0
D4
DVOLC
R/W
1
D3
OVOLC
R/W
1
D2
IVOLC
R/W
1
D1
DEM1
R/W
0
D0
DEM0
R/W
1
DEM1-0: De-emphasis Control (Table 39)
Default: “01” (OFF)
IVOLC: Input Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume levels, while register values of IVL7-0
bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits
control Rch level, respectively.
OVOLC: Output Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When OVOLC bit = “1”, OVL7-0 bits control both Lch and Rch volume levels, while register values of
OVL7-0 bits are not written to OVR7-0 bits. When OVOLC bit = “0”, OVL7-0 bits control Lch level and
OVR7-0 bits control Rch level, respectively.
DVOLC: Output Digital Volume2 Control Mode Select
0: Independent
1: Dependent (default)
When DVOLC bit = “1”, DVL7-0 bits control both Lch and Rch volume levels, while register values of
DVL7-0 bits are not written to DVR7-0 bits. When DVOLC bit = “0”, DVL7-0 bits control Lch level and
DVR7-0 bits control Rch level, respectively.
SMUTE: Soft Mute Control
0: Normal Operation (default)
1: DAC outputs soft-muted
THDET: Thermal Shutdown Detection
0: Thermal Shutdown Off (default)
1: Thermal Shutdown On
READ: Read Function Enable
0: Disable (default)
1: Enable
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Addr
08H
Register Name
Digital MIC
R/W
Default
D7
0
R
0
D6
0
R
0
D5
PMDMR
R/W
0
D4
PMDML
R/W
0
D3
DCLKE
R/W
0
D2
0
R
0
D1
DCLKP
R/W
0
D0
DMIC
R/W
0
DMIC: Digital Microphone Connection Select
0: Analog Microphone (default)
1: Digital Microphone
DCLKP: Data Latching Edge Select
0: Lch data is latched on the DMCLK rising edge (“↑”). (default)
1: Lch data is latched on the DMCLK falling edge (“↓”).
DCLKE: DMCLK pin Output Clock Control
0: “L” Output (default)
1: 64fs Output
PMDML/R: Input Signal Select with Digital Microphone (Table 21)
Default: “00”
ADC digital block is powered-down by PMDML = PMDMR bits = “0” when selecting a digital microphone input
(DMIC bit = “1”, INL/R bits = “00”, “01” or “10”).
Addr
09H
Register Name
Timer Select
R/W
Default
D7
ADRST1
R/W
0
D6
ADRST0
R/W
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
DVTM1
R/W
0
D0
DVTM0
R/W
1
DVTM1-0: Digital Volume Soft Transition Time Setting (Table 41)
Default: “01” (1024/fs)
This is the transition time between DVL/R7-0 bits = 00H and FFH.
ADRST1-0: ADC Initialization Cycle Setting
00: 1059/fs (default)
01: 267/fs
10: 2115/fs
11: 2115/fs
Addr
0AH
Register Name
ALC Timer Select
D7
0
D6
ZTM1
D5
ZTM0
D4
WTM2
D3
WTM1
D2
WTM0
D1
RFST1
D0
RFST0
R/W
Default
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RFST1-0: ALC First recovery Speed (Table 34)
Default: “00” (4times)
WTM2-0: ALC Recovery Waiting Period (Table 30)
Default: “000” (128/fs)
A period of recovery operation when any limiter operation does not occur during ALC operation
ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 29)
Default: “00” (128/fs)
In case of the μP WRITE operation or ALC recovery operation, the volume is changed at zero crossing or
timeout.
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Addr
0BH
Register Name
ALC Mode Control 1
R/W
Default
D7
LFST
R/W
0
D6
ALC2
R/W
0
D5
ALC1
R/W
0
D4
ZELMN
R/W
0
D3
LMAT1
R/W
0
D2
LMAT0
R/W
0
D1
LMTH1
R/W
0
D0
LMTH0
R/W
0
D1
IREF1
R/W
0
D0
IREF0
R/W
1
D1
OREF1
R/W
0
D0
OREF0
R/W
0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 27)
Default: “00”
LMAT1-0: ALC Limiter ATT Step (Table 28)
Default: “00”
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
0: Enable (default)
1: Disable
ALC1: ALC Enable for Recording
0: Recording ALC Disable (default)
1: Recording ALC Enable
ALC2: ALC Enable for Playback
0: Playback ALC Disable (default)
1: Playback ALC Enable
LFST: ALC Limiter operation when the output level exceed FS(Full-scale) level.
0: The volume is changed at zero crossing or zero crossing time out. (default)
1: When output of ALC is larger than FS, OVOL value is changed immediately (1/fs).
Addr
0CH
Register Name
ALC Mode Control 2
R/W
Default
D7
IREF7
R/W
1
D6
IREF6
R/W
1
D5
IREF5
R/W
1
D4
IREF4
R/W
0
D3
IREF3
R/W
0
D2
IREF2
R/W
0
IREF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 32)
Default: “E1H” (+30.0dB)
Addr
0DH
Register Name
ALC Mode Control 3
R/W
Default
D7
RGAIN1
R/W
0
D6
RGAIN0
R/W
0
D5
OREF5
R/W
1
D4
OREF4
R/W
0
D3
OREF3
R/W
1
D2
OREF2
R/W
0
OREF5-0: Reference value at Playback ALC Recovery Operation. 0.375dB step, 50 Level (Table 33)
Default: “28H” (+6.0dB)
RGAIN1: ALC Recovery GAIN Step (Table 31)
Default: “00”
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Addr
0EH
Register Name
ALC Volume
R/W
Default
D7
VOL7
D6
VOL6
D5
VOL5
D4
VOL4
D3
VOL3
D2
VOL2
D1
VOL1
D0
VOL0
R
1
R
0
R
0
R
1
R
0
R
0
R
0
R
1
D2
IVL2
IVR2
R/W
0
D1
IVL1
IVR1
R/W
0
D0
IVL0
IVR0
R/W
1
VOL7-0: Current ALC volume value; 0.375dB step, 242 Level. Read operation only (Table 35)
Addr
0FH
10H
Register Name
Lch Input Volume Control
Rch Input Volume Control
R/W
Default
D7
IVL7
IVR7
R/W
1
D6
IVL6
IVR6
R/W
1
D5
IVL5
IVR5
R/W
1
D4
IVL4
IVR4
R/W
0
D3
IVL3
IVR3
R/W
0
IVL7-0, IVR7-0: IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 38)
Default: “E1H” (+30.0dB)
Addr
11H
12H
Register Name
Lch Output Volume Control
Rch Output Volume Control
R/W
Default
D7
OVL7
OVR7
R/W
1
D6
OVL6
OVR6
R/W
0
D5
OVL5
OVR5
R/W
0
D4
OVL4
OVR4
R/W
1
D3
OVL3
OVR3
R/W
0
D2
OVL2
OVR2
R/W
0
D1
OVL1
OVR1
R/W
0
D0
OVL0
OVR0
R/W
1
D5
DVL5
DVR5
R/W
0
D4
DVL4
DVR4
R/W
1
D3
DVL3
DVR3
R/W
1
D2
DVL2
DVR2
R/W
0
D1
DVL1
DVR1
R/W
0
D0
DVL0
DVR0
R/W
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
BPFR1
R/W
0
D0
BPFR0
R/W
0
OVL7-0, OVR7-0: Output Digital Volume (Table 40)
Default: “91H” (0dB)
Addr
13H
14H
Register Name
Lch Digital Volume Control
Rch Digital Volume Control
R/W
Default
D7
DVL7
DVR7
R/W
0
D6
DVL6
DVR6
R/W
0
DVL7-0, DVR7-0: Output Digital Volume2 (Table 41)
Default: “18H” (0dB)
Addr
15H
Register Name
BEEP Frequency
R/W
Default
D7
BPCNT
R/W
0
D6
0
R
0
BPFR1-0: BEEP Signal Output Frequency Setting (Table 44, Table 45)
Default: “00H”
BPCNT: BEEP Signal Output Mode Setting
0: Once Output Mode. (default)
1: Continuous Mode
In once output mode, the BEEP signal is output by the repeat times set by BPTM6-0 bits.
In continuous mode, the BEEP signal is output while BPCNT bit is “1”.
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Addr
16H
Register Name
BEEP ON Time
R/W
Default
D7
BPON7
R/W
0
D6
BPON6
R/W
0
D5
BPON5
R/W
0
D4
BPON4
R/W
0
D3
BPON3
R/W
0
D2
BPON2
R/W
0
D1
BPON1
R/W
0
D0
BPON0
R/W
0
D4
BPOFF4
R/W
0
D3
BPOFF3
R/W
0
D2
BPOFF2
R/W
0
D1
BPOFF1
R/W
0
D0
BPOFF0
R/W
0
D4
BPTM4
R/W
0
D3
BPTM3
R/W
0
D2
BPTM2
R/W
0
D1
BPTM1
R/W
0
D0
BPTM0
R/W
0
D1
BPLVL1
R/W
0
D0
BPLVL0
R/W
0
BPON7-0: BEEP Output ON-time Setting (Table 46, Table 47)
Default: “00H”
Addr
17H
Register Name
BEEP OFF Time
R/W
Default
D7
BPOFF7
R/W
0
D6
BPOFF6
R/W
0
D5
BPOFF5
R/W
0
BPOFF7-0: BEEP Output OFF-time Setting (Table 48, Table 49)
Default: “00H”
Addr
18H
Register Name
BEEP Repeat Count
R/W
Default
D7
0
R
0
D6
BPTM6
R/W
0
D5
BPTM5
R/W
0
BPTM6-0: BEEP Output Repeat Count Setting (Table 50)
Default: “00H”
Addr
19H
Register Name
BEEP Volume Control
R/W
Default
D7
BPOUT
R/W
0
D6
0
R
0
D5
0
R
0
D4
BPLVL4
R/W
0
D3
BPLVL3
R/W
0
D2
BPLVL2
R/W
0
BPLVL4-0: BEEP Output level Setting (Table 51)
Default: “0H” (0dB)
BPOUT: BEEP Signal Control
0: OFF (default)
1: ON
When BPCNT bit = “0”, the beep signal starts outputting by setting BPOUT bit = “1”. The Beep signal stops
after the number of times that is set by BPTM6-0 bit, and BPOUT bit is set to “0” automatically.
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Addr
1CH
Register Name
Digital Filter Select 1
R/W
Default
D7
0
R
0
D6
0
R
0
D5
LPF
R/W
0
D4
HPF
R/W
0
D3
0
R
0
D2
HPFC1
R/W
0
D1
HPFC0
R/W
0
D0
HPFAD
R/W
1
HPFAD: HPF1 Control of ADC
0: OFF
1: ON (default)
When HPFAD bit is “1”, the settings of HPFC1-0 bits are enabled. When HPFAD bit is “0”, HPFAD block is
through (0dB).
When PMADL bit = “1” or PMADR bit = “1”, set HPFAD bit to “1”.
HPFC1-0: Cut-off Frequency Setting of HPF1 (ADC) (Table 26)
Default: “00” (3.4Hz @ fs = 44.1kHz)
HPF: HPF2 Coefficient Setting Enable
0: OFF (default)
1: ON
When HPF bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPF bit is “0”, HPF block
is through (0dB).
LPF: LPF Coefficient Setting Enable
0: OFF (default)
1: ON
When LPF bit is “1”, the settings of F2A13-0 and F2B13-0 bits are enabled. When LPF bit is “0”, LPF block
is through (0dB).
Addr
1DH
Register Name
Digital Filter Mode
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
PFDAC
R/W
0
D1
ADCPF
R/W
1
D0
PFSDO
R/W
1
PFSDO: SDTO Output Signal Select
0: ADC (+ 1st HPF) Output
1: Programmable Filter / ALC Output (default)
ADCPF: Programmable Filter / ALC Input Signal Select
0: SDTI
1: ADC Output (default)
PFDAC: DAC Input Signal Select
0: SDTI (default)
1: Programmable Filter / ALC Output
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Addr
1EH
1FH
20H
21H
Register Name
HPF2 Co-efficient 0
HPF2 Co-efficient 1
HPF2 Co-efficient 2
HPF2 Co-efficient 3
R/W
Default
D7
F1A7
0
F1B7
0
R/W
D6
F1A6
0
F1B6
0
R/W
D5
D4
D3
D2
F1A5
F1A4
F1A3
F1A2
F1A13
F1A12
F1A11
F1A10
F1B5
F1B4
F1B3
F1B2
F1B13
F1B12
F1B11
F1B10
R/W
R/W
R/W
R/W
F1A13-0 bits = 0x1FA9, F1B13-0 bits = 0x20AD
D1
F1A1
F1A9
F1B1
F1B9
R/W
D0
F1A0
F1A8
F1B0
F1B8
R/W
D1
F2A1
F2A9
F2B1
F2B9
R/W
0
D0
F2A0
F2A8
F2B0
F2B8
R/W
0
F1A13-0, F1B13-0: HPF2 Coefficient (14bit x 2)
Default: F1A13-0 bits = 0x1FA9, F1B13-0 bits = 0x20AD
fc = [email protected]=44.1kHz
Addr
22H
23H
24H
25H
Register Name
LPF Co-efficient 0
LPF Co-efficient 1
LPF Co-efficient 2
LPF Co-efficient 3
R/W
Default
D7
F2A7
0
F2B7
0
R/W
0
D6
F2A6
0
F2B6
0
R/W
0
D5
F2A5
F2A13
F2B5
F2B13
R/W
0
D4
F2A4
F2A12
F2B4
F2B12
R/W
0
D3
F2A3
F2A11
F2B3
F2B11
R/W
0
D2
F2A2
F2A10
F2B2
F2B10
R/W
0
F2A13-0, F2B13-0: LPF Coefficient (14bit x 2)
Default: “0000H”
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Addr
30H
Register Name
Digital Filter Select 2
R/W
Default
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
EQ5
R/W
0
D3
EQ4
R/W
0
D2
EQ3
R/W
0
D1
EQ2
R/W
0
D0
EQ1
R/W
0
EQ1: Equalizer 1 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ1 bit is “1”, the settings of E1A15-0, E1B15-0 and E1C15-0 bits are enabled. When EQ1 bit is “0”,
EQ1 block is through (0dB).
EQ2: Equalizer 2 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ2 bit is “1”, the settings of E2A15-0, E2B15-0 and E2C15-0 bits are enabled. When EQ2 bit is “0”,
EQ2 block is through (0dB).
EQ3: Equalizer 3 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ3 bit is “1”, the settings of E3A15-0, E3B15-0 and E3C15-0 bits are enabled. When EQ3 bit is “0”,
EQ3 block is through (0dB).
EQ4: Equalizer 4 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ4 bit is “1”, the settings of E4A15-0, E4B15-0 and E4C15-0 bits are enabled. When EQ4 bit is “0”,
EQ4 block is through (0dB).
EQ5: Equalizer 5 Coefficient Setting Enable
0: Disable (default)
1: Enable
When EQ5 bit is “1”, the settings of E5A15-0, E5B15-0 and E5C15-0 bits are enabled. When EQ5 bit is “0”,
EQ5 block is through (0dB).
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Addr
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
Register Name
E1 Co-efficient 0
E1 Co-efficient 1
E1 Co-efficient 2
E1 Co-efficient 3
E1 Co-efficient 4
E1 Co-efficient 5
E2 Co-efficient 0
E2 Co-efficient 1
E2 Co-efficient 2
E2 Co-efficient 3
E2 Co-efficient 4
E2 Co-efficient 5
E3 Co-efficient 0
E3 Co-efficient 1
E3 Co-efficient 2
E3 Co-efficient 3
E3 Co-efficient 4
E3 Co-efficient 5
E4 Co-efficient 0
E4 Co-efficient 1
E4 Co-efficient 2
E4 Co-efficient 3
E4 Co-efficient 4
E4 Co-efficient 5
E5 Co-efficient 0
E5 Co-efficient 1
E5 Co-efficient 2
E5 Co-efficient 3
E5 Co-efficient 4
E5 Co-efficient 5
R/W
Default
D7
E1A7
E1A15
E1B7
E1B15
E1C7
E1C15
E2A7
E2A15
E2B7
E2B15
E2C7
E2C15
E3A7
E3A15
E3B7
E3B15
E3C7
E3C15
E4A7
E4A15
E4B7
E4B15
E4C7
E4C15
E5A7
E5A15
E5B7
E5B15
E5C7
E5C15
R/W
0
D6
E1A6
E1A14
E1B6
E1B14
E1C6
E1C14
E2A6
E2A14
E2B6
E2B14
E2C6
E2C14
E3A6
E3A14
E3B6
E3B14
E3C6
E3C14
E4A6
E4A14
E4B6
E4B14
E4C6
E4C14
E5A6
E5A14
E5B6
E5B14
E5C6
E5C14
R/W
0
D5
E1A5
E1A13
E1B5
E1B13
E1C5
E1C13
E2A5
E2A13
E2B5
E2B13
E2C5
E2C13
E3A5
E3A13
E3B5
E3B13
E3C5
E3C13
E4A5
E4A13
E4B5
E4B13
E4C5
E4C13
E5A5
E5A13
E5B5
E5B13
E5C5
E5C13
R/W
0
D4
E1A4
E1A12
E1B4
E1B12
E1C4
E1C12
E2A4
E2A12
E2B4
E2B12
E2C4
E2C12
E3A4
E3A12
E3B4
E3B12
E3C4
E3C12
E4A4
E4A12
E4B4
E4B12
E4C4
E4C12
E5A4
E5A12
E5B4
E5B12
E5C4
E5C12
R/W
0
D3
E1A3
E1A11
E1B3
E1B11
E1C3
E1C11
E2A3
E2A11
E2B3
E2B11
E2C3
E2C11
E3A3
E3A11
E3B3
E3B11
E3C3
E3C11
E4A3
E4A11
E4B3
E4B11
E4C3
E4C11
E5A3
E5A11
E5B3
E5B11
E5C3
E5C11
R/W
0
D2
E1A2
E1A10
E1B2
E1B10
E1C2
E1C10
E2A2
E2A10
E2B2
E2B10
E2C2
E2C10
E3A2
E3A10
E3B2
E3B10
E3C2
E3C10
E4A2
E4A10
E4B2
E4B10
E4C2
E4C10
E5A2
E5A10
E5B2
E5B10
E5C2
E5C10
R/W
0
D1
E1A1
E1A9
E1B1
E1B9
E1C1
E1C9
E2A1
E2A9
E2B1
E2B9
E2C1
E2C9
E3A1
E3A9
E3B1
E3B9
E3C1
E3C9
E4A1
E4A9
E4B1
E4B9
E4C1
E4C9
E5A1
E5A9
E5B1
E5B9
E5C1
E5C9
R/W
0
D0
E1A0
E1A8
E1B0
E1B8
E1C0
E1C8
E2A0
E2A8
E2B0
E2B8
E2C0
E2C8
E3A0
E3A8
E3B0
E3B8
E3C0
E3C8
E4A0
E4A8
E4B0
E4B8
E4C0
E4C8
E5A0
E5A8
E5B0
E5B8
E5C0
E5C8
R/W
0
E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3)
Default: “0000H”
E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3)
Default: “0000H”
E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3)
Default: “0000H”
E4A15-0, E4B15-0, E4C15-0: Equalizer 4 Coefficient (16bit x3)
Default: “0000H”
E5A15-0, E5B15-0, E5C15-0: Equalizer 5 Coefficient (16bit x3)
Default: “0000H”
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[AK4953A]
SYSTEM DESIGN
Figure 50 shows the system connection diagram. An evaluation board (AKD4953A) is available for fast evaluation as
well as suggestions for peripheral circuitry.
Analog Ground
Digital Ground
Headphone
Speaker
Power Supply
0.9 ∼ 5.5V
10u
100 0.22u
Power Supply
DVDD ∼ 3.5V
100 0.22u
Internal MIC
26
25
24
23
22
21
20
19
CP
VSS3
PVEE
HPR
HPL
DVDD
SPP
SPN
0.1u
27
CN
32
LIN3
AK4953A
33
RIN3
Top View
VSS4
18
SVDD
17
I2C
16
MCKO
15
12
35
RIN2
SDTO
11
36
MPWR2
BICK
10
MPWR1
LRCK
34
TVDD
9
13
LIN2
SDTI
14
8
MCKI
VSS2
CSN
2.2k
2.2k
2.2k
2.2k
C
VCOM
5
External MIC
31
PDN
C
REGFIL
4
C
30
RIN1
Line In
VSS1
3
C
29
LIN1
2.2u
AVDD
2
2.2u
28
1
0.1u
7
10u
2.2u
CCLK
Power Supply
2.85 ∼ 3.5V
2.2u
CDTIO
10u
6
Power Supply
1.6 ∼ 2.0V
0.1u
0.1u
DSP
C
C
μP
Notes:
- VSS1, VSS2, VSS3 and VSS4 of the AK4953A must be distributed separately from the ground of external
controllers.
- All digital input pins must not be left floating.
- When the AK4953A is used in master mode, LRCK and BICK pins are floating before M/S bit is changed to
“1”. Therefore, around 100kΩ pull-up resistor must be connected to LRCK and BICK pins of the AK4953A.
- 0.1μF capacitors at power supply pins should be ceramic capacitors. Other capacitors do not have specific
types.
Figure 50. System Connection Diagram (3-wire Serial Mode)
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[AK4953A]
1. Grounding and Power Supply Decoupling
The AK4953A requires careful attention to power supply and grounding arrangements. If AVDD, DVDD, TVDD and
SVDD are supplied separately, the power-up sequence is not critical. VSS1, VSS2, VSS3 and VSS4 of the AK4953A
must be connected to the analog ground plane. System analog ground and digital ground must be connected together near
to where the supplies are brought onto the printed circuit board. Decoupling capacitors must be as near to the AK4953A
as possible, with the small value ceramic capacitor being the nearest.
2. Internal Regulated Voltage Power Supply
The input voltage to the REGFIL pin is used as power supply (typ. 2.5V) for the internal analog circuit. A 2.2μF±50%
electrolytic capacitor connected between the REGFIL and VSS1 pins eliminates the effects of high frequency noise. This
capacitor in particular should be connected as close as possible to the pin. No load current may be drawn from the
REGFIL pin. All digital signals, especially clocks, should be kept away from the REGFIL pin in order to avoid unwanted
coupling into the AK4953A.
3. Voltage Reference
VCOM is a signal ground of this chip (typ. 1.25V). A 2.2μF±50% electrolytic capacitor connected between this pin and
the VSS1 pin eliminates the effects of high frequency noise. This capacitor in particular should be connected as close as
possible to the pin. No load current may be drawn from the VCOM pin. All digital signals, especially clocks, must be kept
away from the VCOM pin in order to avoid unwanted coupling into the AK4953A.
4. Charge Pump
2.2μF±50% capacitors between the CP and CN pins, and the PVEE and VSS3 pins should be low ESR ceramic
capacitors. These capacitors must be connected as close as possible to the pins. No load current may be drawn from the
PVEE pin.
5. Analog Inputs
The MIC input is single-ended. The input signal range scales with nominally at typ. 2.4Vpp (@ MGAIN = 0dB), centered
around the internal signal ground (typ. 1.25V). Usually the input signal is AC coupled using a capacitor (1μF or less is
recommended). The cut-off frequency is fc = 1/ (2πRC). The AK4953A can accept input voltages from VSS1 to AVDD.
6. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFFFH (@24bit)
and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit). The
headphone output is single-ended and centered around VSS (0V). There is no need for AC coupling capacitors. The
speaker outputs are centered on 0.5 x SVDD (typ).
MS1252-E-00
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[AK4953A]
CONTROL SEQUENCE
■ Clock Set up
When any circuits of the AK4953A are powered-up, the clocks must be supplied.
1. PLL Master Mode
Example:
Power Supply
PDN pin
PMVCM bit
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1)
(2) (3)
(Addr:00H, D6)
(1) Power Supply & PDN pin = “L” Æ “H”
(4)
MCKO bit
(Addr:01H, D1)
PMPLL bit
(2)Dummy command
Addr:01H, Data:08H
Addr:05H, Data:4AH
Addr:06H, Data:0DH
> 3ms
(Addr:01H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:40H
(Addr:01H, D3)
10msec(max)
(7)
BICK pin
LRCK pin
(6)
Output
(4)Addr:01H, Data:0BH
Output
MCKO, BICK and LRCK output
10msec(max)
(9)
MCKO pin
(8)
Figure 51. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin “L” → “H”.
“L” time of 150ns or more is needed to reset the AK4953A.
(2) After Dummy Command input, M/S, DIF1-0, BCKO, PLL3-0, FS3-0, DS and PS1-0 bits must be set during
this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time is 3ms (max).
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source, and PLL
lock time is 10ms (max).
(6) BICK pin outputs “H” and LRCK pin outputs “L” during this period.
(7) The AK4953A starts to output the LRCK and BICK clocks after the PLL became stable. Then normal operation
starts.
(8) The invalid frequency is output from the MCKO pin during this period if MCKO bit = “1”.
(9) The normal clock is output from the MCKO pin after the PLL is locked if MCKO bit = “1”.
MS1252-E-00
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[AK4953A]
2. PLL Slave Mode (BICK pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
Power Supply
PDN pin
PMVCM bit
(1)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(2) (3)
(Addr:00H, D6)
PMPLL bit
(2) Dummy command
Addr:05H, Data:32H
Addr:06H, Data:02H
> 3ms
(Addr:01H, D0)
BICK pin
Input
(3) Addr:00H, Data:40H
(4)
Internal Clock
(5)
(4) Addr:01H, Data:01H
Figure 52. Clock Set Up Sequence (2)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4953A.
(2) After Dummy Command input, DIF1-0, PLL3-0, FS3-0 and DS bits must be set during this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time is 3ms (max).
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (BICK pin) is supplied. PLL
lock time is 2ms (max) when BICK is a PLL reference clock.
(5) Normal operation stats after that the PLL is locked.
MS1252-E-00
2010/10
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[AK4953A]
3. PLL Slave Mode (MCKI pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
PDN pin
PMVCM bit
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
(2)Dummy command
Addr:05H, Data:42H
Addr:06H, Data:0DH
(2) (3)
(Addr:00H, D6)
(4)
MCKO bit
(Addr:01H, D1)
PMPLL bit
(3)Addr:00H, Data:40H
> 3ms
(Addr:01H, D0)
(5)
MCKI pin
(4)Addr:01H, Data:03H
Input
10msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
BICK pin
LRCK pin
Input
BICK and LRCK input start
Figure 53. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4953A.
(2) After Dummy Command input, DIF1-0, PLL3-0, FS3-0, DS and PS1-0 bits must be set during this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time is 3ms (max).
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 10ms (max).
(6) The normal clock is output from MCKO after PLL is locked.
(7) The invalid frequency is output from MCKO during this period.
(8) BICK and LRCK clocks must be synchronized with MCKO clock.
MS1252-E-00
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[AK4953A]
4. EXT Slave Mode
Example:
Audio I/F Format: MSB jusified (ADC and D AC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L” Æ “H”
Power Supply
PDN pin
PMVCM bit
(1)
(2)
(2)Dummy command
Addr:05H, Data:02H
Addr:06H, Data:02H
(3)
(Addr:00H, D6)
(4)
MCKI pin
Input
(3) Addr:00H, Data:40H
(4)
LRCK pin
BICK pin
Input
MCKI, BICK and LRCK input
Figure 54. Clock Set Up Sequence (4)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4953A.
(2) After Dummy Command input, DIF1-0, FS3-0 and DS bits must be set during this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates.
(4) Normal operation starts after the MCKI, LRCK and BICK are supplied.
MS1252-E-00
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[AK4953A]
5. EXT Master Mode
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
BCKO: 64fs
(1) Power Supply & PDN pin = “L” Æ “H”
(2) Dummy command
Power Supply
PDN pin
(1)
(3) MCKI input
(5)
PMVCM bit
(Addr:00H, D6)
MCKI pin
(4)Addr:05H, Data:0AH
Addr:06H, Data:02H
Addr:01H, Data:08H
(2) (3)
Input
(4)
M/S bit
BICK and LRCK output
(Addr:01H, D3)
LRCK pin
BICK pin
Output
(5) Addr:00H, Data:40H
Figure 55. Clock Set Up Sequence (5)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4953A.
(2) Dummy Command must be input during this period.
(3) MCKI is supplied.
(4) After DIF1-0, BCKO, FS3-0 and DS bits are set. M/S bit should be set to “1”. Then LRCK and BICK are output.
(5) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates.
MS1252-E-00
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[AK4953A]
■MIC Input Recording (Stereo)
FS3-0 bits
(Addr:06H, D3-0)
MIC Control
(Addr:02H,
D3, D2-0)
Timer Select
(Addr:09H, D7-6
Addr:0AH)
ALC Control 2
(Addr:0CH )
IVL7-0 bits
(Addr:0FH)
ALC Control 3
(Addr:0DH, D7-6)
ALC Control 1
(Addr:0BH)
Digital Filter Path
(Addr:1DH)
Filter Co-ef
(Addr:1CH,1E-25H,
32-4FH)
Example:
0000
1101
PLL Master Mode
Audio I/F Format: MSB justified
Pre MIC Amp: +20dB
MIC Power 1 ON
Sampling Frequency: 44.1kHz
ALC1 setting: Refer to Table 35
HPF1: fc=108.8Hz, ADRST1-0 bits = “00”
Programmable Filter OFF
(1)
0, 011
1, 011
(2)
00, 00H
(1) Addr:06H, Data:0DH
00, 70H
(3)
(2) Addr:02H, Data:0BH
E1H
E1H
(4)
(3) Addr:09H, Data:00H
Addr:0AH, Data:70H
E1H
E1H
(5)
(4) Addr:0CH, Data:E1H
00
00
(6)
(5) Addr:0FH, Data:E1H
00H
A1H
00H
(13)
(7)
03H
03H
(6) Addr:0DH, Data:00H
(7) Addr:0BH, Data:A1H
(8)
(8) Addr:1DH, Data:03H
XX....X
XX....X
(9)
(9) Addr:1CH, Data:04H
Filter Select
(Addr:1CH, 30H)
ALC1 State
XX....X
XX....X
(10) Addr:1CH, Data:05H
(10)
ALC1 Disable
ALC1 Enable
ALC1 Disable
PMPFIL bit
PMADL/R bit
Recording
(Addr:00H, D7, D1-0)
SDTO pin
State
(11) Addr:00H, Data:C3H
(11)
0 data Output
1059/fs
Initialize
(12)
Normal
0 data output
Data Output
(12) Addr:00H, Data:40H
(13) Addr:0BH, Data:00H
Figure 56. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=44.1kHz. For changing the parameter of ALC, please refer to
“Registers Set-up Sequence at ALC1 Operation (recording path)”.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4953A is the PLL mode, MIC, ADC and
Programmable Filter of (11) must be powered-up in consideration of PLL lock time after a sampling
frequency is changed.
(2) Set up MIC Gain (Addr = 02H)
(3) Set up ALC1 Timer, ADRST1-0 bits (Addr = 09H, 0AH)
(4) Set up IREF value at ALC1 (Addtr = 0CH)
(5) Set up IVOL value at ALC1 operation start (Addr = 0FH)
(6) Set up RGAIN1-0 bits (Addr =0DH)
(7) Set up LMTH1-0, LMAT1-0, ZELMN, ALC1 and LFST bits (Addr = 0BH)
(8) Set up Programmable Filter Path: PFSDO bit = ADCPF bit = “1” (Addr = 1DH)
(9) Set up Coefficient Programmable Filter (Addr: 1CH, 1EH ~ 25H, 32H ~ 4FH)
(10) Set up of Programmable Filter ON/OFF
(11) Power Up MIC, ADC and Programmable Filter: PMADL =PMADR =PMPFIL bits = “0” →“1”
The initialization cycle time of ADC is 1059/fs=24ms @ fs=44.1kHz, ADRST1-0 bit = “00”. ADC outputs “0”
data during the initialization cycle. After the ALC1 bit is set to “1”, the ALC1 operation starts from IVOL value
of (5).
(12) Power Down MIC, ADC and Programmable Filter: PMADL = PMADR = PMPFIL bits = “1” → “0”
(13) ALC Disable: ALC1 bit = “1” → “0”
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[AK4953A]
■Digital MIC Input Recording (Stereo)
FS3-0 bits
0000
(Addr:06H, D3-0)
Timer Select
(Addr:09H, D7-6
Addr:0AH,)
Example:
1101
PLL Master Mode
Audio I/F Format: MSB justified
Sampling Frequency: 44.1kHz
Digital MIC setting:
D ata is latched on the DMCLK failing edge
ALC1 setting: Refer to Table 35
HPF1: fc=108.8Hz, ADRST1-0 bits = “00”
Programmable Filter OFF
(1)
00, 00H
ALC Control 2
(Addr:0CH )
IVL7-0 bits
(Addr:0FH)
ALC Control 3
(Addr:0DH, D7-6)
00, 70H
(2)
00H
(1) Addr:06H, Data:0DH
E1H
(3)
(2) Addr:09H, Data:00H
Addr:0AH, Data:70H
E1H
E1H
(4)
(3) Addr:0CH, Data:E1H
00
00
(5)
ALC Control 1
(Addr:0BH)
Digital Filter Path
(Addr:1DH)
Filter Co-ef
(Addr:1CH, 1E-25H
32-4FH)
Filter Select
(Addr:1CH, 30H)
00H
(4) Addr:0FH, Data:E1H
A1H
(6)
00H
(14)
03H
03H
(6) Addr:0BH, Data:A1H
(7)
XX....X
(5) Addr:0DH, Data:00H
XX....X
(7) Addr:1DH, Data:03H
XX....X
(8) Addr:1CH, Data:04H
(8)
XX....X
(9)
(9) Addr:1CH, Data:05H
ALC1 State
ALC1 Disable
ALC1 Enable
ALC1 Disable
(10) Addr:00H, Data:C0H
PMPFIL bit
(Addr:00H, D7)
(11) Addr:08H, Data:3BH
(13)
(10)
Digital MIC
0000 X 0 XX
0011 X 0 XX
0000 X 0 XX
Recording
(Addr:08H)
(11)
SDTO pin
State
1059/fs
(12)
Normal
data ouput
0 data output
(12) Addr:08H, Data:0BH
(13) Addr:00H, Data:40H
0 data output
(14) Addr:0BH, Data:00H
Figure 57. Digital MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=44.1kHz. For changing the parameter of ALC, please refer to
“Registers Set-up Sequence at ALC1 Operation (recording path)”.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4953A is PLL mode, Digital MIC of (11) and
Programmable Filter of (10) must be powered-up in consideration of PLL lock time after a sampling frequency
is changed.
(2) Set up ALC1 Timer and ADRST1-0 bits (Addr = 09H, 0AH)
(3) Set up IREF value for ALC1 (Addtr = 0CH)
(4) Set up IVOL value at ALC1 operation start (Addr = 0FH)
(5) Set up RGAIN1-0 bits (Addr =0DH)
(6) Set up LMTH1-0, LMAT1-0, ZELMN, ALC1, LFST bits (Addr = 0BH)
(7) Set up Programmable Filter Path: PFSDO bit = ADCPF bit = “1” (Addr = 1DH)
(8) Set up Coefficient of Programmable Filter (Addr: 1CH, 1EH ~ 25H, 32H ~ 4FH)
(9) Set up Programmable Filter ON/OFF
(10) Power Up Programmable Filter: PMPFIL bit = “0” → “1”
(11) Set up & Power Up Digital MIC: PMDMR = PMDML bits = “0” →“1”
The initialization cycle time of ADC is 1059/fs=24ms @ fs=44.1kHz, .ADRST1-0 bit = “00”. ADC outputs “0”
data during initialization cycle. After the ALC1 bit is set to “1”, the ALC1 operation starts from IVOL value of
(5).
(12) Power Down Digital MIC: PMDMR =PMDML bits = “1” → “0”
(13) Power Down Programmable Filter: PMPFIL bit = “1” → “0”
(14) ALC1 Disable: ALC1 bit = “1” → “0”
MS1252-E-00
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[AK4953A]
■ Headphone-Amp Output
FS3-0 bits
(Addr:06H, D3-0)
Example:
1101
0000
PLL, Master Mode
Audio I/F Format: MSB justified
Sampling Frequency: 44.1KHz
Digital Volume 2: 0dB
PMBP bit = “0”
Programmable Filter OFF
(1)
DVL7-0 bits
(Addr:13H)
18H
18H
(1) Addr:06H, Data:0DH
(2)
Digital Filter Path
(Addr:1DH)
(2) Addr:13H, Data:18H
03H
03H
(3) Addr:1DH, Data:03H
(3)
PMDAC bit
(4) Addr:00H, Data:44H
Addr:01H, Data:39H
(Addr:00H, D2)
PMHPL/R bits
(Addr:01H, D5-4)
(5)
(4)
Playback
> 35ms
(5) Addr:01H, Data:09H
Addr:00H, Data:40H
HPL pin
HPR pin
Figure 58. Headphone-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4953A is PLL mode, DAC of (4) must be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the output digital volume 2 (Addr = 13H)
(3) Set up Programmable Filter Path: PFDAC, ADCPF, PFSDO bits (Addr = 1DH)
(4) Power up DAC and Headphone-Amp: PMDAC = PMHPL = PMHPR bits = “0” Æ “1”
When PMHPL = PMHPR bits = “1”, the charge pump circuit starts to power-up. The power-up time of
Headphone-Amp block is 35ms (max).
(5) Power down DAC and Headphone-Amp: PMDAC = PMHPL = PMHPR bits = “1” Æ “0”
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■ Beep Signal Output from Headphone-Amp
1. Power down DAC → Headphone-Amp
Example:default
(1)
BEEP Gen bits
(Addr:15-19H)
PMHPL bit
PMHPR bit
00H
(1) Addr:15-19H, Data:00H
00H
(2) Addr:01H, Data:30H
(6)
(2)
(3) Addr:00H, D5 bit = “1”
(Addr:01H, D5-4)
(3)
(5)
PMBP bit
(4) Addr:19H, Data:80H
(Addr:00H, D5)
(4)
(4)
BEEP Signal Output
BPOUT bit
(Addr:19H, D7)
HPL pin
HPR pin
Addr:19H, Data:00H (Auto)
> 35ms
0V
(5) Addr:00H, D5 bit = “0”
Beep Output
0V
(6) Addr:01H, Data:00H
Figure 59. “BEEP Generator → Headphone-Amp” Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up BEEP Generator (Addr: 15H ~ 19H) (When repeat output time BPCNT bit = “0”)
(2) Power up Headphone-Amp: PMHPL bit or PMHPR bit = “0” → “1”
(3) Power up BEEP-Generator: PMBP bit = “0” → “1”
Charge pump circuit starts to power-up. The power-up time of Headphone-Amp block is 35ms (max).
(4) BEEP output: BPOUT bit= “0” → “1”
After outputting data particular set times, BPOUT bit automatically goes to “0”.
(5) Power down BEEP Generator: PMBP bit = “1” → “0”
(6) Power down Headphone-Amp: PMHPL bit or PMHPR bit = “1” → “0”
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2. Power up DAC → Headphone-Amp
Example:default
(1)
BEEP Gen bits
(Addr:15-19H)
00H
00H
(1) Addr:15-19H, Data:00H
(2)
(4)
(2) Addr:00H, D5 bit = “1”
PMBP bit
(Addr:00H, D5)
(3)
(3)
(3) Addr:19H, Data:80H
BPOUT bit
(Addr:19H, D7)
HPL pin
HPR pin
PTS1-0
bits
Normal Output
BEEP Signal Output
PTS1-0
bits
Normal Output
+ Beep Output
Addr:19H, Data:00H (Auto)
Normal Output
(4) Addr:00H, D5 bit = “0”
Figure 60. “BEEP Generator → Headphone-Amp” Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence, and Headphone-Amp output should be
started according to “Headphone-Amp Output” sequence.
(1) Set up BEEP Generator (Addr: 15H ~ 19H) (When repeat output time BPCNT bit = “0”)
(2) Power up BEEP Generator: PMBP bit = “0” → “1”
(3) BEEP output: BPOUT bit= “0” → “1”
After the transition time by setting PTS1-0 bits, BEEP signal is started to output. After outputting data
particular set times, BPOUT bit automatically goes to “0”.
(4) Power down BEEP Generator: PMBP bit = “1” → “0”
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■ Speaker-Amp Output
FS3-0 bits
(Addr:06H, D3-0)
0000
Example:
1101
(1)
PLL Master Mode
Audio I/F Format: MSB justified
Sampling Frequency:44.1KHz
Digital Volume: 0dB
ALC2: Enable
Programmable Filter OFF
(12)
DACS bit
(Addr:02H, D5)
(2)
(1) Addr:06H, Data:0DH
SPKG1-0 bits
(Addr:03H, D7-6)
Timer Select
(Addr:0AH)
ALC Control 3
(Addr:0DH)
ALC Control 1
(Addr:0BH)
OVL/R7-0 bits
(Addr:11H&12H)
00
01
(3)
(2) Addr:02H, Data:23H
00H
70H
(4)
(3) Addr:03H, Data:40H
28H
28H
(4) Addr:0AH, Data:70H
(5)
00H
C1H
(5) Addr:0DH, Data:28H
(6)
91H
91H
(6) Addr:0BH, Data:C1H
04H
(7) Addr:11H & 12H, Data:91H
(7)
Digital Filter Path
(Addr:1DH)
ALC2 State
03H
(8)
ALC2 Disable
ALC2 Enable
ALC2 Disable
(9) Addr:00H, Data:D4H
(13)
PMPFIL bit
PMDAC bit
(Addr:00H,D7&D2)
(8) Addr:1DH, Data:04H
(10) Addr:02H, Data:A3H
(9)
PMSPK bit
(Addr:00H, D4)
SPPSN bit
(Addr:02H, D7)
Hi-Z
Hi-Z
(11) Addr:02H, Data:23H
(11)
(10)
SPP pin
SPN pin
Playback
> 1 ms
Normal Output
Hi-Z
SVDD/2 Normal Output SVDD/2
Hi-Z
(12) Addr:02H, Data:03H
(13) Addr:00H, Data:40H
Figure 61. Speaker-Amp Output Sequence
<Example>
At first, clocks must be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4953A is PLL mode, DAC and Speaker-Amp of (9)
must be powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of DAC → SPK-Amp: DACS bit = “0” → “1”
(3) SPK-Amp gain setting: SPKG1-0 bits = “00” → “01”
(4) Set up Timer Select for ALC2 (Addr = 0AH)
(5) Set up OREF value for ALC2 and RGAIN1-0 bits (Addr = 0DH)
(6) Set up LMTH1-0, LMAT1-0, ZELMIN, ALC2 and LFST bits (Addr = 0BH)
(7) Set up the output digital volume (Addr = 11H, 12H)
Set up OVOL value at ALC2 operation start. When OVOLC bit is “1” (default), OVL7-0 bits set the volume of
both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register
setting value by the soft transition. When ALC2 bit = “0”, it could be digital volume control.
(8) Set up Programmable Filter Path: PFDAC, ADCPF, PFSDO bits (Addr = 1DH)
(9) Power up DAC, Programmable Filter and Speaker: PMDAC = PMPFIL = PMSPK bits = “0” → “1”
(10) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
(11) Enter Speaker-Amp Power-save-mode: SPPSN bit = “1” → “0”
(12) Disable the path of “DAC → SPK-Amp”: DACS bit = “1” → “0”
(13) Power down DAC, Programmable Filter and Speaker: PMDAC = PMPFIL = PMSPK bits = “1” → “0”
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■ Beep Signal Output from Speaker-Amp
Example:default
(1) Addr:15-19H, Data:00H
(1)
BEEP Gen bits
(Addr:15-19H)
XXH
00H
(2) Addr:00H, Data:50H
(8)
(2)
PMSPK bit
(3) Addr:00H, D5 bit = “1”
(Addr:00H, D4)
(3)
(7)
(4) Addr:02H, Data:83H
PMBP bit
(Addr:00H, D5)
> 1 ms
SPPSN bit
(4)
(6)
(5) Addr:19H, Data:80H
(Addr:02H, D7)
(5)
BEEP Signal Output
(5)
BPOUT bit
(Addr:19H, D7)
Addr:19H, Data:00H (Auto)
SPP pin
Hi-Z
SPN pin
Hi-Z
SVDD/2
SVDD/2
Beep Output
SVDD/2
Hi-Z
(6) Addr:02H, Data:03H
Beep Output
SVDD/2
Hi-Z
(7) Addr:00H, D5 bit = “0”
(8) Addr:00H, Data:40H
Figure 62. “BEEP Generator → Speaker-Amp” Output Sequence
<Example>
At first, clocks must be supplied according to “Clock Set Up” sequence.
(1) Set up BEEP Generator (Addr: 15H ~ 19H) (When repeat output time BPCNT bit = “0”)
(2) Power up Speaker: PMSPK bit = “0” → “1”
(3) Power up BEEP Generator: PMBP bit = “0” → “1”
(4) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
(5) BEEP output: BPOUT bit= “0” → “1”
After outputting data particular set times, BPOUT bit automatically goes to “0”.
(6) Enter Speaker-Amp Power-save-mode: SPPSN bit = “1” → “0”
(7) Power down BEEP Generator: PMBP bit = “1” → “0”
(8) Power down Speaker: PMSPK bit = “1” → “0”
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■ Stop of Clock
When any circuits of the AK4953A are powered-up, the clocks must be supplied.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
MCKO bit
"0" or "1"
(1) (2) Addr:01H, Data:08H
(Addr:01H, D1)
External MCKI
(3)
Input
(3) Stop an external MCKI
Figure 63. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (BICK pin)
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1)
PMPLL bit
(Addr:01H, D0)
(2)
External BICK
Input
(1) Addr:01H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 64. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks.
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3. PLL Slave (MCKI pin)
Example
(1)
PMPLL bit
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
(Addr:01H, D0)
(1)
MCKO bit
(1) Addr:01H, Data:00H
(Addr:01H, D1)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 65. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
4. EXT Slave Mode
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format :MSB justified(AD C & DAC)
Input MCKI frequency:256fs
(1)
(1) Stop the external clocks
Figure 66. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
■ Power down
Power supply current can not be shut down by stopping clocks and setting PMVCM bit = “0”. Power supply current can
be shut down (typ. 1μA) by stopping clocks and setting the PDN pin = “L”. When the PDN pin = “L”, all registers are
initialized.
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PACKAGE
36pin QFN (Unit: mm)
TOP VIEW
BOTTOM VIEW
5.00 ± 0.10
3.62
#19
#27
#18
#28
#10
#36
#9
B
2.50
#1
0.10 M S A B
0.20 ± 0.05
0.40 ± 0.1
0.25 (min)
2.50
3.62
5.00 ± 0.10
A
C0.30
0.10 S
S
0.75 ± 0.05
0.40
0.20
0.08 S
Note: The exposed pad on the bottom surface of the package must be connected to the ground.
■ Material & Lead finish
Package molding compound: Epoxy Resin, Halogen (bromine and chlorine) free
Lead frame material: Cu Alloy
Lead frame surface treatment: Ni/Pd/Au Plate
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MARKING
4953A
XXXX
1
XXXX: Date code (4 digit)
Pin #1 indication
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REVISION HISTORY
Date (YY/MM/DD)
10/10/20
Revision
00
Reason
First Edition
Page/Line
Contents
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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