AKM AKD4424

[AK4424]
AK4424
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4424 is a 5V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4424 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4424 integrates a combination of switched-capacitor
and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit
word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio
applications, such as DVD, AV receiver system and set-top boxes. The AK4424 is offered in a space
saving 16pin TSSOP package.
FEATURES
† Sampling Rate Ranging from 8kHz to 192kHz
† 128 times Oversampling (Normal Speed Mode)
† 64 times Oversampling (Double Speed Mode)
† 32 times Oversampling (Quad Speed Mode)
† 24-Bit 8 times FIR Digital Filter
† Switched-Capacitor Filter with High Tolerance to Clock Jitter
† Single Ended 2Vrms Output Buffer
† Digital de-emphasis
† Soft mute
† I/F format: I2S
† Master clock: 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
† THD+N: -92dB
† Dynamic Range: 105dB
† Automatic Power-on Reset Circuit
† Power supply: +4.5 ∼ +5.5V
† Ta = -20 to 85°C
† Small Package: 16pin TSSOP (6.4mm x 5.0mm)
MCLK
SMUTE
DEM
Control
Interface
Clock
Divider
De-emphasis
Control
VDD
DZF
VSS1
LRCK
BICK
SDTI
Audio
Data
Interface
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
AOUTL
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
AOUTR
Charge
Pump
CP
CN
1μ
MS0935-E-03
VEE
VSS2
CVDD
1μ
2010/09
-1-
[AK4424]
■ Ordering Guide
-20 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4424
AK4424ET
AKD4424
■ Pin Layout
CN
1
16
VEE
CP
2
15
VSS2
DEM
3
14
CVDD
MCLK
4
13
DZF
BICK
5
12
VSS1
SDTI
6
11
VDD
LRCK
7
10
AOUTL
SMUTE
8
9
AOUTR
AK4424
Top View
■ Main Difference Between AK4420, AK4421 and AK4424
Digital de-emphasis
I/F format
Pin out
Pin#3
Pin#8
Power Supply
THD+N
DR
Operating Temperature
AK4420
24-bit MSB justified
I²S
SMUTE
DIF
+4.5 ∼ +5.5V
-92dB
105dB
ET: -20 ∼ +85°C
VT: -40 ∼ +85°C
AK4421
24-bit MSB justified
I²S
SMUTE
DIF
+3.0 ∼ +3.6V
-92dB (-3dBFS)
102dB
AK4424
X
DEM
SMUTE
+4.5 ∼ +5.5V
-92dB
105dB
ET: -20 ∼ +85°C
ET: -20 ∼ +85°C
I²S
-: Not available
X: Available
MS0935-E-03
2010/09
-2-
[AK4424]
PIN/FUNCTION
No.
Pin Name
I/O
Function
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF capacitor that should have the low ESR
1
CN
I
(Equivalent Series Resistance) over all temperature range. When this
capacitor has the polarity, the positive polarity pin should be connected to the
CP pin. Non polarity capacitors can also be used.
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF capacitor that should have the low ESR
2
CP
I
(Equivalent Series Resistance) over all temperature range. When this
capacitor has the polarity, the positive polarity pin should be connected to the
CP pin. Non polarity capacitors can also be used.
De-emphasis Mode Pin (Internal pull-down pin)
3
DEM
I
When at “H”, the de-emphasis filter is available.
Master Clock Input Pin
4
MCLK
I
An external TTL clock should be input on this pin.
5
BICK
I
Audio Serial Data Clock Pin
6
SDTI
I
Audio Serial Data Input Pin
7
LRCK
I
L/R Clock Pin
Soft Mute Enable Pin
8
SMUTE
I
“H”: Enable, “L”: Disable
Rch Analog Output Pin
9
AOUTR
O
When power down, outputs VSS(0V, typ).
Lch Analog Output Pin
10
AOUTL
O
When power down, outputs VSS(0V, typ).
11
VDD
DAC Power Supply Pin: 4.5V∼5.5V
12
VSS1
Ground Pin1
DZF
O
Zero Input Detect Pin
13
14
CVDD
Charge Pump Power Supply Pin: 4.5V∼5.5V
15
VSS2
Ground Pin2
Negative Voltage Output Pin
Connect to VSS2 with a 1.0μF capacitor that should have the low ESR
16
(Equivalent Series Resistance) over all temperature range. When this
VEE
O
capacitor has the polarity, the positive polarity pin should be connected to the
VSS2 pin. Non polarity capacitors can also be used.
Note: All input pins except for the CN pin should not be left floating.
MS0935-E-03
2010/09
-3-
[AK4424]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
CVDD
IIN
VIND
Ta
Tstg
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
Storage Temperature
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 connect to the same analog grand.
min
-0.3
-0.3
-0.3
-20
-65
max
+6.0
+6.0
±10
VDD+0.3
85
150
Units
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
CVDD
min
+4.5
typ
+5.0
VDD
max
+5.5
Units
V
Note 3. CVDD should be equal to VDD
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0935-E-03
2010/09
-4-
[AK4424]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +5.0V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ)
Parameter
min
typ
max
Resolution
24
Dynamic Characteristics (Note 4)
THD+N (0dBFS)
fs=44.1kHz, BW=20kHz
-92
-84
fs=96kHz, BW=40kHz
-92
fs=192kHz, BW=40kHz
-92
Dynamic Range (-60dBFS with A-weighted. (Note 5)
98
105
S/N (A-weighted. (Note 6)
98
105
Interchannel Isolation (1kHz)
90
100
Interchannel Gain Mismatch
0.2
0.5
DC Accuracy
DC Offset
(at output pin)
-60
0
+60
Gain Drift
100
Output Voltage (Note 7)
1.97
2.12
2.27
Load Capacitance (Note 8)
25
Load Resistance
5
Power Supplies
Power Supply Current: (Note 9)
24
36
Normal Operation (fs≤96kHz)
27
40
Normal Operation (fs=192kHz)
10
100
Power-Down Mode (Note 10)
Note 4. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 5. 98dB for 16bit input data
Note 6. S/N does not depend on input data size.
Note 7. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD,
AOUT ([email protected]) = 2.12Vrms × VDD/5.
Note 8. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load.
Note 9. The current into VDD and CVDD.
Note 10. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD
MS0935-E-03
Units
Bits
dB
dB
dB
dB
dB
dB
dB
mV
ppm/°C
Vrms
pF
kΩ
mA
mA
μA
2010/09
-5-
[AK4424]
FILTER CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V; fs = 44.1 kHz)
Parameter
Symbol
min
typ
max
Digital filter (DEM = OFF)
PB
0
20.0
Passband
±0.05dB (Note 11)
22.05
-6.0dB
Stopband (Note 11)
SB
24.1
Passband Ripple
PR
± 0.02
Stopband Attenuation
SA
54
Group Delay (Note 12)
GD
19.3
De-emphasis Filter (DEM = ON)
De-emphasis Error
fs = 32kHz
–1.5/0
(Relative to 0Hz)
fs = 44.1kHz
–0.2/+0.2
fs = 48kHz
0/+0.6
Digital Filter + LPF (DEM = OFF)
Frequency Response 20.0kHz fs=44.1kHz
FR
± 0.05
40.0kHz fs=96kHz
FR
± 0.05
80.0kHz fs=192kHz
FR
± 0.05
Note 11. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 12. Calculated delay time caused by digital filter. This time is measured from setting the 16/24bit data
of both channels to input register to the output of the analog signal.
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
dB
dB
dB
dB
dB
DC CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V)
Parameter
Symbol
min
typ
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
High-Level Input Voltage (Iout = -80uA)
VIH
VDD-0.4
Low-Level Input Voltage (Iout = 80uA)
VIL
Input Leakage Current (Note 13)
Iin
Note 13. The DEM pin is not included. The DEM pin has internal pull-down resistor. (typ.100kΩ)
MS0935-E-03
max
0.8
0.4
± 10
Units
V
V
V
V
μA
2010/09
-6-
[AK4424]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V)
Parameter
Symbol
min
Typ
fCLK
4.096
11.2896
Master Clock Frequency
dCLK
30
Duty Cycle
LRCK Frequency
8
fsn
Normal Speed Mode
32
fsd
Double Speed Mode
120
fsq
Quad Speed Mode
45
Duty
Duty Cycle
Audio Interface Timing
BICK Period
tBCK
1/128fsn
Normal Speed Mode
tBCK
1/64fsd
Double Speed Mode
tBCK
1/64fsq
Quad Speed Mode
tBCKL
30
BICK Pulse Width Low
tBCKH
30
Pulse Width High
tBLR
20
BICK “↑” to LRCK Edge (Note 14)
tLRB
20
LRCK Edge to BICK “↑” (Note 14)
tSDH
20
SDTI Hold Time
tSDS
20
SDTI Setup Time
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
MS0935-E-03
max
36.864
70
Units
MHz
%
48
96
192
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
2010/09
-7-
[AK4424]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 1. Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Figure 2. Serial Interface Timing
MS0935-E-03
2010/09
-8-
[AK4424]
OPERATION OVERVIEW
■ System Clock
The external clocks required to operate the AK4424 are MCLK, LRCK and BICK. The master clock (MCLK) should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the internal master
clock is set to the appropriate frequency (Table 1).
The AK4424 is automatically placed in power saving mode when MCLK and LRCK stop during normal operation mode,
and the analog output is forced to 0V(typ). When MCLK and LRCK are input again, the AK4424 is powered up. After
power-up, the AK4424 is in the power-down mode until MCLK and LRCK are input.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
-
192fs
-
22.5792
24.5760
33.8688
36.8640
MCLK (MHz)
256fs
384fs
512fs
16.3840
22.5792
24.5760
8.192
12.288
11.2896
16.9344
12.288
18.432
22.5792
33.8688
24.5760
36.8640
Table 1. system clock example
768fs
24.5760
33.8688
36.8640
1152fs
36.8640
-
-
-
Sampling
Speed
Normal
Double
Quad
When MCLK= 256fs/384fs, the AK4424 supports sampling rate of 32kHz~96kHz (Table 1). But, when the sampling rate
is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs. (Table 2)
MCLK
DR,S/N
256fs/384fs
102dB
512fs/768fs
105dB
Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
■ Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The AK4424 supports I2S format as
shown in Table 3. The serial data is MSB-first, two’s complement format and it is latched on the rising edge of BICK. It
can be used for 16/20 bit I2S formats by zeroing the unused LSBs.
SDTI Format
BICK
2
24bit I S
≥48fs
Table 3. Audio Data Format
MS0935-E-03
Figure
Figure 3
2010/09
-9-
[AK4424]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
1
23 22
0
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Audio Interface Timing
„ De-emphasis Filter
The AK4424 integrates digital de-emphasis filter (tc = 50/15µs). The DEM pin which enables the digital de-emphasis
filter by setting “H” is internal pull-down pin. Refer to the section of “FILTER CHARACTERISTICS” regarding the gain
error when the de-emphasis filter is enabled. In case of double speed mode (MCLK=256fs/384fs) and quad speed mode
(MCLK=128fs/192fs), the digital de-emphasis filter is always off.
DEM pin
De-emphasis Filter
1
ON
(default)
0
OFF
Table 4. De-emphasis Filter Control (Normal Speed Mode)
■ Zero detect function
When the input data for both channels are continuously zeros for 8192 LRCK cycles, the DZF pin is set to “H”. If the
input data of Lch and Rch are continuously not zeros orderly, or if each Rch or Lch is continuously not zeros, the DZF pin
immediately returns to “L”.
MS0935-E-03
2010/09
- 10 -
[AK4424]
■ Analog Output Block
The internal negative power supply generation circuit (Figure 4) provides a negative power supply for the internal 2Vrms
amplifier. It allows the AK4424 to output an audio signal centered at VSS (0V, typ) as shown in Figure 5. The negative
power generation circuit (Figure 4) needs 1.0uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). If this
capacitor is polarized, the positive polarity pin should be connected to the CP and VSS2 pins. This circuit operates by
clocks generated from MCLK. When MCLK stops, the AK4424 is placed in the reset mode automatically and the analog
outputs settle to VSS (0V, typ).
AK4424
CVDD
Charge
Pump
CP
CN
Negative Power
VSS2
(+)
1uF
Ca
VEE
Cb
1uF
(+)
Figure 4. Negative power generation circuit
AK4424
2.12Vrms
0V
AOUTR
(AOUTL)
Figure 5. Audio signal output
MS0935-E-03
2010/09
- 11 -
[AK4424]
■ Soft Mute Operation
Soft mute operation is performed in the digital domain. When the SMUTE pin is set “H”, the output signal is attenuated to
-∞ in 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting
this operation, the attenuation is discontinued and it is returned to 0dB by the same cycle. Soft mute is effective for
changing the signal source without stopping the signal transmission. In one cycle of LRCK, eight “H” pulses or more
must not be input to the SMUTE pin.
SMUTE pin
1024/fs
0dB
1024/fs
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) The time for input data attenuation to -∞, is
Normal Speed Mode: 1024 LRCK cycles (1024/fs).
Double Speed Mode: 2048 LRCK cycles (2048/fs).
Quad Speed Mode : 4096 LRCK cycles (4096/fs).
(2) The analog output corresponding to a specific digital input has a group delay, GD.
(3) If soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level in the same cycle.
(4) When the input data for both channels are continuously zeros for 8192 LRCK cycles, the DZF pin is set to “H”. The
DZF pin immediately returns to “L” if the input data are not zero.
Figure 6. Soft Mute and Zero detect function
MS0935-E-03
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[AK4424]
■ System Reset
The AK4424 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up.
The AK4424 is in power-down mode until LRCK are input.
Power Supply
(VDD, CVDD)
(6)
MCLK
Low
20 us
Analog
Circuit
Digital
Circuit
Charge Pump
Circuit
(1)
Power down
Power down
(2)
Power-up
2, 3
LRCK
Power down
Power-up
Power-up
(3)
Charge Pump
Time A
Counter circuit
D/A In
(Digital)
“0” data
D/A Out
(Analog)
DZF
MUTE (D/A Out)
(4)
(5)
Notes:
(1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up.
(2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK.
(3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A = 1024/ (fs x 16): Normal speed mode
Time A = 1024/ (fs x 8) : Double speed mode
Time A = 1024/ (fs x 4) : Quadruple speed mode
(4) No audible click noise occurs under normal conditions.
(5) The DZF pin is “L” in the power-down mode.
(6) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power
supply voltage achieves 80% of VDD. If not, click noise may occur at a different timing from this figure.
Figure 7. System reset diagram
MS0935-E-03
2010/09
- 13 -
[AK4424]
■ Reset Function
When the MCLK or LRCK stops, the AK4424 is placed in reset mode and its analog outputs are set to VSS (0V, typ).
When the MCLK and LRCK are restarted, the AK4424 returns to normal operation mode.
Internal
State
Normal Operation
Reset
D/A In
(Digital)
Normal Operation
(1)
GD
D/A Out
(Analog)
(3)
VSS
(2)
(3)
<Case1:MCLK Stop>
Clock In
(4) MCLK Stop
MCLK, BICK, LRCK
(6)
DZF
<Case2:LRCK Stop>
Clock In
(4) (5) LRCK Stop
MCLK, BICK, LRCK
(6)
DZF
Notes:
(1) Digital data can be stopped. The click noise after MCLK and LRCK are input again can be reduced by inputting
the “0” data during this period.
(2) The analog output corresponding to a specific digital input has group delay (GD).
(3) No audible click noise occurs under normal conditions.
(4) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
(5) The AK4424 detects the stop of LRCK if LRCK for more than 2048/fs. When LRCK is stopped, the AK4424 exits
reset mode after LRCK is input.
(6) The DZF pin is set to “L” in the reset mode.
Figure 8. Reset Timing Example
MS0935-E-03
2010/09
- 14 -
[AK4424]
SYSTEM DESIGN
Figure 9 shows the system connection diagram. An evaluation board (AKD4424) is available for fast evaluation as well
as suggestions for peripheral circuitry.
CN
VEE 16
2
CP
VSS2 15
3
DEM
Master Clock
4
MCLK
64fs
5
BICK
24bit Audio Data
6
SDTI
fs
7
LRCK
AOUTL 10
8
SMUTE
AOUTR
1u (1)
ModeSetting
Digital Ground
+
CVDD 14
DZF 13
AK4424
VSS1 12
VDD 11
9
Analog
5.0V
1u (1)
+
1
0.1u
+ 10u
10Ω
External Mute Circuits
0.1u
+ 10u
Lch Out
Rch Out
Analog Ground
Note:
Use low ESR (Equivalent Series Resistance) capacitors. When using polarized capacitors, the positive polarity pin
should be connected to the CP and VSS2 pin.
VSS1 and VSS2 should be separated from digital system ground.
Digital input pins should not be allowed to float.
Figure 9. Typical Connection Diagram
MS0935-E-03
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[AK4424]
1. Grounding and Power Supply Decoupling
VDD and CVDD are supplied from the analog supply and should be separated from the system digital supply. Decoupling
capacitors, especially 0.1μF ceramic capacitors for high frequency bypass, should be placed as near to VDD and CVDD
as possible. The differential voltage between VDD and VSS pins set the analog output range. The power-up sequence
between VDD and CVDD is not critical.
2. Analog Outputs
The analog outputs are single-ended and centered around the VSS (ground) voltage. The output signal range is typically
2.12Vrms (typ @VDD=5V). The internal switched-capacitor filter (SCF) and continuous-time filter (CTF) attenuate the
noise generated by the delta-sigma modulator beyond the audio passband. Using single a 1st-order LPF (Figure 10) can
reduce noise beyond the audio passband. Figure 11 shows example in the case of 10kΩ, 100kΩ terminus.
The output voltage is a positive full scale for 7FFFFFH (@24bit data) and a negative full scale for 800000H (@24bit
data). The ideal output is 0V (VSS) voltage for 000000H (@24bit data). The DC offset is ±60mV or less.
AK4424
470
Analog
Out
AOUT
2.2nF
2.12Vrms (typ)
(fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
Figure 10. External 1st order LPF Circuit Example1
AK4424
47μ
820
220
AOUT
47k
1000pF
Analog
Out
10kÆ1.92Vrms (typ)
100kÆ2.1Vrms (typ)
Figure 11. External 1st order LPF Circuit Example2
MS0935-E-03
2010/09
- 16 -
[AK4424]
PACKAGE
16pin TSSOP (Unit: mm)
1.1 (max)
*5.0±0.1
16
9
8
1
0.13
M
6.4±0.2
*4.4±0.1
A
0.65
0.22±0.1
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0935-E-03
2010/09
- 17 -
[AK4424]
MARKING
AKM
4424ET
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4424ET
Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD)
08/02/22
08/04/03
Revision
00
01
08/10/07
02
10/09/28
03
Reason
First Edition
Description
Addition
Description
Addition
Specification
Change
Page
Contents
2
AK4421 was added to “■ Main Difference Between
AK4420 and AK4424”.
■ De-emphasis Filter
“In case of double speed and quad speed mode, the
digital de-emphasis filter is always off.” was added.
PACKAGE
The package dimension was changed.
10
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[AK4424]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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