AKM AKD4426

[AK4426]
AK4426
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4426 is a 5V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4426 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4426 integrates a combination of switched-capacitor
and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit
word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio
applications, such as DVD, AV receiver system and set-top boxes. The AK4426 is offered in a space
saving 16pin TSSOP package.
FEATURES
† Sampling Rate Ranging from 8kHz to 192kHz
† 128 times Oversampling (Normal Speed Mode)
† 64 times Oversampling (Double Speed Mode)
† 32 times Oversampling (Quad Speed Mode)
† 24-Bit 8 times FIR Digital Filter
† Switched-Capacitor Filter with High Tolerance to Clock Jitter
† Single Ended 2Vrms Output Buffer
† Digital De-emphasis Filter: 32kHz, 44.1kHz or 48kHz
† Soft mute
† Digital Attenuator (Linear 256 Step)
† Control I/F: I2C-Bus
† Audio I/F format: 24Bit MSB justified, 24/20/16 LSB justified or
I2S compatible
† Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
† THD+N: -91dB
† Dynamic Range: 106dB
† Automatic Power-on Reset Circuit
† Power supply: +4.5 ∼ +5.5V
† Ta = -40 to 85 °C
† Small Package: 16pin TSSOP (6.4mm x 5.0mm)
MS1176-E-02
2011/03
-1-
[AK4426]
MCLK
AVDD
CAD0
SCL
SDA
Control
Interface
Clock
Divider
De-emphasis
Control
VSS2
LRCK
BICK
SDTI
Audio
Data
Interface
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
AOUTL
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
AOUTR
Charge
Pump
CP
CN
1μ
VEE
VSS1
VDD
1μ
Block Diagram
MS1176-E-02
2011/03
-2-
[AK4426]
■ Ordering Guide
AK4426VT
AKD4426
-40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4426
■ Pin Layout
VDD
1
16
VSS1
MCLK
2
15
CP
BICK
3
14
CN
SDTI
4
13
VEE
LRCK
5
12
AOUTL
CAD0
6
11
VSS2
SCL
7
10
AVDD
SDA
8
9
AOUTR
AK4426
Top
View
MS1176-E-02
2011/03
-3-
[AK4426]
PIN/FUNCTION
No.
1
Pin Name
VDD
I/O
-
Function
Digital Circuit and Charge Pump Circuit Power Supply Pin: 4.5V∼5.5V
Master Clock Input Pin
2
MCLK
I
An external TTL clock must be input on this pin.
3
Audio Serial Data Clock Pin
BICK
I
4
Audio Serial Data Input Pin
SDTI
I
5
L/R Clock Pin
LRCK
I
6
Chip Address 0bit
CAD0
I
7
Control Clock input Pin
SCL
I
8
Control Data Input/Output pin
SDA
I/O
Rch Analog Output Pin
9
AOUTR
O
When power down, outputs VSS(0V, typ).
10
Analog Block Power Supply Pin: 4.5V∼5.5V
AVDD
11
Ground Pin2
VSS2
Lch Analog Output Pin
12
AOUTL
O
When power down, outputs VSS(0V, typ).
Negative Voltage Output Pin
Connect to VSS1 with a 1.0μF capacitor which is low ESR (Equivalent
13
Series Resistance) over all temperature range. When this capacitor has the
VEE
O
polarity, the positive polarity pin must be connected to the VSS1 pin. Non
polarity capacitors can also be used.
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF capacitor which is low ESR (Equivalent Series
14
Resistance) over all temperature range. When this capacitor has the polarity,
CN
I
the positive polarity pin must be connected to the CP pin. Non polarity
capacitors can also be used.
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF capacitor which is low ESR (Equivalent Series
15
Resistance) over all temperature range. When this capacitor has the polarity,
CP
I
the positive polarity pin must be connected to the CP pin. Non polarity
capacitors can also be used.
16
Ground Pin1
VSS1
Note: All input pins except for the CN pin should not be left floating.
MS1176-E-02
2011/03
-4-
[AK4426]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V; Note 1)
Parameter
Power Supply
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
Storage Temperature
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 connect to the same analog ground.
Symbol
VDD
CVDD
IIN
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-40
-65
max
+6.0
+6.0
±10
VDD+0.3
85
150
Units
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
AVDD
min
+4.5
typ
+5.0
VDD
max
+5.5
Units
V
Note 3. AVDD should be equal to VDD
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1176-E-02
2011/03
-5-
[AK4426]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +5.0V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ)
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics (Note 4)
THD+N (0dBFS)
fs=44.1kHz, BW=20kHz
-91
-84
dB
fs=96kHz, BW=40kHz
-91
dB
fs=192kHz, BW=40kHz
-91
dB
Dynamic Range (-60dBFS with A-weighted. (Note 5)
100
106
dB
S/N (A-weighted. (Note 6)
100
106
dB
Interchannel Isolation (1kHz)
90
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
DC Accuracy
DC Offset
(at output pin)
-5
0
+5
mV
Gain Drift
100
ppm/°C
Output Voltage (Note 7)
2.05
2.2
2.35
Vrms
Load Capacitance (Note 8)
25
pF
Load Resistance
5
kΩ
Power Supplies
Power Supply Current: (Note 9)
24
36
mA
Normal Operation (fs≤96kHz)
27
40
mA
Normal Operation (fs=192kHz)
10
100
Power-Down Mode (Note 10)
μA
Note 4. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 5. 98dB for 16bit input data
Note 6. S/N does not depend on input data size.
Note 7. Full-scale voltage (0dB). Output voltage is proportional to the voltage of AVDD,
AOUT ([email protected]) = 2.2Vrms × AVDD/5.
Note 8. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load.
Note 9. The current into VDD and AVDD.
Note 10. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS1(VSS2) or VDD(AVDD).
MS1176-E-02
2011/03
-6-
[AK4426]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V; fs = 44.1 kHz; DEM = OFF; SLOW = “0”)
Parameter
Symbol
min
typ
max
Digital filter
PB
0
20.0
Passband
±0.05dB (Note 11)
22.05
–6.0dB
Stopband (Note 11)
SB
24.1
Passband Ripple
PR
± 0.02
Stopband Attenuation
SA
54
Group Delay (Note 12)
GD
19.3
Digital Filter + LPF
Frequency Response 20.0kHz fs=44.1kHz
FR
± 0.05
40.0kHz fs=96kHz
FR
± 0.05
80.0kHz fs=192kHz
FR
± 0.05
Note 11. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 12. Calculated delay time caused by digital filter. This time is measured from setting the 16/24bit data
of both channels to input register to the output of the analog signal.
Units
kHz
kHz
kHz
dB
dB
1/fs
dB
dB
dB
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD = AVDD = +4.5 ∼ +5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)
Parameter
Symbol
min
PB
0
39.2
typ
max
Units
18.2
8.1
-
Digital Filter
±0.04dB (Note 13)
-3.0dB
Stopband
(Note 13)
Passband Ripple
Stopband Attenuation
Group Delay
(Note 12)
Passband
19.3
-
kHz
kHz
kHz
dB
dB
1/fs
FR
+0/-5
20.0kHz fs=44.kHz
40.0kHz fs=96kHz
FR
+0/-4
fs=192kHz
80.0kHz
FR
+0/-5
Note 13. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.185×fs (@±0.04dB), SB=0.888×fs.
-
dB
dB
dB
SB
PR
SA
GD
± 0.005
72
-
Digital Filter + LPF
Frequency Response
MS1176-E-02
2011/03
-7-
[AK4426]
DC CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Symbol
VIH
VIL
Iin
min
2.2
-
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V)
Parameter
Symbol
min
Typ
fCLK
2.048
11.2896
Master Clock Frequency
dCLK
30
Duty Cycle
LRCK Frequency
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
32
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
Audio Interface Timing
BICK Period
tBCK
1/128f
Normal Speed Mode
tBCK
sn
Double Speed Mode
tBCK
1/64fs
Quad Speed Mode
tBCKL
d
BICK Pulse Width Low
tBCKH
1/64fs
Pulse Width High
tBLR
q
BICK “↑” to LRCK Edge (Note 14)
tLRB
30
LRCK Edge to BICK “↑” (Note 14)
tSDH
30
SDTI Hold Time
tSDS
20
SDTI Setup Time
20
20
20
Control Interface Timing (I2C Bus) (Note 15)
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 16)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise
tSP
0
Suppressed by Input Filter
Capacitive load on bus
Cb
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. I2C-bus is a trademark of NXP B.V.
Note 16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS1176-E-02
typ
-
max
0.8
± 10
Units
V
V
μA
max
36.864
70
Units
MHz
%
48
96
192
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
400
-
kHz
μs
μs
0.3
0.3
50
μs
μs
μs
μs
μs
μs
μs
μs
ns
400
pF
2011/03
-8-
[AK4426]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 1. Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Figure 2. Serial Interface Timing
MS1176-E-02
2011/03
-9-
[AK4426]
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 3. I2C Bus mode Timing
MS1176-E-02
2011/03
- 10 -
[AK4426]
OPERATION OVERVIEW
■ System Clock
The external clocks required to operate the AK4426 are MCLK, LRCK and BICK. The master clock (MCLK) should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register
00H), the sampling speed is set by DFS0/1 (Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2) When the power applied, the AK4426 is in Auto Setting Mode. In Auto Setting Mode (ACKS =
“1”: Default), as MCLK frequency is detected automatically (Table 3) and the internal master clock becomes the
appropriate frequency (Table 4), it is not necessary to set DFS0/1.
The AK4426 is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal operation
mode, and the analog output is forced to 0V(typ). When MCLK, LRCK and BICK are input again, the AK4426 is
powered up. After power-up, the AK4426 is in the power-down mode until MCLK, LRCK and BICK are input.
DFS1
0
0
1
DFS1
DFS0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
Sampling
Speed
Normal
Double
Quad
DFS0
Sampling Rate (fs)
0
Normal Speed Mode
8kHz~48kHz
1
Double Speed Mode
60kHz~96kHz
0
Quad Speed Mode
120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
(kHz)
fs
32.0
44.1
48.0
88.2
96.0
176.4
192.0
(default)
MCLK (MHz)
128fs
11.2896
12.2880
22.5792
24.5760
192fs
16.9344
18.4320
33.8688
36.8640
256fs
8.1920
11.2896
12.2880
22.5792
24.5760
-
384fs
12.2880
16.9344
18.4320
33.8688
36.8640
-
512fs
16.3840
22.5792
24.5760
-
768fs
24.5760
33.8688
36.8640
-
1152fs
36.8640
-
BICK
(MHz)
64fs
2.0480
2.8224
3.0720
5.6448
6.1440
11.2896
12.2880
Table 2. System Clock Example (Manual Setting Mode)
MCLK
Sampling Speed
1152fs
Normal (fs=32kHz only)
512fs
768fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 3. Sampling Speed(Auto Setting Mode: Default)
MS1176-E-02
2011/03
- 11 -
[AK4426]
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
-
22.5792
24.5760
MCLK (MHz)
256fs
384fs
512fs
768fs
16.3840
24.5760
22.5792
33.8688
24.5760
36.8640
8.192
12.288
11.2896
16.9344
12.288
18.432
22.5792
33.8688
24.5760
36.8640
33.8688
36.8640
Table 4. System Clock Example (Auto Setting Mode)
192fs
-
1152fs
36.8640
-
Sampling
Speed
Normal
Double
-
Quad
When MCLK= 256fs/384fs, the AK4425 supports sampling rate of 32kHz~96kHz in auto setting mode (Table 4). But,
when the sampling rate is 32kHz~48kHz, DR and S/N will degrade as compared to when MCLK= 512fs/768fs.
MCLK
256fs/384fs
512fs/768fs
DR,S/N
103dB
106dB
Table 5. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz) (Auto Setting Mode)
■ Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The DIF2-0 bit can select within five
serial data modes as shown in Table 6. In all modes the serial data is MSB-first, two’s complement format and it is latched
on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1 DIF0
SDTI Format
BICK
0
0
16bit LSB Justified
≥32fs
0
1
20bit LSB Justified
≥40fs
1
0
24bit MSB Justified
≥48fs
2
1
1
24bit I S Compatible
≥48fs
0
0
24bit LSB Justified
≥48fs
Table 6. Audio Data Format in Serial control mode
MS1176-E-02
Figure
Figure 4
Figure 5
Figure 6
Figure 7
Figure 5
(default)
2011/03
- 12 -
[AK4426]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
14
6
5
1
0
4
14
3
15
2
16
1
17
0
31
15
14
0
6
5
4
14
1
15
3
2
16
1
17
0
31
15
14
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
0
Don’t care
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
0
1
0
1
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 1/4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Mode 2 Timing
MS1176-E-02
2011/03
- 13 -
[AK4426]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 7. Mode 3 Timing
MS1176-E-02
2011/03
- 14 -
[AK4426]
■ De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled
with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always OFF.
DEM1
DEM0
Mode
0
0
44.1kHz
(default)
0
1
OFF
1
0
48kHz
1
1
32kHz
Table 7. De-emphasis Filter Control (Normal Speed Mode)
■ Analog Output Block
The internal negative power supply generation circuit (Figure 8) provides a negative power supply for the internal 2Vrms
amplifier. It allows the AK4426 to output an audio signal centered at VSS (0V, typ) as shown in Figure 9. The negative
power generation circuit (Figure 8) needs 1.0uF low ESR (Equivalent Series Resistance) capacitors (Ca, Cb). If this
capacitor is polarized, the positive polarity pin should be connected to the CP and VSS1 pins. This circuit operates by
clocks generated from MCLK. When MCLK stops, the AK4426 is placed in the reset mode automatically and the analog
outputs settle to VSS (0V, typ).
AK4426
VDD
Charge
Pump
CP
Negative Power
CN
VSS1
(+)
1uF
Ca
VEE
Cb
1uF
(+)
Figure 8. Negative Power Generation Circuit
AK4426
2.2Vrms
0V
AOUTR
(AOUTL)
Figure 9. Audio Signal Output
MS1176-E-02
2011/03
- 15 -
[AK4426]
■ Output Volume
The AK4426 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition
time of 1 level and all 256 levels is shown in Table 8.
Transition Time
1 Level
255 to 0
Normal Speed Mode
4LRCK
1020LRCK
Double Speed Mode
8LRCK
2040LRCK
Quad Speed Mode
16LRCK
4080LRCK
Table 8. ATT Transition Time
Sampling Speed
■ Soft Mute Operation
Soft mute operation is performed in digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
-∞ during ATT_DATA×ATT transition time (Table 8) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued and returned to ATT
level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE bit
ATT Level
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
Notes:
(1) ATT_DATA×ATT transition time (Table 8). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued and returned to ATT level by
the same cycle.
Figure 10. Soft Mute function
MS1176-E-02
2011/03
- 16 -
[AK4426]
■ System Reset
The AK4426 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up.
The AK4426 is in power-down mode until LRCK are input.
tW<20ms
Power Supply 0.8xVDD
(VDD, AVDD)
0.3V
(1)
Low
MCLK
20 µs
Reset Release
(3)
Internal
Reset
Reset
Audio circuit
50ms(max)
)(2)
Power-up
2, 3
LRCK Clocks
(4)
Charge Pump
Circuit
Power-up
Power down
Time A
VEE Pin
0V
D/A In
(5)
“0” data
(Digital)
0V
D/A Out
(Analog)
Active (D/A Out)
MUTE (D/A Out)
Notes:
(1) The AK4426 includes an internal Power on Reset Circuit which is used to reset the digital logic into a default state
after power up. Therefore, the power supply voltage must reach 80% VDD from 0.3V in less than 20msec.
(2) Register writings are valid after 50ms (max).
(3) When internal reset is made, approximately 20us after a MCLK input, the internal analog circuit is powered-up.
(4) The digital circuit and charge pump circuit are powered-up in 2, 3 LRCK cycle when the analog circuit is powered-up.
(5) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A = 1024/(fs x 16): Normal speed mode
Time A = 1024/(fs x 8): Double speed mode
Time A = 1024/(fs x 4): Quad speed mode
Figure 11. System Reset Diagram
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[AK4426]
■ Reset Function
When the MCLK, LRCK or BICK stops, the AK4426 is placed in reset mode and its analog outputs are set to VSS (0V,
typ). When the MCLK, LRCK and BICK are restarted, the AK4426 returns to normal operation mode.
Clock In
(1)
MCLK, BICK, LRCK
MCLK or BIC K or LRCK
Stop
Internal
State
Normal Operation
Reset
D/A In
(Digital)
Normal Operation
(2)
GD
D/A Out
(Analog)
(4)
VSS
(3)
(4)
Notes:
(1) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
(2) Digital data can be stopped. The click noise after MCLK and LRCK are input again can be reduced by inputting
the “0” data during this period.
(3) The analog output corresponding to a specific digital input has group delay (GD).
(4) No audible click noise occurs under normal conditions.
Figure 12. Reset Timing Example
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[AK4426]
■ Mode Control Interface
I2C-bus Control Mode
1. WRITE Operations
Figure 13 shows the data transfer sequence in I2C-bus mode. All commands are preceded by START condition. A HIGH
to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 17). After the START
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit which is a data direction bit (R/W).
The most significant six bits of the slave address are fixed as “001000”. The next bit is CAD0 (device address bit). This
bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets this device address bit (Figure 14).
If the slave address match that of the AK4426 and R/W bit is “0”, the AK4426 generates an acknowledge and the write
operation is executed. If R/W bit is “1”, the AK4426 does not answer any acknowledge (Figure 17). The second byte
consists of the address for control registers of the AK4426. The format is MSB first, and those most significant 6-bits are
fixed to zeros (Figure 15). The data after the second byte contain control data. The format is MSB first, 8bits (Figure 16).
The AK4426 generates an acknowledge after each byte is received. A data transfer is always terminated by STOP
condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP
condition (Figure 17).
The AK4426 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4426
generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 04H prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 19) except for the START and the STOP
condition.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Sub
Address(n)
Slave
Address
A
C
K
Data(n+1)
Data(n)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 13. Data Transfer Sequence at I2C-bus Mode
0
0
1
0
0
0
CAD0
R/W
Figure 14. The First Byte (The CAD0 should match with CAD0 pin)
0
0
0
0
0
0
A1
A0
D2
D1
D0
Figure 15. The Second Byte
D7
D6
D5
D4
D3
Figure 16. Byte Structure After The Second Byte
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[AK4426]
SDA
SCL
S
P
start condition
stop condition
Figure 17. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 18. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 19. Bit Transfer on the I2C-bus
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[AK4426]
■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
01H
02H
03H
04H
Notes:
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
ACKS
0
RRST
ATT7
ATT7
0
0
0
ATT6
ATT6
0
SLOW
0
ATT5
ATT5
DIF2
DFS1
INVL
ATT4
ATT4
DIF1
DFS0
INVR
ATT3
ATT3
DIF0
DEM1
0
ATT2
ATT2
PW
DEM0
0
ATT1
ATT1
RSTN
SMUTE
0
ATT0
ATT0
Do not write any data to the register over 05H directly.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
Do not write the registers within 50msec after the power supplies are fed.
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[AK4426]
■ Register Definitions
Addr
00H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 1
ACKS
0
0
DIF2
DIF1
DIF0
PW
RSTN
default
1
0
0
0
1
0
1
1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
The click noise, which occurs when MCLK frequency or DFS is changed, can be reduced by RSTN
bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (Table 6)
Default: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the settings of DFS1-0
are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr
01H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 2
0
0
SLOW
DFS1
DFS0
DEM1
DEM0
SMUTE
default
0
0
0
0
0
0
1
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft muted
DEM1-0: De-emphasis Response (Table 7)
Default: “01”, OFF
DFS1-0: Sampling speed control
00: Normal Speed Mode
01: Double Speed Mode
10: Quad Speed Mode
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise
occurs.
SLOW: Slow Roll-off Filter Enable
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
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[AK4426]
Addr
02H
D7
D6
D5
D4
D3
D2
D1
D0
Control 3
Register Name
RRST
0
0
INVL
INVR
0
0
0
default
0
0
0
0
0
0
0
0
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
INVR: Inverting Lch Output Polarity
0: Normal Output
1: Inverted Output
INVL: Inverting Rch Output Polarity
0: Normal Output
1: Inverted Output
RRST: Register Reset
0: Normal Operation
1: Register Reset (except RRST bit)
Addr
03H
04H
Register Name
Lch ATT
Rch ATT
default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
ATT = 20 log10 (ATT_DATA / 255) [dB]
00H: Mute
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[AK4426]
SYSTEM DESIGN
Figure 20 shows the system connection diagram. An evaluation board (AKD4426) is available for fast evaluation as well
as suggestions for peripheral circuitry.
Analog
5.0V
0.1u
+
10u
VDD
Master Clock
2
MCLK
CP 15
+
VSS1 16
1
+
64fs
3
BICK
CN 14
1u (1)
1u (1)
24bit Audio Data
4
SDTI
VEE 13
fs
5
LRCK
6
CAD0
VSS2 11
7
SCL
AVDD 10
8
SDA
μP
Digital Ground
AK4426 AOUTL
AOUTR
12
Lch Out
0.1u
+ 10u
9
Rch Out
Analog Ground
Note:
Use low ESR (Equivalent Series Resistance) capacitors. When using polarized capacitors, the positive polarity pin
should be connected to the CP and VSS2 pin.
VSS1 and VSS2 should be separated from digital system ground.
Digital input pins should not be allowed to float.
Figure 20. Typical Connection Diagram
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[AK4426]
1. Grounding and Power Supply Decoupling
VDD and AVDD are supplied from the analog supply and should be separated from the system digital supply.
Decoupling capacitors, especially 0.1μF ceramic capacitors for high frequency bypass, should be placed as near to VDD
and AVDD as possible. The VSS1 and VSS2 must be connected to the same analog ground plane. Power-up sequence
between VDD and AVDD is not critical.
2. Analog Outputs
The analog outputs are single-ended and centered around the VSS (ground) voltage. The output signal range is typically
2.2Vrms (typ @VDD=5V). The internal switched-capacitor filter (SCF) and continuous-time filter (CTF) attenuate the
noise generated by the delta-sigma modulator beyond the audio passband. Using single a 1st-order LPF (Figure 21) can
reduce noise beyond the audio passband.
AK4426
470
Analog
Out
AOUT
2.2Vrms (typ)
2.2nF
(fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
Figure 21. External 1st order LPF Circuit Example1
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[AK4426]
PACKAGE
16pin TSSOP (Unit: mm)
1.1 (max)
*5.0±0.1
16
9
8
1
0.13
M
6.4±0.2
*4.4±0.1
A
0.65
0.22±0.1
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy, Halogen (bromine and chlorine) free
Cu
Solder (Pb free) plate
MS1176-E-02
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[AK4426]
MARKING
AKM
4426VT
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4426VT
Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD)
10/06/07
10/07/22
Revision
00
01
Reason
First Edition
Error Correction
Page
Contents
19-20
11/03/01
02
Error Correction
25
■ Mode Control Interface
The description was corrected.
1. Grounding and Power Supply Decoupling
The description was changed.
MS1176-E-02
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[AK4426]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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