AKM AKD4621-B

[AKD4621-B]
AKD4621-B
AK4621 Evaluation board Rev.2
GENERAL DESCRIPTION
The AKD4621-B is an evaluation board for the AK4621, the 24Bit A/D & D/A converter. The AKD4621-B
can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D→D/A). The
AKD4621-B also has the digital audio interface and can achieve the interface with digital audio systems
via opt-connector.
„ Ordering guide
AKD4621-B
---
Evaluation board for AK4621
(Cable for connecting with printer port of IBM-AT compatible PC
and control software are packed with this. This control software
does not operate on Windows NT.)
FUNCTION
† Digital interface
- DIT (AK4114): optical or BNC
- DIR (AK4114): optical or BNC
† 10pin header for serial control interface
-15V +15V
Regulator
AGND DGND
BNC
LIN
R IN
Input
Buffer
AK4114
(DIR&DIT)
AK4621
Opt In
Opt Out
BNC
LOUT
ROUT
Output
Buffer
10pin Header
Control Data
Figure 1. AKD4621-B Block Diagram
* Circuit diagram are attached at the end of this manual.
<KM100802>
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[AKD4621-B]
Evaluation Board Manual
„ Operation sequence
1) Set up of the power supply lines
Each of the power supply lines should be distributed from the power supply units.
Name
of jack
+15V
Color
of jack
Green
Typ
Voltage
+15V
-15V
Blue
-15V
GND
Black
0V
Using
Default setting
Connect to +15V
Power supply for the plus terminal of OPAmp
(Must be connected)
Power supply for the regulator: T1: +15V→+5V
(Power supply for AVDD and VREF of AK4621,
power supply for Bias of OPAmp, and
power supply for the Regulator: T2: +5V→+3.3V
(Power supply for DVDD and TVDD of AK4621))
Power supply for the regulator: T3: +15V→+3.3V
(Power supply for AVDD, DVDD, TVDD of AK4114,
Power supply for logic)
Power supply for the minus terminal of OPAmp
Connect to -15V
(Must be connected)
Analog ground
Connect to GND
Digital ground
(Must be connected)
Table 1. Set up of the power supply lines
2) Set up the evaluation modes, jumper pins and DIP switch. (See the followings.)
3) Power on
The AK4621 should be reset once bringing SW2 (PDN) “L” upon power-up.
<KM100802>
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[AKD4621-B]
„ Evaluation modes
Applicable evaluation modes
(1) Evaluation of A/D-D/A Loop back (Default)
(2) Evaluation of DAC
(3) Evaluation of ADC
1) Evaluation of A/D-D/A Loop back (Default)
1-1) Sampling speed & MCLK frequency
a) Parallel mode (Default)
SW1-1
(P/S)
ON
ON
Sampling
MCLK
Speed of
Frequency of
AK4621
AK4621
Normal
OFF
OFF
ON
ON
OFF
512fs
Speed
Double
256fs
ON
OFF
ON
OFF
OFF
Speed
Table 2. Sampling Speed & Master clock Frequency in parallel mode
SW1-4
(DFS0)
SW1-6
(CKS1)
SW1-7
(CKS0)
SW3-4
(OCKS1)
SW3-5
(OCKS0)
(Default)
* Parallel mode does not support quad speed mode.
b) Serial mode
SW1
(P/S)
DFS1
bit
DFS0
bit
OFF
0
0
OFF
0
1
OFF
1
0
Sampling
Speed of
AK4621
Normal
0
0
1
ON
OFF
Speed
Double
0
0
1
OFF
OFF
Speed
0
0
1
ON
ON
Quad Speed
Table 3. Sampling Speed & Master clock Frequency in serial mode
CMODE
bit
CKS1
bit
CKS0
bit
SW3-4
(OCKS1)
SW3-5
(OCKS0)
MCLK
Frequency of
AK4621
512fs
256fs
128fs
* In serial mode, SW1-4 (DFS0), SW1-6 (CKS1) and SW1-7 (CSK0) should be always “OFF”, and DFS1, DFS0, CKS1,
CKS0 and CMODE bits in the AK4621 should be set via the printer port (PORT3).
<KM100802>
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[AKD4621-B]
1-2) AK4114’s master clock mode & reference X’tal frequency
Mode
1
SW3-6
(CM1)
OFF
SW3-7
PLL
X'tal
Clock source
(CM0)
ON
OFF
ON
X'tal
Table 4. AK4114’S Clock Operation Mode
SW3-1
(XTL1)
ON
SDTO
DAUX
(Default)
SW3-2
X’tal Frequency
(XTL0)
OFF
24.576MHz
(Default)
Table 5. Reference X’tal frequency
1-3) Set up the digital filter
a) Parallel mode (Default)
SW1-2
Digital Filter
(SDFIL)
OFF
Short Delay
ON
Sharp Roll-off
(Default)
Table 6. Digital Filter Selection in parallel mode
b) Serial mode
SW1-2
SDAD
Digital Filter
(SDFIL)
bit
OFF
0
Sharp Roll-off
OFF
1
Short Delay
Table 7. Digital Filter Selection in serial mode
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[AKD4621-B]
2) Evaluation of D/A using DIR. (Optical link)
The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical
connector (PORT1). PORT1 is also used for the evaluation using such as CD test disk.
BNC connector is recommended for an evaluation of the Sound quality.
2-1) DIR input interface (Default: JP2 (RX3)="OPT")
JP2
(RX3)
OPT (Default) or BNC
Jumper
Normal Speed & Double Speed
Quad Speed
Table 8. DIR Input Interface
BNC
2-2) Sampling speed & MCLK frequency
a) Parallel mode (Default)
SW1-1
(P/S)
ON
ON
ON
Sampling
MCLK
Speed of
Frequency of
AK4621
AK4621
Normal
OFF
OFF
OFF
OFF
OFF
256fs
Speed
Normal
OFF
OFF
ON
ON
OFF
512fs
Speed
Double
ON
OFF
ON
OFF
OFF
256fs
Speed
Table 9. Sampling Speed & Master clock Frequency in parallel mode
SW1-4
(DFS0)
SW1-6
(CKS1)
SW1-7
(CKS0)
SW3-4
(OCKS1)
SW3-5
(OCKS0)
(Default)
* Parallel mode does not support quad speed mode.
b) Serial mode
SW1-1
(P/S)
DFS1
bit
OFF
0
OFF
0
OFF
0
OFF
1
Sampling
Speed of
AK4621
Normal
0
0
0
0
OFF
OFF
Speed
Normal
0
0
0
1
ON
OFF
Speed
Double
1
0
0
1
OFF
OFF
Speed
0
0
0
1
ON
ON
Quad Speed
Table 10. Sampling Speed & Master clock Frequency in serial mode
DFS0
bit
CMODE
bit
CKS1
bit
CKS0
bit
SW3-4
(OCKS1)
SW3-5
(OCKS0)
MCLK
Frequency of
AK4621
256fs
512fs
256fs
128fs
* In serial mode, SW1-4 (DFS0), SW1-6 (CKS1) and SW1-7 (CSK0) should be always “OFF”, and DFS1, DFS0, CKS1,
CKS0 and CMODE bits in the AK4621 should be set via the printer port (PORT3).
<KM100802>
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[AKD4621-B]
2-3) AK4114’s master clock mode & reference X’tal frequency
SW3-6
(CM1)
OFF
Mode
0
SW3-7
PLL
X'tal
Clock source
(CM0)
OFF
ON
OFF
PLL
Table 11. Clock Operation Mode
SDTO
RX
SW3-1
SW3-2
X’tal Frequency
(XTL1)
(XTL0)
ON
ON
OFF
Table 12. Reference X’tal frequency
2-4) Set up the digital filter
a) Parallel mode (Default)
SW1-2
Digital Filter
(SDFIL)
OFF
Minimum Delay
ON
Sharp Roll-off
Table 13. Digital Filter Selection in parallel mode
b) Serial mode
Set up the register of the AK4621 via the pint port (PORT3).
SW1-2
(SDFIL)
OFF
OFF
OFF
SDAD SLOW
Digital Filter
bit
bit
0
0
Sharp Roll-off
0
1
Slow Roll-off
1
0
Minimum Delay
Table 14. Digital Filter Selection in serial mode
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[AKD4621-B]
3) Evaluation of A/D using DIT. (Optical link)
DIT generates audio bi-phase signal from received data and which is output through optical connector (PORT2).
It is possible to connect AKM’s D/A converter evaluation boards on the digital-amplifier which equips DIR
input.
3-1) DIT output interface (Default: JP7 (TX) ="OPT")
Jumper
Normal Speed & Double Speed
JP7
(TX)
OPT (Default) or BNC
BNC
Quad Speed
Table 15. DIT Output Interface
3-2) Sampling speed & MCLK frequency
a) Parallel mode (Default)
SW1-1
(P/S)
ON
ON
ON
Sampling
MCLK
Speed of
Frequency of
AK4621
AK4621
Normal
OFF
OFF
OFF
OFF
OFF
256fs
Speed
Normal
OFF
OFF
ON
ON
OFF
512fs
Speed
Double
256fs
ON
OFF
ON
OFF
OFF
Speed
Table 16. Sampling Speed & Master clock Frequency in parallel mode
SW1-4
(DFS0)
SW1-6
(CKS1)
SW1-7
(CKS0)
SW3-4
(OCKS1)
SW3-5
(OCKS0)
(Default)
* Parallel mode does not support quad speed mode.
<KM100802>
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[AKD4621-B]
b) Serial mode
SW1-1
(P/S)
DFS1
bit
OFF
0
OFF
0
OFF
0
OFF
1
Sampling
Speed of
AK4621
Normal
0
0
0
0
OFF
OFF
Speed
Normal
0
0
0
1
ON
OFF
Speed
Double
1
0
0
1
OFF
OFF
Speed
0
0
0
1
ON
ON
Quad Speed
Table 17. Sampling Speed & Master clock Frequency in serial mode
DFS0
bit
CMODE
bit
CKS1
bit
CKS0
bit
SW3-4
(OCKS1)
SW3-5
(OCKS0)
MCLK
Frequency of
AK4621
256fs
512fs
256fs
128fs
* In serial mode, SW1-4 (DFS0), SW1-6 (CKS1) and S1-7 (CSK0) should be always “OFF”, and DFS1, DFS0, CKS1,
CKS0 and CMODE bits in the AK4621 should be set via the printer port (PORT3).
3-3) AK4114’s master clock mode & reference X’tal frequency
3-3-1) PLL is used as clock source
Synchronized signal should be set via PORT1 (optical) or J6 (BNC).
Mode
0
SW3-6
(CM1)
OFF
SW3-7
PLL
X'tal
Clock source
(CM0)
OFF
ON
OFF
PLL
Table 18. Clock Operation Mode (PLL)
SDTO
RX
SW3-1
SW3-2
X’tal Frequency
(XTL1)
(XTL0)
ON
ON
OFF
Table 19. Reference X’tal frequency (PLL)
3-3-2) X’tal is used as clock source (Default)
Mode
1
SW3-6
(CM1)
OFF
SW3-7
PLL
X'tal
Clock source
(CM0)
ON
OFF
ON
X’tal
Table 20. Clock Operation Mode (X’tal)
SDTO
DAUX
(Default)
SW3-1
SW3-2
X’tal Frequency
(XTL1)
(XTL0)
ON
OFF
24.576MHz
(Default)
Table 21. Reference X’tal frequency (X’tal)
<KM100802>
2010/12
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[AKD4621-B]
3-4) Set up the digital filter
a) Parallel mode (Default)
SW1-2
Digital Filter
(SDFIL)
OFF
Short Delay
ON
Sharp Roll-off
(Default)
Table 22. Digital Filter Selection in parallel mode
b) Serial mode
SW1-2
SDAD
Digital Filter
(SDFIL)
bit
OFF
0
Sharp Roll-off
OFF
1
Short Delay
Table 23. Digital Filter Selection in serial mode
<KM100802>
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[AKD4621-B]
„ Set up of DIP Switch: SW1, SW3
1) Set-up of SW1 (Mode set-up of AK4621)
1-1) Audio data format in parallel mode
Mode
2
3
DIF
(SW1-5)
OFF
ON
SDTO
SDTI
LRCK
24bit MSB Justified
H/L
24bit MSB Justified
2
2
I S Compatible
L/H
I S Compatible
Table 24. Audio data format (Parallel mode)
BICK
≥48fs
≥48fs
(Default)
1-2) De-emphasis control in parallel mode
DEM0 pin
MODE
(SW1-3)
OFF
ON (44.1KHz)
ON
OFF
(Default)
Table 25. De-emphasis control (Parallel mode)
1-3) Parallel mode/ serial mode
P/S pin
MODE
(SW1-1)
OFF
Serial
ON
Parallel
(Default)
Table 26. Set up P/S pin
2) Set-up of SW3 (AK4114’s mode set-up)
2-1) Audio data format
Mode
4
5
DIF0
(SW3-3)
OFF
ON
SDTO
SDTI
24bit MSB Justified
24bit MSB Justified
I2S Compatible
I2S Compatible
Table 27. Audio data format
LRCK
BICK
H/L
L/H
≥48fs
≥48fs
(Default)
* DIF1=L and DIF2=H are fixed in AKD4621-B evaluation board.
„ Other Jumper pin set up
JP3, JP4, JP5, JP6: Input mode selection of A/D converter.
DIFF: Analog differential input mode. <Default>
SINGLE: Analog single-end mode can not be selected on this board.
JP2, JP7: The interface selection of digital input and output.
OPT: Select the optical connector.
BNC: Select the BNC connector. <Default>
<KM100802>
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[AKD4621-B]
„ Toggle Switch: SW2
[SW2]: Resets the AK4621 and the AK4114. Keep “H” during normal operation.
However, “L” must be input once after power supply is done.
„ Serial control mode
The AK4621 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3
(CR-I/F) with PC by 10-wire flat cable packed with the AKD4621-B.
Take care of the direction of connector. There is a mark at pin#1.
Connect
PC
10 wire
flat cable
10pin
Connector
CSN
CCLK
CDTI AKD4621-B
CDTO
10pin Header
Figure 2. Connect of 10 wire flat cable
<KM100802>
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[AKD4621-B]
„ Analog Input Buffer Circuit
The AK4621 can accept input voltages from AGND to AVDD. The input signal range scales with the VREF voltage and
is nominally 2.82Vpp (VREF = 5V). Figure 3 shows an input buffer circuit example. This is a fully differential input
buffer circuit with an inverted amplifier (fc=370KHz,gain: −10dB).
The capacitor of 10nF between AINL+/− (AINR+/−) decreases the clock feed through noise of the modulator, and
composes a 1st order LPF (fc=360kHz) with a 22Ω resistor before the capacitor.
910
4.7k
4.7k
470p
VP+
Analog In
47μ
3k
22
2.82Vpp
AIN+
VP9.3Vpp
Bias
NJM5532
910
AVDD
10k
47μ
22
AIN-
0.1μ 10μ
Bias
10k
3k
AK4621
10n
470p
AVDD = 5V
VP+ = 15V
VP- = -15V
Bias
2.82Vpp
Figure 3. Input buffer circuit in differential input mode
<KM100802>
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[AKD4621-B]
„ Analog Output Buffer Circuit
The differential output circuit (2nd order LPF,fc=182KHz,Q=0.637,G=+3.9dB) and LPF(1st order LPF, fc=284KHz,
G=-0.84dB) is implemented on board. The differential outputs of AK4621 is buffered by non-inverted circuit and output
via Cannon connector (differential output). LPF adds differential outputs. NJM5534D is used for op-amp on this board
that has low noise and high voltage torelance characteristics. Analog signal is output via BNC connectors on the board.
The output level is about 2.8Vrms ([email protected]=5.0V) by BNC.
+15
3.3n
+
AOUTL- +
10k
330
180
7
3
2 +
4
3.9n
-15
10u
0.1u
6
NJM5534D
+
10u
620
620
3.3n
+
100u
+
330
3
+
2 -
3.9n
2 - 4
+
3
7
Lch
1.0n NJM5534D
10u
6
4
680
100
6
0.1u
7
NJM5534D
1.2k
10k
AOUTL+
180
+10u
1.0n
1.2k
680
0.1u
560
0.1u
560
100u
+
0.1u
10u
+
10u
0.1u
Figure 4. Output buffer circuit
* AKM assumes no responsibility for the trouble when using the above circuit examples.
<KM100802>
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[AKD4621-B]
Control Soft Manual
■ Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect the evaluation board to an IBM PC/AT compatible PC by a 10wire flat cable. Be aware of the direction of
the 10pin header. When running this control soft on the Windows 2000/XP, the driver which is included in the CD
must be installed. Refer to the “Driver Control Install Manual for AKM Device Control Software” for installing the
driver. When running this control soft on the windows 95/98/ME, driver installing is not necessary. This control soft
does not support the Windows NT.
3. Proceed evaluation by following the process below.
■ Operation Screen
1. Start up the control program following the process above.
The operation screen is shown below.
Figure 5. Window of [ FUNCTION]
<KM100802>
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[AKD4621-B]
■ Operation Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching
tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting.
1. [Port Reset]: For when connecting to USB I/F board (AKDUSBIF-A)
Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-A).
2. [Write Default]: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executing write commands for all registers displayed.
4. [Save]: Saving current register settings to a file.
5. [Load]: Executing data write from a saved file.
6. [Data R/W]: “Data R/W” dialog box is popped up.
■ Tab Functions
[Data R/W]
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Figure 6. Window of [ Data R/W ]
Address Box : Input data address in hexadecimal numbers for data writing.
Data Box
: Input data in hexadecimal numbers.
Mask Box
: Input mask data in hexadecimal numbers.
This is “AND” processed input data.
[Write] : Writing to the address specified by “Address” box.
[Close] : Closing the dialog box and finish the process.
Data writing can be cancelled by this button instead of [Write] button.
*The register map will be updated after executing [Write] or [Read] commands.
<KM100802>
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[AKD4621-B]
[REG]: Register Map
This tab is for a register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Grayout registers are Read Only registers. They can not be controlled.
The registers which is not defined in the datasheet are indicated as “---”.
Figure 7. Window of [ REG]
<KM100802>
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[AKD4621-B]
[Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.
Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting.
Figure 8. Window of [ Register Set ]
<KM100802>
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[AKD4621-B]
[Tool]: Testing Tools
This tab screen is for evaluation testing tool.
Click buttons for each testing tool.
Figure 9. Window of [ Tool]
<KM100802>
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[AKD4621-B]
[Repeat Test]: Repeat Test Dialog
Click [Repeat Test] button to open repeat test setting dialog box.
Figure 10. Window of [ Repeat Test]
<KM100802>
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[AKD4621-B]
[Loop Setting]: Loop Setting Dialog
Click [Loop Setting] button to open loop setting dialog box.
Figure 11. Window of [ Loop]
<KM100802>
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[AKD4621-B]
Measurement Results
[Measurement condition]
• Measurement unit
• MCLK
• BICK
• fs
• Bit
• Power Supply
• Interface
• Temperature
: Audio Precision System two Cascade (AP2)
: 512fs (fs = 48kHz), 256fs (fs = 96kHz), 128fs (fs = 192kHz)
: 64fs
: 48kHz, 96kHz, 192kHz
: 24bit
: AVDD=5V, DVDD=TVDD=3.3V
: DIT or DIR
: Room
1. ADC (Differencial)
fs=48kHz
Parameter
Input signal
Measurement filter
S/(N+D)
S/(N+D)
DR
S/N
1kHz, -1dB
1kHz, -60dB
1kHz, -60dB
“0” data
20kHzLPF
20kHzLPF
20kHzLPF, A-weighted
20kHzLPF, A-weighted
Parameter
Input signal
Measurement filter
S/(N+D)
S(N+D)
DR
S/N
1kHz, -1dB
1kHz, -60dB
1kHz, -60dB
“0” data
40kHzLPF
40kHzLPF
40kHzLPF, A-weighted
40kHzLPF, A-weighted
Parameter
Input signal
Measurement filter
S/(N+D)
S(N+D)
DR
S/N
1kHz, -1dB
1kHz, -60dB
1kHz, -60dB
“0” data
40kHzLPF
40kHzLPF
40kHzLPF, A-weighted
40kHzLPF, A-weighted
Results
L ch
R ch
104.0
53.7
116.1
116.1
104.0
53.8
116.1
116.1
fs=96kHz
Results
L ch
R ch
102.8
49.5
115.1
115.2
102.8
49.6
115.2
115.4
fs=192kHz
<KM100802>
Results
L ch
R ch
102.7
49.9
115.3
115.5
102.8
50.1
115.6
115.6
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[AKD4621-B]
2. DAC
fs=48kHz
Parameter
Input signal
Measurement filter
S/(N+D)
S/(N+D)
DR
S/N
1kHz, -1dB
1kHz, -60dB
1kHz, -60dB
“0” data
20kHzLPF
20kHzLPF
22kHzLPF, A-weighted
22kHzLPF, A-weighted
Parameter
Input signal
Measurement filter
S/(N+D)
S/(N+D)
DR
S/N
1kHz, -1dB
1kHz, -60dB
1kHz, -60dB
“0” data
40kLPF
40kLPF
40kHzLPF, A-weighted
40kHzLPF, A-weighted
Parameter
Input signal
Measurement filter
S/(N+D)
S/(N+D)
DR
S/N
1kHz, -1dB
1kHz, -60dB
1kHz, -60dB
“0” data
40kHzLPF
40kHzLPF
40kHzLPF, A-weighted
40kHzLPF, A-weighted
Results
L ch
R ch
99.8
52.7
114.8
115.0
100.2
52.7
114.8
114.9
fs=96kHz
Results
L ch
R ch
99.2
50.0
114.9
115.0
99.4
50.0
114.9
115.0
fs=192kHz
<KM100802>
Results
L ch
R ch
99.2
49.7
114.8
115.1
99.4
49.8
114.7
115.1
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[AKD4621-B]
3. PLOT DATA
3.1 ADC (fs=48kHz)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 12. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 13. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 23 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 14. FFT (Noise Floor)
-80
-82
-84
-86
-88
-90
-92
-94
-96
d
B
F
S
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-140
-120
-100
-80
-60
-40
-20
dBr
Figure 15. THD+N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 24 -
[AKD4621-B]
-80
-82
-84
-86
-88
-90
-92
-94
-96
d
B
F
S
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 16. THD +N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 17. Linearity (fin=1kHz)
<KM100802>
2010/12
- 25 -
[AKD4621-B]
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 18. Frequency Response(Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
d
B
-110
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
20
50
100
200
500
1k
2k
Hz
Figure 19. Crosstalk
<KM100802>
2010/12
- 26 -
[AKD4621-B]
3.2 ADC (fs=96kHz)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 20. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
Hz
Figure 21. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 27 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 22. FFT (Noise Floor)
-80
-82
-84
-86
-88
-90
-92
-94
-96
d
B
F
S
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-140
-120
-100
-80
-60
-40
-20
dBr
Figure 23. THD +N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 28 -
[AKD4621-B]
-80
-82
-84
-86
-88
-90
-92
-94
-96
d
B
F
S
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 24. THD +N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 25. Linearity (fin=1kHz)
<KM100802>
2010/12
- 29 -
[AKD4621-B]
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
40 50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 26. Frequency Response(Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
d
B
-110
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
40 50
100
200
500
1k
2k
5k
Hz
Figure 27. Crosstalk
<KM100802>
2010/12
- 30 -
[AKD4621-B]
3.3 ADC (fs=192kHz)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
20k
50k
80k
Hz
Figure 28. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
Hz
Figure 29. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 31 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
S
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 30. FFT (Noise Floor)
-80
-82
-84
-86
-88
-90
-92
-94
-96
d
B
F
S
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-140
-120
-100
-80
-60
-40
-20
dBr
Figure 31. THD+N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 32 -
[AKD4621-B]
-80
-82
-84
-86
-88
-90
-92
-94
-96
d
B
F
S
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
90
200
500
1k
2k
5k
10k
20k
50k
80k
-10
+0
Hz
Figure 32. THD+N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 33. Linearity (fin=1kHz)
<KM100802>
2010/12
- 33 -
[AKD4621-B]
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
d
B
F
S
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
90
200
500
1k
2k
5k
10k
20k
50k
80k
20k
50k
80k
Hz
Figure 34. Frequency Response(Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
d
B
-110
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
90
200
500
1k
2k
5k
10k
Hz
Figure 35. Crosstalk
<KM100802>
2010/12
- 34 -
[AKD4621-B]
3.4 DAC (fs=48kHz)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 36. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
Hz
Figure 37. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 35 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 38. FFT (Noise Floor)
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
A
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 39. THD+N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 36 -
[AKD4621-B]
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
A
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 40. THD +N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 41. Linearity (fin=1kHz)
<KM100802>
2010/12
- 37 -
[AKD4621-B]
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
d
B
r
-1.4
-1.6
A
-1.8
-2
-2.2
-2.4
-2.6
-2.8
-3
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 42. Frequency Response (Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
d
B
-110
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
20
50
100
200
500
1k
2k
Hz
Figure 43. Crosstalk
<KM100802>
2010/12
- 38 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 44. Out-of-band Noise
<KM100802>
2010/12
- 39 -
[AKD4621-B]
3.5 DAC (fs=96kHz)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 45. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
Hz
Figure 46. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 40 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 47. FFT (Noise Floor)
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
A
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 48. THD +N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 41 -
[AKD4621-B]
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
A
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 49. THD +N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 50. Linearity (fin=1kHz)
<KM100802>
2010/12
- 42 -
[AKD4621-B]
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
d
B
r
-1.4
-1.6
A
-1.8
-2
-2.2
-2.4
-2.6
-2.8
-3
40 50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 51. Frequency Response (Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
d
B
-110
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
40 50
100
200
500
1k
2k
5k
Hz
Figure 52. Crosstalk
<KM100802>
2010/12
- 43 -
[AKD4621-B]
3.6 DAC (fs=192kHz)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
20k
50k
80k
Hz
Figure 53. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
Hz
Figure 54. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 44 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
-80
A
-100
-90
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 55. FFT (Noise Floor)
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
A
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 56. THD+N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 45 -
[AKD4621-B]
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
A
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
90
200
500
1k
2k
5k
10k
20k
50k
80k
-10
+0
Hz
Figure 57. THD+N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBFS
Figure 58. Linearity (fin=1kHz)
<KM100802>
2010/12
- 46 -
[AKD4621-B]
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
d
B
r
-1.4
-1.6
A
-1.8
-2
-2.2
-2.4
-2.6
-2.8
-3
90
200
500
1k
2k
5k
10k
20k
50k
80k
20k
50k
80k
Hz
Figure 59. Frequency Response (Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
d
B
-110
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
90
200
500
1k
2k
5k
10k
Hz
Figure 60. Crosstalk
<KM100802>
2010/12
- 47 -
[AKD4621-B]
REVISION HISTORY
Date
(yy/mm/dd)
2010/03/12
2010/03/12
Manual
Revision
KM100800
KM100801
Board
Revision
0
1
2010/12/07
KM100802
2
Reason
Page
First Edition
Evaluation Board
Change
Modification
Modification
21~47
49
Contents
Device Rev. Change
AK4621: Rev.A → Rev.B
Device revision was changed.:
Rev.BÆRev.C
Update of measurement results and Plots.
Circuit diagram was changed.
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use
of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
<KM100802>
2010/12
- 48 -
5
4
3
2
1
T1
OUT
0.1u
3
VOP+
VREF
C2
2
C1
C3
+
0.1u
10
47u
IN
C4
0.1u
AVDD
1
GND
IN
(short)
3
GND
1
VOP+
R501
OUT
CODEC_3.3V
C6
+
C5
2
R77
AVDD
VREF
T2
LP2950A
NJM78M05FA
0.1u
C12
+
10u
47u
+
C13
C14
0.1u
470u
C15
0.1u
AGND
D
AGND
D
Bias
T3
TA48M33F
for 74HC14/74LVC157
IN
10
C16
2
1
GND
OUT
(short)
1
2
BNC
18k
C23
C20
0.47u
10u
48
47
46
45
44
43
42
41
40
39
38
37
C26
5p
DIF0/RX5
2
XTI
X1
C27
1
XTO
24.576MHz
XTL0
XTL1
IPS0/RX4
AVSS
DIF0/RX5
TEST2
DIF1/RX6
AVSS
DIF2/RX7
IPS1/IIC
P/SN
XTL0
XTL1
VIN
PORT2
U2
AK4114
C28
+3.3V
0.1u
OPT
B
C29
10u
JP7
R7
51
XTO
VCOM
AOUTR+
AINR+
AOUTRAINR-/NC
AOUTL+
AINL+
AOUTLAINL-/NC
VSS2
VREF
DVDD
VSS1
TVDD
AK4621
AVDD
SDFIL
P/S
DEM0
MCLK
PDN
LRCK/DSDR
DFS0
BICK/DCLK
CSN/DIF
SDTO
CCLK/CKS1
SDTI/DSDL
CDTI/CKS0
OVFR/DZFR
OVFL/DZFL
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
AOUTR+
AOUTRAOUTL+
AOUTLC24
10u
SDFIL
DEM0
PDN
DFS0
CSN/DIF
CCLK/CKS1
CDTI/CKS0
C25
51
C130
C131 C132 C133
(open)
10p
AGND
0.1u
CODEC_3.3V
OVFR/DZFR
OVFL/DZFL
(open)(open)
1
2
3
4
5
6
7
C32
10u
RP2
5.1
7
6
5
4
3
2
1
C33
74HC14_0
3
4
1
2
3
4
5
PDN
74HC14_0
0.1u
PORT3
10
9
8
7
6
CR-I/F
PDN
XTL1
XTL0
DIF0/RX5
OCKS1
OCKS0
CM1
CM0
14
13
12
11
10
9
8
R12
10k
CSN
CCLK
CDTI
10k
RP1
XTL1
XTL0
DIF0/RX5
OCKS1
OCKS0
CM1
CM0
7
6
5
4
3
2
1
P/S
SDFIL
DEM0
DFS0
DIF
CKS1
CKS0
P/S
SDFIL
DEM0
DFS0
DIF
CKS1
CKS0
47K
R14
U4
R16
R15
470
470
470
DIF
CKS1
P/S
- 49 -
2
3
5
6
11
10
14
13
1A
1B
2A
2B
3A
3B
4A
4B
1
15
A/B
G
1Y
4
CSN/DIF
2Y
7
CCLK/CKS1
3Y
9
CDTI/CKS0
4Y
12
A
Title
74LVC157
Size
A3
Date:
4
B
R13
CKS0
5
14
13
12
11
10
9
8
AK4621 Mode_setting
47K
10k
U3B
2
+3.3V
SW3
1
2
3
4
5
6
7
+3.3V
SW1
AK4114 Mode_setting
TEST1
0.1u
R10
10k
C
51
R11
1
L
AVDD
P/S
R6
51
150
U3A
A
R5
51
+3.3V
D1
VREF
AGND
XTI
C31
C30
+3.3V
SW2
R4
OCKS0
OCKS1
CM1
CM0
PDN
BNC
240
R184
1:1
H
AINL-
R8
R78
TX
R183
TX
1S1588
AINL+
+
0.1u
T4
DA02
BNC_TX
36
35
34
33
32
31
30
29
28
27
26
25
+3.3V
TOTX141
J6
INT0
OCKS0/CSN
OCKS1/CCLK
CM1/CDTI
CM0/CDTO
PDN
XTI
XTO
DAUX
MCKO2
BICK
SDTO
+
GND
1
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
13
14
15
16
17
18
19
20
21
22
23
24
3
2
INT1
TVDD
DVSS
TX0
TX1
BOUT
COUT
UOUT
VOUT
DVDD
DVSS
MCKO1
LRCK
DIF2-0="100"; MSB justified; Master Mode
IN
VCC
0.1u
AINR+
AINR-
RX3
AVSS
RX2
TEST1
RX1
AVSS
RX0
AVSS
VCOM
R
AVDD
INT1
1
2
3
4
5
6
7
8
9
10
11
12
+3.3V
5p
4114_AVDD
C21
0.1u
75
0.1u
R2
+
C
0.1u
0.1u
JP2
C22
R3
47u
C11
C19
RX3
RX
0.1u
C10
10u
+
470
BNC_RX
0.1u
C9
C18
R1
10u
OPT
J1
C8
4114_AVDD
C17
+
0.1u
TORX141
+3.3V
+
C7
+
3
VCC
+3.3V
OUT
+
L5
PORT1
GND
R500
3
2
Document Number
AKD4621-B
Sheet
1
Rev
1
AK4621
Monday, December 06, 2010
1
of
2
5
4
3
2
1
C34
SINGLE
JP3
LIN
LIN
+
J2
(open)
R19
DIFF
R17
R18
4.7k
47k
910
VOP_ADC-
VOP_ADCC35
C36 (open)
C37
3.3n
+
7
AOUTL+
DIFF
C44
100p
U5A
R25
10k
NJM5532
8
8
AINL+
1
R24
180
VOP_ADC+
3
+
2
-
C45
3.9n
VOP_ADC+
+
C42
0.1u
6
C46
0.1u
R27
680
10n
C51
100p
+
C49
VOP_ADC-
C50
C47
10u
C48
1n
R29
620
R30
(short)
R31
1.2k
C52
100p
470p
C53
(open)
R34
(short)
C54
(open)
2
R40
8
0.1u
10u
R102
0
C62
100u
R41
330
R42
180
AOUTLC63
100p
VOP_ADC+
R43
R44
10k
10k
3
+
2
-
C66
3.9n
C71
100p
C73
SINGLE
JP5
RIN
RIN
DIFF
910
4.7k
C74
3.3n
VOP_ADCVOP_ADC-
C75
C69
0.1u
C
VOP_DAC+
VOP_DAC-
R50
330
R51
180
R54
7
2
U10B
3
+
JP6
AINR
C82
100p
22
R55
10k
AINR+
1
+
2
-
C84
3.9n
DIFF
C78
0.1u
U11
C80
0.1u
6
C81
10u
R56
560
U12A
NJM5532
+
8
NJM5532
SINGLE
3
C76
10u
4
3k
4
4
R53
47u
-
8
C83
+
5
C68
10u
C70
10u
NJM5534D
7
C79
100u
+
R103
0
AOUTR+
6
+
C67
0.1u
+
470p
4.7k
C56
(open)
NJM5534D
6
C77 (open)
R52
R36
(open)
U7
R48
R49
47k
C61
1n
C72
100p
(open)
R47
R39
560
R46
1.2k
+
J4
C60
10u
J3
LOUT
U9
R45
680
C
+
VOP_ADC+
C85
0.1u
R57
680
VOP_ADC+
+
C65
AINL-
U5B
NJM5532
7
+
+
C64
C59
0.1u
4
-
5
R33
620
NJM5534D
22
7
+
6
7
C57
3.3n
4
3k
+
R38
47u
10k
R32
100
+
C58
+
R37
C55
(short)
6
3
Bias
D
C43
10u
R26
560
R28
910
C39
10u
U6
+
3
22
R23
330
4
2
JP4
AINL
C41
100u
4
1
U8A
NJM5532
SINGLE
R101
0
+
4
4
3k
R22
+
-
3
NJM5534D
C38
0.1u
47u
+
2
R21
+
D
C40
-
4.7k
-
R20
+
470p
C86
10u
C87
1n
R58
620
R59
(short)
R61
C89
100p
C91
(open)
R64
(short)
C92
(open)
2
6
3
5
22
C106
C107
0.1u
10u
+
R70
330
R71
180
C102
100p
R73
10k
NJM5532
VOP_ADC+
R74
7
C101
100u
AOUTR-
AINR-
U12B
8
B
R104
0
R72
7
3
+
2
-
+
C98
10u
7
R66
560
C99
1n
C103
3.9n
J5
ROUT
R65
(open)
U13
C95
(open)
NJM5534D
U14
6
4
6
+
3k
+
R69
47u
10k
-
C100
+
R68
4
C97
0.1u
Bias
R63
620
NJM5534D
C104
0.1u
10k
C108
0.1u
+
470p
R62
100
+
C96
3.3n
C93
(short)
+
R60
1.2k
10n
4
C88
100p
C90
VOP_ADCC94
-
910
+
B
C105
10u
C109
10u
R75
680
C110
100p
for NJM5532
4
4
2
-
3
+
7
U8B
NJM5532
8
+
8
+
5
+
6
+
VOP_ADC-
+
VOP_ADC-
R76
1.2k
C111
100p
VOP_ADC-
C113
C114
C115
C116
C117
C118
C119
C120
10u
0.1u
10u
0.1u
10u
0.1u
10u
0.1u
1
U10A
for NJM5532
NJM5532
VOP_ADC+
VOP_ADC+
VOP_ADC+
+
+
+
+
C122
C123
C124
C125
C126
C127
C128
C129
10u
0.1u
10u
0.1u
10u
0.1u
10u
0.1u
R503
R505
VOP_ADCA
VOP_ADC+
10
R504
VOP_DACL6
1
VOP_DAC+
+15V
10
(short)
+
47u
10
L7
2
1
C112
A
10
R502
-15V
C121
+
2
VOP+
(short)
- 50 -
47u
Title
Size
A2
Date:
5
4
3
2
Document Number
AKD4621-B
Rev
Analog_I/O
Monday, December 06, 2010
Sheet
1
2
1
of
2