AKM AKD4711

[AK4711]
= Preliminary =
AK4711
Low Power Single SCART Driver with HD
Fil
FEATURES
Audio section
† THD+N: −92dB (@2Vrms)
† Dynamic Range: 96dB (@2Vrms, A-weighted)
† Full Differential or Single-ended input for Decoder DAC
† Stereo Output for TV SCART and CINCH (2Vrms)
† Ground-Referenced Output Eliminates
DC-Blocking Capacitor and Mute Circuit
Video section
† Integrated LPF
SD: [email protected]
HD: [email protected] or 54MHz or 27MHz selectable
† 6dB Gain for Outputs
† 5ch 75ohm driver
4ch for SCART: CVBS/Y, R/C, G, B
1ch for CINCH: CVBS
† Y/Pb/Pr Option (to 6MHz)
Low-power Standby
SCART pin#16(Fast Blanking), pin#8(Slow Blanking) Output Control
Power supply
† 3.3V+/−5% and 12V+/−5%
† Low Power Dissipation / Low Power Standby Mode
Package
† 36pin QFN (0.4mm pitch)
Rev. 0.4
2011/07
-1-
[AK4711]
■ Block Diagram
-6dB to +24dB
VD1
(3dB/step)
VSS1
AINL+
TVOUTL
AINLAMP
TVOUTR
AINRAINR+
TV SCART
MONO
Volume
SCL
Register
SDA
Control
CINCH Audio
Charge Pump
PDN
CP
CN
VEE
VSS2
VD2
Audio Block
( Typical connection )
( Typical connection )
6:8 Selector
VVD
HDVVD
6dB
TVVOUT
6dB
TVRC
6dB
TVG
6dB
TVB
6dB
RCAVOUT
6dB
HDY
6dB
HDPB
6dB
HDPR
VSS3
ENC CVBS/Y
ENCV
ENC Y
ENCY
ENC R/C/Pr
ENC C
TV SCART
ENCRC
ENCC
ENC G/CVBS
ENCG
ENC B/Pb
ENCB
CINCH Video
HD Video
Video Block
( Typical connection )
1.25V
0V
6dB
TVFB
TV SCART
VP
0/ 6/ 12V
TVSB
Video Blanking Block
Rev. 0.4
2011/07
-2-
[AK4711]
■ Ordering Guide
AK4711EN
AKD4711
-10 ∼ +70°C
36pin QFN (0.4mm pitch)
Evaluation board for AK4711
■ Pin Layout
TVSB
VSS1
VD1
TVOUTR
TVOUTL
AINR-
AINR+
AINL-
AINL+
36pin QFN (0.4mm pitch)
27 26 25 24 23 22 21 20 19
VEE
28
18
VP
CN
29
17
ENCY
CP
30
16
ENCV
VSS2
31
15
ENCC
VD2
32
14
ENRC
SCL
33
13
ENCG
SDA
34
12
ENCB
11
VVD
10
TVB
1
2
3
4
5
6
7
8
9
RCAVOUT
VSS3
TVVOUT
TVFB
TVRC
TVG
36
HDPB
HDVDD
HDPR
35
Top View
HDY
PDN
AK4711
Rev. 0.4
2011/07
-3-
[AK4711]
PIN/FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
Pin Name
HDY
HDPR
HDPB
RCAVOUT
VSS3
TVVOUT
TVFB
TVRC
TVG
TVB
I/O
O
O
O
O
O
O
O
O
O
11
VVD
-
12
13
14
15
16
17
ENCB
ENCG
ENCRC
ENCC
ENCV
ENCY
I
I
I
I
I
I
18
VP
-
19
TVSB
O
20
VSS1
-
21
VD1
-
22
TVOUTR
O
Function
Green/Y Output Pin
Red/Pr Output Pin
Blue/Pb Output Pin
Composite/Luminance Output Pin for RCA
Video Ground Pin , 0V
Composite/Luminance Output Pin for TV
Fast Blanking Output Pin for TV
Red/Chrominance Output Pin for TV
Green Output Pin for TV
Blue Output Pin for TV
Video Power Supply Pin: 3.13V ~ 3.47V
Normally connected to VSS3 with a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic capacitor.
Blue Input Pin for Encoder
Green Input Pin for Encoder
Red/Chrominance Input Pin #1 for Encoder
Chrominance Input Pin #2 for Encoder
Composite/Luminance Input Pin #1 for Encoder
Composite/Luminance Input Pin #2 for Encoder
Blanking Power Supply Pin, 10.8V ~ 13.2V
The VP pin must connect to power supply through 10ohm resistor with 0.1μF
ceramic capacitor in parallel with a 1μF electrolytic capacitor to VSS1.
Slow Blanking Output Pin for TV
A 470ohm ±5% resistor must be connected between the TVSB pin and SCART
connector.
Audio Ground Pin , 0V
Audio Power Supply Pin: 3.13V ~ 3.47V
Normally connected to VSS1 with a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic capacitor.
Rch Analog Output Pin #2
23
TVOUTL
O
Lch Analog Output Pin #2
24
25
26
27
AINRN
AINRP
AINLN
AINLP
I
I
I
I
28
VEE
O
29
CN
I
30
CP
I
31
32
VSS2
VD2
-
Rch Negative Analog Input Pin
Rch Positive Analog Input Pin
Lch Negative Analog Input Pin
Lch Positive Analog Input Pin
Negative Voltage Output Pin
Connect to VSS2 with a 1.0μF capacitor that should have the low ESR (Equivalent
Series Resistance) over all temperature range. When this capacitor has the polarity,
the positive polarity pin should be connected to the VSS2 pin. Non polarity
capacitors can also be used.
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF capacitor that should have the low ESR (Equivalent
Series Resistance) over all temperature range. When this capacitor has the polarity,
the positive polarity pin should be connected to the CP pin. Non polarity capacitors
can also be used.
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF capacitor that should have the low ESR (Equivalent
Series Resistance) over all temperature range. When this capacitor has the polarity,
the positive polarity pin should be connected to the CP pin. Non polarity capacitors
can also be used.
Charge Pump Ground Pin , 0V
Charge Pump Power Supply Pin: 3.13V ~ 3.47V
Rev. 0.4
2011/07
-4-
[AK4711]
Normally connected to VSS2 with a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic cap.
33 SCL
I
Control Data Clock Pin
34 SDA
I/O Control Data Pin
Power-Down Mode Pin
35 PDN
I
When at “L”, the AK4711 is in the power-down mode and is held in reset. The
AK4711 should always be reset upon power-up.
Video Power Supply Pin: 3.13V ~ 3.47V
36 HDVVD
Normally connected to VSS3 with a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic capacitor.
Note: All digital input pins should not be left floating.
Rev. 0.4
2011/07
-5-
[AK4711]
ABSOLUTE MAXIMUM RATINGS
(VSS1 =VSS2 =VSS3 = 0V; Note 1)
Parameter
Power Supply
(Note 2)
Symbol
VD1
VD2
VVD
HDVDD
VP
IIN
VIND1
VIND2
VINV
VINA
Ta
Tstg
Min
−0.3
-0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
VEE-0.3
−10
−65
max
4.0
4.0
4.0
4.0
14
±10
VVD+0.3
4.0
VVD+0.3
VD1+0.3
70
150
Input Current (any pins except for supplies)
Digital Input Voltage(PDN pin)
Digital Input Voltage(SCL, SDA pins)
Video Input Voltage
Audio Input Voltage
(Note 3)
Ambient Operating Temperature
Storage Temperature
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 and VSS3 must be connected to the same analog ground plane.
Note 3. VEE: VEE pin voltage.
The internal negative power supply generating circuit provides negative power supply(VEE).
The PDN pin and MUTE bit control operation mode as shown in Table 2 and Table 3.
0
1
Mode
Full Power-down
Mute
2
Normal operation
No video input
Video input
Table 1. VEE pin voltage
Units
V
V
V
V
V
mA
V
V
V
V
°C
°C
VEE pin Voltage
0V
0V
0V
-VD2+0.2V
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Rev. 0.4
2011/07
-6-
[AK4711]
RECOMMENDED OPERATING CONDITIONS
(VSS1 =VSS2 =VSS3 = 0V; Note 1)
Parameter
Symbol
min
typ
Power Supply
(Note 4)
VD1
3.13
3.3
VD2
3.13
3.3
VVD
3.13
3.3
HDVDD
3.13
3.3
VP
10.8
12
Note 1. All voltages with respect to ground.
Note 4. VVD and HDVDD must be connected to the same voltage.
max
3.47
3.47
3.47
3.47
13.2
Units
V
V
V
V
V
*AKM assumes no responsibility for the usage beyond recommended operating conditions in this datasheet.
ELECTRICAL CHARACTERISTICS
(Ta = 25°C; VP=12V, VD1=VD2=VVD=HDVVD= 3.3V)
Power Supplies
min
typ
max
Power Supply Current
Normal Operation (PDN = “H”)
(Note 5)
VD1+VD2+VVD+HDVDD
386
TBD
VP
48
TBD
Power-Down Mode (PDN = “L”)
(Note 6)
VD1+VD2
0
TBD
VVD
0
TBD
HDVDD
0
TBD
VP
48
TBD
Note 5. STBY bit = “0”, All video outputs active. No signal, no load for A/V switches. Refer to Table 3.
Note 6. All digital inputs are held at VVD or VSS3. No signal, no load for A/V switches.
DIGITAL CHARACTERISTICS
(Ta = 25°C; VD1=VD2=VVD=HDVVD= 3.13 ∼ 3.47V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%VVD
Low-Level Input Voltage
VIL
Low-Level Output Voltage
VOL
(SDA pin: Iout= 3mA)
Input Leakage Current
Iin
-
Rev. 0.4
Units
μA
μA
μA
μA
μA
μA
typ
-
max
30%VVD
0.4
Units
V
V
V
-
± 10
μA
2011/07
-7-
[AK4711]
ANALOG CHARACTERISTICS (AUDIO)
(Ta=25°C; VP=12V, VD1=VD2=VVD=HDVVD= 3.3V; Signal Frequency=1kHz; Measurement frequency=20Hz ∼
20kHz; RL ≥4.5kΩ; 0dB=2Vrms output; Volume =0dB, unless otherwise specified)
Parameter
min
typ
max
Units
Analog Input: (AINL+/AINL-/AINR-/AINR+ pins)
Analog Input Characteristics
2.0
Vrms
Input Voltage
(AIN+) − (AIN−)
(Note 7)
Input Resistance
(AINL+, AINR+ pins)
85
120
kΩ
Input Resistance
(AINL-, AINR- pins)
85
120
kΩ
Stereo/Mono Output: (TVOUTL/TVOUTR pins)
(Note 8)
Analog Output Characteristics
Volume Step Width
TBD
3.0
TBD
dB
TBD
dB
THD+N
(at 2Vrms output, Note 10,Note 12)
−92
TBD
96
dB
Dynamic Rang (−60dB Output, A-weighted, Note 10)
S/N
(A-weighted, Note 10, Note 14)
TBD
96
dB
Interchannel Isolation
(Note 10, Note 11)
TBD
90
dB
Interchannel Gain Mismatch
(Note 10, Note 11)
-0.5
0
+0.5
dB
DC offset
(Note 13)
-5
0
+5
mV
Gain Drift
200
ppm/°C
Load Resistance
TVOUTL/R
4.5
kΩ
Load Capacitance
TVOUTL/R
20
pF
Output Voltage
(Note 9)
1.8
2
2.2
Vrms
Power Supply Rejection (PSR)
(Note 15)
50
dB
Note 7. f = 1kHz, THD+N < -80dB, gain = 0dB(Volume=0dB)
Note 8. Measured by Audio Precision System Two Cascade.
Note 9. The output level of the internal AMP with volume should be less than 2Vrms.
Note 10. Analog In to TVOUT. Path : AINL+/− → TVOUTL, AINR+/− → TVOUTR, Volume=0dB.
At 2Vrms single input, TDH+N is -91dB (typ), on path AINL+ → TVOUTL, AINR+ → TVOUTR,
Volume=0dB
Note 11. Between TVOUTL and TVOUTR with analog inputs AINL+/−, AINL/R+/−, 1kHz/0dB.
Inter-channel crosstalk is -80dB (typ), at 20Hz~20kHz other than 1kHz.
Note 12. -79dB (typ) referred to 0.5Vrms output level at Volume=+24dB
: path = AIN+/- → TVOUT.
Note 13. Analog In to TVOUT. Volume=0dB
Path : AINL+/− → TVOUTL, AINR+/− → TVOUTR
Note 14. 82dB (typ) referred to 0.5Vrms output level at Volume=+24dB
84dB (typ), referred to 0.5Vrm output level at Volume = +21dB.
: path = AIN+/- → TVOUT.
Note 15. The PSR is applied to VD1 and VD2 with 1kHz, 100mV.
Rev. 0.4
2011/07
-8-
[AK4711]
ANALOG CHARACTERISTICS (SD VIDEO)
(Ta = 25°C; VP = 12V, VD1=VD2= VVD=HDVVD= 3.3V; unless otherwise specified.)
Parameter
Conditions
min
Sync Tip Clamp Voltage
at output pin.
R/G/B Clamp Voltage
at output pin.
Pb/Pr Clamp Voltage
at output pin.
Chrominance Bias Voltage
at output pin.
Gain
Input = 0.3Vp-p, 100kHz
5.5
Interchannel Gain Mismatch
TVRC, TVG, TVB. Input = 0.3Vp-p, 100kHz.
-0.5
Frequency Response
Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz.
-1.0
at 10MHz.
at 27MHz.
Group Delay Distortion
At 4.43MHz with respect to 1MHz.
Input Impedance
Chrominance input (internally biased)
TBD
Input Signal
f = 100kHz, maximum with distortion < 1.0%,
gain = 6dB.
Load Resistance
150
(Figure 1)
Load Capacitance
C1 (Figure 1)
C2 (Figure 1)
Dynamic Output Signal
f = 100kHz, maximum with distortion < 1.0%
Y/C Crosstalk
f = 4.43MHz, 1Vp-p input. Among TVVOUT,
TVRC and RCAVOUT outputs.
S/N
Reference Level = 0.7Vp-p, CCIR 567 weighting.
BW = 15kHz to 5MHz.
Differential Gain
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
Differential Phase
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
typ
0.20
0.20
1.44
1.44
6
-
100
-20
20
-
Units
V
V
V
V
dB
dB
dB
dB
dB
ns
kΩ
-
1.25
Vpp
-
-
400
15
2.5
Ω
pF
pF
Vpp
−50
-
dB
74
-
dB
0.6
-
%
1.4
-
Degree
-3
-40
max
6.5
0.5
0.5
R1
75 ohm
Video Signal Output
R2
75 ohm
C1
C2
max: 15pF
max: 400pF
Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2.
Rev. 0.4
2011/07
-9-
[AK4711]
ANALOG CHARACTERISTICS (HD VIDEO)
(Ta = 25°C; VP=12V, VD1=VD2=VVD=HDVVD= 3.3V, unless otherwise specified.)
Parameter
Conditions
min
Sync Tip Clamp Voltage at output pin.
R/G/B Clamp Voltage
at output pin.
Pb/Pr Clamp Voltage
at output pin.
Gain
Input=0.3Vp-p, 100kHz
5.5
Frequency response
Input=0.3Vp-p,
FL1/0,FLPB1/0,FLPR1/0= “10”
C1=C2=0pF
100kHz to 20MHz,
-1.0
(Figure 1)
at 30MHz.
at 74.25MHz.
FL1/0,FLPB1/0,FLPR1/0= “01”
100kHz to 15MHz,
-1.0
at 54MHz.
FL1/0,FLPB1/0,FLPR1/0= “00”
100kHz to 6MHz,
-1.0
at 27MHz.
Input Signal
f=100kHz, distortion < 1.0%, gain=6dB
Load Resistance
Load Capacitance
Dynamic Output Signal
S/N
Differential Gain
Differential Phase
C1
C2
f=100kHz, distortion < 1.0%
(Figure 1)
(Figure 1)
(Figure 1)
Reference Level = 0.7Vp-p, CCIR 567 weighting.
BW = 15kHz to 5MHz.
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
FL1/0, FLPB1/0, FLPR1/0= “00”
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
FL1/0, FLPB1/0, FLPR1/0= “00”
Rev. 0.4
typ
0.20
0.20
1.44
6
max
6.5
1.0
Units
V
V
V
dB
-2.5
-40
-25
dB
dB
dB
-40
1.0
-25
dB
dB
-40
-
0.5
-25
1.25
dB
dB
Vpp
Ω
pF
pF
Vpp
150
-
-
-
400
10
2.5
-
74
-
dB
-
+0.3
-
%
-
+0.6
-
Degree
2011/07
- 10 -
[AK4711]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP = 10.8 ∼ 13.2V, VD1=VD2= VVD=HDVVD= 3.13 ∼ 3.47V)
Parameter
Symbol
min
typ
max
Units
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
μs
Start Condition Hold Time
tHD:STA
0.6
μs
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
μs
Clock High Time
tHIGH
0.6
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
μs
SDA Hold Time from SCL Falling (Note 16) tHD:DAT
0
μs
SDA Setup Time from SCL Rising
tSU:DAT
0.1
μs
Rise Time of Both SDA and SCL Lines
tR
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
μs
Pulse Width of Spike Noise
tSP
0
50
ns
Suppressed by Input Filter
Capacitive load on bus
Cb
400
pF
Reset Timing
tPD
150
ns
PDN Pulse Width
(Note 17)
Note 16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 17. The AK4711 should be reset once by bringing the PDN pin = “L” after all power supplies are supplied.
Note 18. I2C-bus is a trademark of NXP B.V.
Rev. 0.4
2011/07
- 11 -
[AK4711]
■ Timing Diagram
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
I2C Bus mode Timing
tPD
PDN
VIL
Power-down Timing
Rev. 0.4
2011/07
- 12 -
[AK4711]
OPERATION OVERVIEW
1. System Reset and Power-down Options
The AK4711 should be reset once by bringing the PDN pin = “L” after all power supplies are supplied. The AK4711 has
several operation modes. The PDN pin and MUTE bit control operation mode as shown in Table 2 and Table 3.
■ System Reset and Full Power-down Mode
The AK4711 should be reset once by bringing the PDN pin = “L” after all power supplies are supplied.
PDN pin: Power down pin
L: Full Power-down Mode. Power-down, reset and initializes control registers.
H: Device active.
■ Mute Mode
When the MUTE bit = “1”, the audio outputs settle to VSS(0V, typ) and the charge pump circuit is in power down mode.
MUTE bit (00H D1): Audio output control
0: Normal operation.
1: All audio outputs to GND (default)
Mode
0
PDN pin
L
MUTE bit
x
Mode
Full Power-down
Mute (Note 19)
1
H
1
(AMP power down)
Normal operation
2
H
0
(AMP operation)
Note 19. TVOUTL/R are muted by Mute bit in the default state.
Table 2. Operation Mode Settings (x: Don’t Care)
Mode
Register
Control
0 Full Power-down
NOT
available
Audio
Charge pump
Video
Output
Hi-Z
TVFB
TVSB
Power
Consumption
(typ.) (Note 20)
Hi-Z
Pull
-down
(Note 21)
0.6mW
No Video
Power down
Input
Video
Hi-Z/
Input
Active
Available
Active
Active
No video
Hi-Z
Normal operation
input
2
(AMP operation)
Video
Hi-Z/
Active
input
Active
Note 20. 1kHz 2Vrms output with 4.5kΩ load at all audio output pins.
47.46 IRE at all video inputs corresponding to all video output pins with 150Ω load.
Note 21. Internally pulled down by 120kΩ (typ) resistor.
Mute
1
(AMP power down)
1.86mW
228mW
1.86mW
250mW
Table 3. Status of each operation modes
Rev. 0.4
2011/07
- 13 -
[AK4711]
■ Normal Operation Mode
To change analog switches, set the MUTE bit to “0”. The AK4710/11 is in power-down mode until the PDN pin = “H”.
The Figure X shows an example of the system timing at the power-down and power-up by the PDN pin.
■ Typical Operation Sequence
Figure 2 shows an example of the system timing at normal operation mode.
PDN pin
“Normal“
MUTE bit
“1” (default)
Video Signal
No Signal
Video Detect
Video Output
TVOUT
“0”
“Normal“
“1”
“0”
“1”
No Signal
Signal In
175ms(MAX)
Hi-z
Hi-z
Active
Analog in
(GND)
Analog in
50ms(MAX)
50ms(MAX)
Charge pump
“Mute”
(Note21)
(Note21)
Note 22. Mute the analog outputs externally if click noise affects the system.
Figure 2. Typical Operating Sequence
Rev. 0.4
2011/07
- 14 -
[AK4711]
2. Audio Block
■ Volume Control (11-Level Volume)
The AK4711 has an 11-level volume control as shown in Table 4. The volume reflects the change of register value
immediately.
2Vrms
AINL/R+
1Vrms
Volume Gain 0dB
300Ω
2Vrms differential
input
0.47μ
TVOUTL/R
300Ω
0.47μ
Volume
AINL/R-
1Vrms
Figure 3. Volume (Volume Gain=0dB: default), Full Differential Stereo Input
(0DH: D6-D3)
VOL3
VOL2
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
VOL1
x
1
1
0
0
1
1
0
0
1
1
0
0
VOL0
x
1
0
1
0
1
0
1
0
1
0
1
0
Volume Gain
-+24dB
+21dB
+18dB
+15dB
+12dB
+9dB
+6dB
+3dB
0dB
-3dB
-6dB
Mute
Output Level (Typ)
Reserved
2Vrms (with 0.13Vrms differential input)
2Vrms (with 0.25Vrms differential input)
2Vrms (with 0.5Vrms differential input)
2Vrms (with 1Vrms differential input)
2Vrms (with 2Vrms differential input: default)
1Vrms (with 2Vrms differential input)
(x: Don’t care)
Table 4. Volume, Full Differential Stereo Input
2Vrms
2Vrms
AINL/R+
0.47μ
300Ω
Volume Gain 0dB
AINL/R0.47μ
300Ω
TVOUTL/R
Volume
Figure 4. Volume (Volume Gain=0dB:default), Single-ended Input
Rev. 0.4
2011/07
- 15 -
[AK4711]
(0DH: D6-D3)
VOL3
VOL2
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
VOL1
x
1
1
0
0
1
1
0
0
1
1
0
0
VOL0
x
1
0
1
0
1
0
1
0
1
0
1
0
Volume Gain
-+24dB
+21dB
+18dB
+15dB
+12dB
+9dB
+6dB
+3dB
0dB
-3dB
-6dB
Mute
Output Level (Typ)
Reserved
2Vrms (with 0.13Vrms input)
2Vrms (with 0.25Vrms input)
2Vrms (with 0.5Vrms input)
2Vrms (with 1Vrms input)
2Vrms (with 2Vrms input: default)
1Vrms (with 2Vrms input)
(x: Don’t care)
Table 5. Volume, Single-ended Input
Rev. 0.4
2011/07
- 16 -
[AK4711]
■ Analog output block
The AK4711 has a charge pump circuit generating negative power supply rail from a 3.3V(typ) power supply. (Figure 5)
It allows the AK4711 to output audio signal centered at VSS (0V, typ) as shown in Figure 6. The negative power
generating circuit (Figure 5) needs 1.0uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). When using
capacitors with a polarity, the positive side should be connected to CP and VSS2 for capacitor Ca and Cb, respectively.
When the MUTE bit = “1”, the charge pump circuit is in power down mode and its analog outputs become VSS (0V, typ).
AK4711
VD
Charge
Pump
CP
Negative Power
CN
VSS2
(+)
1uF
Ca
VEE
Cb
1uF
(+)
Figure 5. Negative Power Generate Circuit
AK4711
2Vrms
0V
TVOUTR/TVOUTL
Figure 6. Audio Signal Output
Rev. 0.4
2011/07
- 17 -
[AK4711]
3. Video Block
■ Video Switch Control
The AK4711 has switches for TV. Each switch can be controlled via the registers independently.
(04H: D1-D0)
Mode
VTV1-0 bit
Shutdown (default)
Encoder
CVBS+RGB
or Encoder YPbPr
00
01
Encoder Y/C 1
10
Encoder Y/C 2
11
Source of
Source of
TVVOUT pin
TVRC pin
(Hi-Z)
(Hi-Z)
ENCV pin
ENCRC pin
(Encoder CVBS
(Encoder Red,C
or Y)
or Pb)
ENCV pin
ENCRC pin
(Encoder Y)
(Encoder C)
ENCY pin
ENCC pin
(Encoder Y)
(Encoder C)
Table 6. TV Video Output (Note 23)
Source of
TVG pin
(Hi-Z)
ENCG pin
(Encoder Green
or Y)
Source of
TVB pin
(Hi-Z)
ENCB pin
(Encoder Blue
or Pr)
(Hi-Z)
(Hi-Z)
(Hi-Z)
(Hi-Z)
(04H: D4-D3)
Source of
RCAVOUT pin
Shutdown(default)
00
(Hi-Z)
Encoder CVBS
01
ENCV pin
Encoder CVBS
10
ENCY pin
(Reserved)
11
Table 7. RCA Video Output (Note 23)
Mode
RCA1-0 bit
Note 23. When input video signals via the ENCRC pin, set CLAMP1-0 bits respectively.
Rev. 0.4
2011/07
- 18 -
[AK4711]
■ Video Output Control (05H: D6-D0)
Each video output can be set to Hi-Z individually via the control registers.
TVV: TVVOUT output control
TVR: TVRCOUT output control
TVG: TVGOUT output control
TVB: TVBOUT output control
RCAV: RCAVOUT output control
TVFB: TVFB output control
0: Hi-Z. (default)
1: Active.
■ Clamp and DC-restore Circuit Control (06H: D7-D3)
Each CVBS and Y input has a sync tip clamp circuit. The DC-restore circuit has two clamp voltages; 0.20V(typ) and
1.44V(typ) to support both RGB and YPbPr signal. They correspond to 0.10V(typ) and 0.72V(typ) at the SCART
connector when matched by 75Ω resistors. CLAMP1 and CLAMPB bits select the input circuit for both the ENCRC pin
(Encoder Red/Chroma) and the ENCB pin (Encoder Blue), and CLAMP2 bit selects the input circuit for the ENCG pin.
VCLP1-0 bits select the sync source of DC- restore circuit.
CLAMPB
CLAMP1
0
0
0
1
1
0
1
1
ENCRC Input Circuit
ENCB Input Circuit
DC restore clamp active
DC restore clamp active
(0.20V at sync timing/output pin) (0.20V at sync timing/output pin)
Biased
DC restore clamp active
(1.44V at sync timing/output pin) (0.20V at sync timing output pin)
DC restore clamp active
DC restore clamp active
(1.44V at sync timing/output pin) (1.44V at sync timing/output pin)
(reserved)
(reserved)
Table 8. DC-restore Control for Encoder Input
CLAMP2
0
1
ENCG Input Circuit
DC restore clamp active
(0.20V at sync timing/output pin)
Sync tip clamp active
(0.20V at sync timing/output pin)
note
for RGB
(default)
for Y/C
for Y/Pb/Pr
note
for RGB
(default)
for Y/Pb/Pr
Note: When the VTV1-0 bits = “01” (source for TV = Encoder CVBS /RGB), TVG bit = “1” (TVG = active) and
VCLP1-0 bits = “11” (DC restore source = ENCG), the sync tip is selected even if the CLAMP2 bit = “0”.
Table 9. DC-restore Control for Encoder Green/Y Input
VCLP1-0: DC restore source control
VCLP1 VCLP0
Sync Source of DC Restore
0
0
ENCV
0
1
ENCY
1
0
(Reserved)
1
1
ENCG
Table 10. DC-restore Source Control
Rev. 0.4
(default)
2011/07
- 19 -
[AK4711]
■ HD Video Control (0AH: D7-D6)
FLY1/0, FLPB1/0, FLPR1/0 bits and HDCP1/0, HDY1/0 bits set the HD video switch and filter response.
HDCP1
0(default)
1
1
0
HDY1
0
0
1
1
HDCP0
HD PbPr – RGB Control
YPbPr.
Y = 0.2V Clamp,
0(default)
ENCB = 1.44V DC-restore,
ENCRC = 1.44V DC-restore.
(Y= Sync Source only for ENCPB, ENCPR)
RGB.
Y = 0.2V Clamp,
0
ENCB = 0.2V DC-restore,
ENCRC = 0.2V DC-restore.
(Y= Sync Source only for ENCPB, ENCPR)
RGB.
Y = 0.2V DC-restore,
1
ENCB = 0.2V DC-restore,
ENCRC = 0.2V DC-restore.
Sync Source = ENCV
1
Hi-Z
Table 11. HD Video Switch Control (3ch common)
HDY0
Y Input Control
0
ENCG(default)
1
ENCV
0
ENCY
1
(Reserved)
Table 12. HD Video Switch Control (3ch common)
Input
Output
FLY1/ FLPB1/FLPR1 bit
FLY0/ FLPB0/FLPR0 bit
LFP response
0
0
6MHz LPF (default)
0
1
12MHz LPF
1
0
30MHz LPF
1
1
(Reserved)
Table 13. HD Video Filter Control (3ch independent)
Rev. 0.4
2011/07
- 20 -
[AK4711]
4. Blanking Control
The AK4711 supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV SCART.
■ Input/Output Control for Fast/Slow Blanking
FB: TV Fast Blanking output control (07H: D1-D0)
Input
Output
FB1 bit FB0 bit
TVFB pin Output Level
0
0
0V (default)
0
1
2V<, 2.5V(typ) at 150Ω load
1
0
(Reserved)
1
1
(Reserved)
Table 14. TV Fast Blanking Output (Note: minimum load is 150Ω)
SBT1-0: TV Slow Blanking output control (07H: D3-D2)
Input
Output
SBT1 bit SBT0 bit
TVSB pin Output Level
0
0
<2V (default)
0
1
4.73V <, < 7V
1
0
(Reserved)
1
1
10V<
Table 15. TV Slow Blanking Output (Note: minimum load is 10kΩ)
Rev. 0.4
2011/07
- 21 -
[AK4711]
5. Control Interface (I2C-bus Control)
1. WRITE Operations
Figure 7 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A HIGH
to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 13). After the START
condition, a slave address is sent. This address is 7bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant seven bits of the slave address are fixed as “0010001”. If the slave address match that of the
AK4711, the AK4711 generates the acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 15). A
“1” for R/W bit indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed. The second byte consists of the address for control registers of the AK4711. The format is MSB first, and those
most significant 3-bits are fixed to zeros (Figure 9). The data after the second byte contain control data. The format is
MSB first, 8bits (Figure 10). The AK4711 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 13).
The AK4711 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4711
generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 0DH prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 15) except for the START and the STOP
condition.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 7. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
0
1
R/W
A2
A1
A0
D2
D1
D0
Figure 8. The first byte
0
0
0
A4
A3
Figure 9. The second byte
D7
D6
D5
D4
D3
Figure 10. Byte structure after the second byte
Rev. 0.4
2011/07
- 22 -
[AK4711]
2. READ Operations
Set R/W bit = “1” for READ operations. After transmission of data, the master can read the next address’s data by
generating an acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of
each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If
the address exceeds 09H prior to generating the stop condition, the address counter will “roll over” to 00H and the
previous data will be overwritten.
The AK4711 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
2-1. CURRENT ADDRESS READ
The AK4711 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4711 generates an
acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address
counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4711
discontinues transmission.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
Data(n+2)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 11. CURRENT ADDRESS READ
2-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start condition,
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledge, the master
immediately reissues the start condition and the slave address with the R/W bit set to “1”. Then the AK4711 generates an
acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but generate the stop condition, the AK4711 discontinues transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Sub
Address(n)
Slave
Address
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 12. RANDOM ADDRESS READ
Rev. 0.4
2011/07
- 23 -
[AK4711]
SDA
SCL
S
P
start condition
stop condition
Figure 13. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 14. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 15. Bit transfer on the I2C-bus
Rev. 0.4
2011/07
- 24 -
[AK4711]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register Name
Control
Switch
Reserve
Zerocross
Video switch
Video output enable
Video volume/clamp
S/F Blanking control
Reserve
Reserve
D7
0
1
0
0
0
0
CLAMPB
0
0
0
D6
0
0
0
0
0
TVFB
VCLP1
0
0
0
D5
0
0
0
CAL
0
0
VCLP0
0
0
0
D4
0
1
0
0
RCA1
RCAV
CLAMP2
0
0
0
D3
1
MONO
0
0
RCA0
TVB
CLAMP1
SBT1
0
0
D2
0
1
0
1
1
TVG
1
SBT0
0
0
D1
MUTE
0
0
1
VTV1
TVR
0
FB1
0
0
D0
1
1
0
1
VTV0
TVV
0
FB0
0
0
0AH
HD switch
HDCP1
HDCP0
HDAPW
0
0
0
1
1
0BH
0CH
0DH
HD filter
Sync filter
Volume
0
0
FLPR1
FLPR0
FLPB1
FLPB0
FLY1
FLY0
0
0
FLT
VOL3
0
VOL2
0
VOL1
0
VOL0
0
1
0
1
0
1
When the PDN pin goes “L”, the registers are initialized to their default values.
While the PDN pin = “H”, all registers can be accessed.
Do not write any data to the register over 0DH.
■ Register Definitions
Addr
00H
Register Name
Control
R/W
Default
D7
0
D6
0
D5
0
D4
0
D3
1
D2
0
D1
MUTE
D0
1
1
0
1
1
D2
1
D1
0
D0
1
1
0
1
R/W
0
0
0
0
MUTE: Audio output control
0: Normal operation
1: ALL Audio outputs to GND (default)
Addr
01H
Register Name
Switch
R/W
Default
D7
1
D6
0
D5
0
D4
1
1
0
0
1
D3
MONO
R/W
0
MONO: Mono select for TVOUTL/R pins
0: Stereo. (default)
1: Mono. (L+R)/2
Rev. 0.4
2011/07
- 25 -
[AK4711]
Addr
03H
Register Name
Volume Control
R/W
Default
D7
0
D6
0
D5
CAL
D4
0
0
0
1
0
D3
0
D2
1
D1
1
D0
1
0
1
1
1
R/W
CAL: Offset calibration Enable
0: Offset calibration disable.
1: Offset calibration enable (default)
Addr
04H
Register Name
Video switch
R/W
Default
D7
0
D6
0
D5
0
D4
RCA1
0
0
0
1
D3
RCA0
D2
1
D1
VTV1
D0
VTV0
1
1
0
0
R/W
VTV1-0: Selector for TV video output
Refer to Table 6.
RCA1-0: Selector for RCA video output
Refer to Table 7.
Addr
05H
Register Name
Output Enable
R/W
Default
D7
0
D6
TVFB
D5
0
0
0
0
D4
D3
RCAV
TVB
R/W
0
0
D2
TVG
D1
TVR
D0
TVV
0
0
0
TVV: TVVOUT output control
TVR: TVRCOUT output control
TVG: TVGOUT output control
TVB: TVBOUT output control
RCAV: RCAVOUT output control
TVFB: TVFB output control
0: Hi-Z (default)
1: Active.
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
06H
Video volume
CLAMPB
VCLP1
VCLP0
CLAMP2
CLAMP1
1
0
0
0
1
0
0
R/W
Default
R/W
0
0
0
0
CLAMPB, CLAMP2-1: Clamp control.
Refer to Table 8 and Table 9.
VCLP1-0: DC restore source control
00: ENCV pin (default)
01: ENCY pin
10: (Reserved)
11: ENCG pin
Rev. 0.4
2011/07
- 26 -
[AK4711]
Addr
07H
Register Name
S/F Blanking
R/W
Default
D7
0
D6
0
D5
0
D4
0
0
0
0
0
D3
SBT1
D2
SBT0
D1
FB1
D0
FB0
0
0
0
0
R/W
FB1-0: TV Fast Blanking output control (for TVFB pin)
00: 0V (default)
01: 2V<, 2.5V(typ) at 150Ω load
10: (Reserved)
11: (Reserved)
SBT1-0: TV Slow Blanking output control (for TVSB pin. minimum load is 10kΩ.)
00: < 2V (default)
01: 4.73V <, < 7V
10: (Reserved)
11: 10V <
Addr
Register Name
0AH
HD switch
R/W
default
D7
D6
D5
D4
D3
D2
D1
D0
HDCP1
HDCP0
HDAPW
0
0
0
1
1
0
0
1
1
R/W
0
0
0
0
HDAPW: HD filter power-up bit(HD Video output)
1: HD filter power-up.
0: HD filter power-down (default).
HDCP1-0: HD Video Switch Control
Refer to Table 11.
Addr
Register Name
0BH
HD filter
R/W
default
D7
D6
D5
D4
D3
D2
D1
D0
HDY1
HDY0
FLPR1
FLPR0
FLPB1
FLPB0
FLY1
FLY0
0
0
0
0
R/W
0
0
0
0
HDY1-0: Y Input Control
Refer to Table 12.
FLY1-0, FLPB1-0, FLPR1-0: HD Video Filter Control
Refer to Table 13.
Addr
Register Name
0CH
Sync filter
R/W
default
D7
D6
D5
D4
D3
D2
D1
D0
0
FLT
0
0
0
0
0
0
0
0
0
0
R/W
0
0
0
0
FLT: HD Sync detection filter (500kHz band-width)
1: filter ON in all case
0: filter OFF when HD path is used (default).
Rev. 0.4
2011/07
- 27 -
[AK4711]
Addr
Register Name
0DH
Main volume
D7
D6
D5
D4
D3
D2
D1
D0
0
VOL3
VOL2
VOL1
VOL0
1
1
1
1
1
1
1
R/W
Default
R/W
0
0
0
1
VOL3-0: Volume control
Those registers control both Lch and Rch of Volume.
1011: Volume gain = +24dB
1010: Volume gain = +21dB
1001: Volume gain = +18dB
1000: Volume gain = +15dB
0111: Volume gain = +12dB
0110: Volume gain = +9dB
0101: Volume gain = +6dB
0100: Volume gain = +3dB
0011: Volume gain = +0dB (default)
0010: Volume gain = -3dB
0001: Volume gain = -6dB
0000: MUTE
Rev. 0.4
2011/07
- 28 -
[AK4711]
SYSTEM DESIGN
Analog
3.3V
Analog
3.3V
Figure 16 shows the system connection diagram example. An evaluation board (AKD4711) demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
4.7u +
4.7u
1.0u
+
1.0u
0.1u
AINR- 24
5
VSS3
6
TVVOUT
7
TVFB
VD1 21
8
TVRC
VSS1 20
9
TVG
TVSB 19
AK4711
300
300
0.47u
300
300
21 VP
20 ENCY
19 ENCV
Audio 3.3V
0.1u
0.1u
470
10
75
75
75
+
1u
+
4.7u
Analog
12V
HD Video
0.1u
0.1u
0.1u
75
75
Analog
3.3V
75
0.1u
Analog Ground
0.47u
TVOUTL 23
75
+
0.47u
TVOUTR 22
0.1u
4.7u
0.47u
TV SCART
RACVOUT
300
CINCH Video
4
0.1u
DACR
Digital
Ground
VEE 28
CP 30
CN 29
VD2 32
VSS2 31
SCL 33
SDA 34
HDVVD 36
AINR+ 25
13 TVB
HDRB
300
0.1u
DACL
Micro
75
3
Encoder
MPEG
decoder
VIDEO
75
Controller
Video 3.3V
AINL- 26
18 ENCC
75
AINL+ 27
17 ENRC
75
HDPR
16 ENCG
75
HDY
2
15 ENCB
75
1
14 VVD
75
75
PDN 35
0.1u
Figure 16. Typical Connection Diagram
Rev. 0.4
2011/07
- 29 -
[AK4711]
■ Grounding and Power Supply Decoupling
VD1, VD2, VP, VVD, VSS1, VSS2 and VSS3 should be supplied from analog supply unit with low impedance and be
separated from system digital supply. An electrolytic capacitor 4.7μF parallel with a 0.1μF ceramic capacitor should be
attached to VD1, VD2, VVD, VSS1, VSS2 and VSS3 pin to eliminate the effects of high frequency noise. The 0.1μF
ceramic capacitor should be placed as near to VD1 (VD2, VVD) as possible.
The VP pin must be connected to the Analogue 12V power supply via a 10ohm resistor and with a 0.1µF ceramic
capacitor in parallel with a 1µF electrolytic capacitor to VSS1, as shown in Figure 16.
■ Analog Audio Outputs
The analog outputs are also single-ended and centered on 0V(typ.). The output signal range is typically 2Vrms .
■ Slow Blanking pins
The Slow Blanking Pin must have a 470ohm ±5% series resistor.
Rev. 0.4
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[AK4711]
■ External Circuit Example
The analog audio input pin must have 300ohm series resistor and 0.47uF capacitor.
Analog Audio Input pin
300Ω
AINR+
AINRAINL+
AINL-
0.47μF
Analog Audio Output pin
TVOUTL/R
300Ω
(Cable)
Total > 4.5kΩ
Analog Video Input pin
75Ω
(Cable)
ENCV, ENCY, ENCRC,
ENCC, ENCG, ENCB,
0.1μF
75Ω
Analog Video Output pin
75Ω
TVVOUT, TVRC
TVG,TVR,TVB,
RCAVOUT, HDY,
HDPR, HDPB
(Cable)
max
400pF
max
15pF
Rev. 0.4
75Ω
2011/07
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[AK4711]
Slow Blanking pin
TVSB
(Cable)
470Ω ±5%
max 3nF
(with 470Ω)
min: 10kΩ
Fast Blanking Output pin
75Ω
TVFB
(Cable)
75Ω
Rev. 0.4
2011/07
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[AK4711]
PACKAGE
36pin QFN (Unit: mm)
TOP VIEW
BOTTOM VIEW
0.90
5.00 ± 0.10
0.28 ± 0.10
#27
#18
#28
A
1.30
#36
#10
#9
B
#1
0.07
0.20 ± 0.05
MS
AB
0.35 ± 0.1
0.28 ± 0.10
0.90
#19
5.00 ± 0.10
1.30
C0.35
0.10 S
S
0.40
0.75 ± 0.05
0.20
0.08 S
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
Rev. 0.4
2011/07
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[AK4711]
MARKING
4711
XXXX
1
XXXX : Date code (4 digit)
Pin #1 indication
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
Rev. 0.4
2011/07
- 34 -