AKM AKD4709

[AK4709]
AK4709
Low Power AV SCART Switch
GENERAL DESCRIPTION
The AK4709 is an I C controlled audio and video switch which has a matrix designed architecture for
digital TV and set-top-box applications. The AK4709 offers the ideal features for digital set-top-box
systems. The AK4709 includes audio switches, video switches, and video filters. The integrated audio
driver supports ground referenced outputs, eliminating the need for large AC-coupling capacitors,
reducing cost and saving board space. The AK4709 is housed in a space saving small 48-pin LQFP
package.
2
FEATURES
Analog switches for SCART
Audio section
† THD+N: −95dB (@2Vrms)
† Dynamic Range: 99dB (@2Vrms), (A-weighted)
† Stereo Analog Volume with Pop-noise Free Circuit (+6dB to –60dB &
Mute)
† Analog Inputs
One Full Differential Stereo Input or Single-ended input for Decoder
DAC
Two Stereo Input (TV & VCR SCART)
† Analog Outputs
Two Stereo Outputs (TV & VCR SCART)
† Ground-Referenced Outputs Eliminate DC-Blocking Capacitor
Video section
† Integrated LPF: [email protected]
† 75ohm driver
† 6dB Gain for Outputs
† Four CVBS/Y inputs (ENCx2, TV, VCR), Two CVBS/Y outputs (TV, VCR)
† Three R/C inputs (ENCx2, VCR), Two R/C output (TV, VCR)
† Two G and B inputs (ENC, VCR), One G and B outputs (TV)
† Bi-Directional Control for VCR-Red/Chroma
† Y/Pb/Pr Option (to 6MHz)
TV/VCR input monitor
Loop-through Mode for standby
Auto-Startup Mode for power saving
SCART pin#16 (Fast Blanking), pin#8 (Slow Blanking) Control
Power supply
† 3.3V+/−5% and 12V+/−10%
† Low Power Dissipation / Low Power Standby Mode
Package
† Small 48pin LQFP
MS1319-E-00
2011/07
-1-
[AK4709]
■ Block Diagram
-6dB to +24dB
+6 to -60dB
(3dB/step)
(2dB/step)
AINL+
TVOUTL
AINLAMP
AINR-
TVOUTR
AINR+
MONO
Volume #1
Volume #0
TV1-0
VD1
VSS1
VCRINL
VCRINR
TVINL
VCROUTL
VCROUTR
TVINR
VMONO
SCL
Register
SDA
Control
VCR1-0
Bias
Charge Pump
PDN
CP
CN
VEE
VSS2
VD2
Audio Block
MS1319-E-00
2011/07
-2-
[AK4709]
( Typical connection )
VVD1
VVD2
( Typical connection )
Monitor
VSS3
ENC CVBS/Y
ENC Y
VCR CVBS/Y
TV CVBS
ENC R/C/Pr
ENC C
VCR R/C/Pr
ENCV
ENCY
6dB
TVVOUT
6dB
TVRC
VCRVIN
TVVIN
ENCRC
ENCC
TV SCART
VCRRC
ENC G/CVBS
ENCG
VCR G
VCRG
ENC B/Pb
ENCB
VCR B/Pb
VCRB
6dB
TVG
6dB
TVB
6dB
VCRVOUT
VCR SCART
6dB
VCRC
Video Block
MS1319-E-00
2011/07
-3-
[AK4709]
( Typical connection )
( Typical connection )
VCR FB
VCRFB
3.0V
0V
6dB
TVFB
FB [1:0]
TV SCART
0/ 6/ 12V
TVSB
SBT [1:0]
VCRSB
0/ 6/ 12V
VCR SCART
SBV [1:0]
Monitor
INT
VP
Video Blanking Block
MS1319-E-00
2011/07
-4-
[AK4709]
■ Ordering Guide
AK4709EQ
AKD4709
-10 ∼ +70°C
48pin LQFP (0.5mm pitch)
Evaluation board for AK4709
VD1
VCRINR
VCRINL
TVINR
TVINL
VCROUTR
VCROUTL
TVOU TR
TVOUTL
AINR-
AINR+
AINL-
■ Pin Layout
36 35 34 3 3 32 31 30 2 9 28 27 26 25
AINL+
37
24
VSS1
VEE
38
23
TVSB
CN
39
22
VC RSB
CP
40
21
VP
VSS2
41
20
VCRB
VD2
42
19
VCRG
INT
43
18
VCRR C
17
VC RFB
AK4709EQ
Top View
VC RVOUT
47
14
EN CY
TVFB
48
13
EN CV
3
4
5
6
7
8
9
MS1319-E-00
ENCC
2
ENCRC
1
10 11 12
ENCG
TVVIN
ENCB
15
VVD 1
46
TVB
PDN
TVG
VC RVIN
TVRC
16
VVD2
45
TVVOUT
SDA
VSS3
44
VCRC
SCL
2011/07
-5-
[AK4709]
PIN/FUNCTION
No.
1
2
3
Pin Name
VCRC
VSS3
TVVOUT
I/O
O
O
4
VVD2
-
5
6
7
TVRC
TVG
TVB
O
O
O
8
VVD1
-
9
10
11
12
13
14
15
16
17
18
19
20
ENCB
ENCG
ENCRC
ENCC
ENCV
ENCY
TVVIN
VCRVIN
VCRFB
VCRRC
VCRG
VCRB
I
I
I
I
I
I
I
I
I
I
I
I
21
VP
-
22
VCRSB
23
TVSB
O
24
VSS1
-
25
VD1
-
26
27
28
29
30
31
32
33
VCRINR
VCRINL
TVINR
TVINL
VCROUTR
VCROUTL
TVOUTR
TVOUTL
I
I
I
I
O
O
O
O
I/O
Function
Chrominance Output Pin for VCR
Video Ground Pin , 0V
Composite/Luminance Output Pin for TV
Video Power Supply Pin #2: 3.13V ~ 3.47V
Normally connected to VSS3 with a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic capacitor.
Red/Chrominance Output Pin for TV
Green Output Pin for TV
Blue Output Pin for TV
Video Power Supply Pin #1: 3.13V ~ 3.47V
Normally connected to VSS3 with a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic capacitor.
Blue Input Pin for Encoder
Green Input Pin for Encoder
Red/Chrominance Input Pin #1 for Encoder
Chrominance Input Pin #2 for Encoder
Composite/Luminance Input Pin #1 for Encoder
Composite/Luminance Input Pin #2 for Encoder
Composite/Luminance Input Pin for TV
Composite/Luminance Input Pin for VCR
Fast Blanking Input Pin for VCR
Red/Chrominance Input Pin for VCR
Green Input Pin for VCR
Blue Input Pin for VCR
Blanking Power Supply Pin, 10.8V ~ 13.2V
The VP pin must be connected to the Analogue 12V power supply via a 10ohm resistor
and with a 0.1µF ceramic capacitor in parallel with a 1µF electrolytic capacitor to
VSS1, as shown in Figure 20.
Slow Blanking Input/Output Pin for VCR, refer to Table 20.
A 470ohm ±5% resistor must be connected between the VCRSB pin and SCART
connector.
Slow Blanking Output Pin for TV
A 470ohm ±5% resistor must be connected between the TVSB pin and SCART
connector.
Audio Ground Pin , 0V
Audio Power Supply Pin: 3.13V ~ 3.47V
Normally connected to VSS1 with a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic capacitor.
Rch VCR Audio Input Pin
Lch VCR Audio Input Pin
Rch TV Audio Input Pin
Lch TV Audio Input Pin
Rch Analog Output Pin #1
Lch Analog Output Pin #1
Rch Analog Output Pin #2
Lch Analog Output Pin #2
MS1319-E-00
2011/07
-6-
[AK4709]
No.
34
35
36
37
Pin Name
AINRN
AINRP
AINLN
AINLP
I/O
I
I
I
I
38
VEE
O
39
CN
I
40
CP
I
41
VSS2
-
42
VD2
-
43
INT
O
44
45
SCL
SDA
I
I/O
46
PDN
I
47
VCRVOUT
O
Function
Rch Negative Analog Input Pin
Rch Positive Analog Input Pin
Lch Negative Analog Input Pin
Lch Positive Analog Input Pin
Negative Voltage Output Pin
Connect to VSS2 with a 1.0μF capacitor that should have the low ESR (Equivalent
Series Resistance) over all temperature range. When this capacitor has the polarity,
the positive polarity pin should be connected to the VSS2 pin. Non polarity capacitors
can also be used.
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF capacitor that should have the low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity, the
positive polarity pin should be connected to the CP pin. Non polarity capacitors can
also be used.
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF capacitor that should have the low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity, the
positive polarity pin should be connected to the CP pin. Non polarity capacitors can
also be used.
Charge Pump Ground Pin , 0V
Charge Pump Power Supply Pin: 3.13V ~ 3.47V
Normally connected to VSS2 with a 0.1μF ceramic capacitor in parallel with a 4.7μF
electrolytic cap.
Interrupt Pin for Video Blanking
Normally connected to VVD1(3.3V) through 10kΩ resistor externally.
I2C Control Data Clock Pin
I2C Control Data Pin
Power-Down Mode Pin
When at “L”, the AK4709 is in the power-down mode and is held in reset. The
AK4709 should always be reset upon power-up.
Composite/Luminance Output Pin for VCR
48 TVFB
O
Fast Blanking Output Pin for TV
Note: SCL, SDA, PDN pins should not be left floating.
MS1319-E-00
2011/07
-7-
[AK4709]
ABSOLUTE MAXIMUM RATINGS
(VSS1 =VSS2 =VSS3 = 0V; Note 1)
Parameter
Power Supply
(Note 2)
Symbol
VD1
VD2
VVD1
VVD2
VP
IIN
VIND1
VIND2
VINV
VINA
Ta
Tstg
Min
−0.3
-0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
VEE-0.3
−10
−65
max
4.0
4.0
4.0
4.0
14
±10
VVD1+0.3
4.0
VVD1+0.3
VD1+0.3
70
150
Input Current (any pins except for supplies)
Digital Input Voltage(PDN pin)
Digital Input Voltage(SCL, SDA pins)
Video Input Voltage
Audio Input Voltage
(Note 3)
Ambient Operating Temperature
Storage Temperature
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 and VSS3 must be connected to the same analog ground plane.
Note 3. VEE: VEE pin voltage.
The internal negative power supply generating circuit provides negative power supply(VEE).
The PDN pin, AUTO bit, MUTE bit, STBY bit and AMP bit control operation mode as shown
in Table 2 and Table 3.
2
3
4
Mode
Full Power-down
Auto Startup mode
(Power-on default)
Standby & mute
Standby
Mute
5
Normal operation
0
1
Units
V
V
V
V
V
mA
V
V
V
V
°C
°C
VEE pin Voltage
No video input
Video input
No video input
Video input
Table 1. VEE pin voltage
0V
-VD2+0.2V
0V
-VD2+0.2V
0V
0V
-VD2+0.2V
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
MS1319-E-00
2011/07
-8-
[AK4709]
RECOMMENDED OPERATING CONDITIONS
(VSS1 =VSS2 =VSS3 = 0V; Note 1)
Parameter
Symbol
Min
typ
Power Supply
(Note 4)
VD1
3.13
3.3
VD2
3.13
3.3
VVD1
3.13
3.3
VVD2
3.13
3.3
VP
10.8
12
Note 1. All voltages with respect to ground.
Note 4. VVD1 and VVD2 must be connected to the same voltage.
max
3.47
3.47
3.47
3.47
13.2
Units
V
V
V
V
V
*AKM assumes no responsibility for the usage beyond recommended operating conditions in this datasheet.
ELECTRICAL CHARACTERISTICS
(Ta = 25°C; VP = 12V, VD1 = VD2 = VVD1 = VVD2 = 3.3V)
Power Supplies
min
typ
max
Power Supply Current
Normal Operation (PDN = “H”)
VD1+VD2+VVD1+VVD2
(No load, Note 5)
0.49
0.74
VD1+VD2+VVD1+VVD2
(With load, Note 6)
85
VP
80
120
Power-Down Mode (PDN = “L”)
(Note7)
VD1+VD2
0
10
VVD1+VVD2
0
10
VP
80
120
Note 5. STBY bit = “0”, All video outputs active. No signal, no load for A/V switches.
Note 6. All video outputs active.
Audio Output: 1kHz 2Vrms output with 4.5kΩ load at all audio output pins.
Video Output: 100% color bar output with 150Ω load at all video output pins.
Slow Blanking (default setting): SBIO1-0 bits= “00”, SBT1-0 bits= “00”, SBV1-0 bits= “00”
Note7. All digital inputs are held at VVD1 or VSS3. No signal, no load for A/V switches.
DIGITAL CHARACTERISTICS
(Ta = 25°C; VD1 = VD2 = VVD1 = VVD2 = 3.13 ∼ 3.47V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%VVD1
Low-Level Input Voltage
VIL
Low-Level Output Voltage
VOL
(SDA pin: Iout= 3mA, INT pin: Iout= 1mA)
Input Leakage Current
Iin
-
MS1319-J-00
Units
mA
mA
μA
μA
μA
μA
typ
-
max
30%VVD1
0.4
Units
V
V
V
-
± 10
μA
2011/07
-9-
[AK4709]
ANALOG CHARACTERISTICS (AUDIO)
(Ta=25°C; VP=12V, VD1=VD2=VVD1=VVD2=3.3V; Signal Frequency=1kHz; Measurement frequency=20Hz ∼
20kHz; RL ≥4.5kΩ; 0dB=2Vrms output; Volume#0=Volume#1=0dB, unless otherwise specified)
Parameter
min
typ
max
Units
Analog Input: (TVINL/TVINR/VCRINL/VCRINR pins)
Analog Input Characteristics
Input Voltage
(Note 6)
2.0
Vrms
Input Resistance
100
150
kΩ
Analog Input: (AINL+/AINL-/AINR-/AINR+ pins)
Analog Input Characteristics
2.0
Vrms
Input Voltage
(AIN+) − (AIN−),
(Note 6)
Input Resistance
80
125
kΩ
Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR pins)
(Note 7)
Analog Output Characteristics
Volume#0 Step Width
2.3
3.0
3.7
dB
Volume#1 Step Width (+6dB to –12dB)
1.6
2
2.4
dB
(-12dB to –40dB)
0.5
2
3.5
dB
(-40dB to –60dB)
0.1
2
3.9
dB
THD+N (at 2Vrms, Note 9, Note 10, Note 11)
dB
−95
−84
92
99
dB
Dynamic Range (−60dB Output, A-weighted, Note 9)
S/N (A-weighted)
92
99
dB
(2Vrms output , Vo1#0=Vo1#1=0dB, Note 9, Note 13)
Interchannel Isolation
(Note 9, Note 12)
80
110
dB
Interchannel Gain Mismatch
(Note 9, Note 12)
-0.5
0
+0.5
dB
DC offset
(Note 14)
-5
0
+5
mV
Gain Drift
200
ppm/°C
Load Resistance
TVOUTL/R, VCROUTL/R
4.5
kΩ
Load Capacitance
TVOUTL/R, VCROUTL/R
20
pF
Output Voltage
(Note 8)
1.85
2
2.15
Vrms
Power Supply Rejection (PSR)
(Note 15)
50
dB
Note 6. f = 1kHz, THD+N < -80dB, gain = 0dB(Volume#0=Volume#1=0dB)
Note 7. Measured by Audio Precision System Two Cascade.
Note 8. The output level of the internal AMP with volume #0 should be less than 2Vrms.
The output level must be adjusted by the volume #1 when output level of the AK4709 exceeds 2Vrms.
The audio output must not exceed 2.15Vrms.
Note 9. Analog In to TVOUT/VCROUT.
Path: AINL+/- → TVOUTL, AINR+/- → TVOUTR, AINL+/- → VCROUTL, AINR+/- → VCROUTR
Volume#0=Volume#1=0dB.
Note 10. Differential Input. -86dB(typ) at VD= 3.13V
When single-ended Input,-90dB(typ) at f = 1kHz. -75dB(typ) at f = 10kHz
Note 11. -78dB (typ) referred to 0.5Vrms output level at Volume#0=+24dB, Volume#1= 0dB.
-80dB (typ) reffered to 0.5Vrms output level at Volume#0 = +21dB, Volume#1=0dB
Path: AINL+/- → TVOUTL, AINR+/- → TVOUTR, AINL+/- → VCROUTL, AINR+/- → VCROUTR
Note 12. Between TVOUTL and TVOUTR with analog inputs AINL+/−, AINL/R+/−, 1kHz/0dB.
Note 13. Analog In to TVOUT/VCROUT.
Path: AINL+/- → TVOUTL, AINR+/- → TVOUTR, AINL+/- → VCROUTL, AINR+/- → VCROUTR
81dB (typ) volume#0 = +24dB, Volume#1= 0dB
83dB (typ) volume#0 = +21dB, Volume#1= 0dB
Note 14. Analog In to TVOUT. Volume#0=Volume#1=0dB
Path: AINL+/- → TVOUTL, AINR+/- → TVOUTR, VCRINL → TVOUTL, VCRINR → TVOUTR
Note 15. The PSR is applied to VD1 and VD2 with 1kHz, 100mV.
MS1319-E-00
2011/07
- 10 -
[AK4709]
ANALOG CHARACTERISTICS (VIDEO)
(Ta = 25°C; VP = 12V, VD1=VD2= VVD1 = VVD2 = 3.3V; unless otherwise specified.)
Parameter
Conditions
min
Sync Tip Clamp Voltage
at output pin.
R/G/B Clamp Voltage
at output pin.
Pb/Pr Clamp Voltage
at output pin.
Chrominance Bias Voltage
at output pin.
Gain
Input = 0.3Vp-p, 100kHz
5.5
Interchannel Gain Mismatch1 TVRC, TVG, TVB. Input = 0.3Vp-p, 100kHz.
-0.5
VCRC, VCRGO, VCRBO.
Interchannel Gain Mismatch2
-0.5
Input = 0.3Vp-p, 100kHz.
Frequency Response
Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz.
-1.0
at 10MHz.
at 27MHz.
Group Delay Distortion
At 4.43MHz with respect to 1MHz.
Input Impedance
Chrominance input (internally biased)
40
Input Signal
f = 100kHz, maximum with distortion < 1.0%,
gain = 6dB.
Load Resistance
150
(Figure 1)
Load Capacitance
C1 (Figure 1)
C2 (Figure 1)
Dynamic Output Signal
f = 100kHz, maximum with distortion < 1.0%
Y/C Crosstalk
f = 4.43MHz, 1Vp-p input. Among TVVOUT,
TVRC and VCRVOUT outputs.
S/N
Reference Level = 0.7Vp-p, CCIR 567 weighting.
BW = 15kHz to 5MHz.
Differential Gain
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
Differential Phase
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
typ
0.24
0.24
1.49
1.49
6
-
max
6.5
0.5
Units
V
V
V
V
dB
dB
-
0.5
dB
0.5
60
-20
20
-
dB
dB
dB
ns
kΩ
-
1.25
Vpp
-
-
400
15
2.5
Ω
pF
pF
Vpp
−50
-
dB
74
-
dB
0.6
-
%
0.8
-
Degree
-3
-40
R1
75 ohm
Video Signal Output
R2
75 ohm
C1
C2
max: 15pF
max: 400pF
Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2.
MS1319-E-00
2011/07
- 11 -
[AK4709]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP = 10.8 ∼ 13.2V, VD1=VD2= VVD1 = VVD2 = 3.13 ∼ 3.47V)
Parameter
Symbol
min
typ
max
Units
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
μs
Start Condition Hold Time
tHD:STA
0.6
μs
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
μs
Clock High Time
tHIGH
0.6
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
μs
SDA Hold Time from SCL Falling (Note 16) tHD:DAT
0
μs
SDA Setup Time from SCL Rising
tSU:DAT
0.1
μs
Rise Time of Both SDA and SCL Lines
tR
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
μs
Pulse Width of Spike Noise
tSP
0
50
ns
Suppressed by Input Filter
Capacitive load on bus
Cb
400
pF
Reset Timing
tPD
150
ns
PDN Pulse Width
(Note 17)
Note 16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 17. The AK4709 should be reset once by bringing the PDN pin = “L” after all power supplies are supplied.
Note 18. I2C-bus is a trademark of NXP B.V.
MS1319-E-00
2011/07
- 12 -
[AK4709]
■ Timing Diagram
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
I2C Bus mode Timing
tPD
PDN
VIL
Power-down Timing
MS1319-E-00
2011/07
- 13 -
[AK4709]
OPERATION OVERVIEW
1. System Reset and Power-down options
The AK4709 should be reset once by bringing PDN pin = “L” after all power supplies are supplied. The AK4709 has
several operation modes. The PDN pin, AUTO bit, MUTE bit, STBY bit and AMP bit control operation mode as shown
in Table 2and Table 3.
■ System Reset and Full Power-down Mode
The AK4709 should be reset once by bringing PDN pin = “L” after all power supplies are supplied.
PDN pin: Power down pin
L: Full Power-down Mode. Power-down, reset and initializes the control register.
H: Device active.
■ Auto Startup Mode
After the PDN pin is set to “H”, the AK4709 is in the auto startup mode. In this mode, all blocks except for the video
detection circuit are powered down (Low power mode). Once the video detection circuit detects video signal from
TVVIN pin or VCRVIN pin, the AK4709 goes to the stand-by mode automatically and sends “L” pulse via INT pin. The
sources of TVOUTL/R are fixed to VCRINL/R, the sources of VCROUTL/R are fixed to TVINL/R respectively. The
source of DC- restore circuit is VCRVIN pin. To exit the auto startup mode, set the AUTO bit to “0”.
AUTO bit (00H D3): Auto startup bit
0: Auto startup disable. (Manual startup)
1: Auto startup enable. (default)
■ Mute Mode
When the MUTE bit = “1” and AUTO bit= “0”, the audio outputs settle to VSS(0V, typ) and the charge pump circuit is in
power down mode.
MUTE bit (00H D1): Audio output control
0: Normal operation.
1: All audio outputs to GND (default)
■ Standby Mode
When the AUTO bit = MUTE bit = “0” and the STBY bit = “1”, the AK4709 is forced into TV-VCR loop through mode.
In this mode, the sources of TVOUTL/R pins are fixed to VCRINL/R pins; the sources of VCROUTL/R are fixed to
TVINL/R pins respectively. All register values are NOT changed by STBY bit = “1”.
STBY bit (00H D0): Standby bit
0: Normal operation.
1: Standby mode. (default)
MS1319-E-00
2011/07
- 14 -
[AK4709]
Mode
0
PDN pin
“L”
AUTO bit
x
STBY bit
x
MUTE bit
x
1
“H”
1
x
x
2
3
“H”
“H”
0
0
1
1
1
0
4
“H”
0
0
1
5
“H”
0
0
0
Mode
Full Power-down
Auto Startup mode
(Power-on default)
Standby & Mute
Standby
Mute (Note 19)
(AMP power down)
Normal operation
(AMP operation)
Note 19. TVOUTL/R are muted by Mute bit in the default state.
Table 2. Operation Mode Settings (x: Don’t Care)
Register
Control
NOT
available
Mode
0 Full Power-down
Auto Startup mode
1
(Power-on default)
No video
input
Video input
(Note 21)
Audio
Charge pump
Video
Output
TVFB
VCRSB
TVSB
Power
Consumption
Hi-Z
Hi-Z
Pull
-down
(Note 20)
1mW (typ)
Power down
Active
2 Standby & mute
Power down
Active
(Note 22)
Hi-Z
290mW(typ)
(Note 23)
2.5mW(typ)
(Note 24)
Active
(Note 25)
260mW (typ)
(Note 23)
Hi-Z
3 Standby
Available
Active
Active
(Note 25)
Hi-Z
4
Mute
(AMP power down)
No video
input
5
Normal operation
(AMP operation)
Video input
2.5mW(typ)
2.5mW (typ)
(Note 24)
Active
Active
290mW(typ)
(Note 23)
2.5mW(typ)
(Note 24)
Power down
Active
(Note 25)
Power down
Hi-Z
2.5mW(typ)
Hi-Z
2.5mW(typ)
Active
(Note 25)
290mW(typ)
(Note 23)
Active
260mW (typ)
(Note 23)
Note 20. Internally pulled down by 120kΩ (typ) resistor.
Note 21. Video input to TVVIN or VCRVIN.
Note 22. VCRC output 0V for termination.
Note 23. All video outputs active.
Audio Output: 1kHz 2Vrms output, Video Output: 100% color bar output.
Slow Blanking (default setting): SBIO1-0 bits= “00”, SBT1-0 bits= “00”, SBV1-0 bits= “00”
Note 24. All video Amp power down.
Note 25. The video output status is Hi-Z (default) when output enable register (05H) is “0”, and it is Active when output
enable register (05H) is “1”.
Table 3. Status of each operation mode
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[AK4709]
■ Typical Operation Sequence (auto setup mode)
The Figure 2 shows an example of the system timing at auto startup mode.
Auto startup enable
PDN pin
Low Power Mode
Low Power Mode
AUTO bit
Low Power Mode
“1”(default)
TVVIN
don’t care
VCRVIN
don’t care
No Signal
Signal in
No Signal
Signal in
No Signal
No Signal
Signal in
125ms(MAX)
don’t care
No Signal
don’t care
125ms(MAX)
Video Detect
TVVOUT,
VCRVOUT
Audio out (DC)
Hi-Z
Active (loop-through)
Hi-Z
Active (loop-through)
Active (loop-through)
(GND)
Hi-Z
Active (loop-through)
50ms(MAX)
50ms(MAX)
Charge pump
Figure 2. Auto Startup Mode Sequence
■ Typical Operation Sequence (except auto setup mode)
Figure 3 shows an example of the system timing at normal operation mode.
PDN pin
AUTO bit
MUTE bit
STBY bit
Video Signal
Video Detect
Video Output
TV-Source
select
TVOUTL/R
“Stand-by“
“Normal“
“Mute”
“1” (default)
“Stand-by“
“0”
“1” (default)
“0”
“1”
“1” (default)
“1”
“0”
“1”
“0”
No Signal
No Signal
Signal In
125ms(MAX)
Hi-z
fixed to VCR in(Loop-through)
“Stand-by
(GND)
Hi-z
Active
AMP
VCR in
VCR in
fixed to VCR in(Loop-through)
&
“Stand-by
VCR in
VCR in
AMP
AMP
50ms(MAX)
50ms(MAX) 50ms(MAX)
Charge pump
“Normal“
(Note26)
VCR in
&
VCR in
50ms(MAX)
(Note26)
Note 26. Mute the analog outputs externally if click noise affects the system.
Figure 3. Typical Operating Sequence
MS1319-E-00
2011/07
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[AK4709]
2. Audio Block
■ Switch Control
The AK4709 has switch matrixes designed primarily for SCART routing. Those are controlled via the control register as
shown in Table 4 and Table 5 (Please refer to the Block Diagram).
(01H: D1-D0)
TV1
TV0
Source of TVOUTL/R
0
0
AMP
0
1
VCRIN
(default)
1
0
Mute
1
1
(Reserved)
Table 4. TVOUT Switch Configuration
(01H: D5-D4)
VCR1
VCR0
Source of VCROUTL/R
0
0
AMP
0
1
TVIN
(default)
1
0
Mute
1
1
Volume#1 output
Table 5. VCROUT Switch Configuration
■ Volume Control #0 (11-Level Volume)
The AK4709 has a 11-level volume control (Volume #0) as shown in Table 6. The volume reflects the change of register
value immediately.
AINL/R+
1Vrms
2Vrms
Volume Gain 0dB
300Ω
2Vrms differential
input
0.47μ
TVOUTL/R
300Ω
0.47μ
1Vrms
AINL/R-
Volume #0
(VCROUTL/R)
Figure 4. Volume #0(Volume Gain=0dB: default), Full Differential Stereo Input
(0DH: D6-D3)
VOL3
VOL2
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
Note: Volume #1=0dB
VOL1
x
1
1
0
0
1
1
0
0
1
1
0
0
VOL0
x
1
0
1
0
1
0
1
0
1
0
1
0
Volume #0 Gain
NA
+24dB
+21dB
+18dB
+15dB
+12dB
+9dB
+6dB
+3dB
0dB
-3dB
-6dB
Mute
Output Level (Typ)
2Vrms (with 0.13Vrms differential input)
2Vrms (with 0.25Vrms differential input)
2Vrms (with 0.5Vrms differential input)
2Vrms (with 1Vrms differential input)
2Vrms (with 2Vrms differential input: default)
1Vrms (with 2Vrms differential input)
(x: Don’t care)
Table 6. Volume #0, Full Differential Stereo Input
MS1319-E-00
2011/07
- 17 -
[AK4709]
2Vrms
2Vrms
AINL/R+
0.47μ
300Ω
Volume Gain 0dB
AINL/R300Ω
0.47μ
TVOUTL/R
Volume #0
(VCROUTL/R)
Figure 5. Volume #0(Volume Gain=0dB:default), Single-ended Input
(0DH: D6-D3)
VOL3
VOL2
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
Note: Volume #1=0dB
VOL1
x
1
1
0
0
1
1
0
0
1
1
0
0
VOL0
x
1
0
1
0
1
0
1
0
1
0
1
0
Volume #0 Gain
NA
+24dB
+21dB
+18dB
+15dB
+12dB
+9dB
+6dB
+3dB
0dB
-3dB
-6dB
Mute
Output Level (Typ)
2Vrms (with 0.13Vrms input)
2Vrms (with 0.25Vrms input)
2Vrms (with 0.5Vrms input)
2Vrms (with 1Vrms input)
2Vrms (with 2Vrms input: default)
1Vrms (with 2Vrms input)
(x: Don’t care)
Table 7. Volume #0, Single-ended Input
MS1319-E-00
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[AK4709]
■ Volume Control #1 (Main Volume)
The AK4709 has main volume control (Volume #1) as shown in Table 8.
(02H: D5-D0)
L5
L4
L3
L2
L1
L0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
…
…
…
…
…
…
0
0
0
0
0
1
0
0
0
0
0
0
Note: The output must not exceed 2.15Vrms.
Table 8. Volume #1
Gain
+6dB
+4dB
+2dB
0dB
…
-60dB
Mute
(default)
When the MOD bit = “1”(default), changing volume levels does not cause pop noise. MDT1-0 bits select the transition
time (Table 9). When the new gain value 1EH(-2dB) is written to gain resistor while the actual (stable) gain is 1FH(0dB),
the gain changes to 1EH(-2dB) within the transition time selected by MDT1-0 bits. The built-in volume controller
compares the actual gain to the value of gain register after finishing the transition time, and re-changes the actual gain to
new resister value within the transition time if the register value is different from the actual gain when compared. When
the MOD bit = “0” then there is no transition time and the gain changes immediately. This change may cause a click noise.
WR
[Gain=1EH]
Gain Register
1FH
WR
[Gain=1DH]
WR
[Gain=1CH]
1DH
1EH
compare
Actual Gain
1FH (to 1EH)
1CH
compare
1EH
(to 1DH)
compare
(to 1CH)
1CH
1DH
Transition Time (5.3ms to 42.7ms pop free.)
Figure 6. Volume Change Operation (MOD bit = “1”)
MDT1
0
0
1
1
MDT0
Transition Time
0
5.3ms
1
10.7ms
0
21.3ms
1
42.7ms
Table 9. Volume Transition Time (typ.)
MS1319-E-00
(default)
2011/07
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[AK4709]
■ Analog output block
The AK4709 has chargepump circuit generating negative power supply rail from a 3.3V(typ) power supply. (Figure 7)
It allows the AK4709 to output audio signal centered at VSS (0V, typ) as shown in Figure 8. Negative power generating
circuit (Figure 7) needs 1.0uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). When using capacitors
with a polarity, the positive side should be connected to CP and VSS2 for capacitor Ca and Cb, respectively. When the
MUTE bit = “1”, the charge pump circuit is in power down mode and its analog outputs become VSS (0V, typ).
AK4709
VD
Charge
Pump
CP
Negative Power
CN
VSS2
(+)
1uF
Ca
Cb
(+)
VEE
1uF
Figure 7. Negative power generate circuit
AK4709
2Vrms
0V
TVOUTR/TVOUTL
(VCROUTR/VCROUTL)
Figure 8. Audio signal output
MS1319-E-00
2011/07
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[AK4709]
3. Video Block
■ Video Switch Control
The AK4709 has switches for TV and VCR. Each switch can be controlled via the registers independently. When AUTO
bit = “1” or STBY bit = “1”, these switches setting is ignored and set to fixed configuration (loop-through mode). Please
refer the auto startup mode and standby mode.
(04H: D2-D0)
Mode
VTV2-0 bit
Shutdown
Encoder
CVBS+RGB
or Encoder YPbPr
000
Encoder Y/C 1
010
Encoder Y/C 2
011
VCR (default)
100
TV CVBS
101
(Reserved)
(Reserved)
110
111
001
Source of
Source of
TVVOUT pin
TVRC pin
(Hi-Z)
(Hi-Z)
ENCV pin
ENCRC pin
(Encoder CVBS
(Encoder Red,C
or Y)
or Pb)
ENCV pin
ENCRC pin
(Encoder Y)
(Encoder C)
ENCY pin
ENCC pin
(Encoder Y)
(Encoder C)
VCRVIN pin
VCRRC pin
(VCR CVBS
(VCR Red,C
or Y)
or Pb)
TVVIN pin
(Hi-Z)
(TV CVBS)
Table 10. TV video output (Note 27)
Source of
TVG pin
(Hi-Z)
ENCG pin
(Encoder Green
or Y)
Source of
TVB pin
(Hi-Z)
ENCB pin
(Encoder Blue
or Pr)
(Hi-Z)
(Hi-Z)
(Hi-Z)
(Hi-Z)
VCRG pin
(VCR Green
or Y)
VCRB pin
(VCR Blue
or Pr)
(Hi-Z)
(Hi-Z)
-
-
(04H: D5-D3)
Source of
Source of
VCRVOUT pin
VCRC pin
Shutdown
000
(Hi-Z)
(Hi-Z)
ENCV pin
ENCRC pin
Encoder CVBS or Y/C 1
001
(Encoder CVBS
(Encoder C)
or Y)
ENCY pin
ENCC pin
Encoder CVBS or Y/C 2
010
(Encoder CVBS
(Encoder C)
or Y)
TVVIN pin
TV CVBS (default)
011
(Hi-Z)
(TV CVBS)
VCRVIN pin
VCRRC pin
VCR
100
(VCR CVBS)
(VCR Red, C)
(Reserved)
101
(Reserved)
110
(Reserved)
111
Table 11. VCR video output (Refer Note 27)
Mode
VVCR2-0 bit
Note 27. When input the video signal via ENCRC pin or VCRRC pin, set CLAMP1-0 bits respectively.
2011/07
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[AK4709]
■ Video Output Control (05H: D6-D0,)
Each video output can be set to Hi-Z individually via the control registers. These settings are ignored when the AUTO bit
= “1”.
TVV: TVVOUT output control
TVR: TVRCOUT output control
TVG: TVGOUT output control
TVB: TVBOUT output control
VCRV: VCRVOUT output control
VCRC: VCRC output control
TVFB: TVFB output control
0: Hi-Z. (default)
1: Active.
■ RGB/Chroma Bi-directional Control for VCR SCART (05H: D7, D5)
The AK4709 supports the bi-directional RGB/Chroma signal on the VCR SCART.
(CIO bit &
VCRC bit)
#15 pin
75
VCRC
pin
VCRRC
pin
VCR SCART
0.1u
(AK4709)
Figure 9. VCR Red/Chroma Bi-directional Control
CIO
0
0
1
1
VCRC
State of VCRC pin
(default)
0
Hi-z
1
Active
0
Connected to GND
1
Connected to GND
Table 12. VCR Red/Chroma Bi-directional Control
2011/07
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[AK4709]
■ Clamp and DC-restore circuit control (06H: D7-D2)
Each CVBS and Y input has the sync tip clamp circuit. The DC-restore circuit has two clamp voltages 0.24V(typ) and
1.49V(typ) to support both RGB and YPbPr signal. They correspond to 0.12V(typ) and 0.75V(typ) at the SCART
connector when matched by 75Ω resistors. The CLAMP1, CLAMP0 and CLAMPB bits select the input circuit for
ENCRC pin (Encoder Red/Chroma), ENCB pin (Encoder Blue), VCRRC pin (VCR Red/Chroma) and VCRB pin (VCR
Blue) respectively. VCLP2-0 bits select the sync source of DC- restore circuit.
CLAMPB
CLAMP0
0
0
0
1
1
0
1
1
CLAMPB
CLAMP1
0
0
0
1
1
0
1
1
VCRRC Input Circuit
VCRB Input Circuit
DC restore clamp active
DC restore clamp active
(0.24V at sync timing/output pin) (0.24V at sync timing/output pin)
Biased
(DC restore clamp active)
(1.49V at sync timing/output pin) (0.24V at sync timing output pin)
DC restore clamp active
DC restore clamp active
(1.49V at sync timing/output pin) (1.49V at sync timing/output pin)
(reserved)
(reserved)
Table 13. DC-restore control for VCR Input
ENCRC Input Circuit
ENCB Input Circuit
DC restore clamp active
DC restore clamp active
(0.24V at sync timing/output pin) (0.24V at sync timing/output pin)
Biased
DC restore clamp active
(1.49V at sync timing/output pin) (0.24V at sync timing output pin)
DC restore clamp active
DC restore clamp active
(1.49V at sync timing/output pin) (1.49V at sync timing/output pin)
(reserved)
(reserved)
Table 14. DC-restore control for Encoder Input
CLAMP2
0
1
ENCG Input Circuit
DC restore clamp active
(0.24V at sync timing/output pin)
Sync tip clamp active
(0.24V at sync timing/output pin)
note
for RGB
for Y/C
(default)
for Y/Pb/Pr
note
for RGB
(default)
for Y/C
for Y/Pb/Pr
note
for RGB
(default)
for Y/Pb/Pr
Note: When the VTV2-0 bits = “001” (source for TV = Encoder CVBS /RGB), TVG bit = “1” (TVG = active) and
VCLP1-0 bits = “11” (DC restore source = ENCG), the sync tip is selected even if the CLAMP2 bit = “0”.
Table 15. DC-restore control for Encoder Green/Y Input
VCLP2-0: DC restore source control
VCLP2 VCLP1 VCLP0
Sync Source of DC Restore
0
0
0
ENCV
0
0
1
ENCY
0
1
0
VCRVIN
0
1
1
ENCG
1
0
0
VCRG
1
0
1
(reserved)
1
1
0
(reserved)
1
1
1
(reserved)
Note: When the AUTO bit = “1”, the source is fixed to VCRVIN.
Table 16. DC-restore source control
(default)
2011/07
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[AK4709]
4. Blanking Control
The AK4709 supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV/VCR SCART.
■ Input/Output Control for Fast/Slow Blanking
FB1-0: TV Fast Blanking output control (07H: D1-D0)
FB1 bit
FB0 bit
TVFB pin Output Level
0
0
0V
(default)
0
1
2V< 3.0V(typ) at 150Ω load
1
0
Same as VCR FB input (2.5V/0V)
1
1
(Reserved)
Table 17. TV Fast Blanking output (Note: minimum load is 150Ω)
SBT1-0: TV Slow Blanking output control (07H: D3-D2)
SBT1 bit
SBT0 bit
TVSB pin Output Level
0
0
< 2V
(default)
0
1
4.73V <, < 7V
1
0
(Reserved)
1
1
10V <
Table 18. TV Slow Blanking output (Note: minimum load is 10kΩ)
SBV1-0: VCR Slow Blanking output control (07H: D5-D4)
SBV1 bit
SBV0 bit
VCRSB pin Output Level
0
0
< 2V
(default)
0
1
4.73V <, < 7V
1
0
(Reserved)
1
1
10V <
Table 19. VCR Slow Blanking output (Note: minimum load is 10kΩ)
SBIO1-0: TV/VCR Slow Blanking I/O control (07H: D7-D6)
SBIO1 bit
SBIO0 bit
0
0
0
1
1
0
1
1
VCRSB pin Direction
TVSB pin Direction
Output
Output
(Controlled by SBV1-0 bits) (Controlled by SBT1-0 bits)
(Reserved)
(Reserved)
Input
Output
(Stored in SVCR1-0 bits)
(Controlled by SBT1-0 bits)
Input
Output
(Stored in SVCR1-0 bits)
(Same output as VCR SB)
Table 20. TV/VCR Slow Blanking I/O control
(default)
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[AK4709]
5. Monitor Options and INT function
■ Monitor Options (08H: D4-D0)
The AK4709 has several detection functions. SVCR1-0 bits, FVCR bit, VCMON bit and TVMON bit reflect the input
DC level of VCR slow blanking, the input DC level of VCR fast blanking and signals input to TVVIN or VCRVIN pins.
SVCR1-0: VCR Slow blanking status monitor
SVCR1-0 bits reflect the voltage at VCRSB pin only when the VCRSB is in the input mode.
When the VCRSB is in the output mode, SVCR1-0 bits hold previous value.
VCRSB pin input level
SVCR1 bit
SVCR0 bit
< 2V
0
0
4.5 to 7V
0
1
(Reserved)
1
0
9.5 <
1
1
Table 21. VCR Slow Blanking monitor
FVCR: VCR Fast blanking input level monitor
This bit is enabled when TVFB bit = “1”.
VCRFB pin input level
FVCR bit
< 0.4V
0
1V <
1
Table 22. VCR Fast Blanking monitor (Typical threshold is 0.7V)
VCMON: VCRVIN pin video input monitor (MCOMN bit = “1”),
TVVIN pin or VCRVIN pin video input monitor (MCOMN bit = “0”)
0: No video signal detected.
1: Detects video signal.
TVMON: TVVIN pin video input monitor (active when MCOMN bit = “1”)
0: No video signal detected.
1: Detects video signal.
AUTO
(00H D3)
0
0
0
0
MCOMN
(09H D7)
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
TVMON
(08H D4)
0
0
0
0
VCMON
(08H D3)
0
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
1
1
1
TVVIN signal
VCRVIN signal
0
0
1
1
1
1
1
1
x
x
x
x
(x: don’t care)
Note 28. TVVIN/VCRVIN signal: signal 0 = No signal applied, signal 1 = signal applied
Table 23. TV/VCR Monitor Function
2011/07
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[AK4709]
■ INT Function and Mask Options (09H: D3-D1)
Changes of the 08H status can be monitored via the INT pin. The INT pin is an open drain output and goes “L” for 2μs
(typ.) when the status of 08H is changed. This pin should be tied to VVD1 (typ. 3.3V) via 10kΩ resistor or lower voltage
through 10kΩ resistor. MTV bit, MVC bit, MCOMN bit, MFVCR bit and MSVCR bit control the reflection of the status
change of these monitors onto the INT pin from report to prevent to masks each monitor.
AK4709
3.3V
R=10kΩ
INT
uP
Figure 10. INT pin
MVC: VCMON Mask. Refer Table 25.
MTV: TVMON Mask. Refer Table 24.
MCOMN: Refer Table 23
AUTO
TVMON
MTV
INT
(00H D3)
(08H D4)
(09H D4)
No Change
0
Hi-Z
0
No Change
1
Hi-Z
0
Change
0
Generates “L” Pulse
0
0
Change
1
Hi-Z
No Change
0
Hi-Z
1
1
No Change
1
Hi-Z
Note 29. When the STBY bit = “0”, the TV Monitor Mask function is enabled.
Note 30. When AUTO bit = “1”, TVMON does not change
Table 24. TV Monitor Mask
AUTO
(00H D3)
0
0
0
0
VCMON
MVC
INT
(08H D3)
(09H D3)
No Change
0
Hi-Z
No Change
1
Hi-Z
Change
0
Generates “L” Pulse
Change
1
Hi-Z
1
No Change
0
Hi-Z
1
No Change
1
Hi-Z
1
Change
0
Generates “L” Pulse
1
Change
1
Generates “L” Pulse
Note 31. When the STBY bit = “0”, the VCR Monitor Mask function is enabled.
Table 25. VCR Monitor Mask
MFVCR: FVCR Monitor mask.
0: Change of FVCR is reflected to INT pin. (default)
1: Change of FVCR is NOT reflected to INT pin.
MSVCR: SVCR1-0 Monitor mask
0: Change of SVCR1-0 is reflected to INT pin. (default)
1: Change of SVCR1-0 is NOT reflected to INT pin.
2011/07
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[AK4709]
6. Control Interface (I2C-bus Control)
1. WRITE Operations
Figure 11 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 17). After the
START condition, a slave address is sent. This address is 7bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant seven bits of the slave address are fixed as “0010001”. If the slave address match that of the
AK4709, the AK4709 generates the acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 19). A
“1” for R/W bit indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed. The second byte consists of the address for control registers of the AK4709. The format is MSB first, and those
most significant 3-bits are fixed to zeros (Figure 13). The data after the second byte contain control data. The format is
MSB first, 8bits (Figure 14). The AK4709 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 17).
The AK4709 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4709
generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 0DH prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 19) except for the START and the STOP
condition.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 11. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
0
1
R/W
A2
A1
A0
D2
D1
D0
Figure 12. The first byte
0
0
0
A4
A3
Figure 13. The second byte
D7
D6
D5
D4
D3
Figure 14. Byte structure after the second byte
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[AK4709]
2. READ Operations
Set R/W bit = “1” for READ operations. After transmission of data, the master can read the next address’s data by
generating an acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of
each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If
the address exceeds 09H prior to generating the stop condition, the address counter will “roll over” to 00H and the
previous data will be overwritten.
The AK4709 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
2-1. CURRENT ADDRESS READ
The AK4709 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4709 generates an
acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address
counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4709
discontinues transmission.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
Data(n+2)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 15. CURRENT ADDRESS READ
2-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start condition,
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledge, the master
immediately reissues the start condition and the slave address with the R/W bit set to “1”. Then the AK4709 generates an
acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but generate the stop condition, the AK4709 discontinues transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Sub
Address(n)
Slave
Address
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 16. RANDOM ADDRESS READ
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[AK4709]
SDA
SCL
S
P
start condition
stop condition
Figure 17. START and STOP conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 18. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 19. Bit transfer on the I2C-bus
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[AK4709]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
Register Name
Control
Switch
Main Volume
Zerocross
Video switch
Video output enable
Video volume/clamp
S/F Blanking control
S/F Blanking monitor
Monitor mask
DC restore
Reserved
Reserved
Volume
D7
0
VMUTE
0
0
0
CIO
CLAMPB
SBIO1
0
MCOMN
0
0
0
0
D6
0
0
0
VMONO
0
TVFB
VCLP1
SBIO0
0
0
0
0
0
VOL3
D5
0
VCR1
L5
CAL
VVCR2
VCRC
VCLP0
SBV1
FVCR1
0
0
0
0
VOL2
D4
0
VCR0
L4
0
VVCR1
VCRV
CLAMP2
SBV0
TVMON
MTV
0
0
0
VOL1
D3
AUTO
MONO
L3
0
VVCR0
TVB
CLAMP1
SBT1
VCMON
MVC
VCLP2
0
0
VOL0
D2
0
1
L2
MOD
VTV2
TVG
CLAMP0
SBT0
FVCR0
MFVCR
0
0
0
1
D1
MUTE
TV1
L1
MDT1
VTV1
TVR
0
FB1
SVCR1
MSVCR
1
0
0
1
D0
STBY
TV0
L0
MDT0
VTV0
TVV
0
FB0
SVCR0
0
1
0
0
1
When the PDN pin goes “L”, the registers are initialized to their default values.
While the PDN pin = “H”, all registers can be accessed.
Do not write any data to the register over 0DH.
■ Register Definitions
Addr
00H
Register Name
Control
R/W
Default
D7
0
D6
0
D5
0
D4
0
0
0
0
0
D3
AUTO
D2
0
D1
MUTE
D0
STBY
1
0
1
1
R/W
STBY: Standby control
0: Normal Operation
1: Standby Mode (default). All registers are not initialized.
AMP: Powered down and timings are reset.
Source of TVOUT: fixed to VCRIN.
Source of VCROUT: fixed to TVIN.
Source of TVVOUT: fixed to VCRVIN (or Hi-Z).
Source of TVRC: fixed to VCRRC (or Hi-Z).
Source of TVG: fixed to VCRG (or Hi-Z).
Source of TVB: fixed to VCRB (or Hi-Z).
Source of VCRVOUT: fixed to TVVIN (or Hi-Z).
Source of VCRC: fixed to Hi-Z.
MUTE: Audio output control
0: Normal operation
1: ALL Audio outputs to GND (default)
AUTO: Auto startup bit
0: Auto startup disable (Manual startup).
1: Auto startup enable (default).
Note: When the SBIO1 bit = “1”(default = “0”), the change of AUTO bit may cause a “L” pulse on INT pin.
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[AK4709]
Addr
01H
Register Name
Switch
R/W
Default
D7
VMUTE
D6
0
D5
VCR1
D4
VCR0
1
0
0
1
D3
MONO
R/W
0
D2
1
D1
TV1
D0
TV0
1
0
1
TV1-0: TVOUTL/R pins source switch
00: AMP
01: VCRINL/R pins (default)
10: MUTE
11: Reserved
MONO: Mono select for TVOUTL/R pins
0: Stereo. (default)
1: Mono. (L+R)/2
VCR1-0: VCROUTL/R pins source switch
00: AMP
01: TVINL/R pins (default)
10: MUTE
11: Volume#1 output
VMUTE: Mute switch for volume #1
0: Normal operation
1: Mute the volume #1 (default)
Addr
Register Name
02H
Main volume
D7
D6
D5
D4
D3
D2
D1
D0
0
0
L5
L4
L3
L2
L1
L0
1
1
1
1
R/W
Default
R/W
0
0
0
1
L5-0: Volume #1 control
Those registers control both Lch and Rch of Volume #1.
111111 to
100011: (Reserved)
100010: Volume gain = +6dB
100001: Volume gain = +4dB
100000: Volume gain = +2dB
011111: Volume gain = +0dB (default)
011110: Volume gain = -2dB
...
000011: Volume gain = -56dB
000010: Volume gain = -58dB
000001: Volume gain = -60dB
000000: Volume gain = Mute
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[AK4709]
Addr
03H
Register Name
Volume Control
R/W
Default
D7
0
VMONO
D6
D5
CAL
D4
0
0
0
1
0
D3
0
D2
MOD
D1
MDT1
D0
MDT0
0
1
1
1
R/W
MDT1-0: The time length control of volume transition time
00: typ. 5.3 ms
01: typ. 10.7 ms
10: typ. 21.3 ms
11: typ. 42.7 ms (default)
MOD: Soft transition enable for volume #1 control
0: Disable
The volume value changes immediately without soft transition.
1: Enable (default)
The volume value changes with soft transition.
This function is disabled when STBY bit = “1”.
CAL: Offset calibration Enable
0: Offset calibration disable.
1: Offset calibration enable (default)
VMONO: Mono select for VCROUTL/R pins
0: Stereo. (default)
1: Mono. (L+R)/2
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[AK4709]
Addr
04H
Register Name
Video switch
R/W
Default
D7
0
D6
0
D5
VVCR2
0
0
0
D4
D3
VVCR1 VVCR0
R/W
1
1
D2
VTV2
D1
VTV1
D0
VTV0
1
0
0
D4
D3
VCRV
TVB
R/W
0
0
D2
TVG
D1
TVR
D0
TVV
0
0
0
VTV2-0: Selector for TV video output
Refer Table 10.
VVCR2-0: Selector for VCR video output
Refer Table 11.
Addr
05H
Register Name
Output Enable
R/W
Default
D7
CIO
D6
TVFB
D5
VCRC
0
0
0
TVV: TVVOUT output control
TVR: TVRCOUT output control
TVG: TVGOUT output control
TVB: TVBOUT output control
VCRV: VCRVOUT output control
VCRC: VCRC output control
TVFB: TVFB output control
0: Hi-Z (default)
1: Active.
CIO: VCR RGB I/O control for VCR SCART
Refer Table 12.
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[AK4709]
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
06H
Video volume
CLAMPB
VCLP1
VCLP0
CLAMP2
CLAMP1
CLAMP0
0
0
0
1
0
0
D2
SBT0
D1
FB1
D0
FB0
0
0
0
R/W
Default
R/W
0
0
0
0
CLAMPB, CLAMP2-0: Clamp control.
Refer Table 13, Table 14 and Table 15.
VCLP1-0: DC restore source control
00: ENCV pin (default)
01: ENCY pin
10: VCRVIN pin
11: (Reserved)
When the AUTO bit = “1”, the source is fixed to VCRVIN pin.
Addr
07H
Register Name
S/F Blanking
R/W
Default
D7
SBIO1
D6
SBIO0
D5
SBV1
0
0
0
D4
D3
SBV0
SBT1
R/W
0
0
FB1-0: TV Fast Blanking output control (for TVFB pin)
00: 0V (default)
01: 2V<, 2.5V(typ) at 150Ω load
10: follow VCR FB input (2.5V/0V)
11: (Reserved)
SBT1-0: TV Slow Blanking output control (for TVSB pin. minimum load is 10kΩ.)
00: < 2V (default)
01: 4.73V <, < 7V
10: (Reserved)
11: 10V <
SBV1-0: VCR Slow Blanking output control (for VCRSB pin. minimum load is 10kΩ.)
00: < 2V (default)
01: 4.73V <, < 7V
10: (Reserved)
11: 10V <
SBIO1-0: TV/VCR Slow Blanking I/O control
Refer Table 20.
Addr
08H
Register Name
Monitor
R/W
Default
D7
D6
D5
D4
0
0
FVCR1
TVMON
D3
D2
D1
D0
VCMON
FVCR0
SVCR1
SVCR0
0
0
0
READ
0
0
0
0
0
SVCR1-0, FVCR1-0: VCR fast blanking/slow blanking monitor
Refer Table 21, Table 22.
VCMON, TVMON: VCR/TV video input monitor
Refer Table 23.
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[AK4709]
Addr
09H
Register Name
Monitor mask
R/W
Default
D7
MCOMN
D6
0
D5
0
D4
MTV
0
0
0
0
D3
MVC
R/W
1
D2
MFVCR
D1
MSVCR
D0
0
0
0
0
MSVCR: SVCR1-0 bits Monitor mask
0: The INT pin reflects the change of SVCR1-0 bit. (default)
1: The INT pin does not reflect the change of SVCR1-0 bits.
MFVCR: FVCR Monitor mask
0: The INT pin reflects the change of MFVCR bit. (default)
1: The INT pin does not reflect the change of MFVCR bit.
MVC: VCR input monitor mask
Refer Table 25.
MTV: TV input monitor mask
Refer Table 24.
MCOMN: Monitor mask option
Refer Table 23.
Addr
Register Name
0AH
DC restore
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
VCLP2
0
1
1
0
0
1
1
D3
D2
D1
D0
VOL0
1
1
1
1
1
1
1
R/W
0
0
0
0
D7
D6
D5
D4
0
VOL3
VOL2
VOL1
VCLP2: DC restore source control
Refer Table 16
Addr
Register Name
0DH
Main volume
R/W
Default
R/W
0
0
0
1
VOL3-0: Volume #0 control
Those registers control both Lch and Rch of Volume #0.
1011: Volume gain = +24dB
1010: Volume gain = +21dB
1001: Volume gain = +18dB
1000: Volume gain = +15dB
0111: Volume gain = +12dB
0110: Volume gain = +9dB
0101: Volume gain = +6dB
0100: Volume gain = +3dB
0011: Volume gain = +0dB (default)
0010: Volume gain = -3dB
0001: Volume gain = -6dB
0000: MUTE
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[AK4709]
SYSTEM DESIGN
Analog
3.3V
Figure 20 shows the system connection diagram example. The evaluation board AKD4709 demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
0.47u
1.0uF
4.7u +
75
1.0uF
300
0.1u
DACR
VEE 38
TVRC
TVOUTR 32
6
TVG
7
TVB
AK4709
0.47u
0.47u
300
300
VCROUTL 31
300
VCROUTR 30
8
VVD1
TVINL 29
9
ENCB
TVINR 28
10 ENCG
VCRINL 27
11 ENCRC
VCRINR
12 ENCC
VD1 25
300
300
300
0.47u
0.47u
0.47u
0.47u
Audio 3.3V
+
4.7u
VCR SCART
0.1u
300
10
470
+
1u
470
0.1u
75
0.1u
0.1u
75
0.1u
0.1u
0.1u
0.1u
75
0.1u
75
26
300
Analog Ground
Analog
12V
Digital
Ground
AINL+ 37
CP 40
CN 39
VSS2 41
INT 43
VD2 42
SCL 44
SDA 45
5
0.47u
TV SCART
0.1u
TVOUTL 33
24 VSS1
0.1u
75
VVD2
23 TVSB
75
4
22 VCRSB
0.1u
300
21 VP
75
AINR- 34
13 ENCV
0.1u
TVVOUT
DACL
Micro
75
Encoder
MPEG
decoder
VIDEO
Controller
Video 3.3V
3
20 VCRB
75
300
19 VCRG
75
AINR+ 35
18 VCRRC
75
VSS3
17 VCRFB
+
VCRC
2
16 VCRVIN
+
AINL- 36
300
1
15 TVVIN
75
PDN 46
TVFB 48
4.7u0.1u 4.7u0.1u
14 ENCY
75
VCRVOUT 47
75
Figure 20. Typical Connection Diagram
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[AK4709]
■ Grounding and Power Supply Decoupling
VD1, VD2, VP, VVD1, VVD2, VSS1, VSS2 and VSS3 should be supplied from analog supply unit with low impedance
and be separated from system digital supply. An electrolytic capacitor 4.7μF parallel with a 0.1μF ceramic capacitor
should be attached to VD1, VD2, VVD1, VVD2, VSS1, VSS2 and VSS3 pin to eliminate the effects of high frequency
noise. The 0.1μF ceramic capacitor should be placed as near to VD1 (VD2, VVD1, VVD2) as possible.
The VP pin must be connected to the Analogue 12V power supply via a 10ohm resistor and with a 0.1µF ceramic
capacitor in parallel with a 1µF electrolytic capacitor to VSS1, as shown in Figure 20.
■ Analog Audio Outputs
The analog outputs are also single-ended and centered on 0V(typ.). The output signal range is typically 2Vrms .
■ Slow Blanking pins
The Slow Blanking Pin must have a 470ohm ±5% series resistor.
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[AK4709]
■ External Circuit Example
The analog audio input pin must have 300ohm series resistor and 0.47uF capacitor.
Analog Audio Input pin
300Ω
TVINL/R
VCRINL/R
(Cable)
0.47μF
Analog Audio Input pin
300Ω
AINR+
AINRAINL+
AINL-
0.47μF
Analog Audio Output pin
TVOUTL/R
VCROUTL/R
300Ω
(Cable)
Total > 4.5kΩ
Analog Video Input pin
75Ω
(Cable)
ENCV, ENCY, VCRVIN,
TVVIN, ENCRC, ENCC,
VCRRC, ENCG, VCRG,
ENCB, VCRB
0.1μF
75Ω
Analog Video Output pin
TVVOUT, TVRC
TVG, TVR, TVB,
VCRVOUT,VCRC
75Ω
(Cable)
max
400pF
max
15pF
75Ω
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[AK4709]
Slow Blanking pin
TVSB
VCRSB
(Cable)
470Ω ±5%
max 3nF
(with 470Ω)
min: 10kΩ
Fast Blanking Input pin
VCRFB
75Ω
(Cable)
75Ω
Fast Blanking Output pin
75Ω
TVFB
(Cable)
75Ω
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[AK4709]
PACKAGE
48pin LQFP (Unit: mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
1.40 ± 0.05
24
48
13
7.0
37
12
1
0.5
9.0 ± 0.2
25
0.22 ± 0.08
0.09 ∼ 0.20
0.10 M
0° ∼ 10°
S
0.10 S
0.3 ∼ 0.75
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
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[AK4709]
MARKING
AK4709EQ
XXXXXXX
1
XXXXXXX: Date code
REVISION HISTORY
Date (YY/MM/DD)
11/07/28
Revision
00
Reason
First Edition
Page
Contents
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[AK4709]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
2011/07
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