AKM AKD7782-A

[AKD7782-A]
AKD7782-A
AK7782 Evaluation Board Rev.0
GENERAL DESCRIPTION
The AKD7782-A is an evaluation board for AK7782, which is a highly integrated audio processor including
5ch 24bit ADC, 4ch SRC and two audio DSP cores. This board is composed of a main board and a sub
board. It is possible to control the setting of board via USB port. RCA connectors are used for the input
and output of analog signal. This board also has digital interface and can achieve the interface with digital
audio system via optical connector.
„ Ordering guide
AKD7782-A
--- Evaluation board for AK7782
Control software is packed with this.
FUNCTION
† Read/Write access to PRAM, CRAM, OFREG and control registers of AK7782
† Compatible with 2 types of digital audio interface
- Optical input (x1) / Optical output (x1)
- 10pin header for interface with external data source (x2)
† ADC1/ADC2 18ch input, ADCM 1ch input, DAC 8ch output
(Note: There is no DAC within AK7782. 8ch DAC AK4359 is equipped.)
† USB port for board control
+12V
Regulator
Regulator
USB 3.3V
Regulator
3.3V
Regulator
1.8V
3.3V
PIC18F
USB
GND
AIN 18ch
4550
Amp
FPGA
AK7782
AINM 1ch
(XC95144XL)
Opt In
Regulator
AK4118A
AOUT 8ch
5.0V
Opt Out
AK4359
SMUX
SMUX2
10 Pin Header
Figure 1. AKD7782-A Block Diagram
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Evaluation Board Diagram
„ Board Diagram
Figure 2. AKD7782-A Board Diagram
„ Description
(1) AIN/DAC (RCA Jack)
AIN: Analog input jacks. DAC: Analog output jacks.
The white jacks are used for left channel and the red ones are for right channel.
(2) AK4118A
AK4118A has DIR, DIT and X’tal oscillator. It transports digital data to AK7782 when working in master mode and
outputs data from AK7782 when working in slave mode.
(3) SPDIF-IN/SPDIF-OUT (Optical Connector)
SPDIF-IN (input): It inputs optical digital signal to AK4118A and supports sampling frequencies from 8 to 96kHz.
SPDIF-OUT (output): It outputs optical digital signal from AK4118A and supports sampling frequencies from 8 to
96kHz.
(4) +12V/GND (Power supply)
Connect to +12V and GND according to the following operation sequence on page 4.
(5) PIC18F4550
USB control chip. It is possible to set up the registers of AK7782, FPGA and AK4118A from PC via USB port.
(6) SW1
Push type switch. It is used to initialize PIC18F4550. Please push down the button once when PC has trouble
identifying the evaluation board.
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(7) XC95144XL(Xilinx)
FPGA used for data path control. It is possible to run a variety of tests by way of controlling the data path via control
software.
(8) SMUX PORT (PORT1/PORT2)
10 pin header for interface with external data source. Two ports are equipped and available to achieve with other
audio system.
Pin I/O Function
pin
I/O Function
1
I/O MCLK
2
P
GND
3
I/O BITCLK
4
P
GND
5
I/O LRCLK
6
P
GND
7
I
SDTI
8
P
GND
9
P
VDD
10
O
SDTO
Table 1. Pin assignment of SMUX port
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Evaluation Board Manual
„ Operation sequence
(1) Set up the power supply lines.
Setting of jumper pins
(short)
(short)
JP10
CHIP-DVDD
P-DVDD
PIC-VDD-SEL
(short)
(short)
USB-5V
CHIP-AVDD CHIP-DVDD18
JP12
JP4
USB-3.3V
JP3
DVDD
JP2
Connection of power supply lines (Each supply line should be distributed from the power supply unit.)
Name Color
Voltage
Comment
Attention
+12V
Red
+9~+12V
Regulator, Power supply for op-amp
This jack is always needed.
GND Black
0V
Ground
This jack is always needed.
Table 2. Power supply connection
(2) Set up the evaluation mode, jumper pins and connectors according to the follows.
(3) Connect the board to PC with the USB cable packed.
(4) Power On.
(5) Start the control soft and setup the registers.
„ Evaluation Mode
In case of AK7782 evaluation using AK4118A, it is necessary to correspond to audio interface format for
AK7782 and AK4118A. About AK7782’s audio interface format, please refer to datasheet of AK7782. About
AK4118A’s audio interface format, please refer to Table 11 in this manual.
Applicable Evaluation Mode
(1) Evaluation mode of ADC using DIT of AK4118A: CKM Master Mode = 0
(2) Evaluation mode of DSP using DIR/DIT of AK4118A: CKM Slave Mode = 2/4/5
(3) Evaluation mode of SRC using DIR of AK4118A and SMUX port: CKM Master Mode = 0
(4) Evaluation mode of sound (tone) quality using DAC of AK4359
Please refer to the control software manual from page 12 and the datasheet of AK7782 to set up FPGA, AK4118A and
AK7782 from PC.
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(1) Evaluation mode of ADC using DIT of AK4118A : CKM Master Mode = 0
SPDIF-OUT is used. Set the clock mode of AK7782 to Master Mode 0 (12.288MHz).
AK7782 supplies MCLK, BICK, and LRCK to AK4118A and AK4118A outputs the data from ADC1, ADC2 and
ADCM.
[Setting of jumper]
JP101
JP1
XTL
CRY-XTI
TX-CLK
EXT-XTI
[Connection of other connectors]
For ADC1 and ADC2, RCA1/RCA2 or RCA3/RCA4 are available. Please refer to Table 5 for the setting of
jumpers which used to select input channels.
For ADCM, RCA5(AINM) is available.
(2) Evaluation mode of DSP using DIR/DIT of AK4118A : CKM Slave Mode = 2/4/5
SPDIF-IN and SPDIF-OUT are used. Set the clock mode of AK7782 to Master Mode 2/4/5.
AK4118A supplies MCLK, BICK, LRCK and digital data to AK7782 and outputs data from AK7782.
(MCLK is needed when CKM Slave Mode = 2.)
[Setting of jumper]
JP101
JP1
XTL
CRY-XTI
TX-CLK
EXT-XTI
(JP101 is needed only when CKM Mode = 2)
(3) Evaluation mode of SRC using DIR of AK4118A and SMUX port : CKM Master Mode = 0
SPDIF-OUT and SMUX PORT are used. Set the clock mode of AK7782 to Master Mode 0 (12.288MHz).
SMUX PORT is used as input and supplies BICK, LRCK and digital data to SRC of AK7782.
AK7782 supplies MCLK, BICK, and LRCK to AK4118A and AK4118A outputs the data from SRC.
[Setting of jumper]
JP101
JP1
XTL
CRY-XTI
EXT-XTI
TX-CLK
Crystal of 12.288MHz is equipped on the sub board for frequencies of 48kHz series. Please change the cystal to
11.2896MHz when using 44.1kHz series’s frequencies.
[Connection of other connectors]
SMUX PORT 1 or PORT 2 is available. Please refer to Table 1 about the pin assignment of SMUX port.
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(4) Evaluation mode of sound (tone) quality using DAC of AK4359
AK4359 is used. AK7782 supplies MCLK, BICK, LRCK and digital data to AK4359, which converts digital data
to analog signal and output it.
[Connection of other connectors]
For analog output, RCA6 ~ RCA13 (DAC1-4) are available.
„ Board control
It is possible to control AKD7782-A via general USB port. Connect the USB port on the board to PC with the packed
cable.
Control software is packed with this board and the software manual is included in this manual.
„ Indication for LED
[LED]: U12
When power is supplied, LED is lighted to red. It monitors PC-RQN signal and changes color when
the board is communicating with PC.
[LED] D1:
Monitor the status of INITRSTN pin of AK7782.
‘L’ → light up, ‘H’ → light out.
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„ Setting of Jumper Pins
Main board:
Jumper
Setting (Default)
JP1 (AK4118A Clock)
“XTL”
JP2 (CHIP-AVDD)
JP3 (CHIP-DVDD18)
JP4 (CHIP-DVDD)
JP5 (AIN1L-SEL)
JP6 (AIN1R-SEL)
JP7 (AIN2L-SEL)
JP8 (AIN2R-SEL)
JP9 (AINM)
Short
Short
Short
AINL+, AINLAINR+, AINRAINL2
AINR2
Short
JP10 (PIC-VDD-SEL)
JP12 (P-DVDD)
Note
AK4118A Clock Source
“XTL”: Crystal Clock
“TX-CLK”: External Clock
AK7782 AVDD
AK7782 DVDD18
AK7782 DVDD
Input channel selector for ADC1/ADC2
Input for ADCM
USB chip power supply
“USB-5V”:USB 5V
“USB 3.3V”
“USB-3.3V”:USB 3.3V
“DVDD”:Peripheral DVDD 3.3V
Short
Peripheral DVDD 3.3V
Table 3. Setting of jumper pins on main board
Sub board:
Jumper
JP101 (Clock)
Setting (Default)
Note
AK7782 Clock Source
“XTL”: Crystal Clock
“EXT”: External Clock
Table 4. Setting of jumper pins on sub board
“EXT-XTI”
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„ Analog Input Circuit
+
Figure 3. Analog Input Circuit 1 for ADC1/ADC2
For ADC1/ADC2 analog differential input and single-end input, RCA1(AIN1L)、RCA2(AIN1R) are available.
The input range of each channel is [email protected]
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Figure 4. Analog Input Circuit 2 for ADC1/ADC2
For ADC1/ADC2 analog single-end input, RCA3(AIN2L)、RCA4(AIN2R) are available.
The input range of each channel is [email protected]
Setting of JP5, JP6, JP7, JP8 for ADC1/ADC2 analog input:
Setting of JP5 and JP6
Setting of JP7 and JP8
Input Pin
when using RCA1/RCA2
when using RCA3/RCA4
7-8 pin short
AINL±/ AINR±
9-10 pin short
AINL2/ AINR2
5-6 pin short
5-6 pin short
AINL3/ AINR3
3-4 pin short
3-4 pin short
AINL4/ AINR4
1-2 pin short
1-2 pin short
AINL5/ AINR5
11-12 pin short
7-8 pin short
AINL6/ AINR6
13-14 pin short
9-10 pin short
AINL7/ AINR7
15-16 pin short
11-12 pin short
AINL8/ AINR8
17-18 pin short
13-14 pin short
Table 5. Setting of jumpers for ADC1/ADC2 analog input
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Figure 5. Analog Input Circuit for ADCM
For ADCM analog single-end input, RCA5(AINM) is available. The input range channel is [email protected]
„ Analog Output Circuit
Figure 6. Analog Output Circuit for DAC
For DAC analog output, RCA6~RCA13(DAC1~DAC4) are available.
The output range of each channel is [email protected]
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„ Digital Input Circuit (DIR: PORT1)
Figure 7. Digital Input Circuit
For digital input SPDIF-IN, optical connector PORT1 is available.
„ Digital Output Circuit (DIT: PORT2)
Figure 8. Digital output circuit
For digital output SPDIF-OUT, optical connector PORT2 is available.
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Control Software Manual
„ Set-up of the evaluation board and control software
(1) Set up the AKD7782-A according to previous terms.
(2) Connect AKD7782-A to PC with the cable packed.
(3) Insert the CD-ROM labeled “AKD7782-A Evaluation Kit” into the CD-ROM drive.
(4) Access the CD-ROM drive and double-click the icon of “AK7782.exe” to start the control software.
AK7782.exe:Control Software for AK7782
(5) Then please evaluate according to the follows.
„ Operation flow
Keep the following flow
(1) Start the control software according to the explanation above.
(2) Select the needed dialogue to evaluate by modifying the setting. (If the USB cable is removed when control
software is used, please close the software and start it again when operation is needed again.)
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„ Description of Control Software
(1) Main Dialogue
Figure 9. Main Dialogue of Control Software
Control software is used to download program, to set up the registers of AK7782 and FPGA and to process script file.
These functions can be selected by the tab items above. The buttons of control signals which are frequently used and the
initialization buttons are placed outside the tab dialogue. The control interface of the control software, “Serial (4 lines)” or
“I2C”, is displayed in the “Control I/F” column.
[PDN pin]:
[DSP]:
[AD]:
[SRC]:
[CK]:
[Board Init]:
[READ]:
[EXIT]:
Initial Reset. It is used to initialize AK7782.
DSP Reset.
AD Reset.
SRC Reset.
Clock Reset. Clock Reset is required when changing the clock mode or the frequency of input clock
without initial reset. The registers will not be initialized.
Execute initial reset and then write the setting of AK7782’s registers, FPGA and AK4118A on the
software to the board again.
Read back the setting of registers of AK7782 and display them in “Register” column.
Close the control soft.
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(2) “DownLoad” Dialogue
Figure 10. “DownLoad” Dialogue
Because AK7782 has two DSP cores, there are two sets of control buttons on the dialogue for DSP1 and DSP2, like
program select columns, JX setup buttons and so on. The following descriptions are common to DSP1 and DSP2.
File of Source column, Program column, CRAM column or OFREG column can be selected by clicking the [refer] button
of each column or by way of dropping or tracking files from desktop.
CRAM file or OFREG file can be selected and be written to CRAM or OFREG by clicking the [refer] button of CRAM
[email protected] column or OFREG [email protected] column when system is running. The data will be written to
specific address of CRAM or OFREG when the [write] button at right side is clicked.
[Assemble]:
[Write]:
[Assemble Write]:
[PRAM read]:
[CRAM read]:
[OFREG read]:
[CRAM SAVE]:
[OFREG SAVE]:
[MIR1/MIR2]:
[JX]:
[Verify]:
[Auto RUN]:
Compile the source file and the output file will be selected to the download file automatically.
Download the program file to AK7782.
Compile the source file and then download the program file to AK7782.
Read the data of PRAM to temporary file and then open the file.
Read the data of CRAM to temporary file and then open the file.
Read the data of OFREG to temporary file and then open the file.
Read the data of CRAM and save to file.
Read the data of OFREG and save to file.
Read the data of register MIR1/MIR2 when program is running and display the result.
JX code setting column.
When it is checked, the verification of data will be done when downloading files to AK7782.
When it is checked, DSP/AD/SRC will be released and AK7782 will be set to run mode automatically
after downloading data to AK7782. Otherwise, AK7782 will be set to DSP reset mode after
downloading.
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(3) “REG” Dialogue
Figure 11. “REG1” Dialogue
Dialogues REG1~REG6 are used to set up the register of AK7782. (It is prohibited to modify test and reserved items.)
As the checkbox is clicked, the data will be written to AK7782. Please set up the registers during system reset mode.
The reference pages of registers in datasheet are as follows:
Register
Reference Page
Register
Reference Page
CONT00
31
CONT0C
43
CONT01
32
CONT0D
44
CONT02
33
CONT0E
45
CONT03
34
CONT0F
46
CONT04
35
CONT10
47
CONT05
36
CONT11
48
CONT06
37
CONT12
49
CONT07
38
CONT13
50
CONT08
39
CONT14
51
CONT09
40
CONT15
52
CONT0A
41
CONT16
53
CONT0B
42
Table 6. Reference page of registers
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(4) “FPGA” Dialogue
Figure 12. “FPGA1” Dialogue
FPGA1/FPGA2 dialogues are used to modify the data path and the setting of AK4118A.
(It is prohibited to modify test and reserved items.)
FPGA Setting Table:(Bold type items are the default setting.)
ADDRESS:00
Bit
D[15:14]
Function
SDIN1
D[13:12]
SDIN2
D[11:10]
SDIN3
D[9:8]
SDIN4
Description
Input data source to SDIN1 pin of AK7782
00 : AK4118A-IN
01 : SMUX1-DAT1
10 : SMUX2-DAT1
11 : LOW
Input data source to SDIN2 pin of AK7782
00 : AK4118A-IN
01 : SMUX1-DAT1
10 : SMUX2-DAT1
11 : LOW
Input data source to SDIN3 pin of AK7782
00 : AK4118A-IN
01 : SMUX1-DAT1
10 : SMUX2-DAT1
11 : LOW
Input data source to SDIN4 pin of AK7782
00 : AK4118A-IN
01 : SMUX1-DAT1
10 : SMUX2-DAT1
11 : LOW
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D[7:6]
SDIN5
D[5:3]
SDIN6/JX1
D[2:0]
SDIN7/JX2
ADDRESS:01
Bit
D[15:13]
Function
TX-DAT
D[12:10]
CKM Mode
D[9:8]
EXT-XTI
D[7:6]
BITCLKI/LRCLKI
D[5:4]
SRC1-CLK
D[3:2]
SRC2-CLK
Input data source to SDIN5 pin of AK7782
00 : AK4118A-IN
01 : SMUX1-DAT1
10 : SMUX2-DAT1
11 : LOW
Input data source to SDIN6/JX1 pin of AK7782
000 : AK4118A-IN
001 : SMUX1-DAT1
010 : SMUX2-DAT1
011 : LOW
100 : HIGH
Input data source to SDIN7/JX2 pin of AK7782
000 : AK4118A-IN
001 : SMUX1-DAT1
010 : SMUX2-DAT1
011 : LOW
100 : HIGH
Table 7. FPGA Setting Table 1
Description
Output data source to AK4118A
000 : SDOUT1
001 : SDOUT2
010 : SDOUT3
011 : SDOUT4
100 : SDOUT5
101 : SDOUT6
110 : SDOUT7
111 : SDOUTA
High/Low setup of AK7782’s CKM[2:0] pin
000 : CKM Mode 0 – Master
001 : CKM Mode 1 – Master
010 : CKM Mode 2 – Slave
011 : CKM Mode 3 – Slave
100 : CKM Mode 4 – Slave
101 : CKM Mode 5 – Slave
Input clock source to XTI pin of AK7782
000 : AK4118A-MCLK
001 : SMUX1-MCLK
010 : SMUX2-MCLK
011 : LOW
Input clock source to BITCLKI/LRCLKI pin of AK7782
00 : AK4118A
01 : SMUX1
10 : SMUX2
11 : LOW
Input clock source to SRCBICK/SRCLRCK pin of AK7782
00 : AK4118A
01 : SMUX1
10 : SMUX2
11 : LOW
Input clock source to SRC2BICK/SRC2LRCK pin of AK7782
00 : AK4118A
01 : SMUX1
10 : SMUX2
11 : LOW
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D[1:0]
ADDRESS:02
Bit
D[15]
AK4118A-CLK
Function
AK4118A-PDN
D[14]
DAC-PDN
D[13]
PADRSTN
D[12]
PSRCRSTN
D[11]
PDSPRSTN
D[10]
PCKRSTN
D[9]
PSRCSMUTE
D[8]
TESTI1
D[7]
TESTI2
D[6]
JX0
D[5:0]
Reserved
I/O clock setup of AK4118A
00 : Input
01 : AK7782-CLK
10 : SMUX1-CLK
11 : SMUX2-CLK
Table 8. FPGA Setting Table 2
Description (Check Box only)
High/Low setup of AK4118A’s PDN pin
Default : H
High/Low setup of AK4359’s PDN pin
Default : H
High/Low setup of AK7782’s PADRSTN pin
Default : L
High/Low setup of AK7782’s PSRCRSTN pin
Default : L
High/Low setup of AK7782’s PDSPRSTN pin
Default : L
High/Low setup of AK7782’s PCKRSTN pin
Default : H
High/Low setup of AK7782’s PSRCSMUTE pin
Default : L
High/Low setup of AK7782’s TESTI1 pin
Default : L
High/Low setup of AK7782’s TESTI2 pin
Default : L
High/Low setup of AK7782’s JX0 pin
Default : L
Table 9. FPGA Setting Table 3
ADDRESS:03
Bit
D[15:14]
Function
SMUX1-CLK
D[13:12]
SMUX2-CLK
D[11:9]
SMUX1-DAT2
D[8:6]
SMUX2-DAT2
Description
I/O clock setup of SMUX1
00 : Input
01 : AK7782-CLK
10 : AK4118A-CLK
11 : SMUX2-CLK
I/O clock setup of SMUX2
00 : Input
01 : AK7782-CLK
10 : AK4118A-CLK
11 : SMUX1-CLK
Output data source to DAT2 pin of SMUX PORT1
000 : SDOUT1
001 : SDOUT2
010 : SDOUT3
011 : SDOUT4
100 : SDOUT5
101 : SDOUT6
110 : SDOUT7
111 : SDOUTA
Output data source to DAT2 pin of SMUX PORT2
000 : SDOUT1
001 : SDOUT2
010 : SDOUT3
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D[5:4]
CAD[1:0]
D[3]
DAC-OUT1
D[2]
DAC-OUT2
D[1]
DAC-OUT3
D[0]
DAC-OUT4
AK4118A Setting Table:
Function
MCLK
CM
DIF
011 : SDOUT4
100 : SDOUT5
101 : SDOUT6
110 : SDOUT7
111 : SDOUTA
High/Low setup of AK7782’s CAD1,CAD0 pin
00 : Low, Low
01 : Low, High
10 : High, Low
11 : High, High
Output data source to DAC1
0 : SDOUT1
1 : SDOUT5
Output data source to DAC2
0 : SDOUT2
1 : SDOUT6
Output data source to DAC3
0 : SDOUT3
1 : SDOUT7
Output data source to DAC4
0 : SDOUT4
1 : SDOUTA
Table 10. FPGA Setting Table 4
Description
Frequency of main clock output from AK4118A
00: 265fs
01: 256fs
10: 512fs
11: 128fs
Master clock operation mode of AK4118A
00: CM = 00
01: CM = 01
10: CM = 10
11: CM = 11
Audio I/O format of AK4118A
000: 16bit Right( O )
001: 18bit Right( O )
010: 20bit Right( O )
011: 24bit Right( O )
100: 24bit Left( O )
101: 24bit I2S( O )
110: 24bit Left( I )
111: 24bit I2S( I )
Table 11. AK4118A Setting Table
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(5) “SCRIPT” Dialogue
Figure 13. “SCRIPT” Dialogue
As the script file is selected, it will be executed directly. If [Repeat] button is clicked, the selected script file will be
executed once again.
Command
[SCRIPT]
;注釈
W,<address>,<data>
W,0xC0,0x00
WL,<command>,<address>,<data>,…
WL,0x82,0x0022,0x4000,0x4000,0x4000
WS,<command>,<address>,<data>,…
WS,0x81,0x00,0x22,0x40,0x00,0x40,0x00
RI : H / RI : L
RA : H / RA : L
RD : H / RD : L
RR : H / RR : L
RC : H / RC : L
D,<address>,<data>
X,<address>,<data>
A,<address>,<data>
P,<message>
T,<wait>
T,50mS
LP1:<filename> / LP2:<filename>
LC1:<filename> / LC2:<filename>
LO1:<filename> / LO2:<filename>
Description
Header of script file. The script file will be compiled to error without this header.
The content after semicolon is ignored as comment.
Write data to register. Both address and data must be BYTE (8bit).
Write data continuously. It can be used when CRAM is running.
The command must be BYTE (8bit) and the data below must be WORD (16bit).
Write data continuously. It can be used when CRAM is running.
The command, address and data must be BYTE (8bit).
Init Reset
ADC Reset
DSP Reset
SRC Reset
CK Reset
Write data to AK4118A.
Write data to the registers of FPGA.
Write data to the registers of AK4359.
Show message and pause the processing of script.
Wait some milliseconds.
When actual operation, it is possible to wait longer than this.
Download program file to DSP1/DSP2.
Download CRAM file to DSP1/DSP2.
Download OFREG file to DSP/DSP2.
Table 12. Script Command Table
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Measurement Results
[Measurement condition]
・ Measurement unit
・ MCKI
・ BICK
・ fs
・ Bit
・ Measurement Mode
・ Power Supply
・ Input Frequency
・ Measurement Frequency
・ Temperature
: Audio Precision, System two Cascade
: 12.288MHz
: 64fs
: 48kHz, 96kHz
: 24bit
: CKM Mode 0, Master Mode
: +12V, GND
: 1kHz
: 20 ~ [email protected], 20Hz ~ [email protected]
: Room
[Measurement Results]
1. ADC1
Result
ADC1 : AIN1(Differential) => ADC1 => SDOUTA1
fs = 48kHz (-1dBFS)
S/(N+D)
fs = 96kHz (-1dBFS)
fs = 48kHz (-60dBFS, A-Weighted)
DR
fs = 96kHz (-60dBFS)
fs = 48kHz (A-weighted)
S/N
fs = 96kHz
Lch
Rch
90.4
87.5
96.1
92.3
96.2
92.3
90.3
87.4
96.1
92.2
96.1
92.3
Unit
dB
dB
dB
2. ADC2
Result
ADC2 : AIN1(Differential) => ADC2 => SDOUTA1
fs = 48kHz (-1dBFS)
S/(N+D)
fs = 96kHz (-1dBFS)
fs = 48kHz (-60dBFS, A-Weighted)
DR
fs = 96kHz (-60dBFS)
fs = 48kHz (A-weighted)
S/N
fs = 96kHz
Lch
Rch
90.2
87.3
96.0
92.3
96.2
92.4
90.2
87.3
96.1
92.4
96.2
92.4
Unit
dB
dB
dB
3. ADCM
Result
ADCM : ADCM => ADCM => SDOUT7
fs = 48kHz (-1dBFS)
S/(N+D)
fs = 96kHz (-1dBFS)
fs = 48kHz (-60dBFS, A-Weighted)
DR
fs = 96kHz (-60dBFS)
fs = 48kHz (A-weighted)
S/N
fs = 96kHz
<KM106200>
88.5
87.0
95.5
91.5
95.6
91.6
Unit
dB
dB
dB
2011/03
- 21 -
[AKD7782-A]
[Plot Data]
1. ADC1 (fs=48kHz)
AK7782 AIN1=>ADC1=>SDOUTA1 FFT
[fs=48kHz, fin=1kHz, -1dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 14. ADC1 – FFT (-1dBFS) [fs=48kHz]
AK7782 AIN1=>ADC1=>SDOUTA1 FFT
[fs=48kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
Figure 15. ADC1 – FFT (-60dBFS) [fs=48kHz]
<KM106200>
2011/03
- 22 -
[AKD7782-A]
AK7782 AIN1=>ADC1=>SDOUTA1 FFT
[fs=48kHz, No Signal]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 16. ADC1 – FFT (No Signal) [fs=48kHz]
AK7782 AIN1=>ADC1=>SDOUTA1 THD+N vs. InputLevel
[fs=48kHz, fin=1kHz]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 17. ADC1 – THD+N vs. InputLevel [fs=48kHz]
<KM106200>
2011/03
- 23 -
[AKD7782-A]
AK7782 AIN1=>ADC1=>SDOUTA1 THD+N vs. InputFrequency
[fs=48kHz, fin=-1dBFS]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 18. ADC1 – THD+N vs. InputFrequency [fs=48kHz]
AK7782 AIN1=>ADC1=>SDOUTA1 Linearity
[fs=48kHz, fin=1kHz]
+0
TTT TT
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 19. ADC1 – Linearity [fs=48kHz]
<KM106200>
2011/03
- 24 -
[AKD7782-A]
AK7782 AIN1=>ADC1=>SDOUTA1 Frequency Response
[fs=48kHz, fin=-1dBFS]
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 20. ADC1 – Frequency Response [fs=48kHz]
AK7782 AIN1=>ADC1=>SDOUTA1 Crosstalk
[fs=48kHz, fin=-1dBFS]
-60
TTTTTTTTTT
TTT
TTTTT
TTTTT
T T
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
Figure 21. ADC1 – Crosstalk [fs=48kHz]
<KM106200>
2011/03
- 25 -
[AKD7782-A]
2. ADC1 (fs=96kHz)
AK7782 AIN1=>ADC1=>SDOUTA1 FFT
[fs=96kHz, fin=1kHz, -1dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
Figure 22. ADC1 – FFT (-1dBFS) [fs=96kHz]
AK7782 AIN1=>ADC1=>SDOUTA1 FFT
[fs=96kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
Figure 23. ADC1 – FFT (-60dBFS) [fs=96kHz]
<KM106200>
2011/03
- 26 -
[AKD7782-A]
AK7782 AIN1=>ADC1=>SDOUTA1 FFT
[fs=96kHz, No Signal]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 24. ADC1 – FFT (No Signal) [fs=96kHz]
AK7782 AIN1=>ADC1=>SDOUTA1 THD+N vs. InputLevel
[fs=96kHz, fin=1kHz]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 25. ADC1 – THD+N vs. InputLevel [fs=96kHz]
<KM106200>
2011/03
- 27 -
[AKD7782-A]
AK7782 AIN1=>ADC1=>SDOUTA1 THD+N vs. InputFrequency
[fs=96kHz, fin=-1dBFS]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 26. ADC1 – THD+N vs. InputFrequency [fs=96kHz]
AK7782 AIN1=>ADC1=>SDOUTA1 Linearity
[fs=96kHz, fin=1kHz]
+0
T TTT T
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 27. ADC1 – Linearity [fs=96kHz]
<KM106200>
2011/03
- 28 -
[AKD7782-A]
AK7782 AIN1=>ADC1=>SDOUTA1 Frequency Response
[fs=96kHz, fin=-1dBFS]
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 28. ADC1 – Frequency Response [fs=96kHz]
AK7782 AIN1=>ADC1=>SDOUTA1 Crosstalk
[fs=96kHz, fin=-1dBFS]
-60
TTT
TT
TTTTTTTTTTTTT
TTTTTTTTTT TT T T
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 29. ADC1 – Crosstalk [fs=96kHz]
<KM106200>
2011/03
- 29 -
[AKD7782-A]
3. ADC2 (fs=48kHz)
AK7782 AIN1=>ADC2=>SDOUTA1 FFT
[fs=48kHz, fin=1kHz, -1dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 30. ADC2 – FFT (-1dBFS) [fs=48kHz]
AK7782 AIN1=>ADC2=>SDOUTA1 FFT
[fs=48kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
Figure 31. ADC2 – FFT (-60dBFS) [fs=48kHz]
<KM106200>
2011/03
- 30 -
[AKD7782-A]
AK7782 AIN1=>ADC2=>SDOUTA1 FFT
[fs=48kHz, No Signal]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 32. ADC2 – FFT (No Signal) [fs=48kHz]
AK7782 AIN1=>ADC2=>SDOUTA1 THD+N vs. InputLevel
[fs=48kHz, fin=1kHz]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 33. ADC2 – THD+N vs. InputLevel [fs=48kHz]
<KM106200>
2011/03
- 31 -
[AKD7782-A]
AK7782 AIN1=>ADC2=>SDOUTA1 THD+N vs. InputFrequency
[fs=48kHz, fin=-1dBFS]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 34. ADC2 – THD+N vs. InputFrequency [fs=48kHz]
AK7782 AIN1=>ADC2=>SDOUTA1 Linearity
[fs=48kHz, fin=1kHz]
+0
TTTT
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 35. ADC2 – Linearity [fs=48kHz]
<KM106200>
2011/03
- 32 -
[AKD7782-A]
AK7782 AIN1=>ADC2=>SDOUTA1 Frequency Response
[fs=48kHz, fin=-1dBFS]
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 36. ADC2 – Frequency Response [fs=48kHz]
AK7782 AIN1=>ADC2=>SDOUTA1 Crosstalk
[fs=48kHz, fin=-1dBFS]
-60
TTTT
TTTT TTTTTT
T TTTTTT TT
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
Figure 37. ADC2 – Crosstalk [fs=48kHz]
<KM106200>
2011/03
- 33 -
[AKD7782-A]
4. ADC2 (fs=96kHz)
AK7782 AIN1=>ADC2=>SDOUTA1 FFT
[fs=96kHz, fin=1kHz, -1dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
Figure 38. ADC2 – FFT (-1dBFS) [fs=96kHz]
AK7782 AIN1=>ADC2=>SDOUTA1 FFT
[fs=96kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
Figure 39. ADC2 – FFT (-60dBFS) [fs=96kHz]
<KM106200>
2011/03
- 34 -
[AKD7782-A]
AK7782 AIN1=>ADC2=>SDOUTA1 FFT
[fs=96kHz, No Signal]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 40. ADC2 – FFT (No Signal) [fs=96kHz]
AK7782 AIN1=>ADC2=>SDOUTA1 THD+N vs. InputLevel
[fs=96kHz, fin=1kHz]
-60
T
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 41. ADC2 – THD+N vs. InputLevel [fs=96kHz]
<KM106200>
2011/03
- 35 -
[AKD7782-A]
AK7782 AIN1=>ADC2=>SDOUTA1 THD+N vs. InputFrequency
[fs=96kHz, fin=-1dBFS]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 42. ADC2 – THD+N vs. InputFrequency [fs=96kHz]
AK7782 AIN1=>ADC2=>SDOUTA1 Linearity
[fs=96kHz, fin=1kHz]
+0
T
T T TTTT T
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 43. ADC2 – Linearity [fs=96kHz]
<KM106200>
2011/03
- 36 -
[AKD7782-A]
AK7782 AIN1=>ADC2=>SDOUTA1 Frequency Response
[fs=96kHz, fin=-1dBFS]
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
40k
10k
20k
40k
Hz
Figure 44. ADC2 – Frequency Response [fs=96kHz]
AK7782 AIN1=>ADC2=>SDOUTA1 Crosstalk
[fs=96kHz, fin=-1dBFS]
-60
TTT
TTTTTTTT
TT
TTTTT TTTTTTTTTTT
-70
-80
-90
d
B
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
Hz
Figure 45. ADC2 – Crosstalk [fs=96kHz]
<KM106200>
2011/03
- 37 -
[AKD7782-A]
5. ADCM (fs=48kHz)
AK7782 AINM=>ADCM=>SDOUT7 FFT
[fs=48kHz, fin=1kHz, -1dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 46. ADCM – FFT (-1dBFS) [fs=48kHz]
AK7782 AINM=>ADCM=>SDOUT7 FFT
[fs=48kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
Figure 47. ADCM – FFT (-60dBFS) [fs=48kHz]
<KM106200>
2011/03
- 38 -
[AKD7782-A]
AK7782 AINM=>ADCM=>SDOUT7 FFT
[fs=48kHz, No Signal]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 48. ADCM – FFT (No Signal) [fs=48kHz]
AK7782 AINM=>ADCM=>SDOUT7 THD+N vs. InputLevel
[fs=48kHz, fin=1kHz]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 49. ADCM – THD+N vs. InputLevel [fs=48kHz]
<KM106200>
2011/03
- 39 -
[AKD7782-A]
AK7782 AINM=>ADCM=>SDOUT7 THD+N vs. InputFrequency
[fs=48kHz, fin=-1dBFS]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 50. ADCM – THD+N vs. InputFrequency [fs=48kHz]
AK7782 AINM=>ADCM=>SDOUT7 Linearity
[fs=48kHz, fin=1kHz]
+0
TTTT TT
T
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 51. ADCM – Linearity [fs=48kHz]
<KM106200>
2011/03
- 40 -
[AKD7782-A]
AK7782 AINM=>ADCM=>SDOUT7 Frequency Response
[fs=48kHz, fin=-1dBFS]
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 52. ADCM – Frequency Response [fs=48kHz]
6. ADCM (fs=96kHz)
AK7782 AINM=>ADCM=>SDOUT7 FFT
[fs=96kHz, fin=1kHz, -1dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 53. ADCM – FFT (-1dBFS) [fs=96kHz]
<KM106200>
2011/03
- 41 -
[AKD7782-A]
AK7782 AINM=>ADCM=>SDOUT7 FFT
[fs=96kHz, fin=1kHz, -60dBFS]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
40k
5k
10k
20k
40k
Hz
Figure 54. ADCM – FFT (-60dBFS) [fs=96kHz]
AK7782 AINM=>ADCM=>SDOUT7 FFT
[fs=96kHz, No Signal]
+0
-10
-20
-30
-40
-50
d
B
F
S
-60
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
Hz
Figure 55. ADCM – FFT (No Signal) [fs=96kHz]
<KM106200>
2011/03
- 42 -
[AKD7782-A]
AK7782 AINM=>ADCM=>SDOUT7 THD+N vs. InputLevel
[fs=96kHz, fin=1kHz]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 56. ADCM – THD+N vs. InputLevel [fs=96kHz]
AK7782 AINM=>ADCM=>SDOUT7 THD+N vs. InputFrequency
[fs=96kHz, fin=-1dBFS]
-60
-65
-70
-75
d
B
F
S
-80
-85
-90
-95
-100
-105
-110
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 57. ADCM – THD+N vs. InputFrequency [fs=96kHz]
<KM106200>
2011/03
- 43 -
[AKD7782-A]
AK7782 AINM=>ADCM=>SDOUT7 Linearity
[fs=96kHz, fin=1kHz]
+0
TTT TTT
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 58. ADCM – Linearity [fs=96kHz]
AK7782 AINM=>ADCM=>SDOUT7 Frequency Response
[fs=96kHz, fin=-1dBFS]
+0
-0.2
-0.4
-0.6
d
B
F
S
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
20
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 59. ADCM – Frequency Response [fs=96kHz]
<KM106200>
2011/03
- 44 -
[AKD7782-A]
REVISION HISTORY
Date
(yy/mm/dd)
11/03/25
Manual
Revision
KM106200
Board
Revision
0
Reason
Page
Contents
First edition
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
<KM106200>
2011/03
- 45 -
4
3
XILINX
D
AK4118A
TRX-LRCK
TRX-BICK
TX-DAT
TX-CLK
RX-DAT
RX-CLK
RX-CLK2
TRX-LRCK
TRX-BICK
TESTI1
TESTI2
TRX-LRCK
TRX-BICK
TX-DAT
TX-CLK
EXT-XTI
LRCLKI
BITCLKI
CKM0
CKM1
CKM2
TX-DAT
TX-CLK
TRX-PDN
SDIN1
SDIN2
SDIN3
SDIN4
SDIN5
SDIN6/JX1
SDIN7/JX2
TRX-PDN
PC-SI
PC-SCLK
PC-CS3N
TRX-PDN
RX-DAT
RX-CLK
RX-CLK2
SI/CAD0
RQN/CAD1
SCLK/SCL
SO
JX0
C
SRCLRCK
SRCBICK
SRC2LRCK
SRC2BICK
SDOUT5
SDOUT6
SDOUT7
SDOUTA1
POWER
CLKO
LRCLKO
BITCLKO
SDOUT1
SDOUT2
SDOUT3
SDOUT4
I2CSEL
INITRSTN
PCKRSTN
PADRSTN
PDSPRSTN
PSRCRSTN
PSRCSMUTE
SI/CAD0
RQN/CAD1
SCLK/SCL
SO
TESTI1
TESTI2
EXT-XTI
LRCLKI
BITCLKI
CKM0
CKM1
CKM2
SDIN1
SDIN2
SDIN3
SDIN4
SDIN5
SDIN6/JX1
SDIN7/JX2
JX0
SRCLRCK
SRCBICK
SRC2LRCK
SRC2BICK
SDOUT5
SDOUT6
SDOUT7
SDOUTA1
CLKO
LRCLKO
BITCLKO
SDOUT1
SDOUT2
SDOUT3
SDOUT4
1
Analog-IN
AK7782
I2CSEL
INITRSTN
PCKRSTN
PADRSTN
PDSPRSTN
PSRCRSTN
PSRCSMUTE
RX-DAT
RX-CLK
RX-CLK2
2
I2CSEL
INITRSTN
PCKRSTN
PADRSTN
PDSPRSTN
PSRCRSTN
PSRCSMUTE
AINL+
AINLAINR+
AINRAINL2
AINR2
AINL3
AINR3
AINL4
AINR4
AINL5
AINR5
AINL6
AINR6
AINL7
AINR7
AINL8
AINR8
SI/CAD0
RQN/CAD1
SCLK/SCL
SO
TESTI1
TESTI2
EXT-XTI
LRCLKI
BITCLKI
CKM0
CKM1
CKM2
AINM
AINL+
AINLAINR+
AINRAINL2
AINR2
AINL3
AINR3
AINL4
AINR4
AINL5
AINR5
AINL6
AINR6
AINL7
AINR7
AINL8
AINR8
AINM
AINL+
AINLAINR+
AINR-
D
AINL2
AINR2
AINL3
AINR3
AINL4
AINR4
AINL5
AINR5
AINL6
AINR6
AINL7
AINR7
AINL8
AINR8
AINM
SDIN1
SDIN2
SDIN3
SDIN4
SDIN5
SDIN6/JX1
SDIN7/JX2
JX0
C
SRCLRCK
SRCBICK
SRC2LRCK
SRC2BICK
SDOUT5
SDOUT6
SDOUT7
SDOUTA1
CLKO
LRCKO
BITCLKO
SDOUT1
SDOUT2
SDOUT3
SDOUT4
SDA
5
DAC
PC-SCL
LED-IND
PC-I2CSEL
PC-INITRSTN
B
PC-CS2N
PC-CS3N
PC-CS4N
PC-RQN
PC-SI
PC-SCLK
PC-SO
CLKO
LRCLKO
BITCLKO
DAC-SDIN1
DAC-SDIN2
DAC-SDIN3
DAC-SDIN4
DAC-PDN
DAC-SDIN1
DAC-SDIN2
DAC-SDIN3
DAC-SDIN4
DAC-PDN
DAC-SDIN1
DAC-SDIN2
DAC-SDIN3
DAC-SDIN4
DAC-PDN
B
PC-IF
PC-RQN
PC-SI
PC-SCLK
PC-SO
PC-CS2N
PC-CS3N
PC-CS4N
PC-I2CSEL
PC-INITRSTN
LED-IND
PC-SCL
PC-SDA
PC-RQN
PC-SI
PC-SCLK
PC-SO
PC-SI
PC-SCLK
PC-CS2N
PC-CS3N
PC-CS4N
PC-CS4N
PC-I2CSEL
PC-INITRSTN
LED-IND
PC-SCL
PC-SDA
A
A
Title
<AKD7782-A>
Size
A3
Date:
5
4
3
2
Document Number
<TOP>
Wednesday, January 12, 2011
Rev
<0>
Sheet
1
1
of
8
5
4
3
2
1
D
D
DVDD-3.3V
DVDD-3.3V
C1
+
C2
L1
SILK-SCREEN
SPDIN-IN
10uF
10uH
0.1uF
PORT1
SPDIF-IN
VCC
GND
OUT
3
2
1
R1
470
C3
R2
DIF-RX
0.1uF
10k
TORX147
U1
48
47
46
45
44
43
42
41
40
39
38
37
C5
10uF
1
2
3
4
5
6
7
8
9
10
11
12
DVDD-3.3V
RX4
NC
RX5
TEST2
RX6
VSS1
RX7
IIC
P/SN
XTL0
XTL1
VIN
L2
AK4118A
13
14
15
16
17
18
19
20
21
22
23
24
SILK-SCREEN
SPDIN-OUT
C
RX3
VSS4
RX2
TEST1
RX1
NC
RX0
VSS3
VCOM
R
AVDD
INT1
C
INT0
CSN
CCLK
CDTI
CDTO
PDN
XTI
XTO
DAUX
MCKO2
BICK
SDTO
36
35
34
33
32
31
30
29
28
27
26
25
TX-CLK
TX-CLK
XTL
R3
R4
R5
100
100
100
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
XTAL1
12.288MHz
C6
22pF
C7
AK4118A
10uH
IN
VCC
GND
JP1
XTI-CLK
TRX-PDN
22pF
PORT2
SPDIF-OUT
PC-CS3N
PC-SCLK
PC-SI
TVDD
NC
TX0
TX1
BOUT
COUT
UOUT
VOUT
DVDD
VSS2
MCKO1
LRCK
+
C4
0.1uF
R6
100
R7
100
TRX-LRCK
RX-CLK
DIF-TX
3
2
1
C8
0.1uF
0.1uF C9
C12
10uF
10uF
TOTX147
B
C10 +
0.1uF
C11
10uF
B
+
+
C13
DVDD-3.3V
DVDD-3.3V
DVDD-3.3V
TP1
TP (Black)
DVSS
+
C14
100uF/16V(A)
A
A
Title
<AKD7782-A>
Size
A3
Date:
5
4
3
2
Document Number
<AK4118A>
Tuesday, January 11, 2011
Rev
<0>
Sheet
1
2
of
8
5
4
3
2
1
AVDD
JP2
HEADER 2
CHIP-AVDD
-> : pin 2
D
1
2
default short
CN1
HEADER 20X2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
D
AINM
AINR4
AINL4
AINR3
AINL3
AINR2
AINL2
AINRAINR+
AINLAINL+
AINR5
AINL5
AINR6
AINL6
AINR7
AINL7
AINR8
AINL8
DVDD-1.8V
JP3
HEADER 2
CHIP-DVDD18
-> : pin 2
1
2
C
C
default short
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
TESTI2
PSRCSMUTE
PSRCRSTN
SDA
SRCLRCK
SRCBICK
SDIN1
JX0
SDIN6/JX1
SDIN7/JX2
SDOUT7
SDOUT6
SDOUTA1
TESTI1
I2CSEL
SRC2LRCK
SRC2BICK
EXT-XTI
CKM1
CKM0
CKM2
LRCKO
BITCLKO
SDOUT1
SDOUT2
SDOUT3
SDOUT4
SDOUT5
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
CN4
HEADER 15X2
CN2
HEADER 15X2
DVDD
JP4
HEADER 2
CHIP-DVDD
-> : pin 2
1
2
default short
B
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
CLKO
SDIN2
SDIN3
SDIN4
SDIN5
BITCLKI
LRCLKI
INITRSTN
PCKRSTN
PADRSTN
PDSPRSTN
RQN/CAD1
SI/CAD0
SCLK/SCL
SO
B
CN3
HEADER 15X2
A
A
Title
<AKD7782-A>
Size
A3
Date:
5
4
3
2
Document Number
<AK7782>
Thursday, January 13, 2011
Rev
<0>
Sheet
1
3
of
8
5
4
3
AREA : SHORTEST WIRING
RCA: WHITE
2
1
RCA: RED
D
D
+
JP5
2k
5
8
R15
R16
1
3
5
7
9
11
13
15
17
8
R19
U3B
LME49720MA
C24
7
2k
5
AINR4
AINR3
AINR2
AINRAINR+
AINR5
AINR6
AINR7
AINR8
2
4
6
8
10
12
14
16
18
HEADER 9X2
22uF(A)
AMP-PW+
+
C32
10uF
C31
0.1uF
C
C36
10uF
+
R26
10k
T
B
S
C41
68pF
22uF(A)
AMP-PW+
R39
10k
C50
0.1uF
+
AVSS
C54
10uF
T
B
S
RCA: YELLOW
A
3
6
R35
2k
C44
7
5
22uF(A)
C48
100pF
+
C52
10uF
U5B
LME49720MA
1
3
5
7
9
11
13
AINR4
AINR3
AINR2
AINR5
AINR6
AINR7
AINR8
2
4
6
8
10
12
14
B
HEADER 7X2
AMP-PW+
C51
0.1uF
TP3
TP (Black)
C55
0.1uF
+
C56
10uF
C57
RCA5
+
C53
0.1uF
1
2k
C46
100pF
R37
10k
R34
10k
4
4
R32
HEADER 7X2
8
C47
100pF
2
AMP-PW+
U5A
LME49720MA
+
+
+
8
5
JP8
8
C43
7
2k
AINL4
AINL3
AINL2
AINL5
AINL6
AINL7
AINL8
8
4
4
-
C45
100pF
R36
10k
6
R33
+
3
-
1
2k
U4B
LME49720MA
2
4
6
8
10
12
14
+
R31
R30
10k
C42
68pF
-
2
AMP-PW+
U4A
LME49720MA
C40 68pF
22uF(A)
MR-552LS(R)
JP7
1
3
5
7
9
11
13
R29
10k
R28 10k
+
+
C39 68pF
22uF(A)
R27
10k
C38
RCA4
+
R25 10k
-
R24
10k
C37
AINM
A
22uF(A)
MR-552LS(Y)
1
2
+
C49
10uF
JP6
SILK-SCREEN
AIN2R
MR-552LS(W)
R38
10k
6
C35
0.1uF
SILK-SCREEN
AIN2L
B
R18
10k
C28
100pF
TP2
TP (Black)
AVSS
T
B
S
3
C34
10uF
+
U3A
LME49720MA
1
2k
C26
100pF
R23
10k
C
RCA3
2
R21
10k
C30
0.1uF
C33
0.1uF
22uF(A)
AMP-PW+
AMP-PW+
+
C29
10uF
22uF(A)
MR-552LS(R)
HEADER 9X2
22uF(A)
C27
100pF
C22
68pF
+
+
C25
100pF
7
+
3
6
C23
C20 68pF
4
4
1
2k
R20
10k
R22
10k
-
R17
U2B
LME49720MA
+
AMP-PW+
R14
10k
-
4
U2A
LME49720MA
AINL4
AINL3
AINL2
AINLAINL+
AINL5
AINL6
AINL7
AINL8
2
4
6
8
10
12
14
16
18
R13 10k
8
1
3
5
7
9
11
13
15
17
MR-552LS(W)
2
T
B
S
4
22uF(A)
C21
68pF
R12 10k
+
+
C19 68pF
C18
RCA2
22uF(A)
8
R10 10k
+
R9 10k
-
C17
C16
R11
10k
+
R8
10k
+
C15
RCA1
T
B
S
SILK-SCREEN
AIN1R
-
SILK-SCREEN
AIN1L
AINM
JP9
HEADER 2
SILK-SCREEN
AINM
Title
<AKD7782-A>
Size
A3
Date:
5
4
3
2
Document Number
<Analog-IN>
Thursday, January 13, 2011
Rev
<0>
Sheet
1
4
of
8
5
4
3
2
1
C58
RCA6
D
D
+
LOUT1
22uF(A)
U6
74HCT541
VDD-DAC
C62
0.1uF
+ C63
10uF
51
1
R40
51
2
R41
51
3
R45
51
4
R46
51
5
R47
51
6
SMUTE/CSN/CAD0
LOUT1
25
R49
51
7
ACKS/CCLK/SDL
ROUT1
24
R50
51
8
DIF0/CDTI/SDA
P/S
23
R51
51
9
SDTI2
LOUT2
22
R52
51
10
SDTI3
ROUT2
21
R53
51
11
SDTI4
LOUT3
20
12
DIF1
ROUT3
19
13
DEM0
LOUT4
18
14
DVDD
ROUT4
17
15
DVSS
DEM/I2C
16
C
U8
GAB
DVDD-DAC
VCC
14
2
NC
GBA
13
DAC-PDN
3
1A
NC
12
PC-CS4N
4
2A
1B
11
PC-SCLK
5
2B
10
PC-SI
3A
6
4A
3B
09
7
GND
4B
08
C68
0.1uF
+ C69
10uF
+ C71
10uF
C72
0.1uF
DZF1
30
BICK
DZF2
29
SDTI1
AVDD
28
LRCK
AVSS
27
RSTB
VCOM
26
MCLK
C60
0.1uF
+ C61
10uF
C64
0.1uF
C65
10uF
RCA7
+
ROUT1
R43
DVDD-DAC
1
C59
22uF(A)
R44
22k
T
B
S
MR-552LS(R)
C66
LOUT2
RCA8
+
G1
G2
DAC1
U7
22uF(A)
R48
22k
T
B
S
MR-552LS(W)
DAC2
C67
ROUT2
RCA9
+
VCC
GND
20
10
MR-552LS(W)
22uF(A)
R54
22k
C
T
B
S
MR-552LS(R)
C70
LOUT3
RCA10
+
18
17
16
15
14
13
12
11
22uF(A)
R55
22k
T
B
S
MR-552LS(W)
DAC3
AK4359
C73
ROUT3
RCA11
+
1
19
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
A2
A3
A4
A5
A6
A7
A8
+
2
3
4
5
6
7
8
9
CLKO
BITCLKO
DAC-SDIN1
LRCLKO
DAC-SDIN2
DAC-SDIN3
DAC-SDIN4
R42
22k
T
B
S
22uF(A)
74HCT243
R56
22k
T
B
S
MR-552LS(R)
C74
RCA12
+
LOUT4
B
22uF(A)
R57
22k
T
B
S
B
MR-552LS(W)
DAC4
DVDD-DAC
AMP-PW+
VDD-DAC
REG1
C75
LM1117-5V
2
+ C78
10uF
C76
0.1uF
OUT
3
10
GND
IN
+
ROUT4
R58
1
22uF(A)
C77
0.1uF
RCA13
+ C79
10uF
R59
22k
T
B
S
MR-552LS(R)
SILK-SCREEN
AGND
1
TP4
TP (Black)
A
A
Title
<AKD7782-A>
Size
A3
Date:
5
4
3
2
Document Number
<DAC>
Wednesday, January 12, 2011
Rev
<0>
Sheet
1
5
of
8
5
4
3
2
1
R60 10k
USB-VDD
USB-RST
18
JP11
MCLR_N/Vpp/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
(default : Release)
R62
10k
VSS1
APE 1F
Reset
VDD1
SW1
VDD0
Release
C83
0.1uF
6
7
U9
28
C84
0.1uF
USB Reset
12
13
33
34
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
30
31
OSC1/CLKI
OSC2/CLKO/RA6
25
26
27
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
37
VUSB
1
2
3
4
5
17
16
15
14
11
10
9
8
D
SILK-SCREEN
1: VDD
2: MCLR
3: PGD
4: PGC
5: GND
SILK-SCREEN
1: USB-5V
3: USB-3.3V
5: DVDD
2
4
6
C81
10uF
1
3
5
+
C80
10uF
VSS0
R61
100k
29
C82
0.1uF
+
D
default 3-4 pin short
JP10
PIC-VDD-SEL
DVDD-3.3V
HEADER 5
C85 22pF
C
DVDD-3.3V
R63
10k
R64
C91
470nF
100
19
20
21
22
23
24
PC-SDA
PC-SCL
PC-SO
PIC18F4550
TQFP 44-PIN
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
38
39
40
41
2
3
4
5
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RA0/AN0
RC2/CCP1/P1A
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RC4/D-/VM
RA5/AN4/SS_N/HLVDIN/C2OUT
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
32
35
36
PC-CS3N
PC-INITRSTN
PC-CS4N
PC-I2CSEL
PC-SCLK
PC-SI
PC-RQN
PC-CS2N
REG2
LM1117-3.3V
C
1
+
C87
C88
10uF
0.1uF
IN
GND
C86 22pF
OUT
2
C89
3
XTI
XTO
XTAL2
20MHz
+
0.1uF
C90
10uF
U10
R65
R66
42
43
44
1
VUSB
DD+
GND
22
22
1
2
3
4
VUSB
DD+
GND
USB(B type)
PIC18F4550
DVDD-3.3V
B
DVSS
TP5
TP (Black)
B
C92
+
100uF/16V(A)
DVDD-3.3V
DVDD-3.3V
U11A
+
R67
C94
0.1uF
LED-IND
10k
16
14
VCC
CEXT
15
REXT/CEXT
U11B
16
6
C93
33uF(A)
1
2
3
8
A
B
CLR
GND
U12
Q
Q
13
4
R68
R69
100
100
1
3
7
GREEN
COM
2
9
10
11
8
RED
BICOLOR LED
74HC221
VCC
CEXT
REXT/CEXT
A
B
CLR
GND
Q
5
Q
12
74HC221
A
A
Title
<AKD7782-A>
Size
A3
Date:
5
4
3
2
Document Number
<PC-IF>
Thursday, January 13, 2011
Rev
<0>
Sheet
1
6
of
8
5
4
3
2
1
D
D
AMP-PW+
DVDD
AVDD
REG3
LM1084-3.3V
heatsink
L3
10uH
2
+ C95
10uF
C96
0.1uF
+ C98
10uF
C97
0.1uF
+ C99
CL1
1
IN
1
1
C100
0.1uF
3
AVSS
OUT
GND
TM1
TP6
TP (Black)
+ C101
10uF
+
i
RED(+12V)
TJ-563
C102
100uF/16V(A)
TM2
100uF/16V(A)
1
2
Wire Short
i
BLACK(GND)
TJ-563
C
C
REG4
LM1117-1.8V
2
+ C105
10uF
CHIP-DVSS
C103
0.1uF
OUT
+ C106
heatsink
IN
1
C104
0.1uF
3
TP7
TP (Black)
GND
DVDD-1.8V
+ C107
10uF
1
2
100uF/16V(A)
CL2
Wire Short
B
B
DVDD-3.3V
JP12
HEADER 2
TP8
TP (Black)
2
default short
+ C110
10uF
C108
0.1uF
OUT
GND
DVSS
REG5
LM1084-3.3V
2
1
3
P-DVDD
-> : pin 2
heatsink
IN
1
C109
0.1uF
+ C111
10uF
A
A
Title
<AKD7782-A>
Size
A3
Date:
5
4
3
2
Document Number
<POWER>
Thursday, January 13, 2011
Rev
<0>
Sheet
1
7
of
8
5
4
3
2
1
DVDD-3.3V
C112
0.1uF
SMUX PORT
+ C113
10uF
JP13
SMUX-MCLK
SMUX-BICK
SMUX-LRCK
SMUX-DAT1
D
1
3
5
7
9
D
2
4
6
8
10
SILK-SCREEN
SMUX PORT/SMUX PORT2
1: MCLK
3: BIT
5: LR
7: DI
9: VDD
10: DO
HEADER 5X2
SMUX-DAT2
SMUX PORT2
U13
JP14
CKM2
CKM0
CKM1
EXT-XTI
SRC2BICK
SRC2LRCK
I2CSEL
TESTI1
DAC-SDIN4
DAC-SDIN3
DAC-SDIN2
DAC-SDIN1
DAC-PDN
TRX-PDN
TX-CLK
TX-DAT
RX-CLK2
TRX-BICK
RX-DAT
TRX-LRCK
RX-CLK
C
PC-SO
PC-SCL
PC-CS2N
PC-RQN
PC-SI
PC-I2CSEL
PC-CS4N
PC-INITRSTN
PC-CS3N
R71
R72
R73
100
100
100
R74
R75
R76
R78
100
100
100
100
R70
R84
100
100
R88
R90
R91
100
100
100
LED-IND
B
PC-SCLK
R97
100
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
25
28
29
30
32
33
34
35
36
37
39
40
41
GTS3
GTS4
GTS1
GTS2
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
99
27
23
22
GSR
GCK3
GCK2
GCK1
JTAG
JP15
2:
4:
6:
8:
10:
TCK
TDI
TDO
TMS
VDD
1
3
5
7
9
48
45
83
47
2
4
6
8
10
HEADER 5X2
TCK
TDI
TDO
TMS
DVDD-3.3V
C124 0.1uF
I/O29
I/O30
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
I/O72
42
43
46
49
50
52
53
54
55
56
58
59
60
61
63
64
65
66
67
68
70
71
72
73
74
76
77
78
79
80
81
82
85
86
87
89
90
91
92
93
94
95
96
97
VINT0
VINT1
VINT2
5
57
98
VIO0
VIO1
VIO2
VIO3
26
38
51
88
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
21
31
44
62
69
75
84
100
SMUX2-MCLK
SMUX2-BICK
SMUX2-LRCK
SMUX2-DAT1
1
3
5
7
9
C114
0.1uF
2
4
6
8
10
HEADER 5X2
SMUX2-DAT2
R77
R79
R80
R82
R83
R85
R86
0
100
100
100
100
100
100
DVDD-3.3V
LEAD RED LED
CLKO
SDIN2
SDIN3
SDIN4
SDIN5
BITCLKI
LRCLKI
R81
2
1
D1
470
C
INITRSTN
R87
R89
100
100
R92
R93
100
100
R94
R95
R96
100
100
100
PCKRSTN
PADRSTN
PDSPRSTN
RQN/CAD1
SI/CAD0
SCLK/SCL
SO
SDOUTA1
SDOUT6
SDOUT7
SDIN7/JX2
SDIN6/JX1
JX0
SDIN1
SRCBICK
SRCLRCK
PSRCRSTN
PSRCSMUTE
TESTI2
SDOUT5
SDOUT4
SDOUT3
SDOUT2
SDOUT1
BITCLKO
LRCLKO
B
DVDD-3.3V
C115
0.1uF
C116
0.1uF
C117
0.1uF
+ C118
10uF
C119
0.1uF
XC95144XL
C120
0.1uF
DVSS
C121
0.1uF
TP9
TP (Black)
C122
0.1uF
+ C123
10uF
DVDD-3.3V
A
A
+ C125
100uF/16V(A)
Title
<AKD7782-A>
Size
A3
Date:
5
4
3
2
Document Number
<XILINX>
Thursday, January 13, 2011
Rev
<0>
Sheet
1
8
of
8
4
CHIP-AVDD
D
C132
0.1uF
1
1
1
1
1
1
AINM
TP147
1
AINL4
TP149
1
AINR4
TP148
1
AINL3
TP151
1
AINR3
TP150
1
AINR2
TP152
1
AINL2
TP153
1
AINRTP155
1
AINLTP157
1
AINR+
TP156
1
AINL+
TP158
1
AINL5
TP160
CN101
HEADER 20X2
AINR5
TP159
2
AINL6
TP162
1
AINL8
TP166
CL101
Short
1
10uF
C133
AINR6
TP161
100uF
D
AINM
AINR4
AINL4
AINR3
AINL3
AINR2
AINL2
AINRAINR+
AINLAINL+
AINR5
AINL5
AINR6
AINL6
AINR7
AINL7
AINR8
AINL8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
AINL7
TP164
+ C139
2
+
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
AINR7
TP163
AVDD
TP170
1
CHIP-AVDD
3
AINR8
TP165
5
1
1
CL102
1
10uF
C135
1
AGND
TP171
VCOM
TP154
1
2
Short
+
NC
TESTI1
TESTI2
72
I2CSEL
TP103
5
I2CSEL
PSRCSMUTE
71
SRC2LRCK
TP104
6
SRC2LRCK
BVSS
70
SRC2BICK
TP105
7
SRC2BICK
DVDD
69
EXT
TP106
C131
10uF
CHIP-AVDD
1
4
C130
0.1uF
TESTI2
TP146
1
77
76
78
AINR4
AINM
79
80
AINL4
AINR3
81
AINL3
82
83
AINL2
AINR2
84
AVDD
86
85
VREFH
87
AVSS
VREFL
VCOM
89
88
AINR-
AINR+
90
91
AINL-
92
AINL+
AINR5
94
93
1
TESTI1
TP102
1
AINR6
AINL5
95
96
97
73
1
PSRCSMUTE
TP145
C
CHIP-DVDD
C128
0.1uF
SRCLRCK
64
XTI
12
XTO
Y101
12.288MHz
C141
22pF(DIP)
13
SRCBICK
63
SDIN1
62
JX0
61
CKM0
SDIN6/JX1
60
CKM2
SDIN7/JX2
59
+
DVDD18
1
DVSS
14
CKM1
TP107
15
CKM1
1
0.1uF
C106
CKM0
TP108
16
1
10uF
C107
CKM2
TP109
17
CHIP-DVDD18
CHIP-DVDD18
18
DVDD18
19
C108
0.1uF
C110
0.1uF
10uF
C111
58
DVSS
DVSS
57
DVDD
DVDD
56
C124
0.1uF
SDIN1
TP140
JX0
TP139
SDIN6/JX1
TP138
SDIN7/JX2
TP137
TESTI2
PSRCSMUTE
PSRCRSTN
SDA
SRCLRCK
SRCBICK
SDIN1
JX0
SDIN6/JX1
SDIN7/JX2
SDOUT7
SDOUT6
SDOUTA1
STO
RDY
53
1
24
SDOUT2
STO
52
1
SDOUT3
TP114
100
R106
25
RDY
51
SDOUT4
TP115
100
R107
SDOUT5
TP116
100
R108
100uF
DGND
TP172
SDOUTA1
TP134
STO
TP133
RDY
TP132
50
DVSS
49
SDOUT6
TP135
C121
+
1
1
10uF
CHIP-DVDD
CHIP-DVDD18
SCLK/SCL
TP130
1
SI/CAD1
TP129
1
RQN/CAD1
TP128
PADRSTN
TP126
1
PDSPRSTN
TP127
1
PCKRSTN
TP125
10uF
INITRSTN
TP124
1
SDIN2
TP118
48
DVDD18
47
46
45
44
43
42
41
40
DVSS
DVDD18
+
LRCLKI
TP123
1
CHIP-DVDD18
1
BITCLKI
TP122
1
SDIN5
TP121
SDIN4
TP120
SDIN3
TP119
CHIP-DVDD18
1
1
CLKO
SDIN2
SDIN3
SDIN4
SDIN5
BITCLKI
LRCLKI
INITRSTN
PCKRSTN
PADRSTN
PDSPRSTN
RQN
SI
SCLK
SO
C119
A
1
R110
100
1
+ C137
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
CHIP-DVDD
CLKO
TP117
A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
SDOUT7
TP136
0.1uF 0.1uF
C118 C120
C117
10uF
10uF
C115
DGND
TP173
+
1
DVDD
TP169
0.1uF
C116
+
+
10uF
C113
39
38
BITCLKI
SDIN5
LRCLKI
37
36
35
SDIN3
SDIN4
34
33
SDIN2
DVDD18
32
31
DVSS
DVDD
30
29
CLKO1
SDOUT4
SDOUT5
28
27
26
0.1uF 0.1uF
C112 C114
C138
100uF
SO
SDOUTA1
100
R105
DVDD
SDOUT1
SDOUT2
TP113
SCLK/SCL
1
23
100
R111
SI/CAD0
100
R112
100
R104
RQN/CAD1
54
SDOUT1
TP112
PDSPRSTN
1
SDOUT6
PADRSTN
55
BITCLKO
PCKRSTN
SDOUT7
22
INITRSTN
1
LRCKO
100
R103
1
+
21
BITCLKO
TP111
100
R109
+
CHIP-DVDD18
B
CHIP-DVDD
100
R113
AK7782
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
C123
10uF
100
R102
SDOUT3
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
TP168
DVDD18
+ C125
10uF
C122
0.1uF
1
20
CHIP-DVDD
DVDD18
LRCKO
TP110
1
SRCBICK
TP141
CN104
HEADER 15X2
+
+ C109
10uF
1
SRCLRCK
TP142
CHIP-DVDD18
B
CHIP-DVDD
SDA
TP143
1
C140
22pF(DIP)
CN102
HEADER 15X2
AK7782
100 pin LQFP
PSRCRSTN
TP144
1
SDA
65
11
CHIP-DVDD18
1
66
1
PSRCRSTN
1
DVSS
C127
10uF
1
10
C126
0.1uF
1
67
C104
0.1uF
1
JP101
XTI-SEL
CRY-XTI
0(DIP)
R114
+ C105
10uF
1
EXT-XTI
1
68
DVDD18
1
DVSS
DVDD
1
BVSS
9
CHIP-DVDD
1
8
+ C129
10uF
1
TESTI1
I2CSEL
SRC2LRCK
SRC2BICK
EXT-XTI
CKM1
CKM0
CKM2
LRCKO
BITCLKO
SDOUT1
SDOUT2
SDOUT3
SDOUT4
SDOUT5
AINL6
AVDD
1
100uF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
AINR7
AVDD
1
1
+ C136
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
98
74
3
+
DVDD18
TP167
AINL7
75
AVSS
+
CHIP-DVDD18
AINR8
100
NC
AVSS
C102
0.1uF
10uF
C103
CHIP-AVDD
C
AINL8
LFLT
2
1
1
1
1.5k(DIP)
R101
+
LFLT
TP101
47nF(DIP)
C101
99
C134
0.1uF
U101
SO
TP131
Title
<AKD7782-A-SUB-100LQFP>
CN103
HEADER 15X2
Size
A2
Date:
5
4
3
2
Document Number
<Plastic-Sub>
Rev
<0>
Thursday, January 13, 2011
1
Sheet
1
of
1
4
CHIP-AVDD
1
10uF(DIP)
C135
2
AINM
TP147
AINL4
TP149
AINR4
TP148
1
NC
TESTI1
TP102
4
TESTI1
TESTI2
72
I2CSEL
TP103
5
I2CSEL
PSRCSMUTE
71
SRC2LRCK
TP104
6
SRC2LRCK
BVSS
70
SRC2BICK
TP105
C130
0.1uF
C131
10uF
CHIP-AVDD
1
73
TESTI2
TP146
1
77
AVDD
PSRCSMUTE
TP145
C
CHIP-DVDD
DVSS
PSRCRSTN
66
11
XTI
SDA
65
12
XTO
SRCLRCK
64
Y101
12.288MHz
C141
22pF(DIP)
13
+
14
DVDD18
1
DVSS
CKM1
TP107
15
CKM1
1
0.1uF
C106
CKM0
TP108
16
1
10uF
C107
CKM2
TP109
17
CHIP-DVDD18
SRCBICK
63
SDIN1
62
JX0
61
CKM0
SDIN6/JX1
60
CKM2
SDIN7/JX2
59
SOCKET
CHIP-DVDD18
C108
0.1uF
+
DVDD18
58
C124
0.1uF
SDIN1
TP140
JX0
TP139
SDIN6/JX1
TP138
SDIN7/JX2
TP137
CN104
HEADER 15X2
TESTI2
PSRCSMUTE
PSRCRSTN
SDA
SRCLRCK
SRCBICK
SDIN1
JX0
SDIN6/JX1
SDIN7/JX2
SDOUT7
SDOUT6
SDOUTA1
STO
RDY
DVSS
DVSS
57
DVDD
DVDD
56
LRCKO
SDOUT7
55
CHIP-DVDD
100
R113
SDOUT6
54
100
R112
100
R111
1
100
R102
21
1
BITCLKO
TP111
100
R103
22
1
SDOUT1
TP112
100
R104
23
SDOUT1
SDOUTA1
53
1
SDOUT2
TP113
100
R105
24
SDOUT2
STO
52
1
SDOUT3
TP114
100
R106
25
RDY
51
1
C122
0.1uF
LRCKO
TP110
SDOUT4
TP115
100
R107
SDOUT5
TP116
100
R108
DGND
TP172
DGND
TP173
B
C123
10uF
SDOUT6
TP135
SDOUTA1
TP134
STO
TP133
RDY
TP132
SO
SDOUT7
TP136
50
DVDD
DVSS
C138
100uF
C121
+
1
1
10uF
CHIP-DVDD
CHIP-DVDD18
SCLK/SCL
TP130
1
SI/CAD1
TP129
1
RQN/CAD1
TP128
PADRSTN
TP126
1
PDSPRSTN
TP127
1
PCKRSTN
TP125
10uF
INITRSTN
TP124
1
49
C119
+
LRCLKI
TP123
1
CHIP-DVDD18
1
BITCLKI
TP122
SDIN5
TP121
SDIN4
TP120
CHIP-DVDD18
SDIN3
TP119
1
SDIN2
TP118
48
DVDD18
SCLK/SCL
47
46
SI/CAD0
45
PDSPRSTN
RQN/CAD1
44
43
PADRSTN
42
PCKRSTN
41
40
C117
10uF
1
1
CLKO
SDIN2
SDIN3
SDIN4
SDIN5
BITCLKI
LRCLKI
INITRSTN
PCKRSTN
PADRSTN
PDSPRSTN
RQN
SI
SCLK
SO
+
CHIP-DVDD18
0.1uF 0.1uF
C118 C120
A
1
R110
100
1
100uF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
CHIP-DVDD
CLKO
TP117
+ C137
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
10uF
C115
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
+
1
DVDD
TP169
0.1uF
C116
+
+
10uF
C113
DVSS
DVDD18
0.1uF 0.1uF
C112 C114
100
R109
39
38
BITCLKI
SDIN5
LRCLKI
37
36
35
SDIN3
SDIN4
34
33
SDIN2
DVDD18
32
31
DVSS
30
29
DVDD
CLKO1
SDOUT5
28
27
AK7782
26
SDOUT4
SDOUT3
INITRSTN
BITCLKO
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
TP168
DVDD18
+ C125
10uF
20
1
CHIP-DVDD
1
SRCBICK
TP141
+
10uF
C111
DVDD18
19
C110
0.1uF
B
1
SRCLRCK
TP142
1
18
CHIP-DVDD
SDA
TP143
CHIP-DVDD18
+ C109
10uF
A
PSRCRSTN
TP144
1
C140
22pF(DIP)
CN102
HEADER 15X2
AK7782
100 pin LQFP
CHIP-DVDD18
1
10
C127
10uF
1
67
1
DVDD18
1
DVDD
C104
0.1uF
1
0(DIP)
R114
+ C105
10uF
JP101
XTI-SEL
CRY-XTI
1
EXT-XTI
+ C129
10uF
C126
0.1uF
1
9
C128
0.1uF
1
68
1
69
DVSS
1
DVDD
BVSS
1
SRC2BICK
8
1
7
CHIP-DVDD
EXT
TP106
2
76
78
AINR4
AINM
79
80
AINL4
AINR3
81
AINL3
82
83
AINL2
AINR2
84
AVDD
86
85
VREFH
87
AVSS
VREFL
VCOM
89
88
AINR-
AINR+
90
91
AINL-
92
AINL+
AINR5
93
94
AINR6
AINL5
95
96
97
AVDD
1
AINR7
AINL6
98
AINL7
74
3
1
AINR8
100
75
AVSS
C102
0.1uF
10uF
C103
1
TESTI1
I2CSEL
SRC2LRCK
SRC2BICK
EXT-XTI
CKM1
CKM0
CKM2
LRCKO
BITCLKO
SDOUT1
SDOUT2
SDOUT3
SDOUT4
SDOUT5
AINL8
NC
AVSS
1
LFLT
1
1
CL102
Short
+
100uF
1
2
+
+ C136
1
1
C
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
1
1
1.5k(DIP)
R101
CHIP-AVDD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
1
47nF(DIP)
C101
99
U101
LFLT
TP101
DVDD18
TP167
1
VCOM
TP154
C134
0.1uF
Short
CHIP-DVDD18
1
AINL3
TP151
1
AGND
TP171
AINR3
TP150
C132
0.1uF
1
AINR2
TP152
1
AINL2
TP153
1
1
1
AINRTP155
1
AINLTP157
1
AINR+
TP156
1
AINL+
TP158
1
AINL5
TP160
1
AINR5
TP159
1
AINL6
TP162
1
+
1
D
+
CL101
1
AINR6
TP161
CN101
HEADER 20X2
1
10uF
C133
AINL7
TP164
100uF
AINM
AINR4
AINL4
AINR3
AINL3
AINR2
AINL2
AINRAINR+
AINLAINL+
AINR5
AINL5
AINR6
AINL6
AINR7
AINL7
AINR8
AINL8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
AINR7
TP163
+ C139
D
2
+
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
AINL8
TP166
AVDD
TP170
1
CHIP-AVDD
3
AINR8
TP165
5
SO
TP131
Title
<AKD7782-SUB-A-100LQFP-SOCKET>
CN103
HEADER 15X2
Size
A2
Date:
5
4
3
2
Document Number
<Ceramic-Sub>
Rev
<0>
Thursday, January 13, 2011
1
Sheet
1
of
1