AMSCO AS1160

D a ta s h e e t
A S 11 6 0 / A S 11 6 1
2 0 M H z - 6 6 M H z , 1 0 - B i t B u s , I E E E 11 4 9 . 1 ( J TA G )
C o m p l i a n t LV D S S e r i a l i z e r / D e s e r i a l i z e r
1 General Description
2 Key Features
The AS1160 (serializer) is designed to convert 10-bit
wide parallel LVCMOS/LVTTL data bus signals into a
single high-speed LVDS serial data stream with clock.
The AS1161 (deserializer) transforms the high-speed
LVDS serial data stream back into a 10-bit wide parallel
data bus with recovered parallel clock.
Both devices are compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture
(including the defined boundary-scan test logic and test
access port consisting of Test Data Input, Test Data Out,
and Test Mode Select, Test Clock, and Test Reset).
The devices also feature an at-speed BIST mode which
allows the interconnects between the serializer and
deserializer to be verified at-speed.
The single differential-pair data-path makes PCB design
easier, and reduced cable/PCB-trace count and connector size significantly reduce cost. Since one output transmits clock and data bits serially, clock-to-data and datato-data skew are eliminated.
Powerdown mode reduces supply current when both
devices are idle.
Both devices are available in a CTBGA 49-bumps pin
package.
!
Serial Bus LVDS Data Rate: 660 Mbps @ 66MHz
Clock
!
10-bit Parallel Interface
!
Synchronization Mode and Lock Indicator
!
Programmable Edge Trigger on Clock
!
High Impedance on Rx Inputs during Poweroff
!
Bus LVDS Serial Output Load: 28Ω
!
IEEE 1149.1 (JTAG) Compliant and At-Speed BIST
Test Mode
!
Clock Recovery from PLL Lock to Random Data
Patterns
!
Guaranteed Transition each Data Transfer Cycle
!
Chipset (Tx + Rx) Power Consumption: < 500 mW
@ 66MHz
!
Single Differential-Pair eliminates Multi-Channel
Skew
!
Flow-Through Pinout for Simple PCB Layout
!
Small CTBGA 49-bumps Package
3 Applications
The devices are ideal for cellular phone base stations,
add drop muxes, digital cross-connects. DSLAMs, networkswitches and routers or backplane interconnect.
Figure 1. Block Diagrams
10
DIN0:9
Input
Latch
Parallelto-Serial
DO+
TCKR/FN
DO-
Parallelto-Serial
RI+
LVDS
PLL
PLL
10
ROUT0:9
RI-
TCLK
Timing &
Control
Output
Latch
Timing &
Control
REFCLK
REN
DEN
LOCKN
SYNC1
SYNC2
AS1160
AS1161
Clock
Recovery
RCKR/FN
TDI
TDO
RCLK
TDI
IEEE 1149.1
Test Access
Port
TRSTN
TRSTN
IEEE 1149.1
Test Access
Port
TDO
TMS
TMS
TCK
TCK
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Revision 1.01
1 - 29
AS1160/AS1161
Datasheet
Contents
1 General Description..............................................................................................................................
1
2 Key Features ........................................................................................................................................
1
3 Applications ..........................................................................................................................................
1
Contents ...............................................................................................................................................................
2
4 Pinout ...................................................................................................................................................
3
Pin Assignments and Descriptions .......................................................................................................................
3
5 Absolute Maximum Ratings..................................................................................................................
5
6 Electrical Characteristics ......................................................................................................................
6
Serializer Timing Requirements for TCLK ....................................................................................................... 6
Serializer Switching Characteristics ................................................................................................................ 6
Deserializer Electrical Characteristics ..............................................................................................................7
Deserializer Timing Requirements for REFCLK.............................................................................................. 8
Deserializer Switching Characteristics ............................................................................................................ 8
Scan Circuitry Timing Requirements............................................................................................................... 9
7 Typical Operating Characteristics AS1160 .........................................................................................
8 Typical Operating Characteristics AS1161
9 Timing Diagrams
.......................................................................................... 11
................................................................................................................................. 12
10 Detailed Description
Initialization
10
.......................................................................................................................... 19
.........................................................................................................................................................19
Data Transfer......................................................................................................................................................
20
Resynchronization ..............................................................................................................................................
21
Powerdown.........................................................................................................................................................
21
Tri-State ..............................................................................................................................................................
21
11 Application Information .................................................................................................................
22
Power Considerations ........................................................................................................................................
22
Powering up the Deserializer .............................................................................................................................
22
Transmitting Data ...............................................................................................................................................
22
Noise Margin ......................................................................................................................................................
23
Lock Loss Recovery ...........................................................................................................................................
23
Hot Insertion .......................................................................................................................................................
23
PCB Considerations ...........................................................................................................................................
24
Transmission Media ...........................................................................................................................................
24
Failsafe Biasing ..................................................................................................................................................
25
Signal Integrity....................................................................................................................................................
25
JTAG Test Modes ...............................................................................................................................................
26
SAMPLE/PRELOAD ......................................................................................................................................
BYPASS.........................................................................................................................................................
EXTEST .........................................................................................................................................................
IDCODE .........................................................................................................................................................
RUNBIST .......................................................................................................................................................
26
26
26
26
26
12 Package Drawings and Markings .....................................................................................................
27
13 Ordering Information........................................................................................................................
28
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Revision 1.01
2 - 29
AS1160/AS1161
Datasheet - P i n o u t
4 Pinout
Pin Assignments and Descriptions
Figure 2. AS1160 Pin Assignments (Top View)
A1
A2
DGND
N/C
B1
B2
DIN1
N/C
C1
DIN3
A3
A4
A5
DIN0 SYNC1 AVDD
B3
B4
SYNC2 AVDD
C2
C3
C4
DGND DVDD DVDD
B5
A6
A7
AVDD
N/C
B6
AGND AGND
C5
N/C
C6
B7
AVDD
C7
AGND PWDNN
D1
D2
D3
D4
D5
D6
D7
DIN5
DIN2
DIN4
N/C
DO-
DEN
DO+
E5
E6
E7
E1
E2
E3
E4
DIN7
DIN6
TMS
TCLK
DVDD DGND AGND
F1
F2
F3
F4
F5
F6
F7
TDI
DIN8
TCK
DIN9
DGND
N/C
AGND
G2
G3
G4
G5
G1
TDO
TRSTNTCKR/FN DGND AVDD
G6
G7
N/C
N/C
Table 1. AS1160 Pin Descriptions
Pin Number
See Figure 2
Pin Name
Description
Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input
DIN0:DIN9
register.
Transmit Clock Rising/Falling Strobe Select. LVTTL level input. Selects TCLK
active edge for strobing of DINx data.
TCKR/FN
1 = Rising edge.
0 = Falling edge.
+ Serial Data Output. Non-inverting Bus LVDS differential output.
DO+
- Serial Data Output. Inverting Bus LVDS differential output.
DOSerial Data Output Enable. LVTTL level input. If DEN is set to logic low the Bus LVDS
DEN
outputs are in tri-state condition.
Powerdown. LVTTL level input. Driving this pin low shuts down the PLL, tri-states the
PWDNN
outputs and puts the device into low power sleep mode.
Transmit Clock. LVTTL level input. Input for 20MHz to 66MHz system clock.
TCLK
Synchronization. LVTTL level input. Assertion of SYNC (high) for at least 5 clock
cycles to be transmit a synchronization signal (SYNCPAT) on the Bus LVDS serial
SYNC1,
SYNC2
output. Synchronization symbols continue to be sent if SYNCx continues to be
asserted. SYNC1 and SYNC2 pins are combined through an OR gate.
+3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital circuitry.
DVDD
Digital Circuit Ground. GND reference point for the digital part of the AS1160.
DGND
+3.0V to +3.6V Analog Power Supply (PLL and Analog Circuits). AVDD and DVDD
should be at the same potential and must not be more than 0.3V apart even on
AVDD
transient basis. Both supplys should be decoupled by a capacitor of typically 10nF.
Analog Ground (PLL and Analog Circuits).
AGND
IEEE 1149.1 Test Data Input
TDI
IEEE 1149.1 Test Data Output
TDO
IEEE 1149.1 Test Mode Select Input
TMS
IEEE 1149.1 Test Clock Input
TCK
IEEE 1149.1 Test Reset Input
TRSTN
No Connection. Leave open-circuit, do not connect these pins.
N/C
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Revision 1.01
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AS1160/AS1161
Datasheet - P i n o u t
Figure 3. AS1161 Pin Assignments (Top View)
A1
DGND
B1
A2
A3
A4
A5
A6
A7
N/C REFCLK AGND ROUT1 DGND DVDD
B2
B3
B4
B5
B6
B7
AVDD AGND RCKR/FN ROUT2 DGND ROUT3 DVDD
C1
C2
C3
RI-
AVDD
N/C
C4
D1
D2
D3
D4
REN
RI+
PWDNN
N/C
E1
E2
LOCKN RCLK
F1
F2
AVDD
AVDD
G1
AVDD
G2
C5
C7
D5
E3
E4
E5
DGND
TCK
F3
F4
F5
AGND AGND ROUT8
G4
D6
D7
DVDD ROUT5 DGND
N/C
G3
C6
ROUT0 DVDD DVDD ROUT4
G5
E6
E7
TRSTN DGND
F6
F7
TDI
ROUT6
G6
AGND DGND ROUT9 ROUT7 TDO
G7
TMS
Table 2. AS1161 Pin Descriptions
Pin Number
Pin Name
Description
ROUT0:ROUT9 Data Output. ±4mA CMOS level outputs.
Recovered Clock Rising/Falling Strobe Select. LVTTL level input. Selects RCLK
active edge for strobing of ROUT0:ROUT9 data.
RCKR/FN
1 = Rising edge.
0 = Falling edge.
Reference Clock Input. LVTTL level input. Input for 20MHz - 66MHz system clock.
REFCLK
+ Serial Data Input. Non-inverting Bus LVDS differential input.
RI+
- Serial Data Input. Inverting Bus LVDS differential input.
RIPowerdown. LVTTL level input. Driving this pin low shuts down the PLL, tri-states
PWDNN
the outputs and puts the device into low power sleep mode.
Lock. CMOS level output. This signal goes low when the deserializer PLL locks onto
LOCKN
the embedded clock edge.
Recovered Clock. CMOS level output. Parallel data rate clock recovered from
RCLK
embedded clock. Used to strobe ROUT0:ROUT9.
Output Enable. LVTTL level input. If REN is set to logic low ROUT0:ROUT9 and RCLK
See Figure 3
REN
are in tri-state condition.
+3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital
DVDD
circuitry.
Digital Circuit Ground
DGND
+3.0V to +3.6V Analog Power Supply (PLL and Analog Circuits). AVDD and DVDD
should be at the same potential and must not be more than 0.3V apart even on
AVDD
transient basis. Both supplys should be decoupled by a capacitor of typically 10nF.
Analog Ground (PLL and Analog Circuits).
AGND
IEEE 1149.1 Test Data Input
TDI
IEEE 1149.1 Test Data Output
TDO
IEEE 1149.1 Test Mode Select Input
TMS
IEEE 1149.1 Test Clock Input
TCK
IEEE 1149.1 Test Reset Input
TRSTN
No Connection. Leave open-circuit, do not connect these pins.
N/C
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Revision 1.01
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AS1160/AS1161
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 6 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 3. Absolute Maximum Ratings
Parameter
Min
Max
Units
AVDD, DVDD
-0.3
+4
V
LVCMOS/LVTTL Input
-0.3
VDD +
0.3
V
LVCMOS/LVTTL Output
-0.3
VDD +
0.3
V
Bus LVDS Receiver Input/Output
-0.3
+3.9
V
Bus LVDS Output Short-Circuit Duration
10
ms
Power Dissipation
1.47
W
θJA
85
ºC/W
ESD
2
kV
Operating Temperature
-40
+85
ºC
Storage Temperature
-65
+150
ºC
+150
ºC
Junction Temperature
Package Body Temperature
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+260
ºC
Revision 1.01
Comments
Derate at 11.8mW/ºC above 25ºC
HBM MIL-Std. 883E 3015.7 methods;
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020D “Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
5 - 29
AS1160/AS1161
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
AVDD = DVDD = 3V to 3.6V, TAMB = -40°C to +85°C, RLOAD=28Ω, CLOAD = 10pF, typical values @ TAMB = +25°C and
VDD = 3.3V (unless otherwise specified).
Serializer Electrical Characteristics
Table 4. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Serializer LVCMOS/LVTTL DC Specifications (pins DINx, TCLK, PWDNN, TCKR/FN, SYNC1, SYNC2, DEN)
VIH
High Level Input Voltage
2.0
VDD
V
VIL
Low Level Input Voltage
GND
0.8
V
IIN
Input Current
-1
+1
µA
VIN = 0V or 3.6V
Serializer Bus LVDS DC Specifications (pins DO+ and DO-)
VOD
Output Differential Voltage
(DO+ to DO-)
ΔVOD
Output Differential Voltage
Unbalance
Figure 34 on page 18
200
1.1
360
mV
1
35
mV
1.2
1.3
V
2
35
mV
-13
-20
mA
VOS
Offset Voltage
ΔVOS
Offset Voltage Unbalance
IOS
Output Short-Circuit
Current
DO = 0V, DIN = High,
PWDNN and DEN = VDD
IOZ
Tri-State Output Current
PWDNN or DEN = GND, DO = 0V or VDD
-1
+1
µA
IOX
Power-Off Output Current
PWDNN = DEN = VDD = 0V,
DO = 0V or 3.6V
-1
+1
µA
Serializer Supply Current (pins DVDD and AVDD)
ICCD
Serializer Supply Current
(Worst Case) ICC-Pattern
ICCXD
Serializer Supply Current
(Powerdown)
Figure 16 on page 12
f = 20MHz
35
50
f = 66MHz
70
90
400
700
µA
Typ
Max
Unit
20
66
MHz
15.15
50
ns
40
60
%
6
ns
150
ps
(RMS)
Typ
Max
Unit
0.25
0.4
ns
0.25
0.4
ns
PWDNN = GND, fCLK = DC (off)
mA
Serializer Timing Requirements for TCLK
Table 5. Serializer Timing Requirements for TCLK
Symbol
Parameter
fCLK
Transmit Clock Freq.
tTCP
Transmit Clock Period
tTCDC
Transmit Clock Duty Cycle
tCLKT
TCLK Input Transition Time
tJIT
TCLK Input Jitter
Conditions
Figure 20 on page 13
Min
3
Serializer Switching Characteristics
Table 6. Serializer Switching Characteristics
Symbol
Parameter
tLLHT
Bus LVDS Low-to-High
Transition Time
tLHLT
1
Bus LVDS High-to-Low
Transition Time
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Conditions
Min
Figure 18 on page 13
Revision 1.01
6 - 29
AS1160/AS1161
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 6. Serializer Switching Characteristics
Symbol
Parameter
tDIS
DINx Setup to TCLK Time
tDIH
DINx Hold from TCLK Time
tHZD
DO+, DO- High-toTri-State Delay
tLZD
DO+, DO- Low-toTri-State Delay
1
Conditions
Min
Figure 21 on page 13
Figure 22 on page 14
Typ
Max
Unit
0
ns
4
ns
2
1.5
5
ns
1.5
5
ns
tZHD
DO+, DO- Tri-State-toHigh Delay
1.5
5
ns
tZLD
DO+, DO- Tri-State-toLow Delay
1.5
5
ns
tPWDL
PWDNN minimum low time
after VDD is in regulation
Figure 23 on page 14
50
µs
tSPW
SYNC Pulse Width
Figure 25 on page 15
5x
tTCP
ns
tPLD
Serializer PLL Lock Time
Figure 24 on page 14
400 x
tTCP
ns
tSD
Serializer Delay
Figure 26 on page 15
/2 tTCP/2
tTCP/2 tTCP
+3
+5
ns
f = 20MHz
150
300
tDJIT
Deterministic Jitter (p-p)
(Worst Case) ICC-Pattern
ps
(pp)
f = 66MHz
50
100
ps
(pp)
f = 20MHz
25
45
f = 66MHz
8
15
tRJIT
Figure 32 on page 18
Random Jitter
(Worst Case) ICC-Pattern
ps
(RMS)
1. Guaranteed by simulation and characterization.
2. Because the serializer is in tri-state mode, the deserializer will lose PLL lock and have to resynchronize before
data transfer.
Deserializer Electrical Characteristics
AVDD = DVDD = 3V to 3.6V, TAMB = -40°C to +85°C, RLOAD=28Ω, CLOAD = 15pF, Receiver Input Range: 0V to 2.4V,
typical values @ TAMB = +25°C and VDD = 3.3V (unless otherwise specified).
Table 7. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
+10
+75
Unit
Deserializer Bus LVDS DC Specifications (pins RI+ and RI-)
VTH
Differential Threshold High
Voltage
VTL
Differential Threshold Low
Voltage
IIN
Input Current
VCM = +1.2V
mv
-75
-20
VIN = 2.4V, VDD = 3.6V or 0V
-1
+1
VIN = 0V, VDD = 3.6V or 0V
-1
+1
µA
Deserializer LVCMOS/LVTTL DC Specifications (input pins PWDNN, RCKR/FN, REN, REFCLK; output pins
ROUT0:ROUT9, RCLK, LOCKN)
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Input Current
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VIN = 0V or 3.6V
Revision 1.01
2.0
VDD
V
GND
0.8
V
-1
+1
µA
7 - 29
AS1160/AS1161
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 7. Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
IILR
Input Current, TMS, TDI,
TRSTN inputs
VIN = 0V
VOH
High Level Output Voltage
IOH = -4 mA
VOL
Low Level Output Voltage
IOH = 4 mA
IOS
Output Short Circuit
Current
VOUT = 0V
IOS
Output Short Circuit
Current, TDO output
IOZ
Tri-State Output Current
Min
PWDNN or REN = 0V,
VOUT = 0V or VDD
Typ
Max
Unit
-30
-60
µA
2.2
3.0
VDD
V
GND
0.25
0.5
V
-15
-35
-60
mA
-80
-150
-220
mA
+1
µA
-1
Deserializer Supply Current (pins DVDD and AVDD)
ICCR
Deserializer Supply
Current (Worst Case)
ICCXR
Deserializer Supply
Current (Powerdown)
Figure 17 on page 12
f = 20MHz
45
60
f = 66MHz
100
130
0.75
1.0
mA
Typ
Max
Unit
66
MHz
PWDNN = 0V, REN = 0V
mA
Deserializer Timing Requirements for REFCLK
Table 8. Deserializer Timing Requirements for REFCLK
Symbol
Parameter
Conditions
Min
fRFCLK
REFCLK Frequency
20
tRFCP
REFCLK Period
15.15
T
50
ns
tRFDC
REFCLK Duty Cycle
30
50
70
%
tRFCP/tTCP
REFCLK-to-TCLK Ratio
95
1
105
tRFTT
REFCLK Transition Time
3
6
ns
Deserializer Switching Characteristics
Table 9. Deserializer Switching Characteristics
1
Symbol
Parameter
Conditions
Pin/
Frequency
Min
tRCP
Receiver Out Clock
Period
tRCP = tTCP,
Figure 26 on page 15
RCLK
15.15
tCLH
CMOS/TTL Low-toHigh Transition Time
Figure 19 on page 13
RCLK,
ROUTx,
LOCKN
tCHL
CMOS/TTL High-toLow Transition Time
All temperatures, all
frequencies
tDD
Typ
Max
Unit
50
ns
1.5
4
ns
1.4
4
ns
1.6 x tRCP
+ 1.0
1.75 x tRCP
+ 7.0
Deserializer Delay,
Figure 27 on page 16 Room temperature, 3.3V
20MHz
1.6 x tRCP
+ 2.0
Room temperature, 3.3V
66MHz
1.75 x tRCP 1.75 x tRCP 1.75 x tRCP
+ 2.0
+ 4.0
+ 6.0
20MHz
0.4 x tRCP
66MHz
0.38 x tRCP 0.5 x tRCP
20MHz
-0.4 x tRCP
0.5 x tRCP
66MHz
-0.38 x
tRCP
-0.5 x tRCP
tROS
ROUT Data Valid
Before RCLK Time
Figure 28 on page 16
tROH
ROUT Data Valid After
RCLK Time
Figure 28 on page 16
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Revision 1.01
1.6 x tRCP
+ 4.0
0.5 x tRCP
1.6 x tRCP
+ 6.0
ns
ns
ns
8 - 29
AS1160/AS1161
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 9. Deserializer Switching Characteristics
Symbol
Parameter
tRDC
RCLK Duty Cycle
tHZR
High to Tri-State Delay
tLZR
Low to Tri-State Delay
tZHR
Tri-State to High Delay
tZLR
tDSR1
tDSR2
2
2
tZHLK
1
tRCLKL
tRNM
1
Pin/
Frequency
Min
Typ
Max
Unit
45
50
55
ns
ROUTx
3
6
ns
ROUTx
3
6
ns
ROUTx
4
6
ns
Tri-State to Low Delay
ROUTx
4
6
ns
Deserializer PLL Lock
Time from PWDNN
(with SYNCPAT)
20MHz
5.2
7.5
µs
66MHz
1.8
3
µs
20MHz
5.1
7.5
µs
66MHz
1.9
3
µs
Tri-State to High Delay
(Powerup)
LOCKN
4
12
ns
RCLK low time before
LOCK achieved
RCLK
32xtRFCP
ns
Deserializer PLL Lock
Time from SYNCPAT
3
Conditions
Figure 29 on page 16
Figure 30 on page 17,
Figure 31 on page 17
Deserializer Noise
Margin
Figure 33 on page 18
20MHz
0.8
1
ns
66MHz
200
300
ps
1. Guaranteed by simulation and characterization.
2. For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK
running and stable, and with specific conditions for the incoming data stream synchronization patterns (SYNCPATs). The derserializer should be initialized using either tDSR1 or tDSR2.
tDSR1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down
mode. SYNCPATs should be sent to the device before initiating either condition.
tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and
RI-) conditions change from not receiving data to receiving SYNCPATs.
3. tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream
before bit errors occur. The deserializer noise margin is guaranteed by design using statistical analysis.
Scan Circuitry Timing Requirements
Table 10. Scan Circuitry Timing Requirements
Symbol
Parameter
Conditions
fTCK
TCK Clock Frequency
25
MHz
tTCK
TCK Clock Period
40
ns
tS
TCK to TDI, TMS Setup Time
2.0
ns
tH
TCK to TDI, TMS Hold Time
3.0
ns
tWH, tWL
TCK Pulse Width, High or Low
10.0
ns
tWR
TRSTN Pulse Width, Low
2.5
ns
tREC
TRSTN-to-TCK Recovery Time
2.0
ns
tD
TCK to TDO Delay
10
ns
tZ
TCK to TDO High Z Delay
10
ns
Figure 15 on page 12
Min
Typ
Max
Unit
Note: All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or
SQC (Statistical Quality Control) methods.
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AS1160/AS1161
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s A S 11 6 0
7 Typical Operating Characteristics AS1160
VDD = 3.6V, RLOAD = 28Ω, CLOAD = 10pF, TAMB = +25ºC (unless otherwise specified);
Figure 4. Supply Current vs Supply Voltage
Figure 5. Power-Down Current vs Supply Voltage
500
90
f clk=20M Hz
80
450
Supply Current (µA) .
.
f clk=66M Hz
Supply Current (mA)
70
60
50
40
30
20
10
400
350
300
250
200
150
100
50
0
0
2.8
3
3.2
3.4
3.6
2.8
3.8
3
3.2
3.4
3.6
3.8
Supply Voltage (V)
Supply Voltage (V)
Figure 6. Supply Current vs Clock Frequency
Figure 7. Supply Current vs Temperature
90
90
IDD @ VDD=3,6V
80
80
.
.
IDD @ VDD=3V
70
Supply Current (mA)
Supply Current (mA)
70
60
50
40
30
20
10
60
50
40
30
20
10
fclk=20M Hz
fclk=66M Hz
0
20
25
30
35
40
45 50
55
60
65
0
-45 -30 -15
70
Clock Frequency (MHz)
Figure 8. Power-Down Current vs. Temperature
.
Deterministic Jitter (Pk-Pk) (ps)
Supply Current (µA) .
500
400
300
0
15
30
45
60
15
30
45
60
75
90
75
90
Figure 9. Deterministic Jitter vs. Temperature
600
200
-45 -30 -15
0
Temperature (°C)
75
90
240
200
160
120
80
40
0
-45 -30 -15
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0
15
30
45
60
Temperature (°C)
Temperature (°C)
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AS1160/AS1161
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s A S 11 6 1
8 Typical Operating Characteristics AS1161
VDD = 3.6V, CLOAD = 15pF, TAMB = +25ºC (unless otherwise specified);
Figure 10. Supply Current vs Supply Voltage
Figure 11. Power-Down Current vs Supply Voltage
1000
120
fclk=20M Hz
110
950
fclk=66M Hz
Supply Current (µA) .
Supply Current (mA) .
100
90
80
70
60
50
40
30
20
900
850
800
750
700
650
600
550
10
0
500
2.8
3
3.2
3.4
3.6
2.8
3.8
3
Supply Voltage (V)
3.2
3.4
3.6
3.8
Supply Voltage (V)
Figure 12. Supply Current vs Clock Frequency
Figure 13. Supply Current vs Temperature
120
120
IDD @ VDD=3,6V
110
IDD @ VDD=3V
100
Supply Current (mA) .
Supply Current (mA) .
110
90
80
70
60
50
40
100
90
80
70
60
50
40
fclk=20M Hz
30
30
20
20
-45 -30 -15
20 25
30 35 40
45 50 55 60
65 70
Clock Frequency (MHz)
fclk=66M Hz
0
15
30
45
60
75
90
Temperature (°C)
Figure 14. Power-Down Current vs. Temperature
Supply Current (µA) .
1000
900
800
700
600
500
-45 -30 -15
0
15
30
45
60
75
90
Temperature (°C)
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AS1160/AS1161
Datasheet - Ti m i n g D i a g r a m s
9 Timing Diagrams
Figure 15. JTAG Timing Diagram
tTCK
tWL
tWH
TCK
tREC
tSPW
tSPW
TDI, TMS
td
ty
TDO
tWR
TRSTN
Figure 16. Worst-Case Serializer ICC Test Pattern
TCLK
Odd DIN
Even DIN
Figure 17. Worst-Case Deserializer ICC Test Pattern
RCLK
Odd ROUT
Even ROUT
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AS1160/AS1161
Datasheet - Ti m i n g D i a g r a m s
Figure 18. Serializer Bus LVDS Output Load and Transition Times
DO+
RLOAD
28Ω
80%
VDIFF
80%
20%
VDIFF = 0V
20%
DO10pF
10pF
tLLHT
tLHLT
VDIFF = DO+ - DO-
Figure 19. Deserializer CMOS/TTL Output Load and Transition Times
CMOS/TTL
Output
Deserializer
80%
80%
20%
20%
15pF
tCLH
tCHL
Figure 20. Serializer Input Clock Transition Time
90%
3V
90%
TCLK
0V
10%
10%
tCLKT
tCLKT
Figure 21. Serializer Setup and Hold Times
tTCP
TCLK
1.5V
1.5V
tDIH
tDIS
DIN0:9
Setup
1.5V
1.5V
Hold
1.5V
Timing shown for TCKR/FN is low
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AS1160/AS1161
Datasheet - Ti m i n g D i a g r a m s
Figure 22. Serializer Tri-State Test Circuit and Timing
3V
DEN
1.5V
1.5V
0V
DO+
tHZD
RLOAD
28Ω
VOH
DO10pF
DO+
DO-
10pF
tZHD
50%
50%
tLZD
tZLD
DEN
VOL
50%
50%
Figure 23. Serializer Power Up Timing
VDD
PWDNN
tPWDL
Figure 24. Serializer PLL Lock Time and PWDNN Tri-State Delays
PWDNN
2.0V
0.8V
tHZD or tLZD
<400 Cycles
...
TCLK
...
tZHD or tZLD
tPLD
DO+
DO-
Output
Active
Tri-State
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Tri-State
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AS1160/AS1161
Datasheet - Ti m i n g D i a g r a m s
Figure 25. SYNC Timing Delays
REN
PWDNN
TCLK
tSPW
SYNC1
or
SYNC2
11111
DO+
DO-
00000
Data
SYNCPAT
TCLK
SYNC1
or
SYNC2
tSPW minimum timing met
DO+
DO-
Data
SYNCPAT
SYNCPAT
SYNCPAT
Figure 26. Serializer Delay
DIN0:9 Symbol n + 2
DIN0:9 Symbol n + 1
DIN0:9 Symbol n
DIN
tTCP
tSD
TCLK
Timing shown for TCKR/FN = high
DO+
DO-
Start
Bit
0
DOUT0:9 Symbol n - 1
1 2
Stop Start
Bit Bit
8 9
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0
DOUT0:9 Symbol n
1 2
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Stop Start
Bit Bit
8 9
0
DOUT0:9 Symbol n + 1
1 2
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AS1160/AS1161
Datasheet - Ti m i n g D i a g r a m s
Figure 27. Deserializer Delay
Start
Bit
Stop Start
Bit Bit
DIN0:9 Symbol n
Stop Start
Bit Bit
DIN0:9 Symbol n + 1
Stop
Bit
DIN0:9 Symbol n + 1
R+
R-
1.3V
1.1V
tDD
RCLK
ROUT
ROUT0:9 Symbol n - 1
ROUT0:9 Symbol
ROUT0:9 Symbol n + 1
Figure 28. Deserializer Data Valid Out Times
RCLK
RCKR/FN = Low
tHIGH
tLOW
RCLK
RCKR/FN = High
tLOW
tHIGH
tROH
tROS
ROUT0:9
1.5V
1.5V
Data valid
before RCLK
Data valid
after RCLK
Figure 29. Deserializer Tri-State Test Circuit and Timing Diagram
+7V LZ, ZL
Open HZ, ZH
VOH
1.5V
REN
1.5V
VOL
500Ω
450Ω
tLZR
OScope
VOL + 0.5V
50Ω
tZLR
VOL + 0.5V
VOL
tHZR
VOH
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VOH - 0.5V
Revision 1.01
tZHR
VOH - 0.5V
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AS1160/AS1161
Datasheet - Ti m i n g D i a g r a m s
Figure 30. Deserializer PLL Lock Times and PWDNN Tri-State Delays
2.0V
PWDNN
0.8V
REFCLK
tDSR1
SYNCPATs
Data
RI+
RI-
Don’t Care
tZHLK
LOCKN
Tri-State
Tri-State
tZHR or tZLR
ROUT0:9
tHZR or tLZR
Tri-State
Tri-State
SYNC Symbol or DIN0:9
RCLK
Tri-State
Tri-State
tRCLKL
RCKR/FN = low
REN
Figure 31. Deserializer PLL Lock Time from SYNCPAT
PWDNN
0.8V
REFCLK
tDSR2
SYNCPATs
Data
RI+
RI-
Don’t Care
1.3V
1.2V
1.1V
Tri-State
LOCKN
tZHR or tZLR
ROUT0:9
tHZR or tLZR
Tri-State
Tri-State
SYNC Symbol or DIN0:9
RCLK
Tri-State
Tri-State
tRCLKL
REN
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AS1160/AS1161
Datasheet - Ti m i n g D i a g r a m s
Figure 32. Definition of Deterministic Jitter (tDJIT)
(DO+) - (DO-)
Waveform
0 Differential
Trigger
Superimposed ICC Pattern
tDJIT(p-p)
Figure 33. Receiver Bus LVDS Input Skew Margin
1.2V
VTH
RIRI+
VTL
tSW
tRNM
tDJIT
1.0V
tRNM
tDJIT
Ideal Sampling Position
Where:
tSW is the setup and hold time (internal data sampling window).
tDJIT is the serializer output bit position jitter as a result of jitter on TCLK.
tRNM is the receiver noise time margin.
Figure 34. Data Transfer Mode, VOD Diagram (VOD = DO+ - DO-)
AS1160
10
DIN0:9
Parallel
to
Serial
DO+
RLOAD
DO-
TCLK
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AS1160/AS1161
Datasheet - D e t a i l e d D e s c r i p t i o n
10 Detailed Description
The serializer/deserializer chipset transfers 10 parallel LVTTL data bits over a serial Bus LVDS link up to 660Mbps at
clock speeds from 20MHz to 66MHz.
For the serializer, an on-board PLL serializes the input data and inserts two control bits (start & stop bit) into the data
stream.
The deserializer uses a separate reference clock (REFCLK) and an onboard PLL to extract the clock information from
the incoming data stream and then deserialize the data. The deserializer monitors the incoming clock information,
determines lock status and asserts the LOCKN output high when loss of lock occurs.
Note: The chipset is also capable of driving data over unshielded twisted pair cable.
The chipset has three active states of operation:
- Initialization
- Data Transfer
- Resynchronization
The chipset also has two passive states:
- Powerdown
- Tri-State
Note: There are also test modes for JTAG access and at-speed BIST (built-in-self-test).
Initialization
Initialization of both devices must occur before data transmission begins. Initialization refers to synchronization of the
serializer and deserializer PLLs to local clocks, which may be the same or separate. Afterwards, synchronization of the
deserializer to the serializer occurs.
1. When VDD is applied and reaches a stable value between +3.0V and +3.6V, the PWDNN of the serializer has
to stay low for at least 50µs to ensure proper operation (see Figure 23 on page 14), the respective output enter
tri-state. After PWDNN is high the PLL in the serializer begins locking to a local clock.
When VDD is applied to the deserializer, the respective outputs enter tri-state and an on-chip power-on circuitry
disables internal circuitry. When VDD reaches VDDOK (2.5V) the PLL in the deserializer begins locking to a local
clock. For the serializer, the local clock is the transmited clock (TCLK) provided by the source ASIC or other
device. For the deserializer, a local clock must be applied to pin REFCLK that can be provided by any source.
The serializer outputs remain in tri-state while the PLL locks to the TCLK. After locking to TCLK, the serializer
is now ready to send data or SYNCPATs (SYNC patterns), depending on the levels of the SYNC1 and SYNC2
inputs or a data stream.
The SYNCPAT sent by the serializer consists of six ones and six zeros switching at the input clock rate. Note
that the deserializer LOCKN output will remain high while its PLL locks to the incoming data or to SYNCPATs
on the input.
2. The deserializer PLL must synchronize to the serializer to complete initialization. The deserializer will lock to
non-repetitive data patterns. However, the transmission of SYNCPATs enables the deserializer to lock to the
serializer signal within a specified time (see Figure 24 on page 14).
The application determines control of pins SYNC1 and SYNC2. A direct feedback loop from the LOCKN pin is
mandatory (see Figure 36 on page 23). In all cases the serializer stops sending SYNCPATs after both SYNC
inputs return low.
When the deserializer detects edge transitions at the bus LVDS input, it will attempt to lock to the embedded
clock information. When the deserializer locks to the bus LVDS clock, the LOCKN output will go low. When
LOCKN is low, the deserializer outputs represent incoming bus LVDS data.
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AS1160/AS1161
Datasheet - D e t a i l e d D e s c r i p t i o n
Data Transfer
After initialization, the serializer will accept data from inputs DIN0:DIN9. The serializer uses TCLK to latch incoming
data. TCKR/FN selects which edge the serializer uses to strobe incoming data. TCKR/FN high selects the rising edge
for clocking data and low selects the falling edge. If SYNC1 or SYNC2 is high for more than 5 TCLK cycles, the data at
DIN0:DIN9 is ignored regardless of clock edge.
After determining which clock edge to use a start and stop bit, appended internally, frame the data bits in the register.
The start bit is always high and the stop bit is always low. In the serial stream the start and stop bits are used as the
embedded clock bits.
The serializer transmits serialized data and clock bits (10 + 2 bits) from the serial data output (DO+ and DO-) at 12
times the TCLK frequency. For example, if TCLK is 66MHz, the serial rate is 66 x 12 = 792 mega bits per second.
Since only 10 bits are from input data, the serial payload rate is 10 times the TCLK frequency (if TCLK = 66MHz, the
payload data rate is 66 x 10 = 660Mbps). The data source provides TCLK and must be in the range of 20MHz to
66MHz nominal.
The serializer outputs (DO+ and DO-) can drive a point-to-point connection (see Figure 37 on page 24) or a multidrop
configuration (see Figure 35). In a multidrop configuration one serializer is connected through a backplane bus with
limited multiple deserializers.
The outputs transmit data when DEN, PWDNN are high and SYNC1, SYNC2 are low.
Note: When DEN is driven low, the serializer output pins will enter tri-state.
Figure 35. Multidrop Configuration
ASIC
ASIC
ASIC
ASIC
ASIC
Transmitter
RX
RX
RX
RX
56Ω
10-bit
10-bit
AS1161
AS1161
10-bit
AS1161
10-bit
AS1161
AS1160
10-bit
56Ω
When the deserializer synchronizes to the serializer, pin LOCKN is low. The deserializer locks to the internal clock and
uses it to recover the serialized data. ROUT0:ROUT9 data is valid when LOCKN is low, otherwise ROUT0:ROUT9 is invalid.
Pins ROUT0:ROUT9 use pin RCLK as the reference to data. The polarity of the RCLK edge is controlled by the RCKR/
FN input (see Figure 28 on page 16). ROUT0:ROUT9, LOCKN and RCLK outputs will drive a maximum of three CMOS
input gates (15pF load) with a 66MHz clock.
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AS1160/AS1161
Datasheet - D e t a i l e d D e s c r i p t i o n
Resynchronization
When the deserializer PLL locks to the embedded clock edge, the deserializer LOCKN pin asserts a low. If the deserializer loses lock, pin LOCKN output will go high and the outputs (including RCLK) will enter tri-state.
The user’s system monitors the pin LOCKN to detect a loss of synchronization. Upon detection, the system can
arrange to pulse the serializer SYNC1 or SYNC2 pin to resynchronize.
Multiple resynchronization approaches are possible. It is mandatory to provide a feedback loop using pin LOCKN to
control the SYNC request of the serializer (SYNC1 or SYNC2). Two SYNC pins are provided for multiple control in a
multi-drop application. Sending SYNCPATs for resynchronization is desirable when lock times within a specific time
are critical.
Powerdown
The low-power powerdown mode can be used while no data transfer is taking place. The serializer and deserializer
use the powerdown mode to reduce power consumption by:
- The deserializer enters powerdown when pins PWDNN and REN are low.
- The serializer enters powerdown when pin PWDNN is driven low.
In powerdown, the PLL stops and the outputs enter tri-state, which disables load current and reduces supply current to
the µA range.
Note: To exit powerdown, drive pin PWDNN high.
Before valid data exchanges between the serializer and deserializer, the devices must re-initialized and resynchronized to each other. Initialization of the serializer takes a maximum of 400 TCLK cycles. The deserializer will initialize
and assert LOCKN high until lock to the Bus LVDS clock occurs.
Tri-State
The serializer enters tri-state when pin DEN is driven low. This puts both driver output pins (DO+ and DO-) into tristate. When DEN is driven high, the serializer returns to the previous state, as long as all other control pins remain
static (SYNC1, SYNC2, PWDNN, TCKR/FN).
When pin REN is driven low, the deserializer enters tri-state. Consequently, the receiver output pins (ROUT0:ROUT9)
and RCLK will enter tri-state. The LOCKN output remains active, reflecting the state of the PLL.
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AS1160/AS1161
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
11 Application Information
Power Considerations
An all CMOS design of the serializer and deserializer makes them inherently low power devices. In addition, the constant current source nature of the bus LVDS outputs minimizes the slope of the speed vs. IDD curve of conventional
CMOS designs.
The pins AVDD and DVDD should be bypassed with a 100nF and a 1nF ceramic capacitor in parallel. The 1nF capacitor should be closest to the pin.
Powering up the Deserializer
The AS1161 can be powered up at any time by following a proper sequence. The REFCLK input can be running before
the deserializer powers up and it must be running in order for the deserializer to lock to incoming data. The deserializer
outputs will remain in tri-state until the deserializer detects data transmission at its inputs and locks to the incoming
data stream.
Table 11. Deserializer Truth Table
Inputs
Outputs
PWDNN
REN
LOCKN
ROUTx
RCLK
High
High
High (not locked)
Z
Z
1
1
High
High
Low (not locked)
Active
Active
Low
X (dont care)
Z
Z
Z
High
Low
Active
Z
Z
2
1. Active indicates the RCLK will be running if the deserializer is locked. The timing of RCLK with respect to
ROUT0:ROUT9 is determined by RCKR/FN. ROUT0:ROUT9 and RCLK are tri-stated when LOCKN is asserted
high.
2. Active indicates the LOCKN output will reflect the state of the deserializer with regard to the selected data
stream.
Transmitting Data
Once the serializer (AS1160) and deserializer (AS1161) are powered up, they must be phase locked to each other to
transmit data. Phase locking occurs when the deserializer locks to incoming data or when the serializer sends patterns.
The serializer sends SYNCPATs whenever the SYNC1 or SYNC2 inputs are high. The LOCKN output of the deserializer remains high until it has locked to the incoming data stream. Connecting the LOCKN output of the deserializer to
one of the SYNC inputs of the serializer will guarantee that enough SYNCPATs are sent to achieve deserializer lock
(see Figure 36 on page 23).
As long as the deserializer LOCKN output is low, valid data is presented at the deserializer outputs (ROUT0:ROUT9),
except for the specific case of loss of lock during transmission (see Lock Loss Recovery on page 23).
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AS1160/AS1161
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 36. Typical Application
10
DIN0:9
ASIC/
FPGA/
DSP
Input
Latch
Parallel
-toSerial
TCKR/FN
DO+
DOVDD
PLL
TCLK
Timing &
Control
AS1160
RIVDD
Output 10
Latch
ROUT0:9
PLL
Timing &
Control
REN
DEN
SYNC1
PWDNN
Parallel
-toSerial
RI+
56Ω
REFCLK
ASIC/
FPGA/
DSP
PWDNN
LOCKN
SYNC2
AS1161
Clock
Recovery
RCLK
RCKR/
JTAG
JTAG
Noise Margin
The deserializer (AS1161) noise margin is the amount of input jitter (phase noise) that the deserializer can tolerate and
still reliably receive data. Various environmental and systematic factors include:
- Serializer: TCLK jitter, VDD noise (noise bandwidth and out-of-band noise)
- Media: ISI (Inter Symbolic Interference), Large VCM shifts
- Deserializer: VDD noise
Lock Loss Recovery
In the case where the deserializer (AS1161) loses lock during data transmission, up to 3 cycles of data that were previously received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that
invalid clock information be received 4 times in a row to indicate loss of lock. Since clock information has been lost, it is
possible that data was also lost during these cycles. Therefore, after the deserializer re-locks to the incoming data
stream and the deserializer LOCKN pin goes low, at least three previous data cycles should be suspect for bit errors.
The deserializer can re-lock to the incoming data stream by making the serializer re-send SYNCPATs.
Hot Insertion
As all BLVDS devices the AS1161 is hot pluggable but you have to follow some rules.
Hot insertion should be performed with pins making contact in the following order:
- Ground pins
- VDD pins
- I/O pins
Note: When removing the device, the pin groups should be removed in reverse order from insertion.
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AS1160/AS1161
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
PCB Considerations
The serializer and deserializer should be placed as close to the PCB edge connector as possible. In multiple deserializer applications, the distance from the deserializer to the slot connector appears as a stub to the serializer driving the
backplane traces. Longer stubs lower the impedance of the bus, increase the load on the serializer and lower the
threshold margin at the deserializers. Deserializer devices should be placed much less than one inch from slot connectors. Because transition times are very fast on the serializer bus LVDS outputs, reducing stub lengths as much as possible is the best method to ensure signal integrity.
For bus LVDS applications the LVTTL, LVCMOS and bus LVDS signals should be separated from each other to prevent coupling into the bus lines. This can be achieved by using a four-layer PCB where the power, ground and input/
output signals are separated.
Transmission Media
The transmission line characteristics affect the performance of the AS1160/AS1161. It’s recommended to use controlled-impedance media and to terminate at both ends of the transmission line (see Figure 37). Twisted pair cables
should be used due to their superior signal quality and the less EMI generation. Noise which is picked up as common
mode in the twisted pair is rejected by the differential receiver.
It’s important to eliminate reflections and to run the differential traces as close together as possible to ensure that the
noise is coupled as common mode. Also take care of matching the electrical length of the traces to prevent a degradation of the magnetic field cancellation. To avoid an external magnetic field, the differential output signals should also be
placed as close together as possible.
The potential of offsetting the ground levels of the serializer vs. the deserializer must be considered. The bus LVDS
provides a +1.2V common mode range at the receiver inputs.
Figure 37. Double-Terminated Point-to-Point
Serialized Data
DO+
Parallel
Data In
RI+
10-bit
10-bit
56Ω
56Ω
Parallel
Data Out
RI-
DO-
AS1161
AS1160
Strip Line or Twisted Pair
Z = 28Ω
The serializer/deserializer chipset can be used in many different topologies. Such as multidrop configurations (see Figure 35 on page 20), through a PCB trace or through twisted pair cable (see Figure 37).
In point-to-point configurations, it’s possible to terminated the transmission line only once at the receiver end. With only
one termination the reflections and the differential signal swing are larger compared to a double termination.
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AS1160/AS1161
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Failsafe Biasing
The AS1161 has an input threshold sensitivity of ±75mV, which allows a greater differential noise margin.
However, in cases where the receiver input is not being actively driven, the increased sensitivity of the AS1161 can
pickup noise as a signal and cause unintentional locking (e.g., when the input cable is left floating).
Figure 38. Failsafe Biasing Setup
VDD
R1
RLOAD
R2
External resistors can be added to the receiver circuit to prevent noise pickup as shown in Figure 38. In such circuits,
the non-inverting receiver input is pulled up and the inverting receiver input is pulled down by high value resistors. The
pull-up and pull-down resistors (R1 and R2 in Figure 38) provide a current path through the termination resistor (RLOAD)
which biases the receiver inputs when they are not connected to an active driver.
Note: The value of the pull-up and pull-down resistors should be chosen so that sufficient current is drawn to provide
a +15mV drop across the termination resistor.
Signal Integrity
For a validation of the signal qualitiy in an application or in a simulation, the parameters tDJIT and tRNM can be used to
generate an eye pattern mask.
tDJIT measures the transmitter’s ability to place data bits in the ideal position to be sampled by the receiver. The typical
tDJIT parameter of 50ps @ 66MHz indicates that the crossing point of the Tx data is 50ps before the ideal crossing
point. The tDJITMIN and tDJITMAX parameters specify the earliest and latest time that a crossing will occur relative to the
ideal position.
Figure 39. Eye Pattern Mask Generation and Signal Quality Validation
tDJIT (typ)
X1
tRNM
Y1
Y2
tDJIT (max)
tDJIT (min)
X2
Vertical = 200mV/Div
Horizontal = 200ps/Div
Ideal Crossing
First of all, tRNM is calculated by measuring how much of the bit the receiver needs to ensure correct sampling. This
calculated amount is subtracted from the ideal bit and what’s left of it is available for external sources of noise and is
called tRNM. It is the offset from tDJIT for the test mask within the eye opening.
The vertical limits of the mask are determined by the AS1161 receiver input threshold of ±75mV.
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AS1160/AS1161
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
JTAG Test Modes
Instructions supported by the AS1160/AS1161 and its respective operational binary codes are shown in Table 12.
Note: Boundary Scan Description Language (BSDL) model files for the AS1160 and the AS1161 are available on the
internet.
Table 12. Instruction Codes
Instruction
Code
SAMPLE/PRELOAD
0101
BYPASS
1111
EXTEST
0001
IDCODE
1010
RUNBIST
1110
SAMPLE/PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the
device can be sampled at the boundary scan test data register without interfering with the normal operation of the
device. SAMPLE/PRELOAD also allows the device to shift data into the boundary scantest data register through TDI.
BYPASS
When the BYPASS instruction is latched into the instruction register, TDI connects to TDO through the 1-bit bypass
test data register. This allows data to pass from TDI to TDO without affecting the device’s normal operation.
EXTEST
Implemented at LVDS levels as a go/no-go test (e.g. missing cables).
IDCODE
The AS1160/AS1161 ID code is provided to the TDO output.
Table 13. 32bit ID Code
MSB
LSB
Device
Version (4bits)
Device ID (16bits)
Manufacturer ID (11bits)
Fixed Value (1bit)
AS1160
0100
0001000101100000
01011011010
1
AS1161
0100
0001000101100001
01011011010
1
RUNBIST
An at-system-speed interconnect test instruction. It is executed in approximately 33mS (@ 66MHz system speed).
There are two bits in the RX BIST data register for notification of PASS/FAIL and TEST_COMPLETE. Pass indicates
-7
that the BER (bit-error-rate) is better than 10 .
If both the AS1160 and the AS1161 have loaded the RUNBIST instruction into their instruction registers, both devices
must move into the RTI state within 4K system clocks (at a SCLK of 66Mhz and TCK of 1MHz this allows for 66 TCK
cycles). This is only an issue when both devices are not on the same scan chain or LSP, although, it can be a problem
with some multi-drop devices.
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AS1160/AS1161
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
12 Package Drawings and Markings
The device is available in an CTBGA 49-bumps package.
Figure 40. CTBGA 49-bumps Package
7
6
5
4
3
2
1
B
0
0 80
0 0 00
M
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AS1160/AS1161
Datasheet - O r d e r i n g I n f o r m a t i o n
13 Ordering Information
The devices are available as the standard products shown in Table 14.
Table 14. Ordering Information
Ordering Code
Description
Delivery Form
Package
AS1160-BCTT
Serializer
Tape and Reel
CTBGA 49-bumps
AS1161-BCTT
Deserializer
Tape and Reel
CTBGA 49-bumps
Note: All products are RoHS compliant and Pb-free.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS1160/AS1161
Datasheet
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