® PCM PCM1726 ® 172 6 Stereo Audio DIGITAL-TO-ANALOG CONVERTER 16 Bits, 96kHz Sampling TM FEATURES DESCRIPTION ● COMPLETE STEREO DAC: Includes Digital Filter and Output Amp The PCM1726 is a complete low cost stereo audio digital-to-analog converter (DAC), operating off of a 256fS or 384fS system clock. The DAC contains a 3rdorder ∆Σ modulator, a digital interpolation filter, and an analog output amplifier. The PCM1726 accepts 16-bit input data in either normal or I2S formats. ● DYNAMIC RANGE: 96dB ● MULTIPLE SAMPLING FREQUENCIES: 16kHz to 96kHz 8X Oversampling at All Sampling Frequencies The digital filter performs an 8X interpolation function and includes soft mute. The PCM1726 can accept standard digital audio sampling frequencies as well as one-half and double sampling frequencies. ● SYSTEM CLOCK: 256fS / 384fS ● NORMAL OR I2S DATA INPUT FORMATS ● SOFT MUTE The PCM1726 is ideal for applications which combine compressed audio and video data such as DVD, DVDROM, set-top boxes and MPEG sound cards. BCKIN LRCIN DIN Serial Input I/F 8X Oversampling Digital Filter with Function Controller MUTE Multi-level Delta-Sigma Modulator DAC Low-pass Filter VOUTL CAP Multi-level Delta-Sigma Modulator DAC Low-pass Filter VOUTR FORMAT LRPL Mode Control I/F ZERO BPZ-Cont. Open Drain RSTB 256fS/384fS Power Supply SCKI VCC AGND VDD DGND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1996 Burr-Brown Corporation PDS-1345B Printed in U.S.A. March, 1997 SPECIFICATIONS All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted. PCM1726 PARAMETER CONDITIONS RESOLUTION DATA FORMAT Audio Data Format Data Bit Length Sampling Frequency (fS) Internal System Clock Frequency MIN THD+N at –60dB Dynamic Range Signal-to-Noise Ratio(2) Channel Separation ANALOG OUTPUT Output Voltage Center Voltage Load Impedance POWER SUPPLY REQUIREMENTS Voltage Range Supply Current: ICC + IDD Bits 96 kHz –90 –88 –34 –31 96 93 100 97 97 –80 dB dB dB dB dB dB dB dB dB ±1.0 ±1.0 ±5.0 ±5.0 % of FSR % of FSR 256fS /384fS TTL fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz fS = 44.1kHz 90 92 90 VOUT = VCC/2 at BPZ ±30 mV Full Scale (0dB) 0.62 x VCC VCC/2 Vp-p VDC kΩ AC Load 5 DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time INTERNAL ANALOG FILTER –3dB Bandwidth Passband Response UNITS 16 16 DC ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error MAX Standard /I2S 16 DIGITAL INPUT/OUTPUT LOGIC LEVEL DYNAMIC PERFORMANCE(1) THD+N at fS (0dB) TYP 0.445 11.125/fS fS fS dB dB sec 100 –0.16 kHz dB 0.555 ±0.17 –35 f = 20kHz VDD, VCC VCC = VDD = 5V, fS = 44.1kHz VCC = VDD = 5V, fS = 96kHz TEMPERATURE RANGE Operation Storage 4.5 –25 –55 5 18 25 5.5 25 35 VDC mA mA +85 +100 °C °C NOTES: (1) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode. (2) SNR is tested with Infinite Zero Detection off. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM1726 2 PIN CONFIGURATION PIN ASSIGNMENTS TOP VIEW SSOP PIN NAME TYPE 1 NC — FUNCTION No Connection. 2 SCKI IN System Clock Input: 256fS or 384fS. NC 1 20 DGND 3 RES — Reserved for Factory Use. Do not connect. SCKI 2 19 VDD 4(1) FORMAT IN Input Data Format Control. 5(1) LRPL IN Left/Right Polarity Control. RES 3 18 RES 6(1) MUTE IN Soft Mute Control. FORMAT 4 17 TEST 7(1) RSTB IN Reset Input. When this pin is low, the digital filters and modulators are held in reset. LRPL 5 16 LRCIN 8 ZERO OUT Zero Data Flag. This pin is low when the data is continuously zero for more than 65,535 cycles of BCKIN. PCM1726 MUTE 6 15 DIN RSTB 7 14 BCKIN ZERO 8 13 CAP VOUTR 9 12 VOUTL AGND 10 11 VCC PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) PCM1726E 20-Pin SSOP 334-1 9 VOUTR OUT Right Channel Analog Output. 10 AGND PWR Analog Ground. Analog Power Supply (+5V). 11 VCC PWR 12 VOUTL OUT 13 CAP — Common Pin for Analog Output Amplifiers. 14(1) BCKIN IN Bit Clock for Clocking in the Audio Data. 15(1) DIN IN Serial Audio Data Input. 16(1) LRCIN IN Left/Right Word Clock. Frequency is equal to fS. 17 TEST — Must be Tied to Ground. 18 RES — Do Not Connect. 19 VDD PWR Digital Power Supply (+5V). Recommended connection is to the analog power supply. 20 DGND PWR Digital Ground. Recommended connection is to the digital ground plane. Left Channel Analog Output. NOTE: (1) These pins include internal pull-up resistors. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Power Supply Voltage ....................................................................... +6.5V +VCC to +VDD Difference ................................................................... ±0.1V Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V) Power Dissipation .......................................................................... 300mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C Thermal Resistance, θJA .............................................................. +70°C/W ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® 3 PCM1726 TYPICAL PERFORMANCE CURVES DYNAMIC PERFORMANCE At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, 16-bit input data, unless otherwise noted. Measurement bandwidth is 20kHz. THD+N vs VCC, VDD THD+N vs TEMPERATURE –84 –30 –84 fS = 96kHz –88 –34 –90 fS = 44.1kHz –92 –86 THD+N at FS (dB) –38 5.0 –90 fS = 44.1kHz –92 –94 4.5 –88 –90 –25 5.5 0 25 VCC, VDD (V) 50 75 85 100 Temperature (°C) THD+N and DYNAMIC RANGE vs fS DYNAMIC RANGE and SNR vs VCC, VDD –86 100 90 SNR 98 THD+N (dB) –88 (dB) 96 Dynamic Range 94 92 THD+N –90 94 Dynamic Range –92 96 92 –94 90 3.5 4.0 4.5 5.0 5.5 98 44.1 6.0 48 88.2 96 Sampling Frequency, fS (kHz) VCC, VDD DIGITAL FILTER At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, fSYS = 384fS, and 16-bit input data, unless otherwise noted. OVERALL FREQUENCY CHARACTERISTIC PASSBAND RIPPLE CHARACTERISTIC 0 –20 –0.2 –40 –0.4 dB dB 0 –60 –0.6 –80 –0.8 –100 –1 0 0.4536fS 1.3605fS 2.2675fS 3.1745fS 4.0815fS 0 ® PCM1726 0.1134fS 0.2268fS Frequency (Hz) Frequency (Hz) 4 0.3402fS 0.4535fS Dynamic Range (dB) THD+N at FS (dB) –86 THD+N at –60dB (dB) fS = 96kHz 1/fs L_ch R_ch LRCIN (pin 4) BCKIN (pin 6) AUDIO DATA WORD = 16-BIT DIN (pin 5) 14 15 16 1 2 14 3 MSB 15 16 1 2 LSB 3 MSB 14 15 16 LSB FIGURE 1. “Normal” Data Input Timing. 1/fs L_ch LRCIN (pin 4) R_ch BCKIN (pin 6) AUDIO DATA WORD = 16-BIT DIN (pin 5) 1 2 3 MSB 14 15 16 1 LSB 2 3 MSB 14 1 15 16 2 LSB FIGURE 2. “I2S” Data Input Timing. LRCKIN 1.4V tBCH tBCL tLB BCKIN 1.4V tBL tBCY 1.4V DIN tDS tDH BCKIN Pulse Cycle Time : tBCY : 100ns (min) BCKIN Pulse Width High : tBCH : 50ns (min) BCKIN Pulse Width Low : tBCL : 50ns (min) BCKIN Rising Edge to LRCIN Edge : tBL : 30ns (min) LRCIN Edge to BCKIN Rising Edge : tLB : 30ns (min) DIN Set-up Time : tDS : 30ns (min) DIN Hold Time : tDH : 30ns (min) FIGURE 3. Audio Data Input Timing. ® 5 PCM1726 +5V Analog 20 DGND 15 14 PCM Audio Data Processor 16 2 19 VDD VOUTL DIN BCKIN CAP 12 13 200Ω + LRCIN SCKI VOUTR 256fS/384fS CLK PCM1726 ZERO FORMAT LRPL MUTE RSTB AGND 10 Post LPF Analog Mute Lch Analog Out Post LPF Analog Mute Rch Analog Out 10µF 9 8 4 5 6 MUTE 7 RESET VCC 11 +5V Analog FIGURE 4. Typical Connection Diagram For I2S Data Format. INPUT DATA FORMAT TYPICAL CONNECTION DIAGRAM Figure 4 illustrates the typical connection diagram for PCM1726 used in a stand-alone application. PCM1726 can accept input data in either normal (MSB-first, right-justified) or I2S formats. When pin 4 (FORMAT) is LOW, normal data format is selected; a HIGH on pin 4 selects I2S format. SYSTEM CLOCK The system clock for PCM1726 must be either 256fS or 384fS, where fS is the audio sampling frequency (LRCIN), typically 32kHz, 44.1kHz or 48kHz. The system clock is used to operate the digital filter and the noise shaper. The system clock input (SCKI) is at pin 2. FORMAT 0 Normal Format (MSB-first, right-justified) 1 I2S Format (Philips serial data protocol) TABLE II. Input Format Selection. PCM1726 has a system clock detection circuit which automatically detects the frequency, either 256fS or 384fS. The system clock should be synchronized with LRCIN (pin 16), but PCM1726 can compensate for phase differences. If the phase difference between LRCIN and system clock is greater than ±6 bit clocks (BCKIN), the synchronization is performed automatically. The analog outputs are forced to a bipolar zero state (VCC/2) during the synchronization function. Table I shows the typical system clock frequency inputs for the PCM1726. SOFT MUTE The outputs of the PCM1726 can be muted by taking pin 6 (MUTE) to a LOW state. This pin has an internal pull-up resistor and may be left open for non-muted operation of the DAC. MUTE 0 Soft Mute ON 1 Soft Mute OFF TABLE III. Soft Mute Enable. SAMPLING RATE (LRCIN) SYSTEM CLOCK FREQUENCY (MHz) 256fS 384fS 32kHz 8.192 12.288 44.1kHz 11.2896 16.9340 48kHz 12.288 18.432 WORD POLARITY The polarity of the input data word (LRCIN) may be controlled by pin 5 (LRPL). A LOW on pin 5 interprets the HIGH portion on LRCIN as left-channel data, and the LOW portion of LRCIN as right-channel data. Taking pin 5 HIGH reverses the polarity. TABLE I. System Clock Frequencies vs Sampling Rate. LRPL LRCIN VALUE 0 Left-Channel is HIGH; Right-Channel is LOW 1 Left-Channel is LOW; Right-Channel is HIGH TABLE IV. Left/Right Polarity Selection. ® PCM1726 6 order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1726: RESET PCM1726 has an internal power-on reset circuit, as well as an external forced reset (RSTB, pin 7). The internal power-on reset initializes (resets) when the supply voltage VDD > 4.0V (typ). External forced reset occurs when RSTB = LOW and the outputs of the DAC are at VCC/2. The power-on reset has an initialization period equal to 1024 system clock periods after VDD > 4.0V and RSTB = HIGH. During the initialization period, the outputs of the DAC are invalid, and the analog outputs are forced to VCC/2. Figures 5 and 6 illustrate the power-on reset and reset-pin reset timing. TD = 11.125 x 1/fS For fS = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs Applications using data from a disc or tape source, such as CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. OUTPUT FILTERING For testing purposes all dynamic tests are done on the PCM1726 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out of band noise. Although it is not audible, it may affect dynamic specification numbers. APPLICATION CONSIDERATIONS DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the 4.4V VCC = VDD 4.0V 3.6V Reset Reset Removal Internal Reset 1024 system (= XTI) clocks XTI Clock FIGURE 5. Internal Power-On Reset Timing. RSTB 50% of VDD tRST(1) Reset Reset Removal Internal Reset 1024 system (XTI) clocks XTI Clock NOTE: (1) tRST = 20ns min FIGURE 6. External Forced Reset Timing. ® 7 PCM1726 INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) 1.0 dB dB 0.5 0 –0.5 –1.0 20 100 1k Frequency (Hz) 10k 24k 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 10 100 1k 10k 100k 1M 10M Frequency (Hz) FIGURE 7. Low Pass Filter Frequency Response. FIGURE 8. Low Pass Filter Wideband Frequency Response. GAIN vs FREQUENCY 6 90 + 10kΩ VSIN 10kΩ 680pF OPA134 10kΩ –14 0 –34 –90 –54 –180 Phase (°) 1500pF Gain (dB) Gain Phase 100pF – –74 –270 –94 –360 100 1k 10k Frequency (Hz) 100k 1M FIGURE 9. 3rd-Order LPF. An application circuit to avoid a latch-up condition is shown in Figure 10. The performance of the internal low pass filter from DC to 24kHz is shown in Figure 7. The higher frequency rolloff of the filter is shown in Figure 8. If the user’s application has the PCM1726 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 9. For some applications, a passive RC filter or 2nd-order filter may be adequate. Digital Power Supply POWER SUPPLY CONNECTIONS PCM1726 has two power supply connections: digital (VDD) and analog (VCC). Each connection also has a separate ground. If the power supplies turn on at different times, there is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection between the digital and analog power supplies. If separate supplies are used without a common connection, the delta between the two supplies during ramp-up time must be less than 0.6V. VDD VCC DGND AGND FIGURE 10. Latch-up Prevention Circuit. BYPASSING POWER SUPPLIES The power supplies should be bypassed as close as possible to the unit. It is also recommended to include a 0.1µF ceramic capacitor in parallel with the 10µF tantalum bypass capacitor. ® PCM1726 Analog Power Supply 8 + In + 8fS 18-Bit + Z–1 + + – + Z–1 Z–1 – + + 5-level Quantizer + 4 3 Out 48fS (384fS) 64fS (256fS) 2 1 0 FIGURE 11. 5-Level ∆Σ Modulator Block Diagram. THEORY OF OPERATION 3rd ORDER ∆Σ MODULATOR 20 The delta-sigma section of PCM1726 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level deltasigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 11. This 5-level delta-sigma modulator has the advantage of stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8X interpolation filter is 48fS for a 384fS system clock, and 64fS for a 256fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 12. 0 Gain (–dB) –20 –40 –60 –80 –100 –120 –140 –160 0 5 10 15 20 25 Frequency (kHz) FIGURE 12. Quantization Noise Spectrum. ® 9 PCM1726