® PCM61P PCM 61P Serial Input 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● 18-BIT MONOLITHIC AUDIO D/A CONVERTER ● LOW MAX THD + N: –92dB Without External Adjust The PCM61P is an 18-bit totally pin compatible performance replacement for the popular 16-bit PCM56P. With the addition of two extra bits, lower max THD+N (–92dB; PCM61P-K) can be achieved in audio applications already using the PCM56P. The PCM61P is complete with internal reference and output op amp and requires no external parts to function as an 18-bit DAC. The PCM61P is capable of an 8-times oversampling rate (single channel) and meets all of its specifications without an external output deglitcher. ● 100% PIN COMPATIBLE WITH INDUSTRY STD 16-BIT PCM56P ● LOW GLITCH OUTPUT OF ±3V OR ±1mA ● CAPABLE OF 8X OVERSAMPLING RATE IN VOUT MODE ● COMPLETE WITH INTERNAL REFERENCE AND OUTPUT OP AMP ● RELIABLE PLASTIC 16-PIN DIP PACKAGE The PCM61P comes in a small, reliable 16-pin plastic DIP package that has passed operating life tests under simultaneous high temperature, high humidity and high pressure testing. VREF Ref MSB Adj RF Clock Control Logic 18-Bit IOUT DAC IOUT SJ Latch Enable _ Data Serial-To-Parallel Shift Register VOUT + International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1989 Burr-Brown Corporation 1 PDS-972E PCM61P Printed in U.S.A. October, 1993 SPECIFICATIONS ELECTRICAL All specifications at 25°C, and +VCC = +5V, unless otherwise noted. PCM61P-P, J-P, K PARAMETER CONDITIONS MIN TYP MAX UNITS 18 Bits RESOLUTION DYNAMIC RANGE DIGITAL INPUT Logic Family Logic Level: VIH VIL IIH IIL Data Format Input Clock Frequency DYNAMIC CHARACTERISTICS Total Harmonic Distortion + N(2) PCM61P f = 991Hz (0dB)(3) f = 991Hz (–20dB) f = 991Hz (–60dB) PCM61P-J f = 991Hz (0dB) f = 991Hz (–20dB) f = 991Hz (–60dB) PCM61P-K f = 991Hz (0dB) f = 991Hz (–20dB) f = 991Hz (–60dB) IDLE CHANNEL SNR TRANSFER CHARACTERISTICS ACCURACY Gain Error Bipolar Zero Error Differential Linearity Error Total Drift(6) Bipolar Zero Drift Warm-up Time 108 VIH = +2.7V VIL = +0.4V dB TTL/CMOS Compatible +2.4 +VL 0 +0.8 +1 –50 Serial BTC(1) 16.9 V V µA µA MHz Without MSB Adjustments fS = 176.4kHz(4) fS = 176.4kHz fS = 176.4kHz –88 –74 –34 –82 –68 –28 dB dB dB fS = 176.4kHz fS = 176.4kHz fS = 176.4kHz –94 –76 –36 –88 –74 –34 dB dB dB fS = 176.4kHz fS = 176.4kHz fS = 176.4kHz –98 –80 –40 –92 –74 –34 dB dB dB 20Hz to 20kHz at BPZ(5) 112 dB 0°C to 70°C 0°C to 70°C ±2 ±30 ±0.001 ±25 ±4 %FSR mV %FSR ppm of FSR/°C ppm of FSR/°C Minute 16 Bits ±3 V mA Ω mA kΩ 1 MONOTONICITY ANALOG OUTPUT Voltage: Output Range Output Current Output Impedance Current: Output Range Output Impedance SETTLING TIME Voltage: 6V Step 1 LSB Slew Rate Current: 1mA Step 1mA Step Glitch Energy ±2 0.1 ±1 1.2 ±30% ±30% To ±0.006% of FSR 1.5 1.0 12 10Ω to 100Ω Load 250 1kΩ Load 350 Meets all THD+N specs without external deglitching µs µs V/µs ns ns POWER SUPPLY REQUIREMENTS(7) ±VCC Supply Voltage Supply Current: +ICC +ICC –ICC –ICC Power Dissipation ±4.75 +VCC = +5V +VCC = +12V –VCC = –5V –VCC = –12V ±VCC = ±5V ±VCC = ±12V ±5 +10 +12 –25 –27 175 475 ±13.2 +17 –35 260 V mA mA mA mA mW mW TEMPERATURE RANGE Specification Operating Storage 0 –30 –60 +70 +70 +100 °C °C °C NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS)/SignalRMS. (3) D/A converter output frequency/signal level. (4) D/A converter sample frequency (4 x 44.1kHz; 4 times oversampling). (5) Bipolar zero, using A-weighted filter. (6) This is the combined drift error due to gain, offset, and linearity over temperature. (7) All positive and all negative supply pins must be tied together respectively. ® PCM61P 2 PIN ASSIGNMENTS CONNECTION DIAGRAM PIN FUNCTION DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 –VS LOG COM +VL NC CLK LE DATA –VL VOUT RF SJ ANA COM IOUT MSB ADJ TRIM +VS Analog Negative Supply Logic Common Logic Positive Supply No Connection Clock Input Latch Enable Input Serial Data Input Logic Negative Supply Voltage Output Feedback Resistance Summing Junction Analog Common Current Output MSB Adjustment Terminal MSB Trim-pot Terminal Analog Positive Supply –5V 1µF +5V –VS Logic Com +V L 1 2 –5V ABSOLUTE MAXIMUM RATINGS 4 CLK 5 LE 6 Data 7 –V L 8 PACKAGE DRAWING NUMBER(1) PCM61P-P PCM61P-J PCM61P-K 16-Pin Plastic DIP 16-Pin Plastic DIP 16-Pin Plastic DIP 180 180 180 13 11 10 – + DIGITAL INPUT PACKAGE (1) 14 MSB Adjust I OUT Analog Common 9 SJ RF Analog VOUT Output (±3V) NOTE: (1) MSB error (Bipolar Zero differential linearity error) can be adjusted to zero using the external circuit shown in Figure 4. PACKAGE INFORMATION PRODUCT 18-Bit IOUT DAC 12 1µF DC Supply Voltages ...................................................................... ±16VDC Input Logic Voltage ............................................................. –1V to VS /+VL Power Dissipation .......................................................................... 850mW Operating Temperature Range ......................................... –25°C to +70°C Storage Temperature Range .......................................... –60°C to +100°C Lead Temperature (soldering, 10s) ............................................... +300°C 15 Trim(1) 18-Bit Serial to Parallel Conversion Control Logic and Level Shifting Circuit +5V +V S 1µF 18-Bit DAC Latch 3 1µF NC 16 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ANALOG OUTPUT Binary Two’s Complement (BTC) DAC Output Voltage (V) VOUT Mode Current (mA) IOUT Mode 1FFFF Hex 00000 Hex 3FFFF Hex 20000 Hex +FS BPZ BPZ – 1LSB –FS –0.99999237 0.00000000 +0.00000763 +1.00000000 +2.99997711 0.00000000 –0.00002289 –3.00000000 TABLE I. PCM61P Input/Output Relationships. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PCM61P P16 (Clock) P18 (Data) 1 MSB 2 3 4 10 11 12 13 14 15 16 17 18 LSB 1 P17 (Latch Enable) NOTES: (1) If clock is stopped between input of 18-bit data words, latch enable (LE) must remain low until after the first clock of the next 18-bit data word stream. (2) Data format is binary two‘s complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going negative. FIGURE 1. PCM61P Timing Diagram. MSB ERROR ADJUSTMENT PROCEDURE (OPTIONAL) The MSB error of the PCM61P can be adjusted to make the differential linearity error (DLE) at BPZ essentially zero. This is important when the signal output levels are very low, because zero crossing noise (DLE at BPZ) becomes very significant when compared to the small code changes occurring in the LSB portion of the converter. >25ns Data Input MSB LSB >15ns >15ns Clock Input >25ns >25ns >5ns >60ns To statically adjust DLE at BPZ, refer to the circuit shown in Figure 3 or the PCM61P connection diagram. >15ns Latch Enable > One Clock Cycle Differential linearity error at bipolar zero and THD are guaranteed to meet data sheet specifications without any external adjustment. However, a provision has been made for an optional adjustment of the MSB linearity point, which makes it possible to eliminate DLE error at BPZ. Two procedures are given to allow either static or dynamic adjustment. The dynamic procedure is preferred because of the difficulty associated with the static method (accurately measuring 16bit LSB steps). > One Clock Cycle FIGURE 2. PCM61P Setup and Hold Timing Diagram. MAXIMUM CLOCK RATE The maximum clock rate of 16.9MHz for the PCM61P is derived by multiplying the standard audio sample rate of 44.1kHz times sixteen (16 x oversampling) times the standard audio word bit length of 24 (44.1kHz x 16 x 24 = 16.9MHz). Note that this clock rate accommodates a 24-bit word length, even though only 18 bits are actually being used. 470kΩ 100kΩ After allowing ample warm-up time (5-10 minutes) to assure stable operation of the PCM61P, select input code 3FFFF hexadecimal (all bits on except the MSB). Measure the output voltage using a 6-1/2 digit voltmeter and record it. Change the digital input code to 00000 hexadecimal (all bits off except the MSB). Adjust the 100kΩ potentiometer to make the output read 22.9µV more than the voltage reading of the previous code (a 1LSB step = 22.9µV). A much simpler method is to dynamically adjust the DLE at BPZ. Assuming the device has been installed in a digital audio application circuit, send the appropriate digital input to produce a –60dB level sinusoidal output, then adjust the 100kΩ potentiometer until a minimum level of distortion is observed. 200kΩ 1 –VS Trim 15 MSB Adjust 14 FIGURE 3. MSB Adjust Circuit. ® PCM61P 4