ADS1253 ADS 125 3 SBAS199 – MAY 2001 24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 24 BITS—NO MISSING CODES ● 19 BITS EFFECTIVE RESOLUTION UP TO 20kHz DATA RATE ● LOW NOISE: 1.8ppm ● FOUR DIFFERENTIAL INPUTS ● INL: 15ppm (max) ● EXTERNAL REFERENCE (0.5V to 5V) ● POWER-DOWN MODE ● SYNC MODE ● LOW POWER: 8mW at 20kHz 5mW at 10kHz The ADS1253 is a precision, wide dynamic range, deltasigma, Analog-to-Digital (A/D) converter with 24-bit resolution operating from a single +5V supply. The delta-sigma architecture is used for wide dynamic range and to guarantee 24 bits of no missing codes performance. An effective resolution of 19 bits (1.8ppm of rms noise) is achieved for conversion rates up to 20kHz. The ADS1253 is designed for high-resolution measurement applications in cardiac diagnostics, smart transmitters, industrial process control, weight scales, chromatography, and portable instrumentation. The converter includes a flexible, two-wire synchronous serial interface for low-cost isolation. The ADS1253 is a four-channel converter and is offered in an SSOP-16 package. APPLICATIONS ● ● ● ● ● ● CARDIAC DIAGNOSTICS DIRECT THERMOCOUPLE INTERFACES BLOOD ANALYSIS INFRARED PYROMETERS LIQUID/GAS CHROMATOGRAPHY PRECISION PROCESS CONTROL ADS1253 VREF CH1+ CH1– CLK CH2+ CH2– Mux CH3+ 4th-Order ∆Σ Modulator Digital Filter Serial Interface CH3– SCLK DOUT/DRDY +VDD CH4+ GND CH4– Control CHSEL0 CHSEL1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Analog Input: Current (Momentary) .............................................. ±100mA (Continuous) ............................................... ±10mA Voltage ................................... GND – 0.3V to VDD + 0.3V VDD to GND ............................................................................ –0.3V to 6V VREF Voltage to GND ............................................... –0.3V to VDD + 0.3V Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V Lead Temperature (soldering, 10s) .............................................. +300°C Power Dissipation (any package) ................................................. 500mW This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER ADS1253E SSOP-16 322 –40°C to +85°C ADS1253E " " " " " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA ADS1253E ADS1253E/2K5 Rails Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “ADS1253E/2K5” will get a single 2500-piece Tape and Reel. ELECTRICAL CHARACTERISTICS All specifications at TMIN to TMAX, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. ADS1253E PARAMETER ANALOG INPUT Input Voltage Range Input Impedance Input Capacitance Input Leakage DYNAMIC CHARACTERISTICS Data Rate Bandwidth Serial Clock (SCLK) System Clock Input (CLK) ACCURACY Integral Non-Linearity(1) THD Noise Resolution No Missing Codes Common-Mode Rejection Gain Error Offset Error Gain Sensitivity to VREF Power-Supply Rejection Ratio CONDITIONS MIN GND CLK = 3,840Hz CLK = 1MHz CLK = 8MHz 260 1 125 6 5 At +25°C At TMIN to TMAX MAX UNITS ±VREF V MΩ MΩ kΩ pF pA nA 50 1 20.8 –3dB 4.24 16 8 ±0.0002 105 1.8 1kHz Input; 0.1dB below FS 60Hz, AC 24 24 90 70 PERFORMANCE OVER TEMPERATURE Offset Drift Gain Drift VOLTAGE REFERENCE VREF Load Current TYP 102 0.1 ±20 1:1 88 ±0.0015 2.7 1 ±100 4.096 32 % of FSR dB ppm of FSR, rms Bits Bits dB % of FSR ppm of FSR dB 0.07 0.4 0.5 kHz kHz MHz MHz ppm/°C ppm/°C VDD V µA NOTE: (1) Applies to full-differential signals. 2 ADS1253 SBAS199 ELECTRICAL CHARACTERISTICS (Cont.) All specifications at TMIN to TMAX, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. ADS1253E PARAMETER CONDITIONS DIGITAL INPUT/OUTPUT Logic Family Logic Level: VIH VIL VOH VOL Input (SCLK, CLK, CHSEL0, CHSEL1) Hysteresis Data Format MIN MAX UNITS +VDD + 0.3 +0.8 V V V V V CMOS +4.0 –0.3 +4.5 IOH = –500µA IOL = 500µA 0.4 0.6 Offset Binary Two’s Complement POWER-SUPPLY REQUIREMENTS Operation Quiescent Current Operating Power Power-Down Current +4.75 TEMPERATURE RANGE Operating Storage +5 1.5 7.5 0.4 –40 –60 PIN CONFIGURATION +5.25 2 10 1 VDC mA mW µA +85 +100 °C °C PIN DESCRIPTIONS Top View CH1+ TYP SSOP-16 PIN NAME PIN DESCRIPTION 1 CH1+ Analog Input: Positive Input of the Differential Analog Input. 2 CH1– Analog Input: Negative Input of the Differential Analog Input. 3 CH2+ Analog Input: Positive Input of the Differential Analog Input. 4 CH2– Analog Input: Negative Input of the Differential Analog Input. 1 16 CH4+ CH1– 2 15 CH4– CH2+ 3 14 VREF 5 CH3+ Analog Input: Positive Input of the Differential Analog Input. CH2– 4 13 GND 6 CH3– Analog Input: Negative Input of the Differential Analog Input. 7 +VDD Input: Power Supply Voltage, +5V. 8 CLK Digital Input: Device System Clock. The system clock is in the form of a CMOScompatible clock. This is a Schmitt-Trigger input. 9 DOUT/DRDY Digital Output: Serial Data Output/Data Ready. This output indicates that a new output word is available from the ADS1253 data output register. The serial data is clocked out of the serial data output shift register using SCLK. 10 SCLK Digital Input: Serial Clock. The serial clock is in the form of a CMOS-compatible clock. The serial clock operates independently from the system clock, therefore, it is possible to run SCLK at a higher frequency than CLK. The normal state of SCLK is LOW. Holding SCLK HIGH will either initiate a modulator reset for synchronizing multiple converters or enter power-down mode. This is a Schmitt-Trigger input. 11 CHSEL1 Digital Input: Used to select analog input channel. This is a Schmitt-Trigger input. 12 CHSEL0 Digital Input: Used to select analog input channel. This is a Schmitt-Trigger input. 13 GND Input: Ground. 14 15 VREF CH4– 16 CH4+ Analog Input: Reference Voltage Input. Analog Input: Negative Input of the Differential Analog Input. Analog Input: Positive Input of the Differential Analog Input. ADS1253E CH3+ 5 12 CHSEL0 CH3– 6 11 CHSEL1 +VDD 7 10 SCLK CLK 8 9 ADS1253 SBAS199 DOUT/DRDY 3 TYPICAL CHARACTERISTICS At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. EFFECTIVE RESOLUTION vs DATA OUTPUT RATE RMS NOISE vs DATA OUTPUT RATE 2.0 20.0 Effective Resolution (Bits) RMS Noise (ppm of FS) 19.8 1.8 1.6 1.4 1.2 19.6 19.4 19.2 19.0 18.8 18.6 18.4 18.2 1.0 100 18.0 1k 10k 100k 100 1k Data Output Rate (Hz) 100k EFFECTIVE RESOLUTION vs TEMPERATURE RMS NOISE vs TEMPERATURE 20.0 2.0 1.8 19.8 1.6 19.6 Effective Resolution (Bits) RMS Noise (ppm of FS) 10k Data Output Rate (Hz) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 19.4 19.2 19.0 18.8 18.6 18.4 18.2 0.0 –40 –20 0 20 40 60 80 100 18.0 –40 Temperature (°C) –20 0 20 40 60 80 100 Temperature (°C) RMS NOISE vs VREF VOLTAGE RMS NOISE vs VREF VOLTAGE 18 14 16 12 RMS Noise (ppm of FS) RMS Noise (µV) 14 12 10 8 6 4 8 6 4 2 2 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VREF Voltage (V) 4 10 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VREF (V) ADS1253 SBAS199 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. INTEGRAL NON-LINEARITY vs TEMPERATURE 5 1.8 4 INL (ppm of FS) RMS Noise (ppm of FS) RMS NOISE vs INPUT VOLTAGE (VREF = 5.0V) 2.0 1.6 1.4 3 2 1 1.2 0 1.0 –5 –4 –3 –2 –1 0 1 Input Voltage (V) 2 3 4 –40 5 –20 0 20 40 60 80 100 80 100 Temperature (°C) INTEGRAL NON-LINEARITY vs DATA OUTPUT RATE OFFSET vs TEMPERATURE 20 5 18 DC Offset (ppm of FS) INL (ppm of FS) 4 3 2 16 14 12 10 8 6 4 1 2 0 –40 0 100 1k 10k 100k –20 0 Data Output Rate (Hz) GAIN ERROR vs TEMPERATURE 60 PSRR vs CLK FREQUENCY 570 0 560 –20 550 –40 PSRR (dB) Gain Error (ppm of FS) 20 40 Temperature (°C) 540 530 –60 –80 520 –100 510 500 –120 –40 –20 0 20 40 Temperature (°C) ADS1253 SBAS199 60 80 100 0 2 4 6 8 Clock Frequency (MHz) 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +5V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified. CMR vs FREQUENCY CMR AT 60Hz vs CLK FREQUENCY –60 –70 –65 –75 –70 –80 CMR (dB) CMR at 60Hz (dB) –75 –80 –85 –90 –85 –90 –95 –95 –100 –100 –105 –110 0 1 2 3 4 5 Clock Frequency (MHz) 6 –105 a0873473 8 nn 7 10 9 1.62 8 1.60 7 1.58 1.56 1.54 1.52 1.50 1.48 6 5 4 3 2 1 1.46 0 –40 –20 0 20 40 60 80 100 0 1 2 3 Temperature (°C) 5 6 7 8 TYPICAL FFT (1kHz input at 0.1dB less than full-scale) 0 35 –20 Relative Magnitude (dB) 30 VREF Current (µA) 4 Clock Frequency (MHz) VREF CURRENT vs CLK FREQUENCY 25 20 15 10 –40 –60 –80 –100 –120 –140 5 –160 0 0 6 100k POWER DISSIPATION vs CLK FREQUENCY 1.64 Power Dissipation (mW) Current (mA) CURRENT vs TEMPERATURE 100 1k 10k Common-Mode Signal Frequency (Hz) 1 2 3 4 5 6 Clock Frequency (MHz) 7 8 9 0 1 2 3 4 5 6 7 8 9 10 11 Input Signal Frequency (kHz) ADS1253 SBAS199 THEORY OF OPERATION The ADS1253 is a precision, high-dynamic range, 24-bit, delta-sigma, A/D converter capable of achieving very high-resolution digital results at high data rates. The analog-input signal is sampled at a rate determined by the frequency of the system clock (CLK). The sampled analog input is modulated by the delta-sigma A/D modulator, which is followed by a digital filter. A sinc5 digital low-pass filter processes the output of the delta-sigma modulator and writes the result into the data-output register. The DOUT/DRDY pin is pulled LOW, indicating that new data is available to be read by the external microcontroller/microprocessor. As shown in the block diagram, the main functional blocks of the ADS1253 are the fourth-order delta-sigma modulator, a digital filter, control logic, input multiplexer, and a serial interface. Each of these functional blocks is described below. ANALOG INPUT The ADS1253 contains a fully differential analog input. In order to provide low system noise, common-mode rejection of 98dB and excellent power-supply rejection, the design topology is based on a fully differential switched-capacitor architecture. The bipolar input voltage range is from –4.096 to +4.096V, when the reference input voltage equals +4.096V. The bipolar range is with respect to –VIN, and not with respect to GND. Figure 1 shows the basic input structure of the ADS1253. The impedance is directly related to the sampling frequency of the input capacitor which is set by the CLK rate. Higher CLK rates result in lower impedance, and lower CLK rates result in higher impedance. RSW (1300Ω typical) Internal Circuitry AIN Modulator Frequency = fMOD CINT (6pF typical) VCM system clock frequency of 8MHz, the data-output rate is 20.8kHz with a –3dB frequency of 4.24kHz. The –3dB frequency scales with the system clock frequency. To guarantee the best linearity of the ADS1253, a fully differential signal is recommended, and the capacitance to ground must be equal on both sides. INPUT MULTIPLEXER The CHS1 and CHS0 pins are used to select the analog input channel as shown in Table I. The recommended method for changing channels is to change the channel after the conversion from the previous channel has been completed and read. When a channel is changed, internal logic senses the change on the falling edge of CLK and resets the conversion process. The conversion data from the new channel is valid on the first DRDY after the channel change. When multiplexing inputs it is possible to achieve sample rates close to 4kHz. This is due to the fact that it requires five internal conversion cycles for the data to fully settle, the data also must be read before the channel is changed. The DRDY signal indicates a valid result after the five cycles have occurred CHSEL1 CHSEL0 CHANNEL 0 0 1 1 0 1 0 1 CH1 CH2 CH3 CH4 TABLE I. Channel Selection. BIPOLAR INPUT Each of the differential inputs of the ADS1253 must stay between AGND – 0.3V and VDD + 0.3V. With a reference voltage at less than half of VDD, one input can be tied to the reference voltage, and the other input can range from 0 to 2 • VREF. By using a three op amp circuit featuring a single amplifier and four external resistors, the ADS1253 can be configured to accept bipolar inputs referenced to ground. The conventional ±2.5V, ±5V, and ±10V input ranges can be interfaced to the ADS1253 using the resistor values shown in Figure 2. FIGURE 1. Analog-Input Structure. R1 The input impedance of the analog input changes with ADS1253 system clock frequency (CLK). The relationship is: 10kΩ AIN Impedance (Ω) = (8MHz/CLK) • 125,000 With regard to the analog-input signal, the overall analog performance of the device is affected by three items: first, the input impedance can affect accuracy. If the source impedance of the input signal is significant, or if there is passive filtering prior to the ADS1253, a significant portion of the signal can be lost across this external impedance. The magnitude of the effect is dependent on the desired system performance. Second, the current into or out of the analog inputs must be limited. Under no conditions should the current into or out of the analog inputs exceed 10mA. Third, to prevent aliasing of the input signal, the analog-input signal must be band limited. The bandwidth of the A/D converter is a function of the system clock frequency. With a ADS1253 SBAS199 +IN OPA4350 20kΩ Bipolar Input –IN ADS1253 VREF R2 OPA4350 OPA4350 BIPOLAR INPUT ±10V ±5V ±2.5V R1 R2 2.5kΩ 5kΩ 10kΩ 5kΩ 10kΩ 20kΩ REF 2.5V FIGURE 2. Level Shift Circuit for Bipolar Input Ranges. 7 DELTA-SIGMA MODULATOR REFERENCE INPUT The ADS1253 operates from a nominal system clock frequency of 8MHz. The modulator frequency is fixed in relation to the system clock frequency. The system clock frequency is divided by 6 to derive the modulator frequency. Therefore, with a system clock frequency of 8MHz, the modulator frequency is 1.333MHz. Furthermore, the oversampling ratio of the modulator is fixed in relation to the modulator frequency. The oversampling ratio of the modulator is 64, and with the modulator frequency running at 1.333MHz, the data rate is 20.8kHz. Using a slower system clock frequency will result in a lower data output rate, as shown in Table II. Reference input takes an average current of 32µA with a 8MHz system clock. This current will be proportional to the system clock. A buffered reference is recommended for ADS1253. The recommended reference circuit is shown in Figure 3. Reference voltages higher than 4.096V will increase the full-scale range, while the absolute internal circuit noise of the converter remains the same. This will decrease the noise in terms of ppm of full scale, which increases the effective resolution (see the Typical Performance Curve “RMS Noise vs VREF Voltage”). CLK (MHz) DATA OUTPUT RATE (Hz) 8(1) 7.372800(1) 6.144000(1) 6.000000(1) 4.915200(1) 3.686400(1) 3.072000(1) 2.457600(1) 1.843200(1) 0.921600 0.460800 0.384000 0.192000 0.038400 0.023040 0.019200 0.011520 0.009600 0.007680 0.006400 0.005760 0.004800 0.003840 20,833 19,200 16,000 15,625 12,800 9,600 8,000 6,400 4,800 2,400 1,200 1,000 500 100 60 50 30 25 20 16.67 15 12.50 10 DIGITAL FILTER The digital filter of the ADS1253, referred to as a sinc5 filter, computes the digital result based on the most recent outputs from the delta-sigma modulator. At the most basic level, the digital filter can be thought of as simply averaging the modulator results in a weighted form and presenting this average as the digital output. The digital output rate, or data rate, scales directly with the system CLK frequency. This allows the data output rate to be changed over a very wide range (five orders of magnitude) by changing the system CLK frequency. However, it is important to note that the –3dB point of the filter is 0.2035 times the data output rate, so the data output rate should allow for sufficient margin to prevent attenuation of the signal of interest. Since the conversion result is essentially an average, the data-output rate determines the location of the resulting notches in the digital filter (see Figure 4). Note that the first notch is located at the data-output rate frequency, and subsequent notches are located at integer multiples of the data-output rate to allow for rejection of not only the fundamental frequency, but also harmonic frequencies. In this manner, the data-output rate can be used to set specific notch frequencies in the digital filter response. For example, if the rejection of power-line frequencies is desired, then the data-output rate can simply be set to the power-line frequency. For 50Hz rejection, the system CLK NOTE: (1) Standard Clock Oscillator. TABLE II. CLK Rate versus Data Output Rate. +5V +5V 0.10µF 7 4.99kΩ 2 To VREF Pin 14 of the ADS1253 6 10kΩ 3 1 OPA350 + + LM404-4.1 10µF 0.10µF 10µF 0.1µF 4 FIGURE 3. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1253. 8 ADS1253 SBAS199 DIGITAL FILTER RESPONSE 0 –20 –20 –40 –40 –60 –60 –80 –80 Gain (dB) Gain (dB) NORMALIZED DIGITAL FILTER RESPONSE 0 –100 –120 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 0 1 2 3 4 5 6 7 8 9 10 0 50 100 Frequency (Hz) FIGURE 4. Normalized Digital Filter Response. 250 300 DIGITAL FILTER RESPONSE 0 0 –20 –20 –40 –40 –60 –60 –80 Gain (dB) Gain (dB) 200 FIGURE 5. Digital Filter Response (50Hz). DIGITAL FILTER RESPONSE –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 0 50 100 150 200 250 300 0 10 20 30 Frequency (Hz) 40 50 60 70 80 90 100 53 54 55 Frequency (Hz) FIGURE 6. Digital Filter Response (60Hz). FIGURE 7. Digital Filter Response (10Hz). DIGITAL FILTER RESPONSE DIGITAL FILTER RESPONSE 0 0 –20 –20 –40 –40 –60 –60 –80 Gain (dB) Gain (dB) 150 Frequency (Hz) –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 45 46 47 48 49 50 51 52 53 54 55 Frequency (Hz) FIGURE 8. Expanded Digital Filter Response (50Hz with a 50Hz Data Output Rate). ADS1253 SBAS199 45 46 47 48 49 50 51 52 Frequency (Hz) FIGURE 9. Expanded Digital Filter Response (50Hz with a 10Hz Data Output Rate). 9 DIGITAL FILTER RESPONSE 0 –20 –20 –40 –40 –60 –60 –80 Gain (dB) Gain (dB) DIGITAL FILTER RESPONSE 0 –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 –200 –200 55 56 57 58 59 60 61 62 63 64 65 Frequency (Hz) 55 56 57 58 59 60 61 62 63 64 65 Frequency (Hz) FIGURE 10. Expanded Digital Filter Response (60Hz with a 60Hz Data Output Rate). FIGURE 11. Expanded Digital Filter Response (60Hz with a 10Hz Data Output Rate). frequency should be 19.200kHz, this will set the data-output rate to 50Hz (see Table I and Figure 5). For 60Hz rejection, the system CLK frequency should be 23.040kHz, this will set the data-output rate to 60Hz (see Table I and Figure 6). If both 50Hz and 60Hz rejection is required, then the system CLK should be 3.840kHz; this will set the data-output rate to 10Hz and reject both 50Hz and 60Hz (See Table I and Figure 7). There is an additional benefit in using a lower data-output rate. It provides better rejection of signals in the frequency band of interest. For example, with a 50Hz data-output rate, a significant signal at 75Hz may alias back into the passband at 25Hz. This is due to the fact that rejection at 75Hz may only be 66dB in the stopband—frequencies higher than the first-notch frequency (see Figure 5). However, setting the data-output rate to 10Hz will provide 135dB rejection at 75Hz (see Figure 7). A similar benefit is gained at frequencies near the data-output rate (see Figures 8, 9, 10, and 11). For example, with a 50Hz data-output rate, rejection at 55Hz may only be 105dB (see Figure 8). However, with a 10Hz data-output rate, rejection at 55Hz will be 122dB (see Figure 9). If a slower data-output rate does not meet the system requirements, then the analog front end can be designed to provide the needed attenuation to prevent aliasing. Additionally, the data-output rate may be increased and additional digital filtering may be done in the processor or controller. The digital filter is described by the following transfer function: 10 5 π • f • 64 sin fMOD H( f ) = π•f 64 • sin fMOD or 1 – z –64 H( z ) = 64 • 1 – z –1 ( ) 5 The digital filter requires five conversions to fully settle. The modulator has an oversampling ratio of 64, therefore, it requires 5 • 64, or 320 modulator results, or clocks, to fully settle. Since the modulator clock is derived from the system clock (CLK) (modulator clock = CLK ÷ 6), the number of system clocks required for the digital filter to fully settle is 5 • 64 • 6, or 1920 CLKs. This means that any significant step change at the analog input requires five full conversions to settle. However, if the step change at the analog input occurs asynchronously to the DOUT/DRDY pulse, six conversions are required to ensure full settling. ADS1253 SBAS199 CONTROL LOGIC time defined by t4. If more than 24 SCLKs were provided during DOUT mode, the DOUT/DRDY line would stay LOW until the time defined by t4. The internal data pointer for shifting data out on DOUT/DRDY is reset on the falling edge of the time defined by t1 and t4. This ensures that the first bit of data shifted out of the ADS1253 after DRDY mode is always the MSB of new data. The control logic is used for communications and control of the ADS1253. Power-Up Sequence Prior to power-up, all digital and analog-input pins must be LOW. At the time of power-up, these signal inputs can be biased to a voltage other than 0V, however, they should never exceed +VDD. Once the ADS1253 powers up, the DOUT/DRDY line will pulse LOW on the first conversion for which the data is valid from the analog input signal. SYNCHRONIZING MULTIPLE CONVERTERS The normal state of SCLK is LOW, however, by holding SCLK HIGH, multiple ADS1253s can be synchronized. This is accomplished by holding SCLK HIGH for at least four, but less than twenty, consecutive DOUT/DRDY cycles (see Figure 15). After the ADS1253 circuitry detects that SCLK has been held HIGH for four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin will pulse LOW for 3 CLK cycles and then be held HIGH, and the modulator will be held in a reset state. The modulator will be released from reset and synchronization will occur on the falling edge of SCLK. With multiple converters the falling edge transition of SCLK must occur simultaneously on all devices. It is important to note that prior to synchronization, the DOUT/DRDY pulse of multiple ADS1253s in the system could have a difference in timing up to one DRDY period. Therefore to ensure synchronization, the SCLK should be held HIGH for at least five DRDY cycles. The first DOUT/DRDY pulse after the falling edge of SCLK will occur at t14. The first DOUT/DRDY pulse indicates valid data. POWER-DOWN MODE The normal state of SCLK is LOW, however, by holding SCLK HIGH, the ADS1253 will enter power-down mode. This is accomplished by holding SCLK HIGH for at least twenty consecutive DOUT/DRDY periods (see Figure 15). After the ADS1253 circuitry detects that SCLK has been held HIGH for four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin will pulse LOW for 3 CLK cycles and then be held HIGH, and the modulator will be held in a reset state. If SCLK is held HIGH for an additional sixteen DOUT/DRDY periods, the ADS1253 will enter power-down mode. The part will be released from powerdown mode on the falling edge of SCLK. It is important to note that the DOUT/DRDY pin will be held HIGH after four DOUT/DRDY cycles, but power-down mode will not be entered for an additional sixteen DOUT/DRDY periods. The first DOUT/DRDY pulse after the falling edge of SCLK will occur at t16 and will indicate valid data. Subsequent DOUT/DRDY pulses will occur normally. DOUT/DRDY The DOUT/DRDY output signal alternates between two modes of operation. The first mode of operation is the Data Ready mode (DRDY) to indicate that new data has been loaded into the data-output register and is ready to be read. The second mode of operation is the Data Output (DOUT) mode and is used to serially shift data out of the Data Output Register (DOR). See Figure 12 for the time domain partitioning of the DRDY and DOUT function. See Figure 14 for the basic timing of DOUT/DRDY. During the time defined by t2, t3, and t4, the DOUT/DRDY pin functions in DRDY mode. The state of the DOUT/DRDY pin would be HIGH prior to the internal transfer of new data to the DOR. The result of the A/D conversion would be written to the DOR from MSB to LSB in the time defined by t1 (see Figures 12 and 14). The DOUT/DRDY line would then pulse LOW for the time defined by t2, and then pulse HIGH for the time defined by t3 to indicate that new data was available to be read. At this point, the function of the DOUT/DRDY pin would change to DOUT mode. Data would be shifted out on the pin after t7. The device communicating with the ADS1253 can provide SCLKs to the ADS1253 after the time defined by t6. The normal mode of reading data from the ADS1253 would be for the device reading the ADS1253 to latch the data on the rising edge of SCLK (since data is shifted out of the ADS1253 on the falling edge of SCLK). In order to retrieve valid data, the entire DOR must be read before the DOUT/DRDY pin reverts back to DRDY mode. If SCLKs were not provided to the ADS1253 during the DOUT mode, the MSB of the DOR would be present on the DOUT/DRDY line until the time defined by t4. If an incomplete read of the ADS1253 took place while in DOUT mode (i.e., less than 24 SCLKs were provided), the state of the last bit read would be present on the DOUT/DRDY line until the DOUT Mode DRDY Mode t2 t4 DOUT/DRDY DOUT Mode DATA DRDY Mode t3 DATA DATA t1 FIGURE 12. DOUT/DRDY Partitioning. ADS1253 SBAS199 11 SERIAL INTERFACE The ADS1253 includes a simple serial interface which can be connected to microcontrollers and digital signal processors in a variety of ways. Communications with the ADS1253 can commence on the first detection of the DOUT/DRDY pulse after power up. It is important to note that the data from the ADS1253 is a 24-bit result transmitted MSB-first in Offset Two’s Complement format, as shown in Table IV. The data must be clocked out before the ADS1253 enters DRDY mode to ensure reception of valid data, as described in the DOUT/DRDY section of this data sheet. ISOLATION The serial interface of the ADS1253 provides for simple isolation methods. The CLK signal can be local to the ADS1253, which then only requires two signals (SCLK, and DOUT/DRDY) to be used for isolated data acquisition. The channel select signals (CHS0, CHS1) will also need to be isolated unless a counter is used to auto multiplex the channels. DIFFERENTIAL VOLTAGE INPUT DIGITAL OUTPUT (HEX) +Full Scale Zero –Full Scale 7FFFFFH 000000H 800000H TABLE IV. ADS1253 Data Format (Offset Two's Complement). SYMBOL tOSC tDRDY DRDY Mode DOUT Mode t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 DESCRIPTION MIN CLK Period Conversion Cycle DRDY Mode DOUT Mode DOR Write Time DOUT/DRDY LOW Time DOUT/DRDY HIGH Time (Prior to Data Out) DOUT/DRDY HIGH Time (Prior to Data Ready) Rising Edge of CLK to Falling Edge of DOUT/DRDY End of DRDY Mode to Rising Edge of First SCLK End of DRDY Mode to Data Valid (Propagation Delay) Falling Edge of SCLK to Data Valid (Hold Time) Falling Edge of SCLK to Next Data Out Valid (Propagation Delay) SCLK Setup Time for Synchronization or Power Down DOUT/DRDY Pulse for Synchronization or Power Down Rising Edge of SCLK Until Start of Synchronization Synchronization Time Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode Rising Edge of SCLK Until Start of Power Down Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode Falling Edge of Last DOUT/DRDY to Start of Power Down DOUT/DRDY High Time After Mux Change. 125 TYP MAX 384 • tOSC 36 • tOSC 348 • tOSC 6 • tOSC 6 • tOSC 6 • tOSC 24 • tOSC 30 30 30 5 30 30 3 • tOSC 1537 • CLK 0.5 • CLK 7679 • CLK 6143.5 • CLK 2042.5 • tOSC 7681 • CLK 2318.5 • tOSC 6144.5 • tOSC 2043.5 • tosc UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TABLE III. Digital Timing. t18 DOUT/DRDY DATA DATA CHS0, CHS1 MUX CHANGE FIGURE 13. Multiplexer Operation. 12 ADS1253 SBAS199 ADS1253 SBAS199 13 t4 t1 t10 t2 t3 tDRDY t10 t2 t3 FIGURE 16. Power-Down Mode. DOUT/DRDY SCLK CLK tDRDY FIGURE 15. Synchronization Mode. DOUT/DRDY SCLK CLK FIGURE 14. DOUT/DRDY Timing. DOUT/DRDY SCLK CLK t2 DOUT Mode DATA DOUT Mode DATA t4 t4 DRDY Mode t5 4 tDRDY 4 tDRDY t12 t3 t15 t11 MSB t7 t6 DATA DATA t8 t9 tDRDY t11 t11 t17 t13 t16 Power Down Occurs Here t14 Synchronization Begins Here Synchronization Mode Starts Here DOUT Mode LSB t2 t2 t3 t3 DATA DATA tDRDY DOUT Mode tDRDY DOUT Mode t4 t4 LAYOUT POWER SUPPLY The power supply should be well regulated and low noise. For designs requiring very high resolution from the ADS1253, power-supply rejection will be a concern. Avoid running digital lines under the device as they may couple noise onto the die. High-frequency noise can capacitively couple into the analog portion of the device and will alias back into the passband of the digital filter, affecting the conversion result. This clock noise will cause an offset error. GROUNDING The analog and digital sections of the system design should be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. GND should be connected to the analog ground plane, as well as all other analog grounds. Do not join the analog and digital ground planes on the board, but instead connect the two with a moderate signal trace. For multiple converters, connect the two ground planes at one location as central to all of the converters as possible. In some cases, experimentation may be required to find the best point to connect the two planes together. The printed circuit board can be designed to provide different analog/digital ground connections via short jumpers. The initial prototype can be used to establish which connection works best. DECOUPLING Good decoupling practices should be used for the ADS1253 and for all components in the design. All decoupling capacitors, and specifically the 0.1µF ceramic capacitors, should be placed as close as possible to the pin being decoupled. A 1µF to 10µF capacitor, in parallel with a 0.1µF ceramic capacitor, should be used to decouple VDD to GND. SYSTEM CONSIDERATIONS The recommendations for power supplies and grounding will change depending on the requirements and specific design of the overall system. Achieving 24 bits of noise performance is a great deal more difficult than achieving 12 bits of noise performance. In general, a system can be broken up into four different stages: • • • • Analog Processing Analog Portion of the ADS1253 Digital Portion of the ADS1253 Digital Processing For the simplest system consisting of minimal analog signal processing (basic filtering and Gain), a microcontroller, and one clock source, one can achieve high resolution by powering all components by a common power supply. In addition, all components could share a common ground plane. Thus, there would be no distinctions between “analog” power and ground, and “digital” power and ground. The layout should still include a power plane, a ground plane, and careful decoupling. In a more extreme case, the design 14 could include: • Multiple ADS1253s • Extensive Analog Signal Processing • One or More Microcontrollers, Digital Signal Processors, or Microprocessors • Many Different Clock Sources • Interconnections to Various Other Systems High resolution will be very difficult to achieve for this design. The approach would be to break the system into as many different parts as possible. For example, each ADS1253 may have its own “analog” processing front end. DEFINITION OF TERMS An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the definition of each term is given as follows: Analog-Input Differential Voltage—for an analog signal that is fully differential, the voltage range can be compared to that of an instrumentation amplifier. For example, if both analog inputs of the ADS1253 are at 2.048V, the differential voltage is 0V. If one analog input is at 0V and the other analog input is at 4.096V, then the differential voltage magnitude is 4.096V. This is the case regardless of which input is at 0V and which is at 4.096V. The digital-output result, however, is quite different. The analog-input differential voltage is given by the following equation: +VIN – (–VIN) A positive digital output is produced whenever the analog-input differential voltage is positive, while a negative digital output is produced whenever the differential is negative. For example, a positive full-scale output is produced when the converter is configured with a 4.096V reference, and the analog-input differential is 4.096V. The negative full-scale output is produced when the differential voltage is –4.096V. In each case, the actual input voltages must remain within the –0.3V to +VDD range. Actual Analog-Input Voltage—the voltage at any one analog input relative to GND. Full-Scale Range (FSR)—as with most ADC’s, the fullscale range of the ADS1253 is defined as the “input” which produces the positive full-scale digital output minus the “input” which produces the negative full-scale digital output. For example, when the converter is configured with a 4.096V reference, the differential full-scale range is: [4.096V (positive full scale) – (–4.096V) (negative full scale)] = 8.192V Least Significant Bit (LSB) Weight—this is the theoretical amount of voltage that the differential voltage at the analog input would have to change in order to observe a change in the output data of one least significant bit. It is computed as follows: LSB Weight = Full – Scale Range 2 • VREF = N 2N – 1 2 –1 where N is the number of bits in the digital output. ADS1253 SBAS199 Conversion Cycle—as used here, a conversion cycle refers to the time period between DOUT/DRDY pulses. Effective Resolution (ER)—of the ADS1253 in a particular configuration can be expressed in two different units: bits rms (referenced to output) and µVrms (referenced to input). Computed directly from the converter's output data, each is a statistical calculation based on a given number of results. Noise occurs randomly; the rms value represents a statistical measure which is one standard deviation. The ER in bits can be computed as follows: 2 • VREF 20 • log Vrms noise ER in bits rms = 6.02 The 2 • VREF figure in each calculation represents the full-scale range of the ADS1253. This means that both units are absolute expressions of resolution—the performance in different configurations can be directly compared, regardless of the units. fMOD—frequency of the modulator and the frequency the input is sampled. fMOD = CLK Frequency 6 fDATA—Data output rate. fDATA = ADS1253 SBAS199 Noise Reduction—for random noise, the ER can be improved with averaging. The result is the reduction in noise by the factor √N, where N is the number of averages, as shown in Table V. This can be used to achieve true 24-bit performance at a lower data rate. To achieve 24 bits of resolution, more than 24 bits must be accumulated. A 36-bit accumulator is required to achieve an ER of 24 bits. The following uses VREF = 4.096V, with the ADS1253 outputting data at 20kHz, a 4096 point average will take 204.8ms. The benefits of averaging will be degraded if the input signal drifts during that 200ms. N (Number of Averages) NOISE REDUCTION FACTOR ER IN Vrms ER IN BITS rms 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 1 1.414 2 2.82 4 5.66 8 11.3 16 22.6 32 45.25 64 14.6µV 10.3µV 7.3µV 5.16µV 3.65µV 2.58µV 1.83µV 1.29µV 0.91µV 0.65µV 0.46µV 0.32µV 0.23µV 19.1 19.6 20.1 20.6 21.1 21.6 22.1 22.6 23.1 23.6 24.1 24.6 25.1 TABLE V. Averaging. fMOD CLK Frequency = 64 384 15 PACKAGE DRAWING 16 ADS1253 SBAS199 PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY ADS1253E ACTIVE SSOP DBQ 16 100 ADS1253E/2K5 ACTIVE SSOP DBQ 16 2500 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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