Data Sheet CDK3405 8-bit, 180MSPS, Triple Video DACs n 8-bit resolution, 180MSPS n ±2.5% gain matching n ±0.5% linearity error n Sync and blank controls n 1.0Vpp video into 37.5Ω or 75Ω load n Internal bandgap voltage reference n Low glitch energy n Single +3.3V power supply CDK3405 is a low-cost triple D/A converter that is tailored to fit graphics and video applications where speed is critical. CMOS-level inputs are converted to analog current outputs that can drive 25-37.5Ω loads corresponding to doubly-terminated 50-75Ω loads. A sync current following SYNC input timing is added to the IOG output. BLANK will override RGB inputs, setting IOG, IOB and IOR currents to zero when BLANK = L. Although appropriate for many applications, the internal 1.25V reference voltage can be overridden by the VREF input. Few external components are required, just the current reference resistor, current output load resistors, bypass capacitors, and decoupling capacitors. APPLICATIONS Video signal conversion – RGB – YCBCR – Composite, Y, C n n Multimedia systems n Image processing n PC Graphics Package is a 48-lead TQFP. Fabrication technology is CMOS. Performance is guaranteed from -40°C to +125°C. Block Diagram G7-0 B7-0 R7-0 Rev 1B SYNC SYNC BLANK 8 8-bit D/A Converter IO G 8 8-bit D/A Converter IO B 8 8-bit D/A Converter IO R CLOCK COMP R REF V REF +1.25V Ref Ordering Information Part Number Package Pb-Free RoHS Compliant Operating Temp Range Packaging Method Package Quantity CDK3405ATQ48 TQFP-48 Yes Yes -40°C to +125°C Tray 250 CDK3405ATQ48Y TQFP-48 Yes Yes -40°C to +125°C Tray 1,250 Moisture sensitivity level for all parts is MSL-3. ©2009-2010 CADEKA Microcircuits LLC CDK3405 8-bit, 180MSPS, Triple Video DACs General Description FEATURES www.cadeka.com Data Sheet Pin Configuration R7 R6 R5 R4 R3 R2 R1 R0 GND GND NC RSET TQFP-48 48 47 46 45 44 43 42 41 40 39 38 37 CDK3405 8-bit, 180MSPS, Triple Video DACs 1 2 3 4 5 6 7 8 9 10 11 12 TQFP CDK3405 36 35 34 33 32 31 30 29 28 27 26 25 VREF COMP IOR NC IOG NC VAA VAA IOB NC GND GND VAA GND GND B0 B1 B2 B3 B4 B5 B6 B7 CLOCK 13 14 15 16 17 18 19 20 21 22 23 24 GND GND G0 G1 G2 G3 G4 G5 G6 G7 BLANK SYNC Pin Assignments Pin No. Pin Name Description Clock and Pixel I/O CLK Clock Input R7-0 Red Pixel Data Inputs 3-10 G7-0 Green Pixel Data Inputs 16-23 B7-0 Blue Pixel Data Inputs 12 SYNC Sync Pulse Input 11 BLANK Blanking Input Rev 1B 24 41-48 Controls Video Outputs 34 IOR Red Current Output 32 IOG Green Current Output 28 IOB Blue Current Output Voltage Reference 36 VREF Input for DACs or Voltage Reference Output (1.25V) 37 RSET Current-Setting Resistor 35 COMP Compensation Capacitor Power and Ground 13, 29, 30 1, 2, 14, 15, 25, 26, 39, 40 27, 31, 33 VAA Analog Power Supply GND Ground NC No Connect ©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Power Supply Voltage VAA (Measured to GND) Digital Inputs Applied Voltage (measured to GND)(2) Forced Current(3,4) Analog Inputs Applied Voltage (measured to GND)(2) Forced Current(3,4) Analog Outputs Applied Voltage (measured to GND)(2) Forced Current(3,4) Short Circuit Duration (single output in HIGH state to GND) Min Max Unit -0.5 4.0 V -0.5 -5.0 VAA + 0.5 5.0 V mA -0.5 -10.0 VAA + 0.5 10.0 V mA -0.5 -60.0 VAA + 0.5 60.0 unlimited V mA sec Min Max Unit -40 125 150 300 220 150 °C °C °C °C °C °C/W CDK3405 8-bit, 180MSPS, Triple Video DACs Parameter Reliability Information Parameter -65 Package Thermal Resistance (θJA) 65 Rev 1B Temperature Operating, Ambient Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage Notes: ESD Protection Parameter TQFP-48 Human Body Model (HBM) Charged Device Model (CDM) TBD TBD CDK3405 Power Derating Maximum Power Dissipation (W) 1.Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 3 2.5 2 TQFP-48 1.5 1 0.5 0 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (°C) Recommended Operating Conditions Symbol VAA VREF CC RL TA Parameter Min Typ Max Unit Power Supply Voltage Reference Voltage, External Compensation Capacitor Output Load Ambient Temperature, Still Air 3.0 1.0 3.3 1.25 0.1 37.5 3.6 1.5 V V µF Ω °C ©2009-2010 CADEKA Microcircuits LLC -40 +125 www.cadeka.com 3 Data Sheet Electrical Characteristics (TA = 25°C, VAA =3.3V, VREF = 1.25V, RL = 37.5Ω, unless otherwise noted) Symbol Parameter Conditions Power Supply Current PD TA = 25°C Typ Max Units 80 85 mA TA = -40°C to +125°C (2) 95 mA Total Power Dissipation(2) TA = -40°C to +125°C 300 mW VIH Input Voltage, HIGH (1) TA = -40°C to +125°C VIL Input Voltage, LOW (1) TA = -40°C to +125°C IIH Input Current, HIGH TA = -40°C to +125°C IIL Input Current, LOW (1) TA = -40°C to +125°C CI Input Capacitance Digital Inputs (1) 2.5 V 0.8 V -1 1 μA -1 1 μA 4 pF Analog Outputs Output Current (1) 30 mA RO Output Resistance 40 kΩ CO Output Capacitance 7 pF Reference Output VREF Reference Voltage Output (1) TA = -40°C to +125°C 1.25 1.365 V Min Typ Max Units 180 MSPS Notes: 1. 100% tested at 25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. Switching Characteristics (TA = 25°C, VAA =3.3V, VREF = 1.25V, RL = 37.5Ω, unless otherwise noted) Symbol Parameter Conditions Clock Input Conversion Rate (1) TA = -40°C to +125°C tPWH Pulse-width HIGH (2) TA = -40°C to +125°C 2 ns tPWL Pulse-width LOW TA = -40°C to +125°C 2 ns 1.5 ns (2) Data Inputs tS tH Setup Hold TA = 25°C (1) TA = -40°C to +125°C (2) 2 ns TA = 25°C (1) 0.6 ns TA = -40°C to +125°C (2) 0.6 ns Data Outputs, with 50Ω doubly terminated load tD Clock to Output Delay TA = -40°C to +125°C 1.6 ns tR Output Risetime TA = -40°C to +125°C 0.6 ns tF Output Falltime TA = -40°C to +125°C 0.4 ns tSET Settling Time 2.5 ns tSKEW Output Skew 0.3 ns Notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. ©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 4 Rev 1B 1.135 CDK3405 8-bit, 180MSPS, Triple Video DACs IDD Min (1) Data Sheet DC Performance (TA = 25°C, VAA =3.3V, VREF = 1.25V, RL = 37.5Ω, unless otherwise noted) Symbol Parameter Conditions Min Resolution Integral Linearity Error DNL Differential Linearity Error PSRR TA = 25°C bits -0.5 0.5 LSB -0.5 0.5 LSB TA = 25°C (1) -0.5 0.5 LSB TA = -40°C to +125°C (2) TA = -40°C to +125°C (2) Gain Matching Error TA = -40°C to +125°C (1) Absolute Gain Error TA = -40°C to +125°C Power Supply Rejection Ratio Units TA = -40°C to +125°C (2) (1) Offset Error Full-Scale Output Current Max -0.5 -2.5 LSB %FS 2.5 %FS 3.5 %FS TA = 25°C (1) 18.0 18.7 19.4 mA TA = -40°C to +125°C (2) 18.0 18.7 19.4 mA (1) -3.5 0.5 0.01 TA = -40°C to +125°C , With internal reference. Trim RSET to calibrate full-scale current. TA = -40°C to +125°C (2) 18.7 mA -0.01 0 0.01 %/% Min Typ Max Units Notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. AC Performance (TA = 25°C, VAA = 3.3V, VREF = 1.25V, RL = 37.5Ω, unless otherwise noted) Symbol Parameter Conditions Analog Outputs 20 pVsec DAC-to-DAC Crosstalk 30 dB Data Feedthrough 50 dB Clock Feedthrough 60 dB Notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. ©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 5 Rev 1B Glitch Energy CDK3405 8-bit, 180MSPS, Triple Video DACs INL Typ 8 Data Sheet Table 1. Output Voltage vs. Input Code, SYNC and BLANK, VREF = 1.25V, RREF = 348Ω, RL = 37.5Ω RGB7-0 (MSB…LSB) BLUE AND RED GREEN BLANK VOUT (V) SYNC BLANK VOUT (V) 1111 1111 1 1 0.700 1 1 1.007 1111 1111 0 1 0.700 0 1 0.700 1111 1110 1 1 0.697 1 1 1.004 1111 1101 1 1 0.695 1 1 1.001 • • • • • • • • • • • • • • 1000 0000 1 1 0.351 1 1 0.658 0111 1111 1 1 0.349 1 1 0.656 0111 1111 0 1 0.349 0 1 0.349 • • • • • • • • • • • • • • 0000 0010 1 1 0.005 1 1 0.312 0000 0001 1 1 0.003 1 1 0.310 0000 0000 1 1 0.000 1 1 0.307 0000 0000 0 1 0.000 0 1 0.000 XXXX XXXX 1 0 0.000 1 0 0.307 XXXX XXXX 0 0 0.000 0 0 0.000 tPWH ts tH 1/fs Rev 1B tPWL CDK3405 8-bit, 180MSPS, Triple Video DACs SYNC CLK Pixel Data and Controls Data N Data N+1 Data N+2 3%/FS tD 90% tSET OUTPUT 50% tF tR 10% Figure 1. CDK3405 Timing Diagram ©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 6 Data Sheet Functional Description Within the CDK3405 are three identical 8-bit D/A converters, each with a current source output. External loads are required to convert the current to voltage outputs. Data inputs RGB7-0 are overridden by the BLANK input. SYNC BLANK gates the D/A inputs. If BLANK = HIGH, the D/A inputs control the output currents to be added to the output blanking level. If BLANK = Low, data inputs and the pedestal are disabled. Data: 660mV max. VDDA V AA IOS SYNC VVDDA AA Pedestal: 54mV G7-0 Sync: 286mV VVDDA AA Figure 3. Normal Output Levels Sync Pulse Input - SYNC B7-0 VVDDA AA R7-0 Figure 2. CDK3405 Current Source Structure Incoming GBR data is regsitered on the rising edge of the clock input, CLK. Analog outputs follow the rising edge of Blanking Input - BLANK When BLANK is LOW, pixel data inputs are ignored and the D/A converter outputs are driven to the blanking level. BLANK is registered on the rising edge of CLK. CLK after a delay, tDO. D/A Outputs Clock Input - CLK Each D/A output is a current source from the VDDA supply. Expressed in current units, the GBR transformation from data to current is as follows: Pixel data is registered on the rising edge of CLK. CLK should be driven by a dedicated buffer to avoid reflection induced jitter, overshoot, and undershoot. Pixel Data Inputs - R7-0, B7-0, G7-0 RGB digital inputs are registered on the rising edge of CLK. SYNC and BLANK SYNC and BLANK inputs control the output level (Figure 3 and Table 1, on the previous page) of the D/A converters during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC = L turns off a current source, IOS, that is connected to the green D/A converter. SYNC = H adds a 112/256 fraction of full-scale current to the green output. SYNC = L extinguishes the sync current during the sync tip. ©2009-2010 CADEKA Microcircuits LLC G = G7-0 & BLANK + SYNC * 112 B = B7-0 & BLANK R = R7-0 & BLANK Typical LSB current step is 73.2μA. To obtain a voltage output, a resistor must be connected to ground. Output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor connected between RREF and GND. To implement a doubly-terminated 75Ω transmission line, a shunt 75Ω resistor should be placed adjacent to the analog output pin. With a terminated 75Ω line connected to the analog output, the load on the CDK3405 current source is 37.5Ω. www.cadeka.com 7 Rev 1B Digital Inputs Bringing SYNC LOW, disables a current source which superimposes a sync pulse on the IOG output. SYNC and pixel data are registered on the rising edge of CLK. SYNC does not override any other data and should be used only during the blanking interval. If sync pulses are not required, SYNC should be connected to GND. CDK3405 8-bit, 180MSPS, Triple Video DACs = H activates, sync current from IOS for sync-on-green video signals. Data Sheet The CDK3405 may also be operated with a single 75Ω terminating resistor. To lower the output voltage swing to the desired range, the nominal value of the resistor on RREF should be doubled. Current source outputs can drive VESA VSIS, and RS343A/SMPTE-170M compatible levels into doubly-terminated 75Ω lines. Sync pulses can be added to the green output. When SYNC is HIGH, the current added to IOG is: Voltage Reference Output/Input - VREF IOS = 2.33 (VREF/ RREF) An internal voltage source of +1.25V is output on the VREF pin. An external +1.25V reference may be applied to override the internal reference. Decoupling VREF to GND with a 0.1µF ceramic capacitor is required. Current-Setting Resistor - RREF Full-scale output current of each D/A converter is determined by the value of the resistor connected between RREF and GND. Nominal value of RREF is found from: RREF = 5.31 (VREF/IFS) where IFS is the full-scale (white) output current (in amps) from the D/A converter (without sync). Sync is 0.439 * IFS. D/A full-scale (white) current may also be calculated from: IFS = VFS/RL Voltage Reference Full scale current is a multiple of the current ISET through an external resistor, RSET connected between the RREF pin ©2009-2010 CADEKA Microcircuits LLC Required power is a single +3.3V supply. To minimize power supply induced noise, analog +3.3V should be connected to all three supply pins with 0.1µF and 0.01µF decoupling capacitors placed adjacent to each VAA pin or pin pair. The high slew-rate of digital data makes capacitive coupling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins should be connected to a common solid ground plane for best performance. www.cadeka.com 8 Rev 1B Where VFS is the white voltage level and RL is the total resistive load (Ω) on each D/A converter. VFS is the blank to full-scale voltage. Power and Ground CDK3405 8-bit, 180MSPS, Triple Video DACs R, G, and B Current Outputs - IOR, IOG, IOB and GND. Voltage across RSET is the reference voltage, VREF, which can be derived from either the 1.25 volt internal bandgap reference or an external voltage reference connected to VREF. To minimize noise, a 0.1μF capacitor should be connected between VREF and ground. ISET is mirrored to each of the GBR output current sources. To minimize noise, a 0.1μF capacitor should be connected between the COMP pin and the analog supply voltage VAA. Data Sheet Applications Dicussion Figure 9 (on the following page) illustrates a typical CDK3405 interface circuit. In this example, an optional 1.2V bandgap reference is connected to the VREF output, overriding the internal voltage reference source. It is important that the CDK3405 power supply is wellregulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. The CDK3405 has separate analog and digital circuits. To keep digital system noise from the D/A converter, it is recommended that power supply voltages come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin. Printed Circuit Board Layout Improved Transisiton Times Output shunt capacitance dominates slowing of output transition times, whereas series inductance causes a small amount of ringing that affects overshoot and settling time. With a doubly terminated 75Ω load, transition times can be improved by matching the capacitive impedance output of the CDK3405. Output capacitance can be matched with a 220nH inductor in series with the 75Ω source termination. IOG W1 COAX 32 R1 75Ω U1 CDK3405 IOB W2 COAX 29 Rev 1B Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 5. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. R2 75Ω 1. Keep the critical analog traces (VREF, IREF, COMP, IOS, IOR, IOG) as short as possible and as far as possible from all digital signals. The CDK3405 should be located near the board edge, close to the analog out-put connectors. 2. The power plane for the CDK3405 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VAA pins. If the power supply for the CDK3405 is the same as that of the system’s digital circuitry, power to the CDK3405 should be decoupled with 0.1µF and 0.01µF capacitors and isolated with a ferrite bead. 3. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. ©2009-2010 CADEKA Microcircuits LLC IOR W3 COAX 33 R3 75Ω L1 220nH R4 75Ω L2 220nH R5 75Ω L3 220nH R6 75Ω Figure 4. Schematic, Transition Time Sharpening Circuit A 220nH inductor trims the performance of a 4ft cable, quite well. In Figures 5 through 8, the glitch at 12.5ns, is due to a reflection from the source. Not shown, are smaller glitches at 25 and 37.5ns, corresponding to secondary and tertiary reflections. Inductor values should be selected to match the length and type of the cable. www.cadeka.com CDK3405 8-bit, 180MSPS, Triple Video DACs Grounding 4. If the digital power supply has a dedicated power plane layer, it should not be placed under the CDK3405, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the CDK3405 and its related analog circuitry can have an adverse effect on performance. 9 0.8 0.8 0.7 0.7 0.6 0.6 GOUT (V) 0.5 0.4 0.3 0.2 0.5 0.4 0.3 0.2 0.1 0.1 0 0 -0.1 -0.1 -5 0 5 10 15 -0.2 20 -5 0 5 Time (ns) 15 20 Figure 7. Unmatched tF 0.8 0.8 0.7 0.7 0.6 0.6 0.5 GOUT (V) GOUT (V) 10 Time (ns) Figure 5. Unmatched tR 0.4 0.3 0.2 0.5 0.4 0.3 0.2 0.1 0.1 0 0 -0.1 -0.1 CDK3405 8-bit, 180MSPS, Triple Video DACs ROUT (V) Data Sheet -5 0 5 10 15 -0.2 20 -5 0 5 Time (ns) 10 15 20 Time (ns) Figure 8. Matched tF Rev 1B Figure 6. Matched tR +3.3V 0.1µF 10µF 0.01µF 0.1µF VDDD VAA RED PIXEL INPUT R7-0 GREEN PIXEL INPUT G7-0 BLUE PIXEL INPUT B7-0 CLOCK SYNC BLANK GND (13) VDDA VAA (29, 30) IOG CDK3405 Red IOR IOB Zo = 75Ω Zo = 75Ω Blue 75Ω Zo = 75Ω 75Ω 75Ω 75Ω Triple 8-bit D/A Converter VVDDA AA COMP CLK SYNC BLANK Green w/Sync 75Ω 75Ω 0.1µF 3.3kΩ (not required without external reference) V REF R REF LM185-1.2 348Ω 0.1µF (Optional) Figure 9. Typical Interface Circuit Diagram Evaluation boards are available (CEB3405), contact CADEKA for more information. Related Products n CDK3400/3401 Triple 10-bit 180MSPS DACs n CDK3404 Triple 8-bit 180MSPS DAC ©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 10 Data Sheet Mechanical Dimensions TQFP-48 Package CDK3405 8-bit, 180MSPS, Triple Video DACs Rev 1B For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2009-2010 by CADEKA Microcircuits LLC. All rights reserved.