TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 D D D D D D D D D Organization: – TM2SN64EPU . . . 2 097 152 x 64 Bits – TM4SN64EPU . . . 4 194 304 x 64 Bits Single 3.3-V Power Supply (±10% Tolerance) Designed for 66-MHz 4-Clock Systems JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket TM2SN64EPU — Uses Eight 16M-Bit Synchronous Dynamic RAMs (SDRAMs) (2M × 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) TM4SN64EPU — Uses Sixteen 16M-Bit SDRAMs (2M × 8-Bit) in Plastic TSOPs Byte-Read/Write Capability Performance Ranges: SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 (CL = 3)† (CL = 2) ACCESS TIME CLOCK TO OUTPUT tCK3 tCK2 (CL = 3) (CL = 2) D D D D D D D D High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface Read Latencies 2 and 3 Supported Support Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Two Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0°C to 70°C Gold-Plated Contacts Pipeline Architecture Serial Presence-Detect (SPD) Using EEPROM REFRESH INTERVAL ’xSN64EPU-12A‡ 12 ns 15 ns 9 ns 9 ns 64 ms ’xSN64EPU-12 12 ns 18 ns 9 ns 10 ns 64 ms † CL = CAS latency ‡ –12A speed device is supported only at –5 to +10% VDD description The TM2SN64EPU is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of eight TMS626812DGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812 data sheet (literature number SMOS687). The TM4SN64EPU is a 32M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS626812DGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS626812 data sheet (literature number SMOS687). operation The TM2SN64EPU operates as eight TMS626812DGE devices that are connected as shown in the TM2SN64EPU functional block diagram. The TM4SN64EPU operates as 16 TMS626812DGE devices connected as shown in the TM4SN64EPU functional block diagram. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 DUAL-IN-LINE MEMORY MODULE ( TOP VIEW ) TM2SN64EPU ( SIDE VIEW ) TM4SN64EPU ( SIDE VIEW ) PIN NOMENCLATURE A[0:10] A[0:8] A11/BA0 CAS CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7] 1 10 NC RAS S[0:3] SA[0:2] 11 SCL SDA VDD VSS WE 40 41 84 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Row Address Inputs Column Address Inputs Bank-Select Zero Column-Address Strobe Clock Enable System Clock Data-In / Data-Out Data-In/Data-Out Mask Enable No Connect Row-Address Strobe Chip-Select Serial Presence-Detect (SPD) Device Address Input SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 Pin Assignments ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁ PIN PIN NAME NO. PIN NAME NO. PIN NAME NO. NAME NO. 1 VSS DQ0 43 86 VSS DQ32 127 44 VSS NC 85 2 128 VSS CKE0 3 DQ1 45 S2 87 DQ33 129 S3 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6 VDD DQ4 48 NC 90 NC 49 91 133 8 DQ5 50 VDD NC VDD DQ36 132 7 92 DQ37 134 VDD NC 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 NC 94 DQ39 136 NC 11 DQ8 53 NC 95 DQ40 137 NC 12 VSS DQ9 54 97 VSS DQ41 138 55 VSS DQ16 96 13 139 VSS DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 DQ45 143 60 102 VDD DQ52 61 NC 103 VDD DQ46 144 19 VDD DQ14 VDD DQ20 101 18 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 NC 63 CKE1 105 NC 147 NC 22 NC 64 NC 148 65 107 VSS DQ53 66 DQ22 108 VSS NC 149 24 VSS NC VSS DQ21 106 23 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 68 111 VDD CAS 152 69 VSS DQ24 110 27 VDD WE 153 VSS DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 S0 72 DQ27 114 S1 156 DQ59 31 NC 73 115 RAS 157 32 74 116 158 75 DQ29 117 VSS A1 VDD DQ60 33 VSS A0 VDD DQ28 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 120 A7 162 37 A8 79 VSS CK2 121 A9 163 VSS CK3 38 A10 80 NC 122 A11/BA0 164 NC 39 NC 81 NC 123 NC 165 SA0 40 VDD VDD 82 SDA 124 SA1 83 SCL 125 VDD CK1 166 41 167 SA2 42 CK0 84 VDD 126 NC 168 VDD POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 dual-in-line memory module and components The dual-in-line memory module and components include: D D D PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper functional block diagram for the TM2SN64EPU S0 RC CS CK: U0, U4 CS RC CK0 CK: U1, U5 U0 DQMB0 DQM R DQ[0:7] 8 DQMB4 DQ[32:39] 8 CK: U2, U6 RC CK1 DQM R DQ[0:7] RC U4 CK: U3, U7 DQ[0:7] RC CK2 CS C CS RC CK3 U1 DQMB1 DQM R DQ[8:15] 8 U5 DQMB5 R DQ[0:7] C DQM DQ[40:47] 8 DQ[0:7] R = 10 Ω RC = 10 Ω C = 10 pF S2 VDD CS U2 DQMB2 DQM R DQ[16:23] 8 U[0:7] Two 0.1 µF (minimum) per SDRAM U[0:7] CS U6 DQMB6 DQM R DQ[0:7] VSS DQ[48:55] 8 DQ[0:7] SPD EEPROM CS CS U3 DQMB3 DQM R DQ[24:31] RAS CAS WE CKE0 A[0:11] 4 8 SDA A0 A1 A2 SA0 SA1 SA2 U7 DQMB7 DQM R DQ[0:7] SCL DQ[56:63] RAS: SDRAM U[0:7] CAS: SDRAM U[0:7] WE: SDRAM U[0:7] CKE: SDRAM U[0:7] A[0:11]: SDRAM U[0:7] POST OFFICE BOX 1443 8 DQ[0:7] LEGEND: CS = SPD = • HOUSTON, TEXAS 77251–1443 Chip select Serial Presence Detect TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 functional block diagram for the TM4SN64EPU S1 VDD S0 CS CS CS U[0:7], UB[0:7] Two 0.1 µF (minimum) per SDRAM U[0:7], UB[0:7] CS VSS U0 DQMB0 DQM R DQ[0:7] 8 UB0 DQM U4 DQMB4 R DQ[0:7] DQ[0:7] CS CS DQ[32:39] 8 UB4 DQM DQM DQ[0:7] DQ[0:7] CS CS R = 10 Ω Rc = 10 Ω VDD U1 DQMB1 DQM R DQ[8:15] 8 UB1 DQM U5 DQMB5 R DQ[0:7] DQ[0:7] DQ[40:47] 8 UB5 DQM DQM DQ[0:7] DQ[0:7] 10 K CKE1 CKE: UB[0:7] CKE0 CKE: U[0:7] RAS RAS: U[0:7], UB[0:7] CAS CAS: U[0:7], UB[0:7] WE WE: U[0:7], UB[0:7] A[0:11] A[0:11]: U[0:7], UB[0:7] RC S3 CK: U0, U4 CK0 S2 RC CK: U1, U5 CS CS CS RC CS CK: UB0, UB4 CK1 U2 DQMB2 DQM R DQ[16:23] 8 UB2 DQM U6 DQMB6 DQM R DQ[0:7] DQ[0:7] DQ[48:55] 8 CK: UB1, UB5 UB6 RC CK: U2, U6 DQM CK2 DQ[0:7] RC DQ[0:7] RC CK: U3, U7 RC CK: UB2, UB6 CS U3 DQMB3 R DQ[24:31] 8 CS CS U7 UB3 DQM DQM DQ[0:7] DQ[0:7] CS DQMB7 R DQ[56:63] 8 CK3 CK: UB3, UB7 UB7 DQM DQM DQ[0:7] DQ[0:7] RC SPD EEPROM SCL SDA A0 A1 A2 SA0 SA1 SA2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 absolute maximum ratings over ambient temperature range (unless otherwise noted)† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM2SN64EPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W TM4SN64EPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ v ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ recommended operating conditions MIN NOM MAX UNIT 3 3.3 3.6 V VDD VSS Supply voltage VIH VIH-SPD High-level input voltage 2 High-level input voltage for the SPD device Low-level input voltage ‡ 2 Supply voltage VIL TA Ambient temperature ‡ VIL MIN = –1.5 V ac (pulse width 0 V VDD + 0.3 5.5 V V –0.3 0.8 V 0 70 °C 5 ns) capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ TM2SN64EPU PARAMETER MIN MAX TM4SN64EPU MIN MAX UNIT Ci(CK) Input capacitance, CK input 22 22 pF Ci(AC) Input capacitance, address and control inputs: A0 – A11, RAS, CAS, WE 42 82 pF Ci(CKE) Input capacitance, CKE input 42 42 pF Co Output capacitance 10 18 pF Ci(DQMBx) Input capacitance, DQMBx input 12 12 pF Ci(Sx) Input capacitance, Sx input 22 22 pF Ci/o(SDA) Input/output capacitor, SDA input 9 9 pF 7 7 pF Ci(SPD) Input capacitor, SA0, SA1, SA2, SCL inputs NOTE 2: VDD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3) ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ " " ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ " ÁÁÁ " ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ TM2SN64EPU PARAMETER VOH VOL High-level output voltage II Input current (leakage) IO ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 TEST CONDITIONS IOH = – 2 mA IOL = 2 mA Low-level output voltage ’2SN64EPU-12A MIN MAX 2.4 ’2SN64EPU-12 MIN MAX 2.4 UNIT V 0.4 0.4 V 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 10 10 µA Output current (leakage) 0 V < VO < VDD +0.3 V, Output disabled 10 10 µA 680 600 mA Operating current Burst length = 1, CAS latency = 2 tRC ≥ tRC MIN IOH/IOL = 0 mA, one bank CAS latency = 3 activated (see Note 4) 760 760 mA CKE ≤ VIL MAX, tCK = 15 ns (see Note 5) 16 16 mA CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 6) 16 16 mA CKE ≥ VIH MIN, tCK = 15 ns (see Note 5) 240 240 mA CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Note 6) 16 16 mA CKE ≤ VIL MAX, tCK = 15 ns (see Note 5) 64 64 mA CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 6) 64 64 mA CKE ≥ VIH MIN, tCK = 15 ns (see Note 5) 280 280 mA CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Note 6) 80 80 mA Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated,, nCCD = one cycle CAS latency = 3 (see Note 7) 1040 880 mA 1240 1240 mA CAS latency = 2 600 560 mA CAS latency = 3 680 680 mA Precharge g standby y current in power-down mode Precharge standby current in non-power-down mode Active standbyy current power-down mode in Active standby current non-power-down mode in Burst current Auto refresh current Auto-refresh tRC ≤ tRC MIN ICC6 Self-refresh current CKE ≤ VIL MAX 16 16 mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Control, DQ, and address inputs change state twice during tRC. 5. Control, DQ, and address inputs change state once every 30 ns. 6. Control, DQ, and address inputs do not change. 7. Control, DQ, and address inputs change once every cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3) ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ " " ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ " ÁÁÁ " ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ TM4SN64EPU PARAMETER VOH VOL High-level output voltage II Input current (leakage) IO ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 TEST CONDITIONS IOH = – 2 mA IOL = 2 mA Low-level output voltage ’4SN64EPU-12A MIN MAX 2.4 ’4SN64EPU-12 MIN MAX 2.4 UNIT V 0.4 0.4 V 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 20 20 µA Output current (leakage) 0 V < VO < VDD +0.3 V, Output disabled 20 20 µA 696 616 mA Operating current Burst length = 1, CAS latency = 2 tRC ≥ tRC MIN IOH/IOL = 0 mA, one bank CAS latency = 3 activated (see Note 4) 776 776 mA CKE ≤ VIL MAX, tCK = 15 ns (see Note 5) 32 32 mA CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 6) 32 32 mA CKE ≥ VIH MIN, tCK = 15 ns (see Note 5) 480 480 mA CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Note 6) 32 32 mA CKE ≤ VIL MAX, tCK = 15 ns (see Note 5) 128 128 mA CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 6) 128 128 mA CKE ≥ VIH MIN, tCK = 15 ns (see Note 5) 560 560 mA CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞ (see Note 6) 160 160 mA Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated,, nCCD = one cycle CAS latency = 3 (see Note 7) 1056 896 mA 1256 1256 mA CAS latency = 2 616 570 mA CAS latency = 3 696 696 mA Precharge g standby y current in power-down mode Precharge standby current in non-power-down mode Active standbyy current power-down mode in Active standby current non-power-down mode in Burst current Auto refresh current Auto-refresh tRC ≤ tRC MIN ICC6 Self-refresh current CKE ≤ VIL MAX 32 32 mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Control, DQ, and address inputs change state twice during tRC. 5. Control, DQ, and address inputs change state once every 30 ns. 6. Control, DQ, and address inputs do not change. 7. Control, DQ, and address inputs change once every cycle. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 ac timing requirements† ’xSN64EPU-12A‡ MIN MAX ’xSN64EPU-12 MIN 9 MAX UNIT tAC2 tAC3 Access time, CK high to data out, CAS latency = 2 (see Note 8) tCK2 tCK3 Cycle time, CK, CAS latency = 2 15 18 ns Cycle time, CK, CAS latency = 3 12 12 ns tLZ tHZ Delay time, CK high to DQ in low-impedance state (see Note 9) tRAS Delay time, ACTV command to DEAC or DCAB command 60 tRC Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command 90 108 ns tRCD Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 11) 30 30 ns tRP tRRD Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command 30 36 ns Delay time, ACTV command in one bank to ACTV command in the other bank 24 24 ns tRSA tAPR Delay time, MRS command to ACTV, MRS, REFR, or SLFR command 24 24 ns tOH tIH Hold time, CK high to data out 3 3 ns Hold time, address, control, and data input 1 1.5 ns tCESP tCH Power down/self-refresh exit time 10 10 ns Pulse duration, CK high 4 4 ns tCL tIS Pulse duration, CK low 4 4 ns Setup time, address, control, and data input 3 3 ns tAPW tWR Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command 60 60 ns Delay time, final data in of WRT operation to DEAC or DCAB command 15 tT tREF Transition time (see Note 12) nCCD nCDD Delay time, READ or WRT command to an interrupting command 1 Delay time, CS low or high to input enabled or inhibited 0 0 0 0 cycle nCLE nCWL Delay time, CKE high or low to CK enabled or disabled 1 1 1 1 cycle Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P 1 nDID nDOD Delay time, ENBL or MASK command to enabled or masked data in 0 0 0 0 cycle Delay time, ENBL or MASK command to enabled or masked data out 2 2 2 2 cycle Access time, CK high to data out, CAS latency = 3 (see Note 8) 9 3 Delay time, CK high to DQ in high-impedance state (see Note 10) 10 ns 9 ns 3 10 100 000 72 ns 10 ns 100 000 ns tRP – (CL –1) ∗ tCK Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command 1 Refresh interval ns 20 5 1 64 ns 5 64 1 ns ms cycle 1 cycle nHZP2 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 2 2 2 cycle nHZP3 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 3 3 3 cycle nWCD Delay time, WRT command to first data in 0 0 0 0 cycle † All references are made to the rising transition of CK unless otherwise noted. ‡ -12A speed device is supported only at – 5% to +10% VDD NOTES: 8. tAC is referenced from the rising transition of CK that is previous to the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is CAS latency – one cycle after the READ command. Access time is measured at output reference level 1.4 V. 9. tLZ is measured from the rising transition of CK that is CAS latency – one cycle after the READ command. 10. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 11. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS. 12. Transition time, tT, is measured between VIH and VIL. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 serial presence detect The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through a IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follows: Table 1 – TM2SN64EPU Table 2 – TM4SN64EPU Table 1. Serial Presence-Detect Data for the TM2SN64EPU BYTE NO. 10 DESCRIPTION OF FUNCTION TM2SN64EPU-12A TM2SN64EPU-12 ITEM DATA ITEM DATA 0 Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h 128 bytes 80h 1 Total number of bytes of SPD memory device 256 bytes 08h 256 bytes 08h 2 Fundamental memory type (FPM, EDO, SDRAM, . . .) SDRAM 04h SDRAM 04h 3 Number of row addresses on this assembly 11 0Bh 11 0Bh 4 Number of column addresses on this assembly 9 09h 9 09h 5 Number of module banks on this assembly 1 bank 01h 1 bank 01h 6 Data width of this assembly 64 bits 40h 64 bits 40h 7 Data width continuation 8 Voltage interface standard of this assembly 00h 00h LVTTL 01h LVTTL 01h 9 SDRAM cycle time at maximum supported CAS latency (CL), CL = X tCK = 12 ns C0h tCK = 12 ns C0h 10 SDRAM access from clock at CL = X tAC = 9 ns 90h tAC = 9 ns 90h 11 DIMM configuration type (non-parity, parity, error correcting code [ECC]) Non-Parity 00h Non-Parity 00h 12 Refresh rate / type 15.6 µs/ self-refresh 80h 15.6 µs/ self-refresh 80h 13 SDRAM width, primary DRAM 14 Error-checking SDRAM data width 15 Minimum clock delay, back-to-back random column addresses 16 17 18 CAS latencies supported 19 20 21 SDRAM module attributes x8 08h x8 08h N/A 00h N/A 00h 1 CK cycle 01h 1 CK cycle 01h Burst lengths supported 1, 2, 4, 8 0Fh 1, 2, 4, 8 0Fh Number of banks on each SDRAM device 2 banks 02h 2 banks 02h 2, 3 06h 2, 3 06h CS latency 0 01h 0 01h Write latency 0 01h 0 01h Non-buffered/ Non-registered 00h Non-buffered/ Non-registered 00h POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 serial presence detect (continued) Table 1. Serial Presence-Detect Data for the TM2SN64EPU (Continued) BYTE NO. DESCRIPTION OF FUNCTION SDRAM device attributes: general 23 Minimum clock cycle time at CL = X – 1 24 Maximum data-access time from clock at CL = X – 1 25 26 27 Minimum row precharge time 28 Minimum row-active to row-active delay 29 Minimum RAS-to-CAS delay 30 Minimum RAS pulse width 31 Density of each bank on module DATA 1Eh VDD tolerance = (+10%), Burst read / write, precharge all, auto precharge 0Eh F0h 90h tCK = 18 ns tAC = 10 ns A0h Minimum clock cycle time at CL = X – 2 N/A 00h N/A 00h Maximum data-access time from clock at CL = X – 2 N/A 00h N/A 00h tRP = 30 ns tRRD = 24 ns 1Eh tRP = 36 ns tRRD = 24 ns 24h tRCD = 30 ns tRAS = 60 ns 1Eh 1Eh 3Ch tRCD = 30 ns tRAS = 72 ns 16M Bytes 04h 16M Bytes 04h Rev. 1 01h Rev. 1 01h 7 07h 89 59h 97h 9700...00h 97h 9700...00h 18h SPD revision Checksum for byte 0 – 62 Manufacturer’s JEDEC ID code per JEP – 106E Manufacturing location† TBD TBD Manufacturer’s part number† Die revision code† TBD TBD TBD TBD TBD TBD 93–94 PCB revision code† Manufacturing date† TBD TBD 95–98 Assembly serial number† TBD TBD 99–125 Manufacturer specific data† Vendor specific data† TBD TBD TBD TBD System integrator’s specific data‡ Open TBD TBD 73–90 91 92 126–127 128–166 167–255 30h 18h 48h Superset features (may be used in the future) 63 72 ITEM tCK = 15 ns tAC = 9 ns 62 64 – 71 TM2SN64EPU-12 DATA VDD tolerance = (+10%) / (– 5%). Burst read / write, precharge all, auto precharge 22 32 – 61 TM2SN64EPU-12A ITEM † TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 serial presence detect (continued) Table 2. Serial Presence-Detect Data for the TM4SN64EPU BYTE NO. TM4SN64EPU-12 ITEM DATA ITEM DATA 0 Defines number of bytes written into serial memory during module manufacturing 128 bytes 80h 128 bytes 80h 1 Total number of bytes of SPD memory device 256 bytes 08h 256 bytes 08h 2 Fundamental memory type (FPM, EDO, SDRAM, . . .) SDRAM 04h SDRAM 04h 3 Number of row addresses on this assembly 11 0Bh 11 0Bh 4 Number of column addresses on this assembly 9 09h 9 09h 5 Number of module banks on this assembly 2 banks 02h 2 banks 02h 6 Data width of this assembly 64 bits 40h 64 bits 40h 7 Data width continuation 8 Voltage interface standard of this assembly LVTTL 01h LVTTL 01h 9 SDRAM cycle time at maximum supported CAS latency (CL), CL = X tCK = 12 ns C0h tCK = 12 ns C0h 10 SDRAM access from clock at CL = X tAC = 9 ns 90h tAC = 9 ns 90h 11 DIMM configuration type (non-parity, parity, error correcting code [ECC]) Non-Parity 00h Non-Parity 00h 12 Refresh rate / type 15.6 µs/ self-refresh 80h 15.6 µs/ self-refresh 80h 13 SDRAM width, primary DRAM x8 08h x8 08h 14 Error-checking SDRAM data width N/A 00h N/A 00h 15 Minimum clock delay, back-to-back random column addresses 1 CK cycle 01h 1 CK cycle 01h 16 Burst lengths supported 1, 2, 4, 8 0Fh 1, 2, 4, 8 0Fh 17 Number of banks on each SDRAM device 2 banks 02h 2 banks 02h 18 CAS latencies supported 2, 3 06h 2, 3 06h 19 CS latency 0 01h 0 01h 20 Write latency 0 01h 0 01h 00h Non-buffered/ Non-registered 00h 1Eh VDD tolerance = (+10%), Burst read / write, precharge all, auto precharge 0Eh 21 12 TM4SN64EPU-12A DESCRIPTION OF FUNCTION 00h Non-buffered/ Non-registered SDRAM module attributes VDD tolerance = (+10%) / (– 5%). Burst read / write, precharge all, auto precharge 22 SDRAM device attributes: general 23 Minimum clock cycle time at CL = X – 1 24 Maximum data-access time from clock at CL = X – 1 25 26 00h tCK = 15 ns tAC = 9 ns F0h 90h tCK = 18 ns tAC = 10 ns A0h Minimum clock cycle time at CL = X – 2 N/A 00h N/A 00h Maximum data-access time from clock at CL = X – 2 N/A 00h N/A 00h POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 30h TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 serial presence detect (continued) Table 2. Serial Presence-Detect Data for the TM4SN64EPU (Continued) BYTE NO. DESCRIPTION OF FUNCTION 27 Minimum row precharge time 28 Minimum row-active to row-active delay 29 Minimum RAS-to-CAS delay 30 Minimum RAS pulse width 31 Density of each bank on module 32–61 SPD revision 63 Checksum for byte 0 – 62 72 TM4SN64EPU-12 DATA ITEM DATA tRP = 30 ns tRRD = 24 ns 1Eh tRP = 36 ns tRRD = 24 ns 24h tRCD = 30 ns tRAS = 60 ns 1Eh 1Eh 3Ch tRCD = 30 ns tRAS = 72 ns 16M Bytes 04h 16M Bytes 04h Rev. 1 01h Rev. 1 01h 8 08h 90 5Ah 97h 9700...00h 97h 9700...00h 18h Manufacturer’s JEDEC ID code per JEP – 106E Manufacturing location† TBD TBD Manufacturer’s part number† Die revision code† TBD TBD TBD TBD TBD TBD 93–94 PCB revision code† Manufacturing date† TBD TBD 95–98 Assembly serial number† TBD TBD 99–125 TBD TBD 126–127 Manufacturer specific data† Vendor specific data† TBD TBD 128–166 System integrator’s specific data‡ TBD TBD 167–255 Open 73–90 91 92 18h 48h Superset features (may be used in the future) 62 64 – 71 TM4SN64EPU-12A ITEM † TBD indicates values are determined at manufacturing time and are module dependent. ‡ These TBD values are determined and programmed by the customer (optional). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 device symbolization (TM2SN64EPU) TM2SN64EPU -SS Unbuffered Key Position 3.3-V Voltage Key Position YY MM T -SS = = = = Year Code Month Code Assembly Site Code Speed Code NOTE A: Location of symbolization may vary. 14 YYMMT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 – AUGUST 1997 MECHANICAL DATA BS (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE 5.255 (133,48) 5.245 (133,22) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places 0.039 (1,00) TYP 0.125 (3,18) (Note D) 0.054 (1,37) 0.046 (1,17) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.050 (1,27) 0.014 (0,35) MAX 0.118 (3,00) TYP 0.125 (3,18) 0.700 (17,78) TYP 0.118 (3,00) DIA 2 Places 1.130 (28,70) 1.120 (28,45) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double Sided DIMM Only) 4088181/A 06/97 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes De–panelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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