TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE SMMS433B – JANUARY 1993 – REVISED JUNE 1995 D D D D D D D D D Organization . . . 4 194 304 × 32 Single 5-V Power Supply (±10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets Utilizes Eight 16-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period 32 ms (2048 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Enhanced Page Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh D D D D D D Presence Detect Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE tRAC tAA tCAC CYCLE (MAX) (MAX) (MAX) (MIN) ’497BBK32-60 60 ns 30 ns 15 ns 110 ns ’497BBK32-70 70 ns 35 ns 18 ns 130 ns ’497BBK32-80 80 ns 40 ns 20 ns 150 ns Low Power Dissipation Operating Free-Air-Temperature Range 0°C to 70°C Gold-Tabbed Version Available:† TM497BBK32 Tin-Lead (Solder) Tabbed Version Available: TM497BBK32S description The TM497BBK32 is a 16M-byte dynamic random-access memory (DRAM) organized as four times 4 194 304 × 8 in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight TMS417400DJ, 4 194 304 × 4-bit DRAMs, each in 24/26-lead plastic small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. The TMS417400DJ is described in the TMS417400 data sheet. The TM497BBK32 SIMM is available in the single-sided BK leadless module for use with sockets. The TM497BBK32 SIMM features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation from 0°C to 70°C. operation The TM497BBK32 operates as eight TMS417400DJs connected as shown in the functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS-only or CBR ) cycle. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE SMMS433B – JANUARY 1993 – REVISED JUNE 1995 BK SINGLE-IN-LINE PACKAGE ( TOP VIEW ) 2 VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 NC RAS2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 NC NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 (SIDE VIEW ) PIN NOMENCLATURE A0 – A10 CAS0 – CAS3 DQ0 – DQ31 NC PD1 – PD4 RAS0, RAS2 VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) PD3 (69) PD4 (70) NC NC 70 ns VSS VSS NC 60 ns VSS NC VSS NC VSS NC 80 ns TM497BBK32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 NC TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE SMMS433B – JANUARY 1993 – REVISED JUNE 1995 Table 1. Connection Table DATA BLOCK RASx CASx DQ0 – DQ7 RAS0 CAS0 DQ8 – DQ15 RAS0 CAS1 DQ16 – DQ23 RAS2 CAS2 DQ24 – DQ31 RAS2 CAS3 single-in-line memory module and components PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM497BBK32: Nickel plate and gold plate over copper Contact area for TM497BBK32S: Nickel plate and tin-lead over copper POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 RAS2 CAS1 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 11 DQ0 – DQ3 11 DQ4 – DQ7 CAS3 CAS2 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 11 DQ8 – DQ11 11 DQ12 – DQ15 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 11 DQ16 – DQ19 11 DQ20 – DQ23 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 DQ24 – DQ27 4M×4 A0 – A10 RAS W CAS OE DQ1 – DQ4 DQ28 – DQ31 Template Release Date: 7–11–94 11 TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE A0 – A10 RAS0 W CAS0 SMMS433B – JANUARY 1993 – REVISED JUNE 1995 4 functional block diagram TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE SMMS433B – JANUARY 1993 – REVISED JUNE 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 5 UNIT VCC VIH Supply voltage 4.5 5.5 V High-level input voltage 2.4 6.5 V VIL TA Low-level input voltage (see Note 2) –1 0.8 V 0 70 °C Operating free-air temperature NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL High-level output voltage II Input current (leakage) IO ICC1 ICC2 Low-level output voltage TEST CONDITIONS‡ IOH = – 5 mA IOL = 4.2 mA ’497BBK32-60 MIN MAX 2.4 ’497BBK32-70 MIN MAX 2.4 ’497BBK32-80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC ± 80 ± 80 ± 80 µA Output current (leakage) VCC = 5.5 V, CAS high VO = 0 V to VCC, ± 10 ± 10 ± 10 µA Read- or write-cycle current (see Note 3) VCC = 5.5 V, Minimum cycle 880 800 720 mA 16 16 16 mA 8 8 8 mA Standby current VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 880 800 720 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, RAS low, 560 480 400 mA tPC = MIN, CAS cycling ‡ For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE SMMS433B – JANUARY 1993 – REVISED JUNE 1995 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) PARAMETER MIN MAX UNIT Ci(A) Input capacitance, address inputs 40 pF Ci(R) Input capacitance, RAS inputs 28 pF Ci(C) Input capacitance, CAS inputs 14 pF Ci(W) Input capacitance, write-enable input 56 pF 7 pF Co(DQ) Output capacitance on DQ pins NOTE 5: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature ’497BBK32-60 PARAMETER MIN MAX ’497BBK32-70 MIN MAX ’497BBK32-80 MIN MAX UNIT tAA tCAC Access time from column address 30 35 40 ns Access time from CAS low 15 18 20 ns tCPA tRAC Access time from column precharge 35 40 45 ns Access time from RAS low 60 70 80 ns tCLZ tOH CAS to output in low-impedance state 0 Output disable time from start of CAS high 3 tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven. 0 0 3 0 15 0 ns 3 18 0 ns 20 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature ’497BBK32-60 MIN tRC tPC Cycle time, random read or write (see Note 7) tRASP tRAS MAX ’497BBK32-70 MIN MAX ’497BBK32-80 MIN MAX 110 130 Cycle time, page-mode read or write (see Notes 7 and 8) 40 45 Pulse duration, page-mode, RAS low 60 100 000 70 100 000 80 100 000 ns Pulse duration, non-page-mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS tCP Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns Pulse duration, CAS high 10 10 10 ns tRP tWP Pulse duration, RAS high (precharge) 40 50 60 ns Pulse duration, W low 10 10 10 ns tASC tASR Setup time, column address before CAS low 0 0 0 ns Setup time, row address before RAS low 0 0 0 ns tDS tRCS Setup time, data before CAS low 0 0 0 ns Setup time, W high before CAS low 0 0 0 ns tCWL tRWL Setup time, W-low before CAS high 15 18 20 ns Setup time, W-low before RAS high 15 18 20 ns tWCS tWRP Setup time, W-low before CAS low Setup time, W-high before RAS low (CBR refresh only) POST OFFICE BOX 1443 ns 50 ns 0 0 0 ns 10 10 10 ns NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP. 6 150 UNIT • HOUSTON, TEXAS 77251–1443 TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE SMMS433B – JANUARY 1993 – REVISED JUNE 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature ’497BBK32-60 MIN MAX ’497BBK32-70 MIN MAX ’497BBK32-80 MIN MAX UNIT tCAH tRHCP Hold time, column address after CAS low 10 15 15 ns Hold time, RAS high from CAS precharge 35 40 45 ns tDH tRAH Hold time, data after CAS low 10 15 15 ns Hold time, row address after RAS low 10 10 10 ns tRCH tRRH Hold time, W high after CAS high (see Note 9) 0 0 0 ns Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH tWRH Hold time, W low after CAS low 10 15 15 ns Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tCHR tCRP Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns Delay time, CAS high to RAS low 5 5 5 ns tCSH tCSR Delay time, RAS low to CAS high 60 70 80 ns tRAD tRAL Delay time, RAS low to column address (see Note 10) 15 Delay time, column address to RAS high 30 35 40 tCAL tRCD Delay time, column address to CAS high 30 35 40 Delay time, RAS low to CAS low (see Note 10) 20 tRPC tRSH Delay time, RAS high to CAS low (CBR only) tREF tT Refresh time interval Delay time, CAS low to RAS low (CBR refresh only) 5 Delay time, CAS low to RAS high 5 30 45 15 20 52 15 20 ns 40 ns ns ns 60 ns 0 0 0 ns 15 18 20 ns 32 Transition time 5 35 3 30 32 3 30 3 32 ms 30 ns 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time. device symbolization TM497BBK32 -SS YY MM T -SS YYMMT = Year Code = Month Code = Assembly Site Code = Speed Code NOTE: The location of the part number may vary. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE SMMS433B – JANUARY 1993 – REVISED JUNE 1995 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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