CMLMICRO FX105AD4

FX105A
Tone Detector
D/105A/5 September 1999
1.0
Features
Provisional Issue
•
Operates in High Noise Conditions
•
Adjustable Bandwidth
•
≥ 36dB Signal Input Range
•
Adjustable Frequency
•
High Sensitivity
•
Wide Voltage Range (2.7V to 5.5V)
•
Low Power
•
Single and Multitone System
Applications
1.1
Brief Description
The FX105A is a monolithic CMOS tone operated switch, designed for tone decoding in single and
multitone signalling systems. The FX105A uses decoding techniques which allow a tone to be
recognised in the presence of high noise levels or strong adjacent signals. Detection centre frequency
and bandwidth can each be independently adjusted. The design is immune to high levels of harmonic
and sub-harmonic interference. Excellent noise immunity and constant bandwidth are maintained over
a wide range of input signal levels.
 1999 Consumer Microcircuits Limited
Tone Detector
FX105A
CONTENTS
Section
Page
1.0 Features ......................................................................................................1
1.1 Brief Description.........................................................................................1
1.2 Block Diagram ............................................................................................3
1.3 Signal List ...................................................................................................4
1.4 External Components.................................................................................5
1.5 General Description....................................................................................6
1.6 Application Notes .......................................................................................7
1.6.1 General ........................................................................................7
1.6.2 Method for Calculating External Component Values................7
1.6.3 Replacement for FX105.............................................................11
1.7 Performance Specification.......................................................................12
1.7.1 Electrical Performance..............................................................12
1.7.2 Packaging..................................................................................14
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1.2
FX105A
Block Diagram
Figure 1 Block Diagram
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1.3
FX105A
Signal List
Package
D4/P3
Signal
Description
Pin No.
Name
Type
1
INPUT AMP IN
I/P
AC couple to this input of the input buffer
amplifier.
2
INPUT AMP OUT
O/P
The input buffer amplifier output.
3
RW
I/P
The input to the Detect/Word filter.
4
RV
I/P
The input to the VCO loop filter.
5
C3A
O/P
Word filter capacitor pin A.
6
C3B
O/P
Word filter capacitor pin B.
7
C2A
O/P
VCO Loop filter capacitor pin A.
8
C2B
O/P
VCO Loop filter capacitor pin B.
9
DETECT OUT
O/P
Open drain CMOS output, active on detect.
Note that a load resistor to VSS is required.
10
VSS
Power
11
R2HI
I/P
Bandwidth control resistor pin A.
12
R2LO
I/P
Bandwidth control resistor pin B.
13
C1B
O/P
VCO capacitor B.
14
C1A
O/P
VCO capacitor A.
15
R1
I/P
VCO discharge resistor. When potentiometer
tuning is required, a series resistor is
recommended to prevent possible shorting to
ground.
16
VDD
Power
Notes: I/P =
O/P =
Ground.
Power supply.
Input
Output
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1.4
FX105A
External Components
C1A
C1B
C2A
C2B
C3A
C3B
C4
C5
C6
Note s:
See section 1.6
See section 1.6
See section 1.6
See section 1.6
See section 1.6
See section 1.6
See section 1.6
0.27µF ±20%
0.1µF
±20%
R1F
R1V
R2
RL
RV
RW
D1
See section 1.6
See section 1.6
See section 1.6
20kohm
±20%
See section 1.6
See section 1.6
IN914 or similar
1. For improved performance C4 may be chosen to provide 30° phase shift at the VCO
loop filter input.
2. For compatibility with the FX105P; capacitors (C1 .... C4) may be connected to VDD
instead of VSS.
3. For improved de-response time, a diode (D1) may be added.
4. Any value load resistance (RL) may be used, providing the maximum load current does
not exceed the value given in section 1.7.1
Figure 2 Recommended External Components
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1.5
FX105A
General Description
The input signal to the FX105A is ac coupled to the buffer amplifier input, which is internally biased at
50% of supply voltage. The signal appears at the output of the buffer amplifier as an ac voltage
superimposed on the dc bias level. The signal is then coupled via RV and RW to the voltage controlled
oscillator (VCO) and word sampling switches, which cyclically connect C2 and C3 into the circuit to
form four sample-and-hold RC circuit integrators. See Figure 3.
With no input signal level, each capacitor charges to the dc bias level so differential voltages are zero.
When an input signal is applied each capacitor receives an additional charge. This charge is
determined by the integrated average of the signal waveform during the time the capacitor is switched
into the circuit.
Figure 3 shows the operating sequence of the VCO sampling switches and their relationship to a
locked-on in-band signal. C2A and C2B should not receive any additional charge since they always
sample the input as it crosses the dc bias level. Should the signal not be locked to the VCO, a
positive or negative charge voltage will appear on C2A or C2B. This voltage, when differentially
amplified, is applied to the VCO as an error correcting signal to enable the VCO to “lock.”
Figure 3 also shows the operating sequence of the “Word” sampling switches and their relationship to
a locked-on in-band signal. As the figure shows, the charge applied to C3A should always be positive,
and the charge applied to C3B should always be negative (with respect to the common bias level).
These capacitor potentials are differentially amplified and applied to a dc comparator, which switches
at a pre-determined threshold voltage VTH (known as the word filter sensitivity). The comparator
output is a logic signal used to control a counter. This counter switches the FX105A output ON when
the comparator output is maintained in the “Word present” state for a minimum number of consecutive
signal samples. The activated output switch reduces the comparator threshold by 50%, introducing
threshold hysteresis. Output chatter with marginal input signal amplitudes is thereby minimised.
Figure 3 Sampling Clocks of Commutating Filters
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FX105A
1.6
Application Notes
1.6.1
General
The external components shown in Figure 2 are used to adjust the various performance parameters of
the FX105A. The signal-to-noise performance, response time and signal bandwidth are all interrelated
factors which should be optimised to meet the requirements of the application.
By selecting component values in accordance with the following formulae, optimum circuit
performance is obtained for any given application.
First define the following application parameters:
(a) The input frequency to be detected (f0). The free running frequency of the VCO is set to 6 times
this frequency by observing the output across C1 or R1. (The frequency observed at pin 15 (R1) is
6 x f0 and the frequency observed at pins 13 or 14 (C1A or C1B) is 3 x f0).
(b) The FX105A Minimu mUsable Bandwidth (MUBW). This is obtained by taking into account the
worst case tolerances ∆(f0) of the input frequency and the variations in the FX105A VCO
frequency due to supply voltage ∆V( DD) and temperature ∆( TEMP) variation of the FX105A and its
supporting components.
(c) The maximum permissible FX105A response time.
(d) The minimum input signal amplitude. (This must be larger than the threshold voltage, VTH).
(e) The maximum input signal amplitude.
Using this information the appropriate component values can be calculated, and the signal-to-noise
performance can be read from a chart. Do not add large safety margins for response time and
minimum signal amplitude: reasonable margins are already included in the formulae. Excessive
margins may result in reduced noise immunity.
1.6.2
Method for Calculating External Component Values
The example on the following pages demonstrates the calculation of component values for any given
application. For the purpose of this example, the values below are used:
(a)
(b)
(c)
(d)
(e)
f0 = 2800Hz
∆TEMP = 100°C, ∆VDD = 1V, ∆f0 = 0.5%
Maximum allowe dresponse time TON = 50msec
Minimum input signal amplitude VIN MIN = 200mVrms
Maximum input signal amplitude VIN MAX = 400mVrms
1.6.2.1 Calculate R1C1 (C1A = C1B)
The components R1, C1A and C1B set the free running frequency of the VCO and therefore the f0 of
the FX105A. As shown below, the frequency of 2800Hz corresponds to a capacitor value of 220pF
and a resistor value of 385 Ωk. This resistance can be achieved with a 330 Ωkfixed resistor and a
100kΩ potentiometer. R1 should lie in the range 100 Ωk to 680 kΩ.
R1C1A = 1/ [2Kf0] = 1/ (2 x 2.1 x 2800 ) = 85µsec
where K is a constan t= 2.1 ± 5%.
Note that the values of C1A and C1B need to include the stray capacitance
attributable to the package style and printed circuit board layout. A typical
value of 6.6pF per pin should be assumed.
If C1A = C1B = 233.2pF, then R1 » 364kohm
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FX105A
1.6.2.2 Calculate Minimum Usable Bandwidth (%)
Minimum Usable Bandwidth (MUBW) is the TOTAL (%) bandwidth required for the following:
(a)
(b)
(c)
Input signal frequency tolerance (∆f0)
FX105A VCO temperature coefficient (TC = −100ppm/ºC)
FX105A VCO supply voltage coefficient (VC = 2330ppm/V)
Add (a), (b) and (c) and express as TOTAL (%) bandwidth, not as a ± (%) value.
MUBW = Df0 + |Tc|DTEMP + VcDVDD
MUBW = 0.5 + 0.01 x 100 + 0.233 x 1 » 2%
1.6.2.3 Calculate the Recommended Operating Bandwidth
Note again that this is the TOTAL (%) bandwidth:
BW = ½ [10 + MUBW] = ½ (10 + 2) = 6%
1.6.2.4 Select R2 for Operating BW
R2 = 4.8 BW/ [10.35 -BW] = 4.8 x 6/ (10.35 -6) » 6.8kW
The exact bandwidth given by any value of R2 will vary slightly. In applications where an exact
bandwidth is required, R2 should be a variable resistor to permit adjustment.
1.6.2.5 Calculate RVC2A (C2A = C2B) Use nearest preferred values
RVC2A » 100/ [3 f0 BW] » 100/ (3 x 2800 x 6) » 2msec
Therefore
RV » 200kW for C2A = C2B = 10nF
1.6.2.6 Define the Maximum Allowed Response Time
The maximum response time (TON) is the sum of the VCO lock time (TLOCK) and the Word integration
time (TWORD). The FX105A’s TON must not exceed the maximum time allowed for the application, but
a value lying near the maximum gives the best S/N performance.
(a)
Calculate TLOCK
TLOCK = 150/ [f0 BW] = 150/ (2800 x 6) » 9msec
Note: TLOCK may vary from near zero to the value given, causing corresponding variations in actual
TON.
(b)
Calculate Maximum Allowable TWORD
TWORD = TONMAX -TLOCK = 50 - 9 = 41msec
Note: Since the maximum allowed response time (TON) is 50msec, a maximum Word integration time
of 41msec is available.
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FX105A
1.6.2.7 Calculate RWC3A (C3A = C3B) Use nearest preferred values.
RWC3A » TWORD/ [-3In (1 - VTH/ VINMIN ) ]
where VTH is the word filter
sensitivity, see Section 1.7.1
A signal amplitude of 200mV and a resistor value RW of 465kΩ with a 220nF capacitor for C3A and
C3B will yield a TWORD time of 41msec. This in turn yields a response time of 9msec + 41msec =
50msec.
1.6.2.8 Calculate the Maximum De-response Time
TOFF » -3 RWC3A In (VTH/ VINMAX )
where VTH is the word filter
sensitivity, see Section 1.7.1
For improved de-response time, a diode (1N914 or similar) can be placed between pins 5 and 6, as
shown in Figure 2. The formula and figure below show the approximate time the FX105A will take to
turn off after an in-band signal has been removed. The effect of this diode is to greatly reduce the
turn-off time with signal input amplitudes greater than 300mVrms. Figure 4 is for VDD = 5V; for lower
VDD then KDT increases.
TOFF » KDTRWC3A
So for a maximum signal amplitude of 400mV, a resistor value RW of 465kΩ with a 220nF capacitor
for C3A and C3B and a diode between pins 5 and 6, a de-response time of ≈ 363msec is obtained.
Figure 4 KDT Factor for TOFF vs. Signal Input Amplitude
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FX105A
1.6.2.9 Calculate Signal to Noise Performance
Worst-case S/N calculations depend on calculation of a value “M” using the formula shown below:
M = RWC3A/ [3 RVC2A]
substituting our example values,
M = 465 x 0.22 / (3 x 200 x 0.01) = 17.05
By substituting this value for M in Figure 5 the minimum required S/N of an in band tone with respect
to an adjacent interfering tone can be found. This has to be increased if the required tone amplitude is
close to the word filter sensitivity VTH.
Figure 5 S/N vs. BW Separation
The following formula expresses the reduction in noise immunity as the input signal approaches the
word filter sensitivity VTH.
required S/N = 20 log (VIN/ [VIN - VTH] ) + S/NFigure 5
If this S/N is better than required for the application, RWC3A can be reduced, or the operating
bandwidth can be increased to obtain a faster tone detection time.
If the S/N performance is not adequate, the operating bandwidth can be reduced toward the MUBW,
or RWC3A can be increased to improve S/N performance at the expense of a slower response time.
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FX105A
1.6.2.10 Calculation of PLL Filter Phase Shift
Capacitor C4 is used to phase shift the input to the VCO commutating filter by 30°, thus shifting the
sampling clocks by the same amount. This enables the "Word" sampling filter to sample and integrate
at the maxima and minima of the input tone.
C4 = tan (30°) / [2p f0 RV] » 0.092 / [f0 RV] » 164pF
1.6.3
Replacement for FX105
Figure 6 depicts the circuit changes required to replace a FX105 with a FX105A device. A 5V zener
diode and a resistor can be used to generate a 5V supply voltage from an existing 12V supply. If the
Detect Output needs to pull up beyond the 5V supply, a transistor amplifier following the output can
be used.
Figure 6 Circuit changes for 12V to 5V conversion
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1.7
Performance Specification
1.7.1
Electrical Performance
FX105A
Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
Supply (VDD - VSS)
Voltage on any pin to VSS
Current into or out of VDD and VSS pins
Current into or out of any other pin
Maximum Output Switch Load Current
P3/D4 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
Units
-0.3
-0.3
-30
-20
7.0
VDD + 0.3
+30
+20
+10
V
V
mA
mA
mA
Min.
Max.
Units
-55
-40
800
13
+125
+85
mW
mW/°C
°C
°C
Min.
Max.
Units
2.7
-40
5.5
+85
V
°C
Operating Limits
Correct operation of the device outside these limits is not implied.
Notes
Supply (VDD - VSS)
Operating Temperature
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FX105A
Operating Characteristics
For the following conditions unless otherwise specified:
VDD = 3.0V to 5.0V, Tamb = -40°C to +85°C, Load resistance on decoder output pin = 20kΩ
Static Parameters
IDD
Amplifier Input Impedance
Digital Output Impedance
Analogue Output Impedance
Dynamic Parameters
Input Signal
Amplitude
Frequency
Response Threshold
Deresponse Threshold
BW Range
Signal to Noise Performance
(f0/2) Subharmonic Rejection
(5 f0) Harmonic Rejection
VCO
Frequency
Frequency Stability (TC)
Frequency Stability (VC)
Notes
Min.
Typ.
Max.
Units
2
-
0.9
200
500
1000
3.0
-
mA
kΩ
Ω
Ω
2
40
5.6
-6
-
30
10
-9
30
20
1.0
20,000
10
-
Vrms
Hz
mVrms
mVrms
%f0
dB
dB
dB
240
-
-100
2330
120,000
-
Hz
ppm/°C
ppm/V
-
60
1.0
0
-
dB
MHz
dB
-
25.0
-
mVrms
1,2
1,2
4
3
Amplifier
Open Loop Gain
Gain Bandwidth Product
Closed Loop Gain
Word Commutating Filter
Sensitivity (VTH)
Notes:
2
1. With diode (D1) fitted.
2. For VDD = 5V. Multiply by VDD/5V for other supply values.
3. Observing pins 13, 14 or 15 (D4/P3 package) will cause a frequency shift due to additional
loading. If tuning the centre frequency by observing the VCO, design in a buffer amplifier
between pin 15 and the probe/calibration point and tune with no input signal. Otherwise, tune
by observing the detect output band edges while sweeping the input signal. The frequency at
pin 15 is 6xfo, while at pins 13 and 14 the frequency is 3xfo.
4. Adjust according to equation for R2 in Section 1.6.2.
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1.7.2
FX105A
Packaging
Figure 7 - SOIC Mechanical Outline: Order as part no. FX105AD4
Figure 8 - DIL Mechanical Outline: Order as part no. FX105AP3
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FX105A
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from
electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent
licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML
has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification.
Specific testing of all circuit parameters is not necessarily performed.
Oval Park - LANGFORD
MALDON - ESSEX
CM9 6WG - ENGLAND
Telephone: +44 (0)1621 875500
Telefax:
+44 (0)1621 875600
e-mail:
sales@cmlmicro.co.uk
http://www.cmlmicro.co.uk
CML Microcircuits
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companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
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Tel: +44 (0)1621 875500
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Tel: +1 336 744 5050,
0800 638 5577
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D/CML (D)/1 February 2002