TLC320AD75C Data Manual 20-Bit Sigma-Delta Stereo ADA Circuit SLAS144 February 1997 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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Copyright 1997, Texas Instruments Incorporated Contents Section Title Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1–1 1–2 1–3 1–4 1–4 1–5 2 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 2.1 Power-Down and Reset Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 2.1.1 ADC Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 2.1.2 Reset Function for ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 2.1.3 Reset/ Initialization for DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 2.2 Differential Input to the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 2.3 Sigma-Delta Modulator for the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 2.4 Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 2.5 High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 2.6 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 2.6.1 Master-Clock Circuit for ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 2.6.2 Master-Clock Circuit for DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 2.7 Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 2.8 Master Mode for ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 2.9 Slave Mode for ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 2.10 Digital-Audio-Data Interface for DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 2.11 Serial-Control Interface for DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 2.11.1 Serial-Control-Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 2.12 DAC De-emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 2.13 Digital Filter Mute for DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 2.14 DAC Digital Attenuation/Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 2.15 Sigma-Delta DAC Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 2.16 DAC Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 2.17 DAC PWM Output (L2 – L1 and R2 – R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 2.18 DAC Control Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10 2.19 Auto-Resynchronization Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Electrical Characteristics, AVDD = LVDD = VDD1 = VDD2 = PVDDL = PVDDR = XVDD = 5 V, V35A = V35D = 3.3 V, TA = 25°C . . . . . . . . . . . . . . . . . . 3.3.1 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 ADC Performance, fs = 44.1 kHz, Bandwidth = 22.05 kHz . . . . . . . . . . 3.3.4 DAC Performance, 20-Bit Mode, fs = 44.1 kHz, Bandwidth = 22.05 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 3–1 3–1 3–2 3–2 3–2 3–3 3–3 iii Contents (Continued) Section 3.4 3.5 Title Page 3.3.5 ADC Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.6 ADC High-Pass Filter, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.7 ADC Decimation Filter, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.8 DAC Filter Characteristics, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.9 Power Supply Current, fs = 44.1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 3–3 3–3 3–4 3–4 3–4 3–5 4 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 5.1 Circuit And Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7 5.2 PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7 Appendix A Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 iv List of Illustrations Figure Title Page Figure 2–1 ADC Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2–2 DAC-Reset Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2–3 Differential Analog-Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2–4 ADC Audio-Data Serial Timing – Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2–5 ADC Audio-Data Serial Timing – Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2–6 Audio Data Serial Timing – ADC and All DAC Modes . . . . . . . . . . . . . . . . . . . . . Figure 2–7 Control-Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2–8 De-emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2–9 Digital Attenuation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2–10 DAC Digital Attenuation Operation With Tapered Gain Response . . . . . . . . . Figure 2–11 Oversampling Noise Power With and Without Noise Shaping . . . . . . . . . . . . . Figure 4–1 ADC Audio-Data Serial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4–2 DAC Control-Data Serial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5–1 TLC320AD75C Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5–2 A-Weighted Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5–3 Land Pattern for PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 2–2 2–3 2–5 2–5 2–6 2–7 2–7 2–8 2–8 2–9 4–1 4–1 5–4 5–6 5–7 List of Tables Table Table 2–1 Table 2–2 Table 2–3 Table 2–4 Table 5–1 Table 5–2 Title Page ADC Master Clock to Sample-Rate Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 DAC Master Clock to Sample-Rate Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Attenuation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10 System Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11 TLC320AD75C Schematic Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 A-Weighted Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6 v vi 1 Introduction The TLC320AD75C is a high-performance stereo 20-bit analog-to-digital and digital-to-analog converter (ADA) using sigma-delta technology to provide four concurrent 20-bit resolution conversions from both analog-to-digital (A/D) and digital-to-analog (D/A) signal paths. Additional functions provided are digital attenuation, digital de-emphasis filtering, soft mute, and on-chip timing and control. Control words from a host controller or processor are used to implement these functions. The TLC320AD75C is characterized for operation from 0°C to 70°C. 1.1 Features • Single 5-V (Analog/Digital) Power Level and 3.3-V to 5-V Digital Interface Level • Sample Rates up to 48 kHz • 20-Bit Resolution Conversions • Signal-to-Noise Ratio (EIAJ) of 100 dB for the ADC • Total Harmonic Distortion + Noise of 0.0017% for the ADC • Signal-to-Noise Ratio (EIAJ) of 104 dB for the DAC • Total Harmonic Distortion + Noise of 0.0013% for the DAC • Internal Voltage Reference (Vref) • Serial Port Interface • Differential Architecture • DAC Provides PWM Output • Digital De-emphasis Filtering for 32-, 44.1-, and 48-kHz Sample Rates for the DAC • Digital Attenuation/Soft Mute Function for the DAC • Small 56-Pin DL Plastic Small-Outline Package 1–1 1.2 Functional Block Diagram 3 V or 5 V V35A Stereo ADC INLP Sigma-Delta Modulator INLM Decimation Filter High-Pass Filter ADOUT SCLKA VREF REFO REFI INRP Sigma-Delta Modulator INRM Decimation Filter High-Pass Filter Serial Interface LRCKA MCLKI Stereo DAC 256CK L1 L2 PWM Digital Modulator Interpolation Filter 512CK Digital Attenuator XOUT XIN De-emphasis Filter Serial Interface De-emphasis Filter LRCKD SCLKD R1 R2 PWM Digital Modulator Interpolation Filter Digital Attenuator DDATA CPU Interface CDIN SHIFT LATCH V35D 3 V or 5 V 1–2 1.3 System Block Diagram TLC320AD75C INRP Right Audio Input Left Audio Input Single to Differential Single to Differential REFI REFO ADC INRM Serial Port LRCKA SCLKA ADOUT INLP M_S MCLKI AVSS ADC Data Out VSS1 INRM 256CK XIN XVSS XOUT XVSS 512CK Right Audio Output Analog Low-Pass Filter R1 Left Audio Output Analog Low-Pass Filter L1 R2 L2 DAC Serial Ports LRCKD SCLKD DDATA CDIN SHIFT LATCH SCLK LRCK DAC Data In DAC Control Data Microcontroller/ Microprocessor 1–3 1.4 Terminal Assignments DL PACKAGE (TOP VIEW) INRP INRM REFI AVDD AVSS APD NU NU TEST1 LRCKA SCLKA ADOUT V35A VSS1B MCLKI DPD VSS2B INIT CDIN SHIFT LATCH 256CK V35D VSS2 512CK SCLKD DDATA LRCKD 1.5 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 INLP INLM REFO LVSS LVDD AVSSB NU NU VSS1B M_S TEST2 VSS1 VDD1 VDD1 VDD2 L1 PVDDL L2 PVSSL XVSS XIN XOUT XVDD PVSSR R2 PVDDR R1 VDD2 Ordering Information PACKAGE 1–4 TA SMALL OUTLINE (DL) 0°C to 70°C TLC320AD75CDL 1.6 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION ADOUT 12 O 20-bit ADC data output. ADOUT provides the MSB first in 2’s-complement data format and is left justified within the 32-bit packet for each channel. The output level is 3.3 V for V35A = 3.3 V (see Figure 2–6). APD 6 I Analog power-down mode. APD disables the ADC analog modulators. The ADC single-bit modulator outputs become invalid, rendering the outputs of the digital filters invalid. When APD is pulled high, normal operation of the device is resumed. AVDD 4 Analog power supply voltage for ADC modulators AVSS 5 Analog ground for ADC modulators AVSSB 51 Analog substrate ground for ADC modulators CDIN 19 I Attenuation mode and system control mode input for DAC. CDIN is a 24-bit stream with a 16-bit data word followed by an 8-bit device address. This stream is configured with the MSB first (see Section 2.15, Sigma-Delta DAC Modulator). DDATA 27 I DAC input data in 2’s-complement data format. MSB/LSB first and 20-bit/16-bit input formats are selectable by using the DAC control registers (see Section 2.15, Sigma-Delta DAC Modulator). DPD 16 I Digital power-down mode. The DPD shuts down the ADC digital decimation filters and clock generators, and provides a digital reset. All digital outputs of the ADC function, are brought to unasserted states. When DPD is pulled high, normal operation of the device is resumed. When in slave mode operation, after the rising edge of DPD, the ADC system is synchronized. INIT 18 I Initial DAC reset signal. The DAC device is activated on the rising edge of INIT. When INIT is brought low, the DAC is reset when LRCKD is present. INLM 55 I Inverting input for the left channel analog modulator INLP 56 I Noninverting input for the left channel analog modulator INRM 2 I Inverting input for the right channel analog modulator INRP 1 I Noninverting input for the right channel analog modulator LATCH 21 I Latch signal for the DAC control serial data. Attenuation/system-control data loads into the internal registers when LATCH is brought low. LRCKA 10 I/O Left/right clock for ADC. LRCKA signifies whether the serial data is associated with the left channel ADC (when LRCKA is high) or the right channel ADC (when LRCKA is low). LRCKA is normally connected to LRCKD. LRCKA is output when configured in master mode. LRCKD 28 I Left/right clock for DAC. LRCKD signifies whether the serial data is associated with the left channel DAC (when LRCKD is high) or the right channel DAC (when LRCKD is low). LRCKD is normally connected to LRCKA. LVDD 52 Digital power supply for analog modulators. LVDD is normally connected to AVDD through a 50-Ω resistor. LVSS 53 Digital ground for analog modulators. LVSS is normally connected to AVSS through a 50-Ω resistor. L1 41 O Left channel DAC PWM output 1 L2 39 O Left channel DAC PWM output 2 MCLKI 15 I Master clock input for ADC. MCLKI operates at 256 times the sample rate (i.e. 256 times LRCKA). MCLKI is normally connected to 256CK through a 50-Ω resistor. 1–5 Terminal Functions (Continued) TERMINAL ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ NAME M_S NU I/O DESCRIPTION 47 I Master/slave selection. The ADC serial port is configured as master mode when M_S is pulled high. M_S is connected to VSS1 for slave mode. 7, 8, 49, 50 – Not used NO. PVDDL PVDDR 40 PWM power supply for left channel DAC 31 PWM power supply for right channel DAC PVSSL PVSSR 38 PWM ground for left channel DAC 33 PWM ground for right channel DAC REFI 3 I Input reference voltage. REFI provides reference voltage for the ADC modulator (normally connected to REFO). REFO 54 O Internal ADC reference voltage (normally connected to REFI). R1 30 O Right channel DAC PWM output 1 R2 32 O Right channel DAC PWM output 2 SCLKA 11 I/O Shift clock for the ADC. The shift clock clocks serial data out of the ADC, and operates at 64 times the sample rate (i.e. 64 times LRCKA). SCLKA is normally connected to SCLKD. SCLKA is output when configured in master mode. SCLKD 26 I Shift clock for the DAC. The shift clock clocks serial audio data into the DAC, and operates at 64 times the sample rate (i.e. 64 times LRCKD). SCLKD is normally connected to SCLKA. SHIFT 20 I Shift data. SHIFT clocks the control data (CDIN) into the internal control registers for the DAC. TEST1 9 I Factory test terminal1. TEST1 should be connected to VSS1 for normal operation. TEST2 46 I Factory test terminal2. TEST2 should be connected to VSS1 for normal operation. XIN 36 I Oscillator input terminal for 512 times the DAC sample rate. XIN derives all of the key logic signals of the DAC device. (XIN can also be driven by an external oscillator.) XOUT 35 O Oscillator output terminal for 512 times the DAC sample rate VDD1 VDD2 43, 44 Digital power supply for ADC 29, 42 Digital power supply voltage for DAC VSS1 VSS1B 45 Digital ground for ADC digital flters 14, 48 Digital substrate ground for ADC VSS2 VSS2B 24 Digital ground for the DAC 17 Digital sustrate ground for DAC V35A V35D 13 Digital power supply for ADC interface logic. V35A is connected to 3 V or 5 V. 23 Digital power supply for DAC interface logic. V35D is connected to 3 V or 5 V. XVDD XVSS 34 Oscillator power-supply voltage for DAC 37 Oscillator circuit ground for DAC 256CK 22 O 256 times sample rate clock output. 256CK is normally connected to MCLKI through a 50-Ω resistor. 256CK is the XIN frequency divided by two. 512CK 25 O 512 times sample rate clock output (output level is 3.3 V for V35D = 3.3 V). 512CK is a buffered version of XIN (master clock input). 1–6 2 Detailed Description The sigma-delta ADC converter consists of an oversampling analog modulator and digital decimation filter. The sigma-delta DAC incorporates an interpolation finite impulse-response (FIR) filter and oversampled modulator. The pulse-width-modulation (PWM) digital output feeds an external low-pass filter to recover the analog audio signal. Two control registers configure the DAC. The attenuation register controls the attenuation range, de-emphasis enable, and mute selection. The system register controls the data format and de-emphasis filter-sample rate. 2.1 2.1.1 Power-Down and Reset Functions ADC Power Down The power-down state is comprised of a separate digital and analog power down for the ADC. The power consumption of each is detailed in the electrical characteristics section. The digital power-down mode shuts down the digital filters and clock generators. When the digital power-down terminal is pulled high, normal operation of the device is initiated. In slave mode, the conversion process must synchronize to an input on LRCKA as well as SCLKA. Therefore, the conversion process is not initiated until the first rising edges of both SCLKA and LRCKA are detected after DPD is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed LRCKA rate after the initial synchronization. After DPD is brought high, the output of the digital filters remains invalid for 26 LRCKA cycles which consists of group delays of the decimation and high-pass filter. The analog power-down mode disables the analog modulators. The single-bit modulator outputs become invalid, which renders the outputs of the digital filters invalid. When the APD terminal is brought high, the modulators are brought back online; however, the settling time of the modulator stage is normally 100 ms. 2.1.2 Reset Function for ADC The conversion process is not initiated until the first rising edges of both SCLKA and LRCKA are detected after DPD is pulled high. This synchronizes the conversion cycle; all conversions are performed at a fixed LRCKA rate after the initial synchronization. 2–1 During general operation of the ADC, APD is recommended to be pulled high (APD is not needed for a reset). When using the analog power-down mode (APD low), the following timing procedure is required to start all of the ADC since the analog modulator portion which includes the external portion needs to be settled after APD is high. APD > 100 msec DPD LRCKA > 26 fs ADOUT Figure 2–1. ADC Start-Up Timing 2.1.3 Reset/ Initialization for DAC When INIT is brought low, an internal reset signal becomes active approximately 120 cycles of the sampling frequency (fs) after the falling edge of INIT. Under this condition, all internal circuits are initialized and the PWM output is held at zero data (50% duty cycle). When INIT is brought high, the internal reset signal goes inactive for a maximum of five LRCKD periods after the rising edge of INIT. At this point, internal clocks are synchronous with LRCKD and the PWM output is valid (see Figure 2–2). LRCKD must be applied for proper initialization. INIT 120 Cycles of fs Internal Reset LRCKD Figure 2–2. DAC-Reset Timing Relationships 2–2 5 periods max 2.2 Differential Input to the ADC The input to the ADC is differential in order to provide common-mode noise rejection and increase the input dynamic range. Figure 2–3 shows the analog input signals used in a differential configuration to achieve a 6.4 VI(PP) differential swing with a 3.2 VI(PP) swing per input line. TLC320AD75C 4.1 V INLP, INRP 2.5 V 0.9 V 4.1 V INLM, INRM 2.5 V 0.9 V Figure 2–3. Differential Analog-Input Configuration 2.3 Sigma-Delta Modulator for the ADC The modulator is a fourth-order sigma-delta modulator with 64 times oversampling. The ADC provides high-resolution, low-noise performance from a 1-bit converter using oversampling techniques. 2.4 Decimation Filter The decimation filter after the sigma-delta ADC modulator reduces the digital data rate to the sampling rate of LRCKA. This is accomplished by decimating with a ratio of 1:64. 2.5 High-Pass Filter The high-pass filter removes dc from the input of the ADC. The output of this filter is a 2’s-complement data word of 20 bits serially clocked out. If the input value exceeds the full range of the converter, the output of the high-pass filter is held at the appropriate extreme until the input returns to the analog input range of the TLC320AD75C. 2–3 2.6 2.6.1 Master Clock Master-Clock Circuit for ADC The master-clock circuit generates and distributes necessary clocks throughout the device. MCLKI is the external master-clock input. The sample rate of the data paths is set as LRCKA = MCLKI/256. With a fixed oversampling ratio of 64 × fs, the effect of changing MCLKI is shown in Table 2–1. Table 2–1. ADC Master Clock to Sample-Rate Comparison MCLKI (MHz) SCLKA (MHz) LRCKA (kHz) 12.2880 3.0720 48 11.2896 2.8224 44.1 8.1920 2.0480 32 When the TLC320AD75C is in master mode (M_S is pulled high) SCLKA is derived from MCLKI in order to provide clocking of the serial communications between the sigma-delta audio ADC and a digital signal processor (DSP) or control logic. This is equivalent to a clock running at 64 × LRCKA. When the TLC320AD75C is in slave mode (M_S is connected to VSS1), SCLKA is externally derived. For SCLKA use of a clock running at 64 times LRCKA is recommended. 2.6.2 Master-Clock Circuit for DAC The timing and control circuit generates and distributes necessary clocks throughout the TLC320AD75C. XIN is the oscillator input terminal or can receive an external master-clock input. The sample rate of the data paths is set as LRCKD = XIN/512. With a fixed oversampling ratio of 32× and each PWM output value requiring 16 XIN cycles, the effect of changing XIN is shown in Table 2–2. Table 2–2. DAC Master Clock to Sample-Rate Comparison XIN (MHz) 256CK (MHz) LRCKD (kHz) 24.5760 12.2880 48.0 22.5792 11.2896 44.1 16.3840 8.1920 32.0 The DAC can be operated at any conversion rate between 48 kHz and 32 kHz by choosing the appropriate master-clock frequency. Some of the functions of the converter, such as the deemphasis filter, operate only at the frequencies shown in Table 2–2. 2–4 2.7 Test TEST1 and TEST2 are reserved for factory test and are tied to digital ground (VSS1). 2.8 Master Mode for ADC Configured as the master device (M_S is connected to VDD1), the TLC320AD75C generates LRCKA and SCLKA from MCLKI. These signals are provided for synchronizing the serial port of a digital signal processor (DSP) or other control devices. LRCKA is generated internally from MCLKI. The frequency of LRCKA is fixed at the sampling frequency, fs (MCLKI/256). During the high period of LRCKA, the left channel data is serially shifted to the output; during the low period, the right channel data is shifted to the output (ADOUT). The conversion cycle is synchronized with the rising edge of LRCKA. Figure 2–4 (master mode) shows 20-bit data, MSB first, ADOUT data shifted out of the TLC320AD75 during the first 20 SCLKA periods of the 32 SCLKA periods for both left and right channel data. 20-BIT MASTER MODE Output SCLKA MSB ADOUT Output 19 18 LRCKA Output Left MSB LSB ... 1 0 19 MSB LSB 18 ... 1 0 19 18 64 SCLKs Right Figure 2–4. ADC Audio-Data Serial Timing – Master Mode 2.9 Slave Mode for ADC Configured as a slave device (M_S is connected to VSS1), the TLC320AD75C receives LRCKA and SCLKA as inputs. The conversion cycle is synchronized to the rising edge of LRCKA, and the data is synchronized to the falling edge of SCLKA. SCLKA must meet the setup requirements specified in the recommended operating conditions section. Synchronization of the slave mode is accomplished with the rising edge of DPD. The slave mode is shown in Figure 2–5. SCLKA and LRCKA are externally generated and sourced. The first rising edges of SCLKA and LRCKA after the rising edge of DPD initiate the conversion cycle (see Section 2.8, Master Mode for ADC for signal functions). Figure 2–5 (slave mode) shows 20-bit data, MSB first, and ADOUT data shifted out of the TLC320AD75 during the first 20 SCLKA periods of the 32 SCLKA periods for both left and right channel data. 20-BIT SLAVE MODE input SCLKA MSB ADOUT output LRCKA input 19 LSB 18 ... 1 0 Left MSB 19 18 64 SCLKs Right LSB ... 1 0 Figure 2–5. ADC Audio-Data Serial Timing – Slave Mode 2.10 Digital-Audio Data Interface for DAC The conversion cycle is synchronized to the rising edge of LRCKD, and the data must meet the setup requirements specified in the timing requirements table. The input data is 16 or 20 bits with the MSB or LSB first as selected in the system register. The recommended SCLKD frequency is 64 × fs. Figure 2–6 illustrates the input timing. 2–5 2–6 LEFT LRCKA and LRCKD RIGHT 1 32 64 SCLKA and SCLKD MSB LSB MSB LSB ADOUT MSB LSB MSB LSB DDOUT (20-Bit, MSB First) MSB LSB MSB LSB DDOUT (16-Bit, MSB First) LSB MSB LSB MSB DDOUT (20-Bit, LSB First) LSB MSB DDOUT (16-Bit, LSB First) Figure 2–6. Audio-Data Serial Timing – ADC and All DAC Modes LSB MSB 2.11 Serial-Control Interface for DAC The TLC320AD75C uses the most-significant-bit-first format. Therefore, for a 16-bit data word, D16 is the most significant bit (MSB) and D1 is the least significant bit (LSB). 2.11.1 Serial-Control-Data Input The 16-bit control-data input implements the device-control functions. The TLC320AD75C has two registers for this data: the system register and the attenuation register. The system register contains most of the system configuration information, and the attenuation register controls the audio output level and deemphasis. Figure 2–7 illustrates the input timing for CDIN, SHIFT, and LATCH. The data loads internally during the low level of LATCH. The shift clock must be high or low for the LATCH setup time before LATCH goes low. As shown in Figure 2–7, CDIN is a 24-bit data stream consisting of 16 bits of control data D16 through D1 followed by 8 bits of device, address A8 through A1. When the TLC320AD75C receives address >E7h, the control data is latched into the device by LATCH. For all other addresses, the data is ignored. Control Data CDIN D16 D15 D14 D13 D12 D11 D10 D9 D8 Control-Device Address D7 D6 D5 D4 D3 D2 D1 A8 A7 A6 A5 A4 A3 A2 A1 SHIFT LATCH Figure 2–7. Control-Data Input Timing 2.12 DAC De-emphasis Filter Three sets of de-emphasis-filter coefficients support the three sampling rates (fs): 32 kHz, 44.1 kHz, and 48 kHz. Internal system-register values select the filter coefficients. The internal register values enable or disable the filter. Figure 2–8 illustrates the de-emphasis filtering characteristics. Many audio sources have been recorded with pre-emphasis characteristics that are the inverse of the characteristics shown in Figure 2–8. This device provides reconstruction of the original frequency response. Response – dB 10 0 De-emphasis – 10 3.18 (50 µs) 10.6 (15 µs) f – Frequency – kHz Figure 2–8. De-emphasis Filter Characteristics 2.13 Digital Filter Mute for DAC When the mute bit in the attenuation register is set to 1, the DAC digital filter mute is active. The output of the digital filter is 0 + dc offset. Operation of the digital filter is normal during mute. 2–7 2.14 DAC Digital Attenuation/Soft Mute A value selected in the internal attenuation register determines the attenuation of the digital-audio data input. The attenuation value is 12 bits long with a valid range of hex values from 400h to 000h. A data value of 001h corresponds to an attenuation value of – 60 dB and a data value of 400h corresponds to 0 dB. The attenuation function is nonlinear. Figure 2–9 illustrates the attenuation function in dB. The default attenuation value is 400h (refer to the attenuator mode register for more detailed description). Attenuation + 20 log ǒ Ǔ attenuation data 1024 0 Attenuation – dB – 10 – 20 – 30 – 40 – 50 – 60 1024 896 768 640 512 384 256 128 0 Attenuation Data (decimal values) Figure 2–9. Digital Attenuation Characteristics The attenuation operation of the DAC has a tapered gain response. It takes time T = 1024/fs(sec) to reach the actual 000H data output after an ATT = 000H data transfer from 400H data as shown in Figure 2–10. 400H 200H Output Level (ATT) 000H T (Soft Mute) ATT = 000H Transfer T ATT = 400H Transfer T = 1024/fs (sec) Figure 2–10. DAC Digital Attenuation Operation with Tapered Gain Response 2–8 2.15 Sigma-Delta DAC Modulator The DAC uses a third-order modulator with 32 times oversampling. The DAC provides high-resolution, low-noise performance using a 15-value PWM output as shown in Figure 2–11. APB(max)† Noise Power – dB Quantization Noise Power With Noise Shaping Audio Signal Noise Excluded by Low-Pass Filter Quantization Noise Power Without Noise Shaping 0 0 fB‡ 0.1 0.2 0.3 0.4 0.5 Normalized Analog-Output Frequency (fO/fs§) † APB(max) is the passband maximum amplitude. ‡ fB is the highest frequency of interest within the baseband. § fO is the output frequency at the external low-pass filter output. Figure 2–11. Oversampling Noise Power With and Without Noise Shaping 2.16 DAC Interpolation Filter The interpolation filter used prior to the DAC increases the digital-data rate from the LRCKD speed to the oversampled rate by interpolating with a ratio of 1:32. The oversampling modulator receives the output of this filter with de-emphasis as an option. 2.17 DAC PWM Output (L2–L1 and R2–R1) The L2 – L1 and the R2 – R1 output pairs are PWM signals with the L2 – L1 differential pulse duration determining the left-channel analog voltage and the R2 – R1 differential pulse duration determining the right-channel analog voltage. Each DAC left and right output consists of 15 levels of PWM and provides a differential signal as the input to two external differential amplifiers configured as a low-pass filter to produce the left and right audio outputs. 2–9 2.18 DAC Control Register Set Tables 2–3 and 2–4 list the bit functions. Table 2–3. Attenuation Mode Register† D16–D5 D4 D3 D2 D1 0h - - - - Muted 1h - - - - Digital attenuation, –60.2 dB 2h - - - - Digital attenuation, –54.2 dB 3h - - - - Digital attenuation, –50.7 dB 1FFh - - - - 200h - - - - Digital attenuation, –6.02 dB 201h - - - - Digital attenuation, –6.02 dB 3FFh - - - - Digital attenuation, –0.01 dB 400h - - - - Digital attenuation, 0 dB - 0 - - - - 1 - - - - - 0 - - - - 1 - - - - - 0 - - - - 1 - - - - - 0 - - - - 1 † The initialization value is 0400h. 2–10 DESCRIPTION C attenuation DAC (D5 = MSB, D16 = LSB) D/F mute De emphasis enable De-emphasis DAC register select DAC mode Digital attenuation, –6.04 dB Unmuted Muted No de-emphasis De-emphasis selected Attenuator-mode register System-mode register Normal Factory test only Table 2–4. System Mode Register† D16 D15 D14 D13 D12–D5 D4 D3 D2 D1 0 - - - - - - - - - 0 - - - - - - - - 1 - - - - - - - - - 0 0 - - - - - - - 0 1 - - - - - - - 1 0 - - - - - - - 1 1 - - - - - - - - - 0 - - - - - - - - - 0 - - - - - - - - 1 - - - - - - - - - 0 - - - - - - - - 1 - - - - - - - - - 0 - - - - - - - - - - - - - † The initialization value is 0000h. - - 1 - - 0 - 1 DESCRIPTION Reserved Resynchronize Off On 44.1 kHz Sample rate/ de emphasis de-emphasis selection Reserved 48 kHz 32 kHz Reserved Input data word width Input-data Input D-data D data protocol DAC register select 20 bits audio data 16 bits audio data MSB first LSB first Attenuator-mode register System-mode register Normal DAC mode Factory test only 2.19 Auto-Resynchronization Functionality The TLC320AD75C has an auto-resynchronization function to keep the entire coversion cycle for the ADC portion and DAC portion respectively checking the LRCK cycle of the fs rate. When the ADC is in slave mode, the ADC portion has a window of 4 clocks of the internal 64 fs clock to check the LRCK cycle with the fs rate detecting the rising edge of LRCK within this window. When an error is detected on the LRCK cycle, the ADC conversion cycle is resynchronized with an external LRCK cycle at the next rising edge of LRCK. This resynchronization occurrs automatically and the ADC portion continues processing based on the new conversion cycle timing. " " The DAC portion has a window of 2 clocks of the internal 128 fs clock to check the LRCK cycle detecting the rising edge of the LRCK clock. When an error is detected, the conversion cycle of the DAC is resynchronized with an external LRCK cycle automatically and the DAC portion continues processing based on the new conversion cycle timing. (The external LRCK rate should be the same as the fs rate. This functionality is to ensure the TLC320AD75C conversion operation even if LRCK has a timing problem due to noise injection for example.) 2–11 2–12 3 Specifications 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage range, AVDD, LVDD (see Note 1) . . . . . . . . . . . . . . . . . . . – 0.3 V to 6.5 V Supply voltage range, VDD1, V35A (see Note 2) . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6.5 V Supply voltage range, PVDD(L/R), VDD2, V35D, XVDD(see Note 3) . . . . – 0.3 V to 6.5 V Analog input voltage range, INLP, INLM, INRP, INRM . . . . . . . – 0.3 V to AVDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD1/2 + 0.3 V Output voltage range, VO: L1, L2, R1, R2 . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values for maximum ratings are with respect to AVSS. 2. Voltage values for maximum ratings are with respect to VSS1. 3. Voltage values for maximum ratings are with respect to VSS2. 3.2 Recommended Operating Conditions MIN NOM MAX UNIT Analog supply voltage, AVDD (see Note 4) 4.75 5 5.25 V Digital supply voltage, VDD1 4.75 5 5.25 V Analog logic supply voltage, LVDD 4.75 5 5.25 V Reference voltage at REFI Digital supply voltage, V35A, V35D 3.2 V 3 3.3 5.25 V Digital supply voltage, VDD2 4.75 5 5.25 V Digital supply voltage, PVDDL, PVDDR 4.75 5 5.25 V Clock supply voltage, XVDD 4.75 5 5.25 Setup time, SCLKA/SCLKD↑ before LRCKA/LRCKD valid, tsu1 (see Figure 4–2) 50 Setup time, LRCKA/LRCKD valid before SCLKA/SCLKD↑, tsu2 (see Figure 4–2) V ns 50 ns Load resistance at ADOUT, RL 8 kΩ Operating free-air temperature, TA 0 70 °C NOTE 4: Voltages at analog inputs and outputs and AVDD are with respect to AVSS. 3–1 3.3 Electrical Characteristics, AVDD = LVDD = VDD1 = VDD2 = PVDDL = PVDDR = XVDD = 5 V, V35A = V35D = 3.3 V, TA = 25°C 3.3.1 Digital Interface VIH VIH High-level input voltage VIL VIL Low-level input voltage PARAMETER High-level input voltage Low-level input voltage TEST CONDITIONS XIN 512CK High-level output voltage 256CK L1, L2, R1, R2 XOUT ADOUT 512CK VOL Low-level output voltage TYP 2 3.3 4.5 XIN ADOUT VOH MIN 256CK L1, L2, R1, R2 XOUT MAX UNIT V 5 V 0.2 0.8 V 0.2 0.8 V IOH = 0.4 mA IOH = 0.4 mA 2.6 3.2 2.6 3.2 IOH = 0.4 mA IOH = 0.4 mA 4.5 4.9 4.5 4.9 IOH = 1.2 mA IOL = 2 mA 4.5 4.9 V 0.2 0.4 IOL = 2 mA IOL = 2 mA 0.2 0.4 0.2 0.4 IOL = 2 mA IOL = 1.2 mA 0.2 0.5 0.2 0.5 V IIH IIL High-level input current, any digital input 0.1 µA Low-level input current, any digital input 0.1 µA Ci Input capacitance 5 pF Co Output capacitance 5 pF 3.3.2 Analog Interface PARAMETER VI( l ) I(analog) Analog input voltage, voltage ADC Zi Input impedance, ADC 3–2 TEST CONDITIONS MIN TYP MAX UNIT Differential 6.4 V 0 to peak 3.2 V 200 kΩ 3.3.3 ADC Performance, fs = 44.1 kHz, Bandwidth = 22.05 kHz PARAMETER TEST CONDITIONS MIN Resolution TYP MAX UNIT 20 Bits 100 dB 100 dB DYNAMIC PERFORMANCE Signal to noise (EIAJ) INLP = INRP = 2.5 V dc INLM = INRM = 2.5 V dc Dynamic range – 60 dB input Signal to noise + distortion (THD + N) Total harmonic distortion (THD) 96 0.0017% – 0.5 0 5 dB input 0.003% 0.001% Interchannel isolation 120 dB ± 0.2 dB DC ACCURACY Absolute gain error ± 0.2 – 0.5 dB IN Offset drift 3.3.4 ± 0.5 ± 0.2 Interchannel gain mismatch dB dB 0 LSB/°C DAC Performance, 20-Bit Mode, fs = 44.1 kHz, Bandwidth = 22.05 kHz PARAMETER TEST CONDITIONS Resolution See Note 5 Signal-to-noise ratio See Note 5 Signal-to-noise + distortion (THD + N) See Note 5 De emphasis De-emphasis not selected MIN 100 TYP MAX UNIT 20 bits 104 dB 0.0013% 0.0025% NOTE 5: These specifications are measured at the output (VO) of the external low-pass filter. 3.3.5 ADC Inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Input voltage range Differential 6.4 0 to peak 3.2 Input impedance 3.3.6 200 kΩ ADC High-Pass Filter, fs = 44.1 kHz PARAMETER TEST CONDITIONS MIN Passband (–3 dB) Passband 5 Hz Group delay 3.3.7 V TYP MAX UNIT 0.86 Hz –0.12 dB 1/fs s ADC Decimation Filter, fs = 44.1 kHz PARAMETER TEST CONDITIONS Passband ripple 20.03 kHz Stopband attenuation 24.07 kHz Group delay MIN TYP ± 0.01 80 MAX UNIT dB dB 25/fs s 3–3 3.3.8 DAC Filter Characteristics, fs = 44.1 kHz PARAMETER TEST CONDITIONS Pass-band ripple MIN Stop-band attenuation TYP UNIT dB 75 dB Group delay 3.3.9 MAX ± 0.002 fs = 20 kHz fs = 24.1 kHz 29 / fs s Power Supply Current, fs = 44.1 kHz PARAMETER TYP MAX AVDD and LVDD 29 40 mA Power-supply current, digital (ADC) VDD1 and V35A 22 30 mA IDD(DA1) Power-supply current, digital (DAC) VDD2 and V35D 20 25 mA IDD(DA2) Power-supply current, PWM/OSC (DAC) PVDDL, PVDDR, and XVDD 17 25 mA IDD(AST) Power-down current, analog (ADC) AVDD and LVDD 250 µA IDD(DST) Power-down current, digital (ADC) VDD1 and V35A 150 µA PD Power dissipation IDD(A) Power-supply current, analog (ADC) IDD(AD) PSRR 3.4 TEST CONDITIONS Power supply rejection ratio Power-supply MIN UNIT 400 mW 0 to 24 kHz 75 dB 24 kHz to 2.798 MHz 85 dB ADC Switching Characteristics (see Figures 2–1 and 4–1) PARAMETER MIN TYP MAX UNIT 11.3 12.8 MHz fMCKI td(MDD) Input clock frequency, MCKI Delay time, SCLKA↓ to ADOUT, master mode 0 50 ns td(MIRD) td(SDD1) Delay time, SCLKA↓ to LRCKA, master mode – 20 20 ns Delay time, LRCKA to ADOUT, slave mode 50 ns td(SDD2) Delay time, SCLKA↓ to ADOUT, slave mode 50 ns 3–4 3.5 DAC Timing Requirements (see Figures 4–1 and 4–2, and Note 6) MIN TYP MAX UNIT 22.6 25.6 MHz fXIN tw1 Input frequency, XIN clock Pulse duration, SCLKD 155 tw2 tw3 Pulse duration, SHIFT 100 ns Pulse duration, LATCH 100 ns tsu3 th1 Setup time, DDATA valid before SCLKD↑ 20 ns Hold time, DDATA valid after SCLKD↑ 20 ns tsu4 th2 Setup time, CDIN valid before SHIFT↑ 20 ns Hold time, CDIN valid after SHIFT↑ 20 ns tsu5 th3 Setup time, LATCH↑ before SHIFT↑ 100 ns 80 ns Hold time, LATCH↓ after SHIFT↑ 177 ns NOTE 6: All timing measurements were taken at the VDD/2 voltage level. 3–5 3–6 4 Parameter Measurement Information tsu2 tsu1 tw1 tw1 SRCKA/ SRCKD td(MIRD) LRCKA/ LRCKD td(sdd1) td(sdd2), td(MDD) ADOUT tsu3 th1 DDATA Figure 4–1. ADC Audio-Data Serial Timing tw2 tw2 SHIFT tsu4 th2 CDIN th3 tsu5 LATCH tw3 Figure 4–2. DAC Control-Data Serial Timing 4–1 4–2 5 Application Information Table 5–1. TLC320AD75C Schematic Components SYMBOL DESCRIPTION C1 220-µF capacitor C2 4700-pF capacitor C3 4700-pF capacitor C4 220-µF capacitor C5 47-µF capacitor C6 22-µF capacitor C7 0.1-µF capacitor C8 100-µF capacitor C9 0.1-µF capacitor C10 220-µF capacitor C12 220-µF capacitor C13 18-pF capacitor C14 12-pF capacitor C15 220-µF capacitor C16 47-µF capacitor C17 0.1-µF capacitor C18 4700-µF capacitor C19 4700-µF capacitor C20 200-pF capacitor C21 100-µF capacitor C22 0.1-µF capacitor C23 200-pF capacitor C24 100-pF capacitor C25 47-µF capacitor C26 22-µF capacitor C27 220-µF capacitor C28 220-µF capacitor C29 47-µF capacitor C30 100-pF capacitor C31 47-µF capacitor C32 30-pF capacitor C33 120-pF capacitor C34 30-pF capacitor C35 30-pF capacitor C36 120-pF capacitor 5–1 Table 5–1. TLC320AD75C Schematic Components (Continued) SYMBOL 5–2 DESCRIPTION C37 30-pF capacitor C38 100-µF capacitor C39 100-µF capacitor C40 4700-pF capacitor C41 1200-pF capacitor C42 1200-pF capacitor C43 4700-pF capacitor C44 47-µF capacitor C45 47-µF capacitor C46 100-µF capacitor C47 100-µF capacitor C48 47-µF capacitor C49 47-µF capacitor C50 0.1-µF capacitor C51 0.1-µF capacitor C52 0.1-µF capacitor C53 47-µF capacitor C54 220-µF capacitor C55 0.1-µF capacitor R1 50-Ω resistor R2 50-Ω resistor R3 50-Ω resistor R4 50-Ω resistor R5 50-Ω resistor R6 50-Ω resistor R7 50-Ω resistor R8 50-Ω resistor R9 50-Ω resistor R10 50-Ω resistor R11 50-Ω resistor R12 50-Ω resistor R13 50-Ω resistor R14 1-MΩ resistor R15 50-Ω resistor R16 50-Ω resistor R17 50-Ω resistor R18 5-kΩ resistor R19 620-Ω resistor R20 10-kΩ resistor R21 5-kΩ resistor Table 5–1. TLC320AD75C Schematic Components (Continued) SYMBOL DESCRIPTION R22 4.7-kΩ resistor R23 5-kΩ resistor R24 620-Ω resistor R25 68-kΩ resistor R26 33-kΩ resistor R27 18-kΩ resistor R28 33-kΩ resistor R29 18-kΩ resistor R30 68-kΩ resistor R31 68-kΩ resistor R32 33-kΩ resistor R33 18-kΩ resistor R34 33-kΩ resistor R35 18-kΩ resistor R36 68-kΩ resistor R37 1.5-kΩ resistor R38 1.5-kΩ resistor R39 1.5-kΩ resistor R40 1.5-kΩ resistor R41 100-Ω resistor R42 100-Ω resistor R43 100-Ω resistor R44 100-Ω resistor R45 330-kΩ resistor R46 330-kΩ resistor R47 10-kΩ resistor R48 10-kΩ resistor R49 10-kΩ resistor R50 10-kΩ resistor 5–3 INRM INRP C2 C3 C1 2 C53 3 4 AVDD C4 C5 AVSS R48 5 6 AVDD 7 8 R49 AVSS R1 LRCK R2 SCLK 9 10 11 12 ADOUT 13 V35A C6 C7 VSS1B 14 15 R3 DPD R4 AVSS R5 R6 CDIN R7 SHIFT R8 LATCH 16 17 18 19 20 21 22 23 V35D C8 C9 VSS2 24 25 512CK R9 R10 INLM REFI REFO AVDD LVSS LVDD AVSS APD AVSSB NU NU NU NU VSS1B LRCKA M_S SCLKA TEST2 ADOUT VSS1 V35A VDD1 VSS1B MCLKI DPD VSS2B INIT 56 INLP C19 55 54 INLM C18 53 R17 52 R16 AVSS AVDD 51 AVSS 50 49 48 TEST1 R50 VSS1B 47 46 VDD1 VDD2 L1 45 VSS1 C17 C16 44 VDD1 43 42 41 L1 R15 40 DVDD PVDDL L2 CDIN PVSSL SHIFT XVSS C15 39 L2 38 DVSS 37 XIN 256CK XOUT V35D XVDD VSS2 PVSSR C12 C11 34 R2 SCLKD PVDDR DDATA R1 VDD2 C14 XTL R14 35 512CK LRCKD C13 36 LATCH 27 28 INLP INRM 26 DDAT R11 INRP TLC320AD75C 1 R13 33 32 R2 C10 31 R12 30 R1 29 C54 C55 AVSS Figure 5–1. TLC320AD75C Application Schematic 5–4 PVSSR C26 R18 INRM INRP AINR C24 R19 C25 INLP R20 C20 C27 INLM 10 9 8 7 6 5 4 3 2 1 16 17 18 19 20 TL32088 11 12 13 14 15 R21 + C21 AVDD C23 R 47 AVDD C29 C28 R22 C30 AINL R23 C31 R24 C32 R25 C40 L1 R26 R27 R39 R40 C33 C48 C49 + + R41 – – R42 AOUTL + + L2 R28 –15 V R29 C34 R46 + C39 + R30 15 V + C41 C22 C47 + C51 PVSSR + C35 R32 C50 + R31 C38 + C52 GND C46 R45 R33 R37 + R38 C36 + – R2 R34 + C42 R43 C44 + C45 + R44 AOUTR – R35 C43 R36 R1 C37 Figure 5–1. TLC320AD75C Application Schematic (Continued) 5–5 Table 5–2. A-Weighted Data FREQUENCY A WEIGHTING (dB) FREQUENCY A WEIGHTING (dB) 25 – 44.6 ± 2 800 – 0.1 ± 1 31.5 – 39.2 ± 2 1000 0 ±0 40 – 34.5 ± 2 1250 0.6 ± 1 50 – 30.2 ± 2 1600 1.0 ± 1 63 – 26.1 ± 2 2000 1.2 ± 1 80 – 22.3 ± 2 2500 1.2 ± 1 100 – 19.1 ± 1 3150 1.2 ± 1 125 – 16.1 ± 1 4000 1.0 ± 1 160 – 13.2 ± 1 5000 0.5 ± 1 200 – 10.8 ± 1 6300 – 0.1 ± 1 250 – 8.6 ± 1 8000 – 1.1 ± 1 315 – 6.5 ± 1 10000 – 2.4 ± 1 400 – 4.8 ± 1 12500 – 4.2 ± 2 500 – 3.2 ± 1 16000 – 6.5 ± 2 630 – 1.9 ± 1 10 Attenuation – dB 0 – 10 – 20 – 30 – 40 – 50 20 100 1k 10 k 20 k f – Signal Frequency – Hz Figure 5–2. A-Weighted Function 5–6 5.1 Circuit And Layout Considerations The designer should follow these guidelines for the best device performance. 5.2 • Separate digital and analog ground planes should be used. All digital device functions should be over the digital ground plane, and all analog device functions should be over the analog ground plane. The ground planes should be connected at only one point to the direct power supply, and this is usually at the connector edge of the board. • A single crystal-controlled clock should synchronously generate all digital signals. • All power supply lines should include a 0.1-µF and a 1-µF capacitor. When clock noise is excessive, a toroidal inductance of 10 µH should be placed in series with XVDD before connecting to DVDD. • The digital input control signals should be buffered when they are generated off of the card. • Clock jitter should be minimized, and precautions taken to prevent clock overshoot. This minimizes any high-frequency coupling to the analog output. PCB Footprint Figure 5–3 shows the printed-circuit-board (PCB) land pattern for the TLC320AD75C small-outline package. W P L1 L L2 S L2 L L1 P S W L L1 L2 1.27 9.53 0.76 1.55 0.64 0.91 NOTE A: All linear dimensions are in millimeters. Figure 5–3. Land Pattern for PCB Layout 5–7 5–8 Appendix A Mechanical Data DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PIN SHOWN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 0.025 (0,635) 0.012 (0,305) 0.008 (0,203) 48 0.005 (0,13) M 25 0.006 (0,15) NOM 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°– 8° 24 A 0.040 (1,02) 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.008 (0,20) MIN 0.004 (0,10) 4040048 / B 02/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 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