LM75B, LM75C www.ti.com SNIS153B – JULY 2009 – REVISED MARCH 2013 LM75B LM75C Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface Check for Samples: LM75B, LM75C FEATURES DESCRIPTION • • The LM75B and LM75C are industy-standard digital temperature sensors with an integrated Sigma-Delta analog-to-digital converter and I2C interface. The LM75 provides 9-bit digital temperature readings with an accuracy of ±2°C from -25°C to 100°C and ±3°C over -55°C to 125°C. 1 2 • • • No External Components Required Shutdown Mode to Minimize Power Consumption Up to Eight LM75s Can be Connected to a Single Bus Power Up Defaults Permit Stand-alone Operation as Thermostat UL Recognized Component (LM75B and LM75C) APPLICATIONS • • • • General System Thermal Management Communications Infrastructure Electronic Test Equipment Environmental Monitoring KEY SPECIFICATIONS • • • Supply Voltage – LM75B, LM75C: 3.0V to 5.5V Supply Current – Operating: 280 μA (typ) – Shutdown: 4 μA (typ) Temperature Accuracy – −25°C to 100°C: ±2°C (max) – −55°C to 125°C: ±3°C (max) Communication is accomplished over a 2-wire interface which operates up to 400kHz. The LM75 has three address pins, allowing up to eight LM75 devices to operate on the same 2-wire bus. The LM75 has a dedicated over-temperature output (O.S.) with programmable limit and hystersis. This output has programmable fault tolerance, which allows the user to define the number of consecutive error conditions that must occur before O.S. is activated. The wide temperature and supply range and I2C interface make the LM75 ideal for a number of applications including base stations, electronic test equipment, office electronics, personal computers, and any other system where thermal management is critical to performance. The LM75B and LM75C are available in an SOIC package or VSSOP package. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2013, Texas Instruments Incorporated LM75B, LM75C SNIS153B – JULY 2009 – REVISED MARCH 2013 www.ti.com Simplified Block Diagram +VS 8 Temperature 10-Bit Digital Decimation Filter Ð 1-Bit D/A TOS Set Point Set Point Comparator Reset Silicon Bandgap Temperature Sensor A1 A2 O.S. Threshold Register 9-Bit Sigma-Delta ADC A0 3 Configuration Register Pointer Register THYST Set Point Register 1 7 6 Two-Wire Interface 5 2 SDA SCL 4 GND Figure 1. Connection Diagram LM75B, LM75C, SOIC and VSSOP PIN DESCRIPTIONS Label 2 Pin # Function Typical Connection SDA 1 I2C Serial Bi-Directional Data Line. Open Drain. SCL 2 I2C Clock Input From Controller, tied to a pull-up resistor or current source O.S. 3 Over temperature Shutdown. Open Drain Output Pull–up Resistor, Controller Interrupt Line GND 4 Power Supply Ground Ground +VS 8 Positive Supply Voltage Input DC Voltage from 3V to 5.5V; 100 nF bypass capacitor with 10 µF bulk capacitance in the near vicinity A0–A2 7,6,5 User-Set I2C Address Inputs Ground (Low, “0”) or +VS (High, “1”) From Controller, tied to a pull-up resistor or current source Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C LM75B, LM75C www.ti.com SNIS153B – JULY 2009 – REVISED MARCH 2013 Typical Application +VS 100 nF (typ) unless mounted close to processor 8 A0 Address A1 (Set as desired) A2 Interface SDA SCL 7 6 5 LM75 3 O.S. To Processor Interrupt Line 1 O.S. set to active low IRU ZLUH 25¶G PXOWLSOH interrupt line 2 4 GND Figure 2. Typical Application These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to 6.5V Supply Voltage Pin (+VS) −0.3V to (+VS + 0.3V) and must be ≤ 6.5V Voltage at A0, A1and A2 Pins −0.3V to 6.5V Voltage at OS, SCL and SDA Pins Input Current at any Pin (2) 5 mA Package Input Current (2) 20 mA −65°C to +150°C Storage Temperature Human Body Model ESD Susceptibility (3) Machine Model LM75B 2500V LM75C 1500V LM75B 250V LM75C 100V O.S. Output Sink Current 10 mA O.S. Output Voltage (1) (2) (3) 6.5V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions. When the input voltage (VI) at any pin exceeds the power supplies (VI < GND or VI > +VS) the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four. Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model, 200 pF discharged directly into each pin. The Charged Device Model (CDM) is a specified circuit characterizing an ESD event that occurs when a device acquires charge through some triboelectric (frictional) or electrostatic induction processes and then abruptly touches a grounded object or surface. Operating Ratings (1) (2) Specified Temperature Range TMIN to TMAX See (3) −55°C to +125°C Supply Voltage Range (+VS) LM75B, LM75C (1) (2) (3) +3.0V to +5.5V Soldering process must comply with Texas Instruments Incorporated Reflow Temperature Profile specifications. Refer to Reflow temperature profiles are different for lead-free and non-lead-free packages. LM75 θJA (thermal resistance, junction-to-ambient) when attached to a printed circuit board with 2 oz. foil similar to the one shown in Figure 5 is summarized in the table below: Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C 3 LM75B, LM75C SNIS153B – JULY 2009 – REVISED MARCH 2013 www.ti.com Device Number Package Number Thermal Resistance (θJA) LM75BIM-3, LM75BIM-5, LM75CIM-3, LM75CIM-5 D (R-PDSO-G8) 200°C/W LM75BIMM-3, LM75BIMM-5, LM75CIMM-3, LM75CIMM-5 DGK (S-PDSOG8) 250°C/W Temperature-to-Digital Converter Characteristics (1) Unless otherwise noted, these specifications apply for: +VS = +5 Vdc for LM75BIM-5, LM75BIMM-5, LM75CIM-5, and LM75CIMM-5; and +VS = +3.3 Vdc for LM75BIM-3, LM75BIMM-3, LM75CIM-3, and LM75CIMM-3 (2). Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted. Parameter Conditions Accuracy Typical (3) TA = −25°C to +100°C ±2.0 TA = −55°C to +125°C ±3.0 Resolution 9 Temperature Conversion Time LM75B Quiescent Current O.S. Output Saturation Voltage THYST Default Temperature (2) (3) (4) (5) (6) (7) 4 °C (max) Bits 100 300 ms (max) I2C Inactive 0.25 0.5 mA (max) Shutdown Mode, +VS = 3V 4 Shutdown Mode, +VS = 5V 6 0.25 Shutdown Mode, +VS = 3V 4 Shutdown Mode, +VS = 5V 6 IOUT = 4.0 mA μA 1.0 0.8 V (max) (6) Conversion (min) 6 See (7) 80 75 mA (max) μA 1 O.S. Delay TOS Default Temperature Units (Limit) See (5) I2C Inactive LM75C (1) Limits (4) Conversions (max) °C For best accuracy, minimize output loading. Higher sink currents can affect sensor accuracy with internal heating. This can cause an error of 0.64°C at full rated sink current and saturation voltage based on junction-to-ambient thermal resistance. All part numbers of the LM75 will operate properly over the +VS supply voltage range of 3V to 5.5V. The devices are tested and specified for rated accuracy at their nominal supply voltage. Accuracy will typically degrade 1°C/V of variation in +VS as it varies from the nominal value. Typicals are at TA = 25°C and represent most likely parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). The conversion-time specification is provided to indicate how often the temperature data is updated. The LM75 can be accessed at any time and reading the Temperature Register will yield result from the last temperature conversion. When the LM75 is accessed, the conversion that is in process will be interrupted and it will be restarted after the end of the communication. Accessing the LM75 continuously without waiting at least one conversion time between communications will prevent the device from updating the Temperature Register with a new temperature conversion result. Consequently, the LM75 should not be accessed continuously with a wait time of less than 300 ms. O.S. Delay is user programmable up to 6 “over limit” conversions before O.S. is set to minimize false tripping in noisy environments. Default values set at power up. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C LM75B, LM75C www.ti.com SNIS153B – JULY 2009 – REVISED MARCH 2013 Logic Electrical Characteristics DIGITAL DC CHARACTERISTICS Unless otherwise noted, these specifications apply for +VS = +5 Vdc for LM75BIM-5, LM75BIMM-5, LM75CIM-5, and LM75CIMM-5; and +VS = +3.3 Vdc for LM75BIM-3, LM75BIMM-3, LM75CIM-3, and LM75CIMM-3 (1). Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted. Symbol Parameter Typical (2) Conditions Limits (3) Units (Limit) +VS × 0.7 V (min) +VS + 0.3 V (max) −0.3 V (min) VIN(1) Logical “1” Input Voltage VIN(0) Logical “0” Input Voltage +VS × 0.3 V (max) IIN(1) Logical “1” Input Current VIN = +VS 0.005 1.0 μA (max) IIN(0) Logical “0” Input Current VIN = 0V −0.005 −1.0 μA (max) CIN All Digital Inputs 5 pF LM75B VOH = 5V 10 μA (max) LM75C IOH High Level Output Current VOH = 5V 100 μA (max) VOL Low Level Output Voltage IOL = 3 mA 0.4 V (max) tOF Output Fall Time CL = 400 pF IO = 3 mA 250 ns (max) (1) (2) (3) All part numbers of the LM75 will operate properly over the +VS supply voltage range of 3V to 5.5V. The devices are tested and specified for rated accuracy at their nominal supply voltage. Accuracy will typically degrade 1°C/V of variation in +VS as it varies from the nominal value. Typicals are at TA = 25°C and represent most likely parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). Logic Electrical Characteristics I2C Digital Switching Characteristics Unless otherwise noted, these specifications apply for VS = +5 Vdc for LM75BIM-5, LM75BIMM-5, LM75CIM-5, and LM75CIMM-5; and +VS = +3.3 Vdc for LM75BIM-3, LM75BIMM-3, LM75CIM-3, and LM75CIMM-3CL (load capacitance) on output lines = 80 pF unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted. Symbol Parameter Conditions Typical (1) Limits (2) (3) Units (Limit) t1 SCL (Clock) Period 2.5 μs (min) t2 Data in Set-Up Time to SCL High 100 ns (min) t3 Data Out Stable after SCL Low 0 ns (min) t4 SDA Low Set-Up Time to SCL Low (Start Condition) 100 ns (min) t5 SDA High Hold Time after SCL High (Stop Condition) 100 ns (min) tTIMEOUT SDA Time Low for Reset of Serial Interface (4) 75 325 ms (min) ms (max) LM75B LM75C (1) (2) (3) (4) Not Applicable Typicals are at TA = 25°C and represent most likely parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when the SCL and SDA edge rates are similar. Holding the SDA line low for a time greater than tTIMEOUT will cause the LM75B to reset SDA to the IDLE state of the serial bus communication (SDA set High). Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C 5 LM75B, LM75C SNIS153B – JULY 2009 – REVISED MARCH 2013 www.ti.com Figure 3. Figure 4. Temperature-to-Digital Transfer Function (Non-linear scale for clarity) Figure 5. Printed Circuit Board Used for Thermal Resistance Specifications 6 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C LM75B, LM75C www.ti.com SNIS153B – JULY 2009 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Static Quiescent Current vs Temperature (LM75C) Dynamic Quiescent Current vs Temperature (LM75C) Figure 6. Figure 7. Accuracy vs Temperature (LM75C) Figure 8. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C 7 LM75B, LM75C SNIS153B – JULY 2009 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION The LM75 temperature sensor incorporates a band-gap type temperature sensor and 9-bit ADC (Sigma-Delta Analog-to-Digital Converter). The temperature data output of the LM75 is available at all times via the I2C bus. If a conversion is in progress, it will be stopped and restarted after the read. A digital comparator is also incorporated that compares a series of readings, the number of which is user-selectable, to user-programmable setpoint and hysteresis values. The comparator trips the O.S. output line, which is programmable for mode and polarity. The LM75B contains all the functionality of the LM75C, plus two additional features: 1. The LM75B has an integrated low-pass filter on both the SDA and the SCL line. These filters increase communications reliability in noisy environments. 2. The LM75B also has a bus fault timeout feature. If the SDA line is held low for longer than tTIMEOUT (see Logic Electrical Characteristics) the LM75B will reset to the IDLE state (SDA set to high impedance) and wait for a new start condition. The TIMEOUT feature is not functional in Shutdown Mode. O.S. OUTPUT, TOS AND THYST LIMITS In Comparator mode the O.S. Output behaves like a thermostat. The output becomes active when temperature exceeds the TOS limit, and leaves the active state when the temperature drops below the THYST limit. In this mode the O.S. output can be used to turn a cooling fan on, initiate an emergency system shutdown, or reduce system clock speed. Shutdown mode does not reset O.S. state in a comparator mode. In Interrupt mode exceeding TOS also makes O.S. active but O.S. will remain active indefinitely until reset by reading any register via the I2C interface. Once O.S. has been activated by crossing TOS, then reset, it can be activated again only by Temperature going below THYST. Again, it will remain active indefinitely until being reset by a read. Placing the LM75 in shutdown mode also resets the O.S. Output. POWER UP AND POWER DOWN The LM75 always powers up in a known state. The power up default conditions are: 1. Comparator mode 2. TOS = 80°C 3. THYST = 75°C 4. O.S. active low 5. Pointer = “00” When the supply voltage is less than about 1.7V, the LM75 is considered powered down. As the supply voltage rises above the nominal 1.7V power up threshold, the internal registers are reset to the power up default values listed above. Stand-Alone Thermostat Mode If the LM75 is not connected to the I2C bus on power up, it will act as a stand-alone thermostat with the power up default conditions listed above. It is optional, but recommended, to connect the address pins (A2, A1, A0) and the SCL and SDA pins together and to a 10k pull-up resistor to +VS for better noise immunity. Any of these pins may also be tied high separately through a 10k pull-up resistor. I2C BUS INTERFACE The LM75 operates as a slave on the I2C bus, so the SCL line is an input (no clock is generated by the LM75) and the SDA line is a bi-directional serial data path. According to I2C bus specifications, the LM75 has a 7-bit slave address. The four most significant bits of the slave address are hard wired inside the LM75 and are “1001”. The three least significant bits of the address are assigned to pins A2–A0, and are set by connecting these pins to ground for a low, (0); or to +VS for a high, (1). Therefore, the complete slave address is: 1 0 0 1 A2 MSB 8 A1 A0 LSB Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C LM75B, LM75C www.ti.com SNIS153B – JULY 2009 – REVISED MARCH 2013 These interrupt mode resets of O.S. occur only when LM75 is read or placed in shutdown. Otherwise, O.S. would remain active indefinitely for any event. Figure 9. O.S. Output Temperature Response Diagram TEMPERATURE DATA FORMAT Temperature data can be read from the Temperature, TOS Set Point, and THYST Set Point registers; and written to the TOS Set Point, and THYST Set Point registers. Temperature data is represented by a 9-bit, two's complement word with an LSB (Least Significant Bit) equal to 0.5°C: Temperature Digital Output Binary Hex +125°C 0 1111 1010 0FAh +25°C 0 0011 0010 032h +0.5°C 0 0000 0001 001h 0°C 0 0000 0000 000h −0.5°C 1 1111 1111 1FFh −25°C 1 1100 1110 1CEh −55°C 1 1001 0010 192h SHUTDOWN MODE Shutdown mode is enabled by setting the shutdown bit in the Configuration register via the I2C bus. Shutdown mode reduces power supply current significantly. See specified quiescent current specification in the Temperature-to-Digital Converter Characteristics table. In Interrupt mode O.S. is reset if previously set and is undefined in Comparator mode during shutdown. The I2C interface remains active. Activity on the clock and data lines of the I2C bus may slightly increase shutdown mode quiescent current. TOS, THYST, and Configuration registers can be read from and written to in shutdown mode. For the LM75B, the TIMEOUT feature is turned off in Shutdown Mode. FAULT QUEUE A fault queue of up to 6 faults is provided to prevent false tripping of O.S. when the LM75 is used in noisy environments. The number of faults set in the queue must occur consecutively to set the O.S. output. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C 9 LM75B, LM75C SNIS153B – JULY 2009 – REVISED MARCH 2013 www.ti.com COMPARATOR/INTERRUPT MODE As indicated in the O.S. Output Temperature Response Diagram, Figure 9, the events that trigger O.S. are identical for either Comparator or Interrupt mode. The most important difference is that in Interrupt mode the O.S. will remain set indefinitely once it has been set. To reset O.S. while in Interrupt mode, perform a read from any register in the LM75. O.S. OUTPUT The O.S. output is an open-drain output and does not have an internal pull-up. A “high” level will not be observed on this pin until pull-up current is provided from some external source, typically a pull-up resistor. Choice of resistor value depends on many system factors but, in general, the pull-up resistor should be as large as possible. This will minimize any errors due to internal heating of the LM75. The maximum resistance of the pull up, based on LM75 specification for High Level Output Current, to provide a 2V high level, is 30 kΩ. O.S. POLARITY The O.S. output can be programmed via the configuration register to be either active low (default mode), or active high. In active low mode the O.S. output goes low when triggered exactly as shown on the O.S. Output Temperature Response Diagram, Figure 9. Active high simply inverts the polarity of the O.S. output. INTERNAL REGISTER STRUCTURE SCL 2 I C Interface SDA Data Address Pointer Register (Selects register for communication) Temperature (Read-Only) Pointer = 00000000 Configuration (Read-Write) Pointer = 00000001 TOS Set Point (Read-Write) Pointer = 00000011 THYST Set Point (Read-Write) Pointer = 00000010 Figure 10. There are four data registers in the LM75B and LM75C selected by the Pointer register. At power-up the Pointer is set to “000”; the location for the Temperature Register. The Pointer register latches whatever the last location it was set to. In Interrupt Mode, a read from the LM75, or placing the device in shutdown mode, resets the O.S. output. All registers are read and write, except the Temperature register which is a read only. A write to the LM75 will always include the address byte and the Pointer byte. A write to the Configuration register requires one data byte, and the TOS and THYST registers require two data bytes. Reading the LM75 can take place either of two ways: If the location latched in the Pointer is correct (most of the time it is expected that the Pointer will point to the Temperature register because it will be the data most frequently read from the LM75), then the read can simply consist of an address byte, followed by retrieving the corresponding number of data bytes. If the Pointer needs to be set, then an address byte, pointer byte, repeat start, and another address byte will accomplish a read. The first data byte is the most significant byte with most significant bit first, permitting only as much data as necessary to be read to determine temperature condition. For instance, if the first four bits of the temperature data indicates an overtemperature condition, the host processor could immediately take action to remedy the excessive temperatures. At the end of a read, the LM75 can accept either Acknowledge or No Acknowledge from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte). 10 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C LM75B, LM75C www.ti.com SNIS153B – JULY 2009 – REVISED MARCH 2013 An inadvertent 8-bit read from a 16-bit register, with the D7 bit low, can cause the LM75 to stop in a state where the SDA line is held low as shown in Figure 11. This can prevent any further bus communication until at least 9 additional clock cycles have occurred. Alternatively, the master can issue clock cycles until SDA goes high, at which time issuing a “Stop” condition will reset the LM75. Figure 11. Inadvertent 8-Bit Read from 16-Bit Register where D7 is Zero (“0”) POINTER REGISTER (Selects which registers will be read from or written to): P7 P6 P5 P4 P3 P2 P1 0 0 0 0 0 P2 P1 P0 0 0 0 Temperature (Read only) (Power-up default) 0 0 1 Configuration (Read/Write) 0 1 0 THYST (Read/Write) 0 1 1 TOS (Read/Write) P0 Register Select P0-P1: Register Select: Register P3–P7: Must be kept zero. TEMPERATURE REGISTER (Read Only): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB X X X X X X X D0–D6: Undefined. D7–D15: Temperature Data. One LSB = 0.5°C. Two's complement format. CONFIGURATION REGISTER (Read/Write): D7 D6 D5 0 0 0 D4 D3 Fault Queue D2 D1 D0 O.S. Polarity Cmp/Int Shutdown Power up default is with all bits “0” (zero). D0: Shutdown: When set to 1 the LM75 goes to low power shutdown mode. D1: Comparator/Interrupt mode: 0 is Comparator mode, 1 is Interrupt mode. D2: O.S. Polarity: 0 is active low, 1 is active high. O.S. is an open-drain output under all conditions. D3–D4: Fault Queue: Number of faults necessary to detect before setting O.S. output to avoid false tripping due to noise. Faults are determind at the end of a conversion. See specified temperature conversion time in the Temperature-to-Digital Converter Characteristics table. D4 D3 Number of Faults 0 0 1 (Power-up default) 0 1 2 1 0 4 1 1 6 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C 11 LM75B, LM75C SNIS153B – JULY 2009 – REVISED MARCH 2013 www.ti.com D5–D7: These bits are used for production testing and must be kept zero for normal operation. THYST AND TOS REGISTER (Read/Write): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB X X X X X X X D0–D6: Undefined 75°C D7–D15: THYST Or TOS Trip Temperature Data. Power up default is TOS = 80°C, THYST = TEST CIRCUIT DIAGRAMS Figure 12. 12 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C LM75B, LM75C www.ti.com SNIS153B – JULY 2009 – REVISED MARCH 2013 Figure 13. I2C Timing Diagrams (Continued) Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C 13 LM75B, LM75C SNIS153B – JULY 2009 – REVISED MARCH 2013 www.ti.com APPLICATION HINTS To get the expected results when measuring temperature with an integrated circuit temperature sensor like the LM75, it is important to understand that the sensor measures its own die temperature. For the LM75, the best thermal path between the die and the outside world is through the LM75's pins. In the VSSOP package for the LM75B and LM75C, the GND pin is directly connected to the die, so the GND pin provides the best thermal path. If the other pins are at different temperatures (unlikely, but possible), they will affect the die temperature, but not as strongly as the GND pin. In the SOIC package, none of the pins is directly connected to the die, so they will all contribute similarly to the die temperature. Because the pins represent a good thermal path to the LM75 die, the LM75 will provide an accurate measurement of the temperature of the printed circuit board on which it is mounted. There is a less efficient thermal path between the plastic package and the LM75 die. If the ambient air temperature is significantly different from the printed circuit board temperature, it will have a small effect on the measured temperature. In probe-type applications, the LM75 can be mounted inside a sealed-end metal tube, and can then be dipped into a bath or screwed into a threaded hole in a tank. As with any IC, the LM75 and accompanying wiring and circuits must be kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit may operate at cold temperatures where condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy paints or dips are often used to insure that moisture cannot corrode the LM75 or its connections. DIGITAL NOISE ISSUES The LM75B features an integrated low-pass filter on both the SCL and the SDA digital lines to mitigate the effects of bus noise. Although this filtering makes the LM75B communication robust in noisy environments, good layout practices are always recommended. Minimize noise coupling by keeping digital traces away from switching power supplies. Also, ensure that digital lines containing high-speed data communications cross at right angles to the SDA and SCL lines. Excessive noise coupling into the SDA and SCL lines on the LM75C-specifically noise with amplitude greater than 400 mVpp (the LM75’s typical hysteresis), overshoot greater than 300 mV above +Vs, and undershoot more than 300 mV below GND-may prevent successful serial communication with the LM75C. Serial bus noacknowledge is the most common symptom, causing unnecessary traffic on the bus. The layout procedures mentioned above apply also to the LM75C. Although the serial bus maximum frequency of communication is only 400 kHz, care must be taken to ensure proper termination within a system with long printed circuit board traces or multiple parts on the bus. Resistance can be added in series with the SDA and SCL lines to further help filter noise and ringing. A 5 kΩ resistor should be placed in series with the SCL line, placed as close as possible to the SCL pin on the LM75C. This 5 kΩ resistor, with the 5 pF to 10 pF stray capacitance of the LM75 provides a 6 MHz to 12 MHz low pass filter, which is sufficient filtering in most cases. TYPICAL APPLICATIONS +VS +12V Optional but Recommended Pull-up In Stand-alone Mode C1 100 nF R3 10k R1 10k R2 10k +12V/300 mA Fan Motor 8 A0 7 A1 6 3 O.S. A2 5 Q1 2N3904 Q2 NDP410A series LM75 SDA 1 SCL 2 4 GND When using the two-wire interface: program O.S. for active high and connect O.S. directly to Q2's gate. Figure 14. Simple Fan Controller, Interface Optional 14 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C LM75B, LM75C www.ti.com SNIS153B – JULY 2009 – REVISED MARCH 2013 + 5 VDC Heater Heater Supply C1 100 nF R2 10k Optional but Recommended Pull-up In Stand-alone Mode 8 R1 +VS 10k K1 5V Relay D1 1N4001 A0 7 A1 6 A2 5 LM75 Q1 2N2222A 3 O.S. SDA 1 SCL 2 4 GND Figure 15. Simple Thermostat, Interface Optional +VS Optional but Recommended Pull-up In Stand-alone Mode R3 10k C6 100 nF R1 10k 8 A0 7 A1 6 3 A2 5 LM75 SDA 1 SCL 2 4 GND SHUTDOWN Vo2 BYPASS C1 100 nF C2 100 nF GND VDD +IN LM4861M -IN Vo1 R5 200k O.S. C3 6.8 nF C4 6.8 nF C5 6.8 nF R2 10k R3 10k R4 10k Figure 16. Temperature Sensor with Loudmouth Alarm (Barking Watchdog) Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C 15 LM75B, LM75C SNIS153B – JULY 2009 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision A (March 2013) to Revision B • 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM75B LM75C PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM75BIM-3 ACTIVE SOIC D 8 95 TBD Call TI Call TI -55 to 125 LM75 BIM-3 LM75BIM-3/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 LM75 BIM-3 LM75BIM-5 ACTIVE SOIC D 8 95 TBD Call TI Call TI -55 to 125 LM75 BIM-5 LM75BIM-5/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 LM75 BIM-5 LM75BIMM-3 ACTIVE VSSOP DGK 8 1000 TBD Call TI Call TI -55 to 125 T01B LM75BIMM-3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 T01B LM75BIMM-5 ACTIVE VSSOP DGK 8 1000 TBD Call TI Call TI -55 to 125 T00B LM75BIMM-5/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 T00B LM75BIMMX-3 ACTIVE VSSOP DGK 8 3500 TBD Call TI Call TI -55 to 125 T01B LM75BIMMX-3/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 T01B LM75BIMMX-5 ACTIVE VSSOP DGK 8 3500 TBD Call TI Call TI -55 to 125 T00B LM75BIMMX-5/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 T00B LM75BIMX-3 ACTIVE SOIC D 8 2500 TBD Call TI Call TI -55 to 125 LM75 BIM-3 LM75BIMX-3/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 LM75 BIM-3 LM75BIMX-5 ACTIVE SOIC D 8 2500 TBD Call TI Call TI -55 to 125 LM75 BIM-5 LM75BIMX-5/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -55 to 125 LM75 BIM-5 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM75BIMM-3 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM75BIMM-3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM75BIMM-5 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM75BIMM-5/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM75BIMMX-3 VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM75BIMMX-3/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM75BIMMX-5 VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM75BIMMX-5/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM75BIMX-3 SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM75BIMX-3/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM75BIMX-5 SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM75BIMX-5/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM75BIMM-3 VSSOP DGK 8 1000 210.0 185.0 35.0 LM75BIMM-3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM75BIMM-5 VSSOP DGK 8 1000 210.0 185.0 35.0 LM75BIMM-5/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM75BIMMX-3 VSSOP DGK 8 3500 367.0 367.0 35.0 LM75BIMMX-3/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM75BIMMX-5 VSSOP DGK 8 3500 367.0 367.0 35.0 LM75BIMMX-5/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM75BIMX-3 SOIC D 8 2500 367.0 367.0 35.0 LM75BIMX-3/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM75BIMX-5 SOIC D 8 2500 367.0 367.0 35.0 LM75BIMX-5/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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