ES51995(6000counts) DMM Analog front end with PEAK Features • 6000 counts dual-slope SADC (2-5 cnvs/s.) • Input signal full scale: 630mV (Max. 6300 count) • Built-in 600 counts fast speed (x10) FADC • Fast ADC conversion rate: 20-50 times/s • 100L LQFP package • 3V DC regulated power supply • Support digital multi-meter function *Voltage measurement (AC/DC) *Current measurement (AC/DC) *Dual mode for frequency with voltage or current *Resistance measurement (600.0Ω – 60.00MΩ) *Capacitance measurement (6.000nF – 60.00mF) (Taiwan patent no.: 323347, 453443) *Diode or continuity mode measurement *Frequency counter with duty cycle display: 60.00Hz – 60.00MHz 5% – 95% • ADP mode (AC or DC mode is available) • 3dB BW selectable for low pass filter at AC mode (Taiwan patent no.: 362409) (China patent no.: 1363073) Description ES51995 is an analog frond end chip of DMM built-in 6000(SADC)/600(FADC) counts dual ADCs. The SADC is operated at slower speed for higher resolution. The FADC is operated at higher speed for lower resolution. ES51995 provides voltage & current (AC/DC) measurement, resistance measurement, capacitance measurement, diode/continuity measurement, frequency measurement, duty cycle measurement and voltage peak-hold function. The ES51995 also supports multi-level battery detection, low-pass-filter feature for AC mode and dual mode measurement for V+F & A+F. A 3-wire serial bus for MPU I/O port will be used easily for firmware design. Flexible function design is supported for different kinds of DMM or Clamp-on meter application. . • Band-gap reference voltage output • Peak-hold measurement (Taiwan patent no.:476418) • 3-wire serial bus for MPU I/O port • MPU I/O power level selectable by external pins • On-chip buzzer driver and frequency selectable by MPU command • High-crest-factor signal detection (Taiwan patent no.: 234661) • Multi-level battery voltage detection • Support sleep mode by external chip select pin Application Clamp-on meter Digital multi-meter ver 2.8 1 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK Pin Assignment 2 3 4 5 6 D C BUFH CAZH NC CL+ CLCIL CAZL BUFL RAZ OHMC3 OHMC2 OHMC1 VRH VA+ VAEXTSRC NC NC OR1 VR5 VR4 VR3 VR2 OVSG VR1 NC NC NC NC NC NC NC NC NC NC FREQ STBEEP CPKIN PMAX PMIN LPFOUT LPC3 LPC2 LPC1 R1K R9K NC NC NC NC ES51995 D 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C B OVX OVH OVH1 NC NC NC NC NC NC NC SGND IVSH IVSL ADP OPINOPIN+ OPOUT ACVL ACVH ADI ADO TEST5 CACA+ OHMC4 B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CIH CHCH+ AGND AGND DGND V+ V+ uPVCC VVLBAT CC+ SDATA SCLK DATA_new NC BZOUT IO_CTRL CS OSC1 OSC2 NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 A 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A 1 ver. 2.8 2 3 4 2 5 6 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK Pin Description Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol BUFH CAZH NC CL+ CLCIL CAZL BUFL RAZ OHMC3 OHMC2 OHMC1 VRH VA+ Type O O IO IO O O O O O O O O I 15 VA- I 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 EXTSRC NC NC OR1 VR5 VR4 VR3 VR2 OVSG VR1 OVX OVH OVH1 NC NC NC NC NC NC NC SGND IVSH IVSL ADP OPINOPIN+ OPOUT ACVL I O O O O O O I I O O G I I I I I O O 44 ACVH O 45 46 47 48 49 ADI ADO TEST5 CACA+ I O O IO IO ver. 2.8 Description High-speed buffer output pin. Connect to integral resistor. High-speed auto-zero capacitor connection. Not connected Positive connection for reference capacitor of high-resolution A/D. Negative connection for reference capacitor of high- resolution A/D. High-resolution integrator output. Connect to integral capacitor. High-resolution auto-zero capacitor connection. High-resolution Buffer output pin. Connect to integral resistor Buffer output pin in AZ and ZI phase. Filter capacitor connection for resistance mode. Filter capacitor connection for resistance mode. Filter capacitor connection for resistance mode. Output of band-gap voltage reference. Typically –1.23V De-integrating voltage positive input. The input should be higher than VA-. De-integrating voltage negative input. The input should be lower than VA+. External source input available for Res/Diode/ADP mode Not connected Not connected Reference resistor connection for 600.0Ω range Voltage measurement ÷10000 attenuator(1000V) Voltage measurement ÷1000 attenuator(600.0V) Voltage measurement ÷100 attenuator(60.00V) Voltage measurement ÷10 attenuator(6.000V) Sense low voltage for resistance/voltage measurement Measurement Input. Connect to a precise 10MΩ resistor. Sense input for resistance/capacitance measurement Output connection for resistance measurement Output connection1 for resistance measurement (optional) Not connected Not connected Not connected Not connected Not connected Not connected Not connected Signal Ground. Current measurement input for 6000μA, 600mA and 60A modes. Current measurement input for 600μA, 60mA. Measurement input in ADP mode. Independent operational amplifier negative input Independent operational amplifier positive input Independent operational amplifier output DC signal low input in ACV/ACA mode. Connect to negative output of external AC to DC converter. DC signal high input in ACV/ACA mode. Connect to positive output of external AC to DC converter. Negative input of internal AC-to-DC OPAMP. Output of internal AC-to-DC OPAMP. Buffer output of OVSG Negative auto-zero capacitor connection for capacitor measurement Positive auto-zero capacitor connection for capacitor measurement 3 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 OHMC4 NC NC NC NC R9K R1K LPC1 LPC2 LPC3 LPFOUT PMIN PMAX CPKIN STBEEP O O O O O O O O O I O 65 66-77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 FREQ NC OSC2 OSC1 CS IO_CTRL BZOUT TEST DATA_NEW SCLK SDATA C+ CLBAT VVuPVCC V+ V+ DGND AGND AGND CH+ CHCIH I O I I I I O I IO O O I P P P O O G G G IO IO O ver. 2.8 Filter capacitor connection for resistance mode. Not connected Not connected Not connected Not connected Connect to a precise 9KΩ resister for capacitor measurement. Connect to a precise 1KΩ resister for capacitor measurement. Capacitor C1 connection for internal low-pass filter Capacitor C2 connection for internal low-pass filter Capacitor C3 connection for internal low-pass filter Capacitor C1 connection for internal low-pass filter Minimum peak hold output Maximum peak hold output. Bypass capacitor for peak mode Fast low-impedance sensed output for CONT./Diode mode Build-in a internal comparator for OVX pin. Frequency counter input, offset V-/2 internally by the chip. Not connected Crystal oscillator output connection Crystal oscillator input connection Set to high to enable ES51995. Set to low to enter sleep mode MPU I/O level LOW setting. Connect to DGND or V-. Buzzer frequency output. Normal low state. Test mode used. Not connected New ADC data ready Serial clock input Serial data input/output Positive capacitor connection for on-chip DC-DC converter. Negative capacitor connection for on-chip DC-DC converter. Low battery configuration input. Negative supply voltage. Negative supply voltage. Switch 5 for function selection. Output of on-chip DC-DC converter. Output of on-chip DC-DC converter. Digital ground. Analog ground. Analog ground. Positive connection for reference capacitor of high-speed A/D. Negative connection for reference capacitor of high-speed A/D. High-speed integrator output. Connect to integral capacitor. 4 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK Absolute Maximum Ratings Characteristic Supply Voltage (V- to AGND) Analog Input Voltage & EXTSRC pin V+ AGND/DGND Digital Input (IO_CTRL=V-) Power Dissipation. Flat Package Operating Temperature Storage Temperature Rating -4V V- -0.6 to V+ +0.6 V+ ≥ (AGND/DGND+0.5V) AGND/DGND ≥ (V- -0.5V) V- -0.6 to uPVCC+0.6 500mW 0℃ to 70℃ -55℃ to 125℃ Electrical Characteristics TA=25℃, V- = -3.0V Parameter Power supply Operating supply current In DCV mode Symbol Test Condition VIDD Normal operation ISS In sleep mode SADC2 Voltage roll-over error 10MΩ input resistor FADC3 Voltage roll-over error 10MΩ input resistor Best case straight line Best case straight line VA+-VA- = 200mV VA+-VA- = 200mV SADC2 voltage nonlinearity NLV1 FADC3 voltage nonlinearity NLV2 Voltage full scale range of SADC2 Voltage full scale range of FADC3 Input Leakage for VR1 input Zero input reading Band-gap reference voltage VRH Open circuit voltage for 600Ω range measurement Open circuit voltage for other Ω measurement Between V- pin and CS Internal pull-high to 0V current AC frequency response at 6.000V range OP unity gain bandwidth OP slew rate at unity gain OP input offset voltage OP input bias current OP input common mode voltage range 3dB frequency for LPF4 active ver. 2.8 10MΩ input resistor 100KΩ resistor between VRH and AGND GB SR VIO IB ±1% ±5% CL=10pF RL=10MΩ VICR f3dB 3dB=Full (ADP) 3dB=10k (ADP) 3dB=1k (ADP) 5 Min. -2.8 — — — Typ. -3.0 2.8 1 — Max -3.2 3.2 3 Units V mA µA ±0.1 %F.S1 — — ±0.5 %F.S1 — — ±0.1 %F.S1 — — ±1.0 %F.S1 — — -10 -000 600 600 1 000 630 — 10 +000 mV mV pA Count -1.30 -1.22 -1.14 V — V- — V — VRH — V — 1.2 — µA — — — — — — 40-400 400-2000 200 3.5 0.1 10 — — — — — — kHz V/us mV pA — +2 — V 100 — — — 10 1 — — — kHz kHz kHz HZ 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK LBAT vs. V- — — — 2.15 2.03 1.83 — — — V V V Peak-hold mode pulse width ACIN =40 ~ 400Hz — 1000 — us STBEEP comparator in Diode mode OVX to SGND — +9 — mV STBEEP comparator in Cont. mode OVX to SGND — -7 — mV HCF detection voltage VR2-VR5 — 1100 — mV Multi-level low battery detector Vt1 Vt2 Vt3 Frequency input sensitivity (FREQ) Fin Square wave with Duty cycle 40-60% 500 — — mVp Frequency input sensitivity (FREQ) Fin Sine wave 400 — — mVrms 100KΩ resister Between VRH 0℃<TA<70℃ — 50 — ppm/℃ -2.5 — 2.5 %F.S -3 — 3 counts Reference voltage temperature coefficient TCRF Capacitance measurement Accuracy5 6.0nF – 60mF Note: 1. Full Scale (6000 counts for SADC and 600 counts for FADC) 2. SADC = High resolution ADC (slow speed) 3. FADC = High speed ADC (lower resolution) 4. ES51995 built-in 3rd order low pass filter available for AC mode 5. Gain calibration is necessary for higher accuracy ver. 2.8 6 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK AC electrical characteristics Parameter Symbol Min. Typ. Max. Unit SCLK clock frequency SCLK clock time “L” SLCK clock time “H” SDATA output delay time SDATA output hold time Start condition setup time Start condition hold time Data input setup time Data input hold time Stop condition setup time SCLK/SDATA rising time SCLK/SDATA falling time Bus release time EOC setup time in read mode EOC hold time in read mode fSCLK tLOW tHIGH tAA tDH tSU.STA tHD.STA tSU.DAT tHD.DAT tSU.STO tR tF tBUF tSU.EOC tHD.EOC 4.7 4.0 0.1 100 4.7 4.0 200 0 4.7 4.7 0 0 - 100 3.5 1.0 0.3 - kHz - - us ns us ns us ns ns MPU I/O timing diagram SCLK SDATA IN SDATA OUT ver. 2.8 7 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK Function Description 1. MPU serial I/O function overview 1.1 Introduction ES51995 configures a 3-wire serial I/O interface to external microprocessor unit (MPU). The SDATA pin is bi-directional and SCLK & DATA_NEW are unilateral. The SDATA pin is configured by open-drain circuit design. The DATA_NEW is used to check the data buffer of ADC ready or not. When the ADC conversion cycle is finished, the DATA_NEW pin will be pulled high until MPU send a valid read command to ES51995. After the first ID byte is confirmed, the DATA_NEW will be driven to low until the next ADC conversion finished again. The data communication protocol is shown below. The write protocol is configured by an ID byte with four command bytes. The read protocol is configured by an ID byte with ten data bytes. Write command: ID byte, Write control byte1, Write control byte2, Write control byte3, Write control byte4 START BIT 1 1 0 0 1 0 B U Z 0 A C K A C K A C K A C K A C K STOP BIT WRITE Read command: ID byte, Read data byte1, Read data byte2 ~ Read data byte9, Read data byte10 START BIT 1 1 0 0 1 A C K B U 0 Z 1 A C K A C K A C K READ A C K N A K STOP BIT DATA_NEW ADC data ready ID code confirmed Next ADC data ready ID code SDATA 1 1 0 0 1 0 1 Read command SCLK Start bit ver. 2.8 Stop bit 8 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK The ID byte of ES51995 is header of “110010” followed by a buzzer on/off control bit and R/W bit. The start/stop bit definition is shown on the diagram below. 1.2 Read/Write command description The write command includes one ID byte with four command bytes. If the valid write ID code is received by ES51995 at any time, the write command operation will be enabled. The next table shows the content of write command. Byte Bit7 Bit6 Bit5 Bit4 Bit3 ID W1 W2 W3 W4 1 SHBP B0 AC PEAK 1 F3 B1 0 PCAL 0 F2 B2 0 0 0 F1 C0 EXT 0 1 F0 C1 FS60 0 Bit2 0 Q2 FQ2 LPF1 OP0 Bit1 BUZ Q1 FQ1 LPF0 OP1 Bit0 R/W=0 Q0 FQ0 FRES EXT_ADP Auxiliary low-resistance detection control bit for Continuity and Diode modes: SHBP Measurement function control bit: F3/F2/F1/F0 Range control bit for V/A/R/C modes: Q2/Q1/Q0 Range control bit for Freq mode: FQ2/FQ1/FQ0 Buzzer frequency selection: B2/B1/B0 Buzzer driver ON/OFF control bit: BUZ ADC conversion rate control bit: C1/C0 AC mode control enable bit: AC PEAK/Calibration mode enable bit: PEAK/PCAL 3dB BW for low-pass-filter selection: LPF1/LPF0 External source for Diode mode control bit: EXT OP configuration control bit: OP1/OP0 Frequency mode input resistance control bit: FRES ADP mode control bit: EXT_ADP ADP DC mode full scale control bit: FS60 ver. 2.8 9 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK The read command includes one ID byte with ten data bytes. When DATA_NEW is ready1, MPU could send the read data command to get the result of ADC conversion (D0/D1/D2/D3)2 or status flag from ES51995. The next table shows the content of read command. Byte Bit7 Bit6 Bit5 Bit4 ID R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 1 ASIGN HF D0:3 D0:11 D1:0 D1:8 D2:6 D2:14 D3:3 D3:11 1 BSIGN LF D0:4 D0:12 D1:1 D1:9 D2:7 D2:15 D3:4 D3:12 0 PMAX LDUTY D0:5 D0:13 D1:2 D2:0 D2:8 D2:16 D3:5 D3:13 0 PMIN STA1 D0:6 D0:14 D1:3 D2:1 D2:9 D2:17 D3:6 D3:14 Bit3 1 BTS0 F_FIN D0:7 D0:15 D1:4 D2:2 D2:10 D2:18 D3:7 D3:15 Bit2 0 BTS1 D0:0 D0:8 D0:16 D1:5 D2:3 D2:11 D3:0 D3:8 D3:16 Bit1 BUZ STA0 D0:1 D0:9 D0:17 D1:6 D2:4 D2:12 D3:1 D3:9 D3:17 Bit0 R/W=1 ALARM D0:2 D0:10 D0:18 D1:7 D2:5 D2:13 D3:2 D3:10 D3:18 1 Note: DATA_NEW will be active with D1 data updated when one fast ADC (FADC) conversion finished. If MCU access slow ADC output only, ten FADC conversion cycle delay is necessary. DATA_NEW for frequency or capacitance mode will be active when D0 or D3 data ready. 2 Note: D0/D1/D2/D3 all are binary code format. D0 is SADC output and D1 is FADC output The ADC data output for measurement mode: F3/F2/F1/F0 F3 F2 F1 F0 Measurement mode 0 0 0 0 V mode 0 0 0 1 ACV + Hz mode 0 0 1 0 A mode 0 0 1 1 ACA + Hz mode D0(0:18), D1(0:9), D3(0:18) 0 1 0 0 Resistance mode D0(0:18), D1(0:9) 0 1 0 1 Continuity mode D0(0:18), D1(0:9) 0 1 1 0 Diode mode D0(0:18), D1(0:9) 0 1 1 1 F + duty mode 1 0 0 0 Capacitance Mode 1 0 0 1 ADP mode 1 0 1 0 ADP + Hz mode ver. 2.8 10 Read data bytes D0(0:18), D1(0:9) D0(0:18), D1(0:9), D3(0:18) D0(0:18), D1(0:9) D0(0:18), D2(0:18), D3(0:18) D0(0:18) D0(0:18), D1(0:9) D0(0:18), D1(0:9), D3(0:18) 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK Buzzer frequency selection: B2/B1/B0 B2 B1 B0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Buzzer frequency 1.00kHz 1.33kHz 2.00kHz 2.22kHz 2.67kHz 3.08kHz 3.33kHz 4.00kHz Set B2-B0 properly to get the target frequency. Use BUZ control bit to enable/disable the BUZOUT (pin82) driver output. If MPU control BUZ only, it is available to set ID byte with ending of stop bit. START BIT A R C 1 1 0 0 1 0 0 /W K STOP BIT Buzzer OFF START BIT R 1 1 0 0 1 0 1 /W STOP BIT Buzzer ON ADC conversion rate selection: C1/C0 C1 C0 SADC Conversion Time (High resolution ADC) 0 0 500ms 0 1 300ms 1 0 250ms 1 1 200ms FADC Conversion Time (High speed ADC) 50ms 30ms 25ms 20ms SADC Line noise rejection 50/60Hz 50Hz 60Hz 50Hz Set C1-C0 to change the target conversion rate for SADC & FADC simultaneously. ver. 2.8 11 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK Status flags for measurement mode: ● = function available Measurement mode V mode ACV + Hz mode A mode ACA + Hz mode Res. mode Cont. mode Diode mode F + duty mode Cap. Mode ADP mode ADP + Hz mode Measurement mode V mode V + Hz mode A mode A + Hz mode Res. mode Cont. mode Diode mode F + duty mode Cap. Mode ADP mode ADP + Hz mode ASIGN ● BSIGN ● ● ● ● ● ● ● HF LF ● PMAX ● ● ● ● PMIN ● ● ● ● ● ● STA0 BTS0 ● ● ● ● ● ● ● ● ● ● ● STA1 BTS1 ● ● ● ● ● ● ● ● ● ● ● F_FIN ● ● LDUTY ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ALARM ● ● ● ● ● Description of status flags: ASIGN: Sign bit of SADC output (-1 * D0 if ASIGN=1) BSIGN: Sign bit of FADC output (-1 * D1 if BSIGN=1) PMAX: Indicates D0 output is the voltage of the peak maximum capacitor (pin62) PMIN: Indicates D0 output is the voltage of the peak minimum capacitor (pin61) BTS0/BTS1: Multi-level battery voltage indication ALARM: Large capacitor indication/High crest factor signal detection in ACV mode HF: Higher frequency indication for Hz mode LF: Lower frequency indication for Hz mode LDUTY: Low duty indication for Hz + duty mode STA0/STA1: divider indication for Hz mode STA0: Status flag for capacitor discharging mode F_FIN: Measurement cycle finished for Hz mode ver. 2.8 12 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 1.3 Power & I/O level selection The ES51995 provide a flexible I/O level setting for different MPU system configuration. The uP_VCC should be connected to the same potential of external Vcc of MCU. The uP_VCC is allowed to be set between DGND ~ V+. The IO_CTRL pin selects the Vss level of MCU. If IO_CTRL is set to DGND, the Vss level of MCU is the same as DGND. If IO_CTRL is set to V-, the Vss level of MCU is the same as V-. ver. 2.8 13 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 2. Operating Modes 2.1. Voltage Measurement MPU send write command to select the voltage measurement function. The Hz mode measurement is available to be enabled with the ACV function (set AC bit to 1) simultaneously. The measured signal is applied to VR1 terminal (pin25) through 10MΩ. See the next table of function command: F3 F2 F1 F0 AC Measurement mode Read data bytes 0 0 0 0 0 DCV mode D0(0:18), D1(0:9) 0 0 0 0 1 ACV mode D0(0:18), D1(0:9) 0 0 0 1 1 ACV + Hz mode D0(0:18), D1(0:9), D3(0:18) Note1: D0/D1/D3 all are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively. Note2: See PEAK mode (section 2.10) also. Range control for voltage mode (ACV/DCV) Q2 0 0 0 0 1 Q1 0 0 1 1 0 Q0 0 1 0 1 0 Full Scale Range 600.0mV 6.000V 60.00V 600.0V 1000V Divider Ratio 1 1/10 1/100 1/1000 1/10000 Resister Connection VR1 (10MΩ) VR2 (1.111MΩ) VR3 (101kΩ) VR4 (10.01kΩ) VR5 (1kΩ) Frequency range control for ACV+Hz mode FQ2 FQ1 FQ0 0 0 0 0 0 1 0 1 0 0 1 1 Full Scale Range 60.00Hz 600.0Hz 6.000kHz 60.00kHz Note: See frequency mode (section 2.8) also ALARM bit at voltage mode is used for high crest factor (HCF) signal detection. If MPU check the ALARM status flag active when data and range are stable, it should consider the making the existing range up to avoid the signal clamping saturation caused by HCF signal. There is higher peak voltage with lower RMS value for HCF signal. So if the range is up according to the ALARM bit, MCU should set the lower under-limit counts temporarily to avoid the ranging unstable for this case. ver. 2.8 14 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 2.2 Current measurement MPU send write command to select the current measurement function. The Hz mode measurement is available to be enabled with the ACA function (set AC bit to 1) simultaneously. The measured signal is applied to IVSL/IVSH terminals (pin37-38). See the next table of function command: F3 F2 F1 F0 AC Measurement mode Read data bytes 0 0 1 0 0 DCA mode D0(0:18), D1(0:9) 0 0 1 0 1 ACA mode D0(0:18), D1(0:9) 0 0 1 1 1 ACA + Hz mode D0(0:18), D1(0:9), D3(0:18) Note1: D0/D1/D3 all are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively. Note2: See PEAK mode (section 2.10) also. Range control for current mode (ACA/DCA) Q2 0 0 Q1 0 0 Q0 0 1 Full Scale Range 300mV 6000counts 300mV 6000counts Input terminal IVSL IVSH Current measurement mode configuration example: (max. voltage drop 300mV) 90K 600.0 / 6000uA 60.00 / 600.0mA 49.5 4 uA / mA V- V+ 10K 2 TL061 + 100K 6 IVSL 5 3 7 FUSE 1 FUSE 1 V+ 100K 6A/ 20A 0.1uF A V- 1 V- 0.495 0.1uF 1.5K Zero Offset 0.005 100K 1 COM 0.005 0.045 0.45 4.5 A mA uA ver. 2.8 45 450 (max voltage drop = ~ 1V) AGND SGND 20A 6A IVSH mA mA uA uA 100K 100K IVSH IVSL 15 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK Frequency range control for ACA+Hz mode FQ2 FQ1 FQ0 0 0 0 0 0 1 0 1 0 0 1 1 Full Scale Range 60.00Hz 600.0Hz 6.000kHz 60.00kHz Note: See frequency mode (section 2.8) also. 2.3 Low pass filter (LPF) mode for ACA/ACV mode A 3rd order low pass filter with is built in ES51995. The 3dB bandwidth of the low pass filter could be selectable by MPU. The LPF mode is active when the LPF control bit is set to be active. When PEAK mode is active, the LPF mode will be disabled temporarily until the PEAK mode is cancelled. The LPF mode is allowed to be enabled in F + duty mode to reject high-frequency noise for sine wave input, but the 3dB will be fixed at 10kHz only. LPF1 LPF0 Low pass filter effect 0 0 Disable 0 1 3dB = 1kHz 1 0 3dB = 10kHz 1 1 3dB > 100kHz 2.4 Resistance Measurement MPU send write command to select the resistance measurement function. F3 F2 F1 F0 Measurement mode 0 1 0 0 Resistance mode Read data bytes D0(0:18), D1(0:9) Note1: D0/D1 both are binary format. ASIGN/BSIGN bits are ignored. Range control for resistance mode Q2 0 0 0 0 1 1 ver. 2.8 Q1 0 0 1 1 0 0 Q0 0 1 0 1 0 1 Full Scale Range 600.0Ω 6.000KΩ 60.00KΩ 600.0KΩ 6.000MΩ 60.00MΩ Relative Resistor OR1 VR5 VR4 || VR1 VR3 || VR1 VR2 || VR1 VR1 16 Equivalent value 100Ω 1KΩ 10KΩ 100KΩ 1MΩ 10MΩ 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 2.5 Capacitance Measurement MPU send write command to select the capacitance measurement function. F3 F2 F1 F0 Measurement mode 1 0 0 0 Capacitance mode Read data bytes D0(0:18) Note1: D0 is binary format. ASIGN bit is ignored. Range control for capacitance mode Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 Full Scale Range 6.000nF 60.00nF 600.0nF 6.000uF 60.00uF 600.0uF 6.000mF 60.00mF Relative Resistor OVX pin VR R9K / R1K R9K / R1K R9K / R1K R9K / R1K R9K / R1K Measurement Period 0.5 sec 0.5 sec 1.25 sec 0.4 sec max. 0.5 sec max. 1.0 sec max. 1.35 sec max. 6.75 sec max. ALARM bit at capacitance mode is used for increasing the ranging speed. If MPU check the ALARM=1 at lower range, it could set the next range to 6.000uF directly and the ADC output should be ignored. STA0 status bit is used for detection of DUT capacitor voltage. If STA0=1, the internal capacitor discharging mode is active and the capacitance measurement is inhibited. It is recommended to discharge the DUT capacitor externally. 2.6 Continuity Check measurement MPU send write command to select the continuity measurement function. F3 F2 F1 F0 Measurement mode 0 1 0 1 Continuity mode Read data bytes D0(0:18), D1(0:9) Note1: D0/D1 both are binary format. ASIGN/BSIGN bits both are ignored. Continuity mode shares the same configuration with 600.0Ω resistance measurement circuit and support the low-resistance detection. If the STBEEP output (pin64) is low, it means the low-resistance status is detected (It means the OVX terminal voltage less than -7mV). It could be faster than the FADC result, so MPU could monitor the STBEEP output and FADC (D1) data output make the high speed detection for short circuit detection. Set SHBP=1 to enable the built-in buzzer driving automatically when STBEEP is active. ver. 2.8 17 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 2.7 Diode Measurement MPU send write command to select the diode measurement function. F3 F2 F1 F0 Measurement mode 0 1 1 0 Diode mode Read data bytes D0(0:18), D1(0:9) Note1: D0/D1 both are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively. Diode measurement mode shares the same configuration with 6.000V voltage measurement circuit and support the low-resistance detection. If the STBEEP output (pin64) is low, it means the low-resistance status is detected (It means the OVX terminal voltage less than 9mV). It could be faster than the FADC result, so MPU could monitor the STBEEP output and FADC (D1) data output make the high speed detection for short circuit detection. Set SHBP=1 to enable the built-in buzzer driving automatically when STBEEP is active. The default source voltage at diode mode is the same as V+ potential. MPU could set the control bit EXT=1 to change the source voltage to external source. The external voltage source (positive or negative) input applied from EXTSRC (pin16). The available external source range should be from V+ to V-. ver. 2.8 18 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 2.8 Frequency/duty cycle mode measurement The default typical input impedance of frequency with duty cycle mode is 1MΩ. The MPU could set control bit FRES=1 to change the input impedance down to 100kΩ. MPU send write command to select the frequency/duty cycle measurement function. F3 F2 F1 F0 Measurement mode 0 1 1 1 Hz + Duty mode Read data bytes D0(0:18), D2(0:18), D3(0:18) Note1: D0/D2/D3 all are binary format. ASIGN bit is ignored. Note2: Set LPF1 = 1 to enable the smooth function for sine wave input automatically Range control for frequency mode FQ2 0 0 0 0 1 1 1 FQ1 0 0 1 1 0 0 1 FQ0 0 1 0 1 0 1 0 Full Scale 60.00Hz 600.0Hz 6.000KHz 60.00KHz 600.0KHz 6.000MHz 60.00MHz Available minimum frequency input (Depends on ADC conversion rate setting) C1 0 0 1 1 C0 0 1 0 1 FMIN(AC+Hz mode) FMIN(Hz+Duty mode) 4.00Hz 6.00Hz 4.00Hz 8.00Hz 10.00Hz Frequency & duty cycle mode computed by D0/D2/D3 (if F_FIN=1) Flag STA0=0 STA0=1 Range STA1=1 STA1=0 60.00Hz FREQ=100000000/D3 FREQ=400000000/D3 FREQ=800000000/D3 600.0Hz FREQ=10000000/D3 FREQ=40000000/D3 FREQ=160000000/D3 6.000KHz FREQ=2000000/D3 FREQ=32000000/D3 FREQ=256000000/D3 60.00KHz FREQ=200000/D3 FREQ=25600000/D3 FREQ=204800000/D3 600.0KHz 6.000MHz FREQ = D0 60.00MHz Status Flag Duty cycle (<60kHz) ver. 2.8 LDUTY=1 10000-D2*10000/D3 19 LDUTY=0 D2*10000/D3 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK The status flag F_FIN indicate the frequency input signal available (> FMIN) or not. If the computed result less than FMIN, the frequency/duty cycle readings should be set to zero. The status flags HF & LF are used for fast judgment of proper range. If frequency input is larger than 7 kHz, HF will be active. If frequency input is floating or frequency detected too low, LF will be active. Auto range consideration for MPU by using Status Flags of frequency mode Flag F_FIN=0 F_FIN=1 F_FIN=1 Range LF=0 LF=1* HF=LF=0 HF=1** 60.00Hz Hz/Duty=0 Set range to 600.0Hz 60.00kHz range 6.000KHz Change range Data and Range depends on data 60.00KHz Set range to is not necessary Change range computed 600.0KHz 60.00Hz range to be updated depends on data 6.000MHz computed 60.00MHz *Note: LF=1 @ 60Hz range implies the frequency is not available to be measured. The Hz/Duty readings should be set to zero. **Note: When ACV+Hz/ACA+Hz/ADP+Hz mode is selected, the HF status should be ignored. Change range depends on data calculation result. Duty cycle mode range (Input sensitivity > 2Vpp @ duty cycle= 5.0% or 95.0%) Freq. range Duty range 60.00Hz 600.0Hz 6.000KHz 10.0% - 90.0% 60.00KHz 20.0% – 80.0% ver. 2.8 5.0% - 95.0% 20 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 2.9 ADP mode MPU send write command to select the ADP mode measurement function. The Hz mode measurement is available to be enabled with the ADP AC function (set AC bit to 1) simultaneously. The measured signal is applied to ADP terminal (pin39). The signal full scale is 600mV for DC mode and 600mVrms for AC mode. The FS60 control bit is used for ADP DC mode. When FS60=1, the full scale will be change from 600mV to 60mV. It means the resolution will be improved to 0.01mV, but the ADC conversion rate will be reduced to 0.9 /sec. See the next table of function command: F3 F2 F1 F0 AC Measurement mode Read data bytes 1 0 0 1 0 ADP DC mode D0(0:18), D1(0:9) 1 0 0 1 1 ADP AC mode D0(0:18), D1(0:9) 1 0 1 0 1 ADP + Hz mode D0(0:18), D1(0:9), D3(0:18) Note1: D0/D1/D3 all are binary format. ASIGN/BSIGN are the sign bit of D0/D1, respectively. Note2: See PEAK mode (section 2.10) also. Frequency range control for ADP+Hz mode FQ2 FQ1 FQ0 0 0 0 0 0 1 0 1 0 0 1 1 Full Scale Range 60.00Hz 600.0Hz 6.000kHz 60.00kHz Note: See frequency mode (section 2.8) also If MPU set the control bit EXT_ADP=1, the voltage on EXTSRC pin could be switched to ADP terminal internally. It is helpful for a voltage pulled application of ADP mode. External source pull high or low EXT_ADP ADC IN+ ADP_IN ADC IN- SGND ver. 2.8 21 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 2.10 Peak-hold measurement mode ES51995 provides a peak hold function to capture the real peak value for voltage or current measurement mode. In a case of a 1V sine wave input voltage, the peak hold function gets a maximum peak value of 1.414V and minimum peak value of –1.414V ideally. Set the control bit PEAK=1 to force the ES51995 entering PEAK measurement mode. Peak Hold function is divided into two parts of peak maximum and peak minimum conversion. High resolution SADC performs peak maximum and peak minimum conversion in turn, not at the same time. The status flag PMAX or PMIN shows which type the peak value is. If PMAX=1(PMIN=1), the SADC output D0 is the conversion data on PMAX (PMIN) terminals (pin 61/62). The MPU should make the comparison procedure to get the maximum value of PMAX data and minimum value of PMIN data. Peak calibration mode At PEAK-Hold measurement mode, the offset voltage of internal operation amplifier will cause an error. To obtain a more accurate value, the offset error must be canceled. ES51995 provides the peak calibration feature to remove the influence on accuracy by internal offset voltage. Set the control bit PCAL=1 to enter peak calibration mode. When PCAL mode is active, the SADC of ES51995 will output the calibration value of peak maximum and minimum conversion in turn. The offset values should be memorized respectively and deducted from the data of PMAX/PMIN at the normal peak measurement mode. Status indication ADC data Set PCAL=1 or PEAK=1 PMAX=1, PMIN=0 PMAX=0, PMIN=1 VPMAX.C VPMIN.C VPMAX.C and VPMIN.C are not the real-time value of peak-hold voltage. They are the voltage stored on terminal capacitor (pin61-62). Because the capacitor will be self-discharging, so MCU need to compare the VPMAX.C & VPMIN.C respectively and memorize the maximum and minimum peak values in turn. ver. 2.8 22 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 2.11 Sleep Set CS pin (pin 80) to logic low to make the ES51995 entering the sleep mode. The current consumption will be less than 3uA typically. Set CS pin to logic high or kept floating, the ES51995 will return to normal operation. 2.12 Multi-level battery voltage indication The ES51995 is built-in a comparator for batter voltage indication. The voltage is applied to LBAT pin (pin 89) vs. V- terminal. MPU could check the status bit BTS1/BTS0 and monitor the LBAT voltage status. Battery voltage VLBT > Vt1 Vt2 < VLBT < Vt1 Vt3 < VLBT < Vt2 VLBT < Vt3 BTS1 1 1 0 0 BST0 1 0 1 0 Low battery configuration for 9V/1.5V*4/1.5V*3 battery Low battery test circuit (a) Low battery test circuit (b) 6V 9V BA 360K TT BA LBAT 0.1u 270K 470K TT AGND V- 180K 0V LBAT 0.1u AGND V- 0V Low battery test circuit (c) 4.5V BA 360K TT LBAT 0.1u 470K AGND V- 0V ver. 2.8 23 12/01/12 ES51995(6000counts) DMM Analog front end with PEAK 2.13 Independent OPAMP ES51995 is built-in an independent OPAMP with low drift offset using for general purpose. MPU could control the OP1/OP0 to change the OPAMP configuration: OP1 OP0 OPAMP configuration 0 0 Normal 0 1 OP disable 1 0 Unity gain buffer 1 1 Zero calibration Independent OPAMP configuration Normal operation OPIN- - OPIN+ + OPOUT Zero offset calibration OPIN- - OPIN+ + OPOUT Unity gain operation ver. 2.8 OPIN- - OPIN+ + OPOUT 24 12/01/12 1 C7 100nF R5 R9 220nF + 47nF C13 V- 220nF 7.5V V + ZR2 R4 V1- 5.6V Regulator DC3.0V ZR1 10uF 0.1uF 0.1uF 10uF 0 C2 R1 C1 100 1K 10.01K 101K 1.111M OVSG 10M U1 BUFH CAZH NC CL+ CLCIL CAZL BUFL RAZ OHMC3 OHMC2 OHMC1 VRH VA+ VAEXTSRC NC NC OR1 VR5 VR4 VR3 VR2 OVSG VR1 V+ 2 V1- ES51995 Y1 4MHz Option C29 5pF NC NC NC NC NC NC NC NC NC NC FREQ STBEEP CPKIN PMAX PMIN LPFOUT LPC3 LPC2 LPC1 R1K R9K NC NC NC NC C3 22nF 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C22 1uF STBEEP C16 C17 C14 C15 R1K R9K R32 9K + R26 1K 3 R12 VDD SDATA 47K SCLK DATA_new C20 STBEEP CS Q1 200 VR3 R33 15K Q2 A4 Date: File: Size Title R13 Q3 MPU 2.2uF 10K + C25 1uF R35 ADO 4 uPVCC (DGND or +3V) 4 56K Revision Ver : 9 C24 0.1uF ACVL ACVH ADI TEST5 VDD R37 R36 56K R34 15K JP1 1 2 FIN C23 4.7uF V- or DGND C26 1uF VSS Q4 2.2K PTC 10K 1N4148 D2 Demo Board schematic Number 11-Nov-2011 F:\Protelfile\KA029\KA029.ddb Sheet of Drawn By: ES51995 Schematic Circuit (AVG) 1N4148 D1 C18 22pF 10nF 10nF 470pF +/- 10% C19 3.3nF +/- 10% 100pF +/- 10% 3 + 2 + Close toIC 680pF 22nF 1 2 3 4 C11 220nF 5 6 7 220K 8 9 0 10 11 12 13 56K 14 VA+ 15 VAEXTSRC 16 17 18 19 20 21 22 23 24 25 470K 22nF Metallized Polypropylene Film Capacitor : C7 Metallized Polyester Capacitor : C1 , C13 , C11 , C16 , C17 C16 C17 C9 470nF R18 R19 R20 R21 R22 R23 C21 OVH VR2 50K R11 C10 VR1 500 C27 R2 220pF 11K C12 4.7uF SW1 SW_RC 1K OVX R24 OVH1 R17 R14 2.2K PTC 1K Q8 Q7 R25 Q5 Q6 R16 2.2K PTC 180K C6 C28 C18 + JP2 1 2 VIN Insulation R+ + D C B A 1 OPINOPIN+ OPout ACVL ACVH ADI ADO TEST5 470nF +/- 10% D C B A 12/01/12 25 ver. 2.8 R6 R7 R8 IVSH 100K IVSL 100K ADP 100K Close to IC Close to IC 100 99 C4 10nF 98 97 96 95 94 93 92 VCC 91 90 89 LBAT9 88 C5 470nF 87 86 SDA 85 SCL 84 DATA_new 83 82 BUZOUT 81 VSS 80 CS 79 78 77 76 CIH CHCH+ AGND AGND DGND V+ V+ uPVCC VVLBAT CC+ SDATA SCLK DATA_new NC BZOUT IO_CTRL CS OSC1 OSC2 NC NC OVX OVH OVH1 NC NC NC NC NC NC NC SGND IVSH IVSL ADP OPINOPIN+ OPOUT ACVL ACVH ADI ADO TEST5 CACA+ OHMC4 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 C8 + ES51995(6000counts) DMM Analog front end with PEAK 3. Application Circuit 3.1 AVG circuit 1 + 220nF V- C7 R1 C2 C1 100 1K 10.01K 101K 1.111M OVSG 10M U1 BUFH CAZH NC CL+ CLCIL CAZL BUFL RAZ OHMC3 OHMC2 OHMC1 VRH VA+ VAEXTSRC NC NC OR1 VR5 VR4 VR3 VR2 OVSG VR1 V+ 2 V1- ES51995 Y1 4MHz Option C30 5pF NC NC NC NC NC NC NC NC NC NC FREQ STBEEP CPKIN PMAX PMIN LPFOUT LPC3 LPC2 LPC1 R1K R9K NC NC NC NC C3 22nF 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C22 1uF STBEEP C16 C17 C14 C15 R1K R9K R32 9K + SW2 ACV RMS R26 1K 3 R12 VDD 47K SDATA SCLK DATA_new Q2 R13 Q3 MPU 2.2uF 1 2 3 4 5 6 7 uPVCC (DGND or +3V) 4 VDD + VS JP1 1 2 FIN 14 13 12 11 10 9 8 10K + 4 + VS C26 10uF C27 + Revision Ver : 9 10uF - VS Close toIC ACVH V- or DGND - VS R33 200 + VSS Q4 2.2K PTC 500K C23 4.7uF U2 + VS Vin NC En NC - VS NC CAV dB COMMON RL BUF out BUF in Iout ES636 R34 + VS VR4 Demo Board schematic Number 11-Nov-2011 F:\Protelfile\KA029\KA029.ddb Sheet of Drawn By: ES51995 Schematic Circuit (TRMS) 200K 3.3nF +/- 10% 22pF C20 STBEEP CS Q1 200 C18 10nF 10nF 470pF +/- 10% C19 100pF +/- 10% VR3 500 + + VS C25 22uF R3 ADI Title Size A4 Date: File: - VS + C21 Close toIC 680pF 22nF 1 2 3 4 C11 220nF 5 6 7 220K 8 9 0 10 11 12 13 56K 14 VA+ 15 VAEXTSRC 16 17 18 19 20 21 22 23 24 25 470K 22nF Metallized Polypropylene Film Capacitor : C7 Metallized Polyester Capacitor : C1 , C13 , C11 , C16 , C17 0 47nF C13 7.5V V + ZR2 V1R10 5.6V Regulator DC3.0V ZR1 10uF 0.1uF 10uF 0.1uF C9 220nF + D C16 C17 C10 100nF R5 R9 R23 R18 R19 R20 R21 R22 R11 470nF VR1 500 C29 R2 220pF 11K JP2 C12 4.7uF C6 C28 C18 + 1 2 VIN Insulation R+ SW1 SW_RC OVH OVX 1K 50K R24 OVH1 VR2 180K R17 R14 2.2K PTC 1K Q7 R25 Q5 Q8 3 2.2uF C24 R16 2.2K PTC Q6 2 ACVH ADI C B A 1 470nF +/- 10% C8 OPINOPIN+ OPout R6 R7 R8 IVSH 100K IVSL 100K ADP 100K Close to IC Close to IC 100 10nF 99 C4 98 97 96 95 94 93 92 VCC 91 90 89 LBAT9 470nF 88 C5 87 86 SDA 85 SCL 84 DATA_new 83 82 BUZOUT 81 VSS 80 CS 79 78 77 76 CIH CHCH+ AGND AGND DGND V+ V+ uPVCC VVLBAT CC+ SDATA SCLK DATA_new NC BZOUT IO_CTRL CS OSC1 OSC2 NC NC OVX OVH OVH1 NC NC NC NC NC NC NC SGND IVSH IVSL ADP OPINOPIN+ OPOUT ACVL ACVH ADI ADO TEST5 CACA+ OHMC4 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 D C B A 12/01/12 26 ver. 2.8 + ES51995(6000counts) DMM Analog front end with PEAK 3.2 RMS circuit (ES636) ES51995(6000counts) DMM Analog front end with PEAK 4. Package Information 4.1 100L LQFP Outline drawing 4.2 Dimension parameters ver. 2.8 27 12/01/12