DAVICOM DM9010BIEP

DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
DAVICOM Semiconductor, Inc.
DM9010BI
Industrial-temperature 10/100 Mbps Single Chip
Ethernet Controller
With General Processor Interface
DATA SHEET
Preliminary
Version: DM9010BI-DS-P01
January 12, 2010
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
1
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
Content
1. GENERAL DESCRIPTION .............................................................................................................................................. 5
2. BLOCK DIAGRAM........................................................................................................................................................... 5
3. FEATURES ......................................................................................................................................................................... 6
4. PIN CONFIGURATION.................................................................................................................................................... 7
4.1 PIN CONFIGURATION I: WITH MII INTERFACE ................................................................................................................. 7
4.2 PIN CONFIGURATION II: WITH 32-BIT DATA BUS ............................................................................................................. 8
5. PIN DESCRIPTION........................................................................................................................................................... 9
5.1 MII INTERFACE ............................................................................................................................................................... 9
5.2 PROCESSOR INTERFACE .................................................................................................................................................. 9
5.3 EEPROM INTERFACE ....................................................................................................................................................11
5.4 CLOCK INTERFACE .........................................................................................................................................................11
5.5 LED INTERFACE ............................................................................................................................................................11
5.6 10/100 PHY/FIBER ....................................................................................................................................................... 12
5.7 MISCELLANEOUS .......................................................................................................................................................... 12
5.8 POWER PINS .................................................................................................................................................................. 13
5.9 STRAP PINS TABLE ......................................................................................................................................................... 13
6. VENDOR CONTROL AND STATUS REGISTER SET............................................................................................... 14
6.1 NETWORK CONTROL REGISTER (00H) .......................................................................................................................... 16
6.2 NETWORK STATUS REGISTER (01H).............................................................................................................................. 16
6.3 TX CONTROL REGISTER (02H) ..................................................................................................................................... 16
6.4 TX STATUS REGISTER I ( 03H ) FOR PACKET INDEX I..................................................................................................... 17
6.5 TX STATUS REGISTER II ( 04H ) FOR PACKET INDEX I I ................................................................................................. 17
6.6 RX CONTROL REGISTER ( 05H ) ................................................................................................................................... 17
6.7 RX STATUS REGISTER ( 06H ) ....................................................................................................................................... 18
6.8 RECEIVE OVERFLOW COUNTER REGISTER ( 07H )........................................................................................................ 18
6.9 BACK PRESSURE THRESHOLD REGISTER (08H) ............................................................................................................ 19
6.10 FLOW CONTROL THRESHOLD REGISTER (09H) ........................................................................................................... 19
6.11 RX/TX FLOW CONTROL REGISTER (0AH).................................................................................................................. 19
6.12 EEPROM & PHY CONTROL REGISTER (0BH) ........................................................................................................... 20
6.13 EEPROM & PHY ADDRESS REGISTER (0CH)............................................................................................................ 20
6.14 EEPROM & PHY DATA REGISTER (EE_PHY_L:0DH EE_PHY_H:0EH) ....................................................... 20
6.15 WAKE UP CONTROL REGISTER (0FH).......................................................................................................................... 20
6.16 PHYSICAL ADDRESS REGISTER (10H~15H) ................................................................................................................ 21
6.17 MULTICAST ADDRESS REGISTER (16H~1DH)............................................................................................................. 21
6.18 GENERAL PURPOSE CONTROL REGISTER (1EH)........................................................................................................... 21
6.19 GENERAL PURPOSE REGISTER (1FH) .......................................................................................................................... 21
6.20 TX SRAM READ POINTER ADDRESS REGISTER (22H~23H) ...................................................................................... 22
6.21 RX SRAM WRITE POINTER ADDRESS REGISTER (24H~25H) .................................................................................... 22
6.22 VENDOR ID REGISTER (28H~29H) ............................................................................................................................. 22
6.23 PRODUCT ID REGISTER (2AH~2BH) .......................................................................................................................... 22
6.24 CHIP REVISION REGISTER (2CH) ................................................................................................................................ 22
6.25 TRANSMIT CONTROL REGISTER 2 (2DH) .................................................................................................................... 22
6.26 OPERATION TEST CONTROL REGISTER (2EH) ............................................................................................................. 23
6.27 SPECIAL MODE CONTROL REGISTER (2FH) ................................................................................................................ 23
6.28 EARLY TRANSMIT CONTROL/STATUS REGISTER (30H) ............................................................................................... 23
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
2
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.29 TRANSMIT CHECK SUM CONTROL REGISTER (31H).................................................................................................... 24
6.30 RECEIVE CHECK SUM CONTROL STATUS REGISTER (32H).......................................................................................... 24
6.31 EXTERNAL PHYCEIVER ADDRESS REGISTER (33H).................................................................................................... 24
6.32 GENERAL PURPOSE CONTROL REGISTER 2 (34H) ....................................................................................................... 25
6.33 GENERAL PURPOSE REGISTER 2 (35H) ....................................................................................................................... 25
6.34 GENERAL PURPOSE CONTROL REGISTER 3 (36H) ....................................................................................................... 25
6.35 GENERAL PURPOSE REGISTER 3 (37H) ....................................................................................................................... 25
6.36 PROCESSOR BUS CONTROL REGISTER (38H) .............................................................................................................. 25
6.37 INT PIN CONTROL REGISTER (39H)............................................................................................................................ 26
6.38 MONITOR REGISTER 1 (40H) ...................................................................................................................................... 26
6.39 MONITOR REGISTER 2 (41H) ...................................................................................................................................... 26
6.40 SYSTEM CLOCK TURN ON CONTROL REGISTER (50H) ............................................................................................... 26
6.41 RESUME SYSTEM CLOCK CONTROL REGISTER (51H) ................................................................................................. 26
6.42 MEMORY DATA PRE-FETCH READ COMMAND WITHOUT ADDRESS INCREMENT REGISTER (F0H)............................... 26
6.43 MEMORY DATA READ COMMAND WITHOUT ADDRESS INCREMENT REGISTER (F1H) ................................................. 27
6.44 MEMORY DATA READ COMMAND WITH ADDRESS INCREMENT REGISTER (F2H)........................................................ 27
6.45 MEMORY DATA READ ADDRESS REGISTER (F4H~F5H) .............................................................................................. 27
6.46 MEMORY DATA WRITE COMMAND WITHOUT ADDRESS INCREMENT REGISTER (F6H)................................................ 27
6.47 MEMORY DATA WRITE COMMAND WITH ADDRESS INCREMENT REGISTER (F8H) ......................................................... 27
6.48 MEMORY DATA WRITE ADDRESS REGISTER (FAH~FBH)............................................................................................. 27
6.49 TX PACKET LENGTH REGISTER (FCH~FDH) ............................................................................................................. 27
6.50 INTERRUPT STATUS REGISTER (FEH).......................................................................................................................... 28
6.51 INTERRUPT MASK REGISTER (FFH)............................................................................................................................ 28
7. EEPROM FORMAT ........................................................................................................................................................ 29
8. MII REGISTER DESCRIPTION ................................................................................................................................... 30
8.1 BASIC MODE CONTROL REGISTER (BMCR) - 00 .......................................................................................................... 31
8.2 BASIC MODE STATUS REGISTER (BMSR) - 01 .............................................................................................................. 32
8.3 PHY ID IDENTIFIER REGISTER #1 (PHYID1) - 02 ........................................................................................................ 33
8.4 PHY ID IDENTIFIER REGISTER #2 (PHYID2) - 03 ........................................................................................................ 33
8.5 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) - 04 .................................................................................... 33
8.6 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) – 05..................................................................... 34
8.7 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) - 06 ............................................................................................. 35
8.8 DAVICOM SPECIFIED CONFIGURATION REGISTER (DSCR) - 16.................................................................................. 35
8.9 DAVICOM SPECIFIED CONFIGURATION AND STATUS REGISTER (DSCSR) - 17 ........................................................... 37
8.10 10BASE-T CONFIGURATION/STATUS (10BTCSR) - 18............................................................................................... 38
8.11 POWER DOWN CONTROL REGISTER (PWDOR) - 19 ................................................................................................... 38
8.12 (SPECIFIED CONFIG) REGISTER – 20 ............................................................................................................................ 39
9. FUNCTIONAL DESCRIPTION..................................................................................................................................... 40
9.1 HOST INTERFACE .......................................................................................................................................................... 40
9.2 DIRECT MEMORY ACCESS CONTROL ............................................................................................................................ 40
9.3 PACKET TRANSMISSION ................................................................................................................................................ 40
9.4 PACKET RECEPTION ...................................................................................................................................................... 40
9.5 100BASE-TX OPERATION ............................................................................................................................................. 40
9.5.1 4B5B Encoder ...................................................................................................................................................... 41
9.5.2 Scrambler ............................................................................................................................................................. 41
9.5.3 Parallel to Serial Converter................................................................................................................................. 41
9.5.4 NRZ to NRZI Encoder .......................................................................................................................................... 41
9.5.5 MLT-3 Converter.................................................................................................................................................. 41
9.5.6 MLT-3 Driver ....................................................................................................................................................... 41
9.5.7 4B5B Code Group ................................................................................................................................................ 42
9.6 100BASE-TX RECEIVER ............................................................................................................................................... 43
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
3
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
9.6.1 Signal Detect ........................................................................................................................................................ 43
9.6.2 Adaptive Equalization .......................................................................................................................................... 43
9.6.3 MLT-3 to NRZI Decoder ...................................................................................................................................... 43
9.6.4 Clock Recovery Module ....................................................................................................................................... 43
9.6.5 NRZI to NRZ ........................................................................................................................................................ 43
9.6.6 Serial to Parallel.................................................................................................................................................. 43
9.6.7 Descrambler......................................................................................................................................................... 43
9.6.8 Code Group Alignment......................................................................................................................................... 44
9.6.9 4B5B Decoder ...................................................................................................................................................... 44
9.7 10BASE-T OPERATION .................................................................................................................................................. 44
9.8 COLLISION DETECTION ................................................................................................................................................. 44
9.9 CARRIER SENSE ............................................................................................................................................................ 44
9.10 AUTO-NEGOTIATION ................................................................................................................................................... 44
9.11 POWER REDUCED MODE ............................................................................................................................................. 45
9.11.1 Power Down Mode ............................................................................................................................................. 45
9.11.2 Reduced Transmit Power Mode.......................................................................................................................... 45
10. DC AND AC ELECTRICAL CHARACTERISTICS.................................................................................................. 46
10.1 ABSOLUTE MAXIMUM RATINGS (-40°C ~ +85°C)....................................................................................................... 46
10.1.1 OPERATING CONDITIONS ......................................................................................................................................... 46
10.2 DC ELECTRICAL CHARACTERISTICS (VDD = 3.3V) ................................................................................................... 46
10.3 AC ELECTRICAL CHARACTERISTICS & TIMING WAVEFORMS ...................................................................................... 47
10.3.1 TP Interface ........................................................................................................................................................ 47
10.3.2 Oscillator/Crystal Timing ................................................................................................................................... 47
10.3.3 Power On Reset Timing...................................................................................................................................... 47
10.3.4 Processor I/O Read Timing ................................................................................................................................ 48
10.3.5 Processor I/O Write Timing................................................................................................................................ 49
10.3.6 External MII Interface Transmit Timing............................................................................................................. 50
10.3.7 External MII Interface Receive Timing .............................................................................................................. 50
10.3.8 MII Management Interface Timing..................................................................................................................... 51
10.3.9 EEPROM Interface Timing ................................................................................................................................ 51
11. APPLICATION NOTES ................................................................................................................................................ 52
11.1 NETWORK INTERFACE SIGNAL ROUTING .................................................................................................................... 52
11.2 10BASE-T/100BASE-TX HP AUTO-MDIX APPLICATION ............................................................................................ 52
11.3 10BASE-T/100BASE-TX ( NON HP AUTO-MDIX TRANSFORMER APPLICATION ) ...................................................... 53
11.4 POWER DECOUPLING CAPACITORS .............................................................................................................................. 54
11.5 GROUND PLANE LAYOUT ............................................................................................................................................ 55
11.6 POWER PLANE PARTITIONING ..................................................................................................................................... 56
11.7 MAGNETICS SELECTION GUIDE................................................................................................................................... 57
11.8 CRYSTAL SELECTION GUIDE ............................................................................................................................................. 57
11.9 APPLICATION OF REVERSE MII.......................................................................................................................................... 58
12. PACKAGE INFORMATION ........................................................................................................................................ 59
13. ORDERING INFORMATION........................................................................................................................................... 60
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
4
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
1. GENERAL DESCRIPTION
The DM9010BI is a fully integrated and cost-effective
Industrial-temperature single chip Fast Ethernet MAC
controller with a general processor interface, a
10/100M PHY and 16K Byte SRAM. It is designed
with low power and high performance process that
support 3.3V with 5V tolerance.
The DM9010BI also provides a MII interface to connect
HPNA device or other transceivers that support MII
interface.
The DM9010BI supports 8-bit, 16-bit and 32-bit uP
interfaces to internal memory accesses for different
processors. The PHY of the DM9010BI can interface to
the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX. It is
fully compliant with the IEEE 802.3u Spec. Its
auto-negotiation function will automatically configure the
DM9010BI to take the maximum advantage of its abilities.
The DM9010BI also supports IEEE 802.3x full- duplex flow
control. This programming of the DM9010BI is very simple,
so user can port the software drivers to any system easily.
2. BLOCK DIAGRAM
External MII
Interface
LED
PHYceiver
MAC
100 Base- TX
PCS
TX Machine
MII
TX+/Auto MDIX
10 Base T
/
Tx Rx
Control & Status
Registers
Memory
Management
Processer
Interface
100BaseTX
transceiver
EEPROM
Interface
RX Machine
RX+/Internal
SRAM
Autonegotiation
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
MII Management
Control
& MII Register
5
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
3. FEATURES
■ 100-pin LQFP.
■ Supports processor interface: Byte/word/Dword of
I/O command to internal memory data operation
■ Integrated 10/100M transceiver with
HP Auto-MDIX
■ Supports MII and reverses MII interface
■ Supports back pressure mode for half-duplex
mode flow control
■ IEEE802.3x flow control for full-duplex mode
■ Supports wakeup frame, link status change and
magic packet events for remote wake up
■
Integrated 16K Byte SRAM
■
■
Build in 3.3V to 1.8V regulator
Supports early Transmit
■
Supports IP/TCP/UDP checksum generation and
■
Supports automatically load vendor ID and
product ID from EEPROM
■ Supports 7 or 23 GPIO pins
■ Optional EEPROM configuration
■ Very low power consumption mode:
– Power reduced mode (cable detection)
– Power down mode
– Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction.
– 1: 1 transformers only when HP Auto-MDIX
Enable.
■ Supports Industrial-temperature: -40 °C.~ +85°C
■
Compatible with 3.3V and 5.0V tolerant I/O
checking
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
6
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
4. PIN CONFIGURATION
SD10
55
54
53
52
51
50
49
Version: DM9010BI--DS-P01
January 12, 2010
TXD0
TXC
TEST5
RXC
RXER
RXDV
COL
CRS
GND
RXD3
RXD2
RXD1
RXD0
LINK_I
NC
TXVDD18
TXTX+
TXGND
RXGND
RXRX+
RXVDD18
RXVDD18
BGRES
SD5
SD6
SD7
RST
GND
TEST1
TEST2
TEST3
TEST4
VDD
X2
X1
GND
SD
BGGND
IOR#
IOW#
AEN#
IOWAIT#
VDD
SD0
SD1
SD2
SD3
SD4
Preliminary
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DM9010BI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SD9
SD8
VDD
IO16
CMD
SA4
SA5
SA6
SA7
SA8
SA9
GND
INT
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
25
GND
GP6
LINK_O
WAKE
PWRST#
GND
SD15
SD14
SD13
SD12
SD11
66
65
64
63
62
61
60
59
58
57
56
75
74
73
72
71
70
69
68
67
GP5
GP4
VDD
VDD
GP3
GP2
GP1
GP0
EECS
EECK
EEDO
EEDI
GND
LKLED
FDLED
SPLED
20MCK
GND
MDC
MDIO
VDD
TXE
TXD3
TXD2
TXD1
4.1 Pin Configuration I: with MII Interface
7
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
SD10
55
54
53
52
51
50
49
Version: DM9010BI--DS-P01
January 12, 2010
SD20
SD21
TEST5
SD22
SD23
SD24
SD25
SD26
GND
SD27
SD28
SD29
SD30
SD31
NC
TXVDD18
TXTX+
TXGND
RXGND
RXRX+
RXVDD18
RXVDD18
BGRES
SD5
SD6
SD7
RST
GND
TEST1
TEST2
TEST3
TEST4
VDD
X2
X1
GND
SD
BGGND
IOR#
IOW#
AEN#
IOWAIT#
VDD
SD0
SD1
SD2
SD3
SD4
Preliminary
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DM9010BI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SD9
SD8
VDD
IO16
CMD
SA4
SA5
SA6
SA7
SA8
SA9
GND
INT
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
25
GND
GP6
LINK_O
WAKE
PWRST#
GND
SD15
SD14
SD13
SD12
SD11
66
65
64
63
62
61
60
59
58
57
56
75
74
73
72
71
70
69
68
67
GP5
GP4
VDD
VDD
GP3
GP2
GP1
GP0
EECS
EECK
EEDO
EEDI
GND
LKLED
FDLED
SPLED
20MCK
GND
IO32
SD16
VDD
NC
SD17
SD18
SD19
4.2 Pin Configuration II: with 32-Bit Data Bus
8
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
5. PIN DESCRIPTION
I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,
LI= reset Latch Input, #= asserted low, PD=internal pull-low about 60K ohm, PU=internal pull-high
5.1 MII Interface
Pin No.
Pin Name
I/O
37
LINK_I
I,PD
41,40,39,
38
43
RXD [3:0]
I,PD
44
COL
45
RX_DV
I,PD
External MII Receive Data Valid
46
RX_ER
I,PD
External MII Receive Error
47
RX_CLK
I,PD
External MII Receive Clock
49
TX_CLK
I/O,PD External MII Transmit Clock. This pin in output in MII interfaces.
53,52,51,
50
TXD [3:0]
O,PD
54
TX_ EN
O,PD
56
MDIO
I/O,PD MII Serial Management Data
57
MDC
O,PD
MII Serial Management Data Clock
This pin is also used as the strap pin of the polarity of the INT pin
When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin
is high active
Processor Read Command
This pin is low active at default; its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
Processor Write Command
This pin is low active at default; its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
Address Enable
A low active signal used to select the DM9010BI.
CRS
Description
External MII device link status
External MII Receive Data
4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode
I/O,PD External MII Carrier Sense
Active high to indicate the pressure of carrier, due to receive or transmit activities
in 10 Base-T or 100 Base-TX modes. This pin is output in reverse MII interface.
I/O,PD External MII Collision Detect. This pin is output in reverse MII interface.
External MII Transmit Data
4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps
nibble mode
TXD [2:0] is also used as the strap pins of IO base address.
IO base = (strap pin value of TXD [2:0]) * 10H + 300H
External MII Transmit Enable
5.2 Processor Interface
1
IOR#
I,PD
2
IOW#
I,PD
3
AEN
I,PD
4
IOWAIT
O,PD
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Processor Command Ready
When a command is issued before last command is completed, the IOWAIT will
be pulled low to indicate the current command is waited
The polarity and output type can be updated by EEPROM. The default is
Open-Drain output and low active.
9
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
14
RST
6,7,8,9,10,
11,12,13,
89,88,87,
86,85,84,
83,82
SD0~15
93,94,95,
96,97,98
SA4~9
92
CMD
91
IO16
100
INT
SD16~31 (in
56,53,52,
double word
51,50,49,
mode)
47,46,45,
44,43,41,
40,39,38
37
57
IO32 (in double
word mode)
I
Hardware Reset Command, active high to reset the DM9010BI
I/O,PD Processor Data Bus bit 0~15
I,PD
Address Bus 4~9
These pins are used to select the DM9010BI.
When SA9 and SA8 are in high states, and SA7 and AEN are in low
states, and SA6~4 are matched with strap pins TXD2~0, the DM9010BI is
selected.
I,PD Command Type
When high, the access of this command cycle is DATA port
When low, the access of this command cycle is INDEX port
O
Word Command Indication
When the access of internal memory is word or Dword width, this pin will
be asserted
This pin is low active at default; its polarity can be modified by EEPROM
setting. See the EEPROM content description for detail
O,PD Interrupt Request
This pin is high active at default, its polarity can be modified by EEPROM
setting or strap pin MDC. See the EEPROM content description for detail
I/O,PD Processor Data Bus bit 16~31
These pins are used as data bus bits 16~31 when the DM9010BI is set to
double word mode (the straps pin EEDO is pulled high and WAKE is not
pull-high)
O,PD Double Word Command Indication
This pins is used as the double word command indication when the
DM9010BI is set to double data word mode, and this pin will be asserted
when the access of internal memory is double word width
This pin is low active at default; its polarity can be modified by EEPROM
setting. See the EEPROM content description for detail
When the IO32 pin is pulled high, the INT pin is low active; otherwise the INT pin
is high active
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
10
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
5.3 EEPROM Interface
64
EEDI
65
EEDO
66
EECK
67
EECS
I
Data from EEPROM
O,PD Data to EEPROM
This pin is also used as a strap pin. It combines with strap pin WOL, and it
can set the data width of the internal memory access
The decoder table is the following, where the logic 1 means the strap pin
is pulled high
WAKE
EEDO data width
0
0
16-bit
0
1
32-bit
1
0
8-bit
1
1
reserved
O,PD Clock to EEPROM
O,PD Chip Select to EEPROM
This pin is also used as a strap pin to define the LED modes.
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
Note: The pins EECS, EECK and EEDO are all have a pulled down resistor about 60 k ohms internally
5.4 Clock Interface
21
X2_25M
22
X1_25M
59
CLK20MO
5.5 LED Interface
60
SPLED
O
Crystal 25MHz Out
I
Crystal 25MHz In
I/O,PD 20Mhz Clock Output
It is used as the clock signal for the external MII device’s clock is 20MHz
This pin has a pulled down resistor about 60k ohm internally.
When pin TEST5 state is high, this pin acts as the system clock.
O
61
FDLED
O
62
LKLED
O
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY
Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the internal
PHY
In LED mode 0, Its low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY
Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
11
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
5.6 10/100 PHY/Fiber
24
SD
I
Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
Band gap Ground, need to connect to AGND.
25
BGGND
P
26
BGRES
I/O
27,28
RXVDD18
P
29
RXI+
I/O
TP RX Input
30
RXI-
I/O
TP RX Input
31
RXGND
P
RX Ground
32
TXGND
P
TX Ground
33
TXO+
I/O
TP TX Output
34
TXO-
I/O
TP TX Output
35
TXVDD18
P
Internal regulator 1.8V output for TP TX
I
Operation Mode
Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application
5.7 Miscellaneous
16,17,18, TEST1~TEST4
19
48
TEST5
68,69,70,
71,
74,75,77
GP0~6
78
LINK_O
79
WAKE
80
PW_RST#
36
NC
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Band gap Pin
Internal regulator 1.8V output for TP RX
I,PD
Internal system clock source
0: use internal 50MHz clock *(Suggestion)
1: use CLK20MO pin
I/O,PD General I/O Ports
Registers GPCR and GPR can program these pins
The GPIO0 is an output mode, and output data high at default is to power
down internal PHY and other external MII device
GP1~3 defaults are input ports, GP 0, 4~6 force to output ports.
O,PD Cable Link Status Output. Active High
This pin is also used as a strap pin to define whether the MII interface is a
reversed MII interface (pulled high) or a normal MII interface (not pulled
high). This pin has a pulled down resistor about 60k ohm internally.
O,PD Issue a wake up signal when wake up event happens
This pin has a pulled down resistor about 60k ohm internally.
I
Power on Reset
Active low signal to initiate the DM9010BI
The DM9010BI is ready after 5us when this pin deasserted
NC NC
12
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
5.8 Power Pins
5,20,55,
DVDD
72,90,73
15,23,42,
GND
58,63,81,
99,76
P
Digital VDD
P
Digital GND
5.9 strap pins table
1: pull-high 1K~10K, 0: floating. (Default)
Pin No.
Pin Name
Description
57
MDC
65
EEDO
79
WAKE
67
EECS
52,51,
50
78
TXD[2:0]
53
TXD[3]
54
TXEN
74
GPIO4
75
GPIO5
77
GPIO6
LINK_O
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Polarity of INT
1: INT pin low active;
0: INT pin high active
DATA Bus Width
WAKE
EEDO data width
0
0
16-bit
0
1
32-bit
1
0
8-bit
1
1
reserved
LED Mode
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
IO base address. (not available in 32-bit mode)
IO base = (strap pin value of TXD [2:0]) * 10H + 300H
Reverse MII
1: Reverse MII mode
0: normal MII mode
External MII mode (not available in 32-bit mode)
force to external MII mode , mapping to bit 5 of REG. 2EH
and set register NCR Bit7 “1”,
Disable to load EEPROM after power on reset.
PHY Power-Up.
1: PHY is power-up after power-ON
0: PHY is power-down after power-ON
Output Type of INT
1: INT pin is Open-Collect
0: INT pin is force output
HP Auto-MDIX
0: HP Auto-MDIX turn ON
1: HP Auto-MDIX turn OFF
13
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6. VENDOR CONTROL AND STATUS REGISTER SET
The DM9010BI implements several control and status
registers, which can be accessed by the host. These CSRs
Register
NCR
NSR
TCR
TSR I
TSR II
RCR
RSR
ROCR
BPTR
FCTR
FCR
EPCR
EPAR
EPDRL
EPDRH
WCR
PAR
MAR
GPCR
GPR
TRPAL
TRPAH
RWPAL
RWPAH
VID
PID
CHIPR
TCR2
OCR
SMCR
ETXCSR
TCSCR
RCSCSR
EPADR
GPCR2
GPR2
GPCR3
GPR3
are byte aligned. All CSRs are set to their default values by
hardware or software reset unless they are specified
Description
Offset
Network Control Register
Network Status Register
TX Control Register
TX Status Register I
TX Status Register II
RX Control Register
RX Status Register
Receive Overflow Counter Register
Back Pressure Threshold Register
Flow Control Threshold Register
RX Flow Control Register
EEPROM & PHY Control Register
EEPROM & PHY Address Register
EEPROM & PHY Low Byte Data Register
EEPROM & PHY High Byte Data Register
Wake Up Control Register
Physical Address Register
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H-15H
Multicast Address Register
General Purpose Control Register
General Purpose Register
TX SRAM Read Pointer Address Low Byte
TX SRAM Read Pointer Address High Byte
RX SRAM Write Pointer Address Low Byte
RX SRAM Write Pointer Address High Byte
Vendor ID
Product ID
CHIP Revision
TX Control Register 2
Operation Control Register
Special Mode Control Register
Early Transmit Control/Status Register
Transmit Check Sum Control Register
Receive Check Sum Control Status Register
External PHY address
General Purpose Control Register 2
General Purpose Register 2
General Purpose Control Register 3
General Purpose Register 3
16H-1DH
1EH
1FH
22H
23H
24H
25H
28H-29H
2AH-2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Default value
after reset
00H
00H
00H
00H
00H
00H
00H
00H
37H
38H
00H
00H
40H
XXH
XXH
00H
Determined by
EEPROM
XXH
01H
XXH
00H
00H
00H
0CH
0A46H
9000H
12H
00H
00H
00H
00H
00H
00H
01H
00H
00H
00H
00H
14
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
BUSCR
INTCR
MONIR1
MONIR2
SCCR
RSCCR
MRCMDX
MRCMDX1
MRCMD
MRRL
MRRH
MWCMDX
MWCMD
MWRL
MWRH
TXPLL
TXPLH
ISR
IMR
Processor Bus Control Register
INT Pin Control Register
Monitor Register 1
Monitor Register 2
System Clock Turn ON Control Register
Resume System Clock Control Register
Memory Data Pre-Fetch Read Command Without Address
Increment Register
Memory Data Read Command With Address Increment
Register
Memory Data Read Command With Address Increment
Register
Memory Data Read_ address Register Low Byte
Memory Data Read_ address Register High Byte
Memory Data Write Command Without Address Increment
Register
Memory Data Write Command With Address Increment
Register
Memory Data Write_ address Register Low Byte
Memory Data Write _ address Register High Byte
TX Packet Length Low Byte Register
TX Packet Length High Byte Register
Interrupt Status Register
Interrupt Mask Register
38H
39H
40H
41H
50H
51H
F0H
01H
00H
XXH
XXH
00H
XXH
XXH
F1H
XXH
F2H
XXH
F4H
F5H
F6H
00H
00H
XXH
F8H
XXH
FAH
FBH
FCH
FDH
FEH
FFH
00H
00H
XXH
XXH
00H
00H
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where:
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
P = power on reset default value
H = hardware reset default value
S = software reset default value
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
E = default value from EEPROM
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
15
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.1 Network Control Register (00H)
Bit
Name
Default
Description
7
EXT_PHY
PH0,RW Selects external PHY when set. Selects Internal PHY when clear. This bit will not
be affected after software reset
6
WAKEEN
P0,RW
Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clears all
wakeup event status
This bit will not be affected after a software reset
5
RESERVED
0,RO
Reserved
4
FCOL
PHS0,RW Force Collision Mode, used for testing
3
FDX
PHS0,RW Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode
2:1
LBK
PHS00,
Loopback Mode
RW
Bit 2 1
0 0
Normal
0 1
MAC Internal Loopback
1 0
Internal PHY 100M mode digital Loopback
1 1
(Reserved)
0
RST
PH0,RW Software reset and auto clear after 10us
6.2 Network Status Register (01H)
Bit
Name
Default
Description
7
SPEED
X,RO
Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no
meaning when LINKST=0
6
LINKST
X,RO
Link Status 0:link failed 1:link OK, when Internal PHY is used
P0,
Wakeup Event Status. Clears by read or write 1
5
WAKEST
RW/C1
This bit will not be affected after software reset
4
RESERVED
0,RO
Reserved
3
TX2END
PHS0,
TX Packet 2 Complete Status. Clears by read or write 1
RW/C1
Transmit completion of packet index 2
2
TX1END
PHS0,
TX Packet 1 Complete status. Clears by read or write 1
RW/C1
Transmit completion of packet index 1
1
RXOV
PHS0,RO RX FIFO Overflow
0
RESERVED
0,RO
Reserved
6.3 TX Control Register (02H)
Bit
Name
Default
7
RESERVED
0,RO
6
TJDIS
PHS0,RW
5
EXCECM
PHS0,RW
4
3
2
1
0
PAD_DIS2
CRC_DIS2
PAD_DIS1
CRC_DIS1
TXREQ
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Description
Reserved
Transmit Jabber Disable
When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is Enable
Excessive Collision Mode Control : 0:aborts this packet when excessive collision
counts more than 15, 1: still tries to transmit this packet
PAD Appends Disable for Packet Index 2
CRC Appends Disable for Packet Index 2
PAD Appends Disable for Packet Index 1
CRC Appends Disable for Packet Index 1
TX Request. Auto clears after sending completely
16
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.4 TX Status Register I ( 03H ) for packet index I
Bit
Name
Default
Description
7
TJTO
PHS0,RO Transmit Jabber Time Out
It is set to indicate that the transmitted frame is truncated due to more than 2048
bytes are transmitted
6
LC
PHS0,RO Loss of Carrier
It is set to indicate the loss of carrier during the frame transmission. It is not valid in
internal Loopback mode
5
NC
PHS0,RO No Carrier
It is set to indicate that there is no carrier signal during the frame transmission. It is
not valid in internal Loopback mode
4
LC
PHS0,RO Late Collision
It is set when a collision occurs after the collision window of 64 bytes
3
COL
PHS0,RO Collision Packet
It is set to indicate that the collision occurs during transmission
2
EC
PHS0,RO Excessive Collision
It is set to indicate that the transmission is aborted due to 16 excessive collisions
1:0
RESERVED
0,RO
Reserved
6.5 TX Status Register II ( 04H ) for packet index I I
Bit
Name
Default
Description
7
TJTO
PHS0,RO Transmit Jabber Time Out
It is set to indicate that the transmitted frame is truncated due to more than 2048
bytes are transmitted
6
LC
PHS0,RO Loss of Carrier
It is set to indicate the loss of carrier during the frame transmission. It is not valid in
internal Loopback mode
5
NC
PHS0,RO No Carrier
It is set to indicate that there is no carrier signal during the frame transmission. It is
not valid in internal Loopback mode
4
LC
PHS0,RO Late Collision
It is set when a collision occurs after the collision window of 64 bytes
3
COL
PHS0,RO Collision packet, collision occurs during transmission
2
EC
PHS0,RO Excessive Collision
It is set to indicate that the transmission is aborted due to 16 excessive collisions
1:0
RESERVED
0,RO
Reserved
6.6 RX Control Register ( 05H )
Bit
Name
Default
7
HASHALL PHS0,RW
WTDIS
PHS0,RW
6
5
DIS_LONG
PHS0,RW
4
3
2
1
0
DIS_CRC
ALL
RUNT
PRMSC
RXEN
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Description
Filter All address in Hash Table
Watchdog Timer Disable
When set, the Watchdog Timer (2048 bytes) is disabled. Otherwise it is enabled
Discard Long Packet
Packet length is over 1522byte
Discard CRC Error Packet
Pass All Multicast
Pass Runt Packet
Promiscuous Mode
RX Enable
17
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.7 RX Status Register ( 06H )
Bit
Name
Default
7
RF
PHS0,RO
6
MF
PHS0,RO
5
LCS
PHS0,RO
4
RWTO
PHS0,RO
3
PLE
PHS0,RO
2
AE
PHS0,RO
1
CE
PHS0,RO
0
FOE
PHS0,RO
Description
Runt Frame
It is set to indicate that the size of the received frame is smaller than 64 bytes
Multicast Frame
It is set to indicate that the received frame has a multicast address
Late Collision Seen
It is set to indicate that a late collision is found during the frame reception
Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes
Physical Layer Error
It is set to indicate that a physical layer error is found during the frame reception
Alignment Error
It is set to indicate that the received frame ends with a non-byte boundary
CRC Error
It is set to indicate that the received frame ends with a CRC error
FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception
6.8 Receive Overflow Counter Register ( 07H )
Bit
Name
Default
Description
7
RXFU
PHS0,R/C Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
6:0
ROC
PHS0,R/C Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
18
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.9 Back Pressure Threshold Register (08H)
Bit
Name
Default
Description
7:4
BPHW
PHS3,
Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
RW
when RX SRAM free space is lower than this threshold value
Default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)
:0
JPT
PHS7,
Jam Pattern Time. Default is 200us
RW
bit3 bit2 bit1 bit0
time
0 0 0 0
5us
0 0 0 1
10us
0 0 1 0
15us
0 0 1 1
25us
0 1 0 0
50us
0 1 0 1
100us
0 1 1 0
150us
0 1 1 1
200us
1 0 0 0
250us
1 0 0 1
300us
1 0 1 0
350us
1 0 1 1
400us
1 1 0 0
450us
1 1 0 1
500us
1 1 1 0
550us
1 1 1 1
600us
6.10 Flow Control Threshold Register (09H)
Bit
Name
Default
Description
7:4
HWOT
PHS3,
RX FIFO High Water Overflow Threshold
RW
Send a pause packet with pause_ time=FFFFH when the RX RAM free space is
less than this value., If this value is zero, its means no free RX SRAM space.
Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes)
3:0
LWOT
PHS8,
RX FIFO Low Water Overflow Threshold
RW
Send a pause packet with pause time=0000 when RX SRAM free space is larger
than this value. This pause packet is enabled after the high water pause packet is
transmitted. Default SRAM free space is 8K-byte. Please do not exceed SRAM
size
(1 unit=1K bytes)
6.11 RX/TX Flow Control Register (0AH)
Bit
Name
Default
Description
7
TXP0
HPS0,RW TX Pause Packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h
6
TXPF
HPS0,RW TX Pause packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
5
TXPEN
HPS0,RW Force TX Pause Packet Enable
Enables the pause packet for high/low water threshold control
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
19
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
4
BKPA
HPS0,RW
3
BKPM
HPS0,RW
2
1
0
RXPS
RXPCS
FLCE
HPS0,R/C
HPS0,RO
HPS0,RW
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when any
packet comes and RX SRAM is over BPHW
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when a packet’s
DA matches and RX SRAM is over BPHW
RX Pause Packet Status, latch and read clearly
RX Pause Packet Current Status
Flow Control Enable
Set to enable the flow control mode (i.e. to disable TX function)
6.12 EEPROM & PHY Control Register (0BH)
Bit
Name
Default
Description
7:6
RESERVED
0,RO
Reserved
5
REEP
PH0,RW Reload EEPROM. Driver needs to clear it up after the operation completes
4
WEP
PH0,RW Write EEPROM Enable
3
EPOS
PH0,RW EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
2
ERPRR
PH0,RW EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
1
ERPRW
PH0,RW EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
0
ERRE
PH0,RO EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
6.13 EEPROM & PHY Address Register (0CH)
Bit
Name
Default
Description
7:6
PHY_ADR PH01,RW PHY Address bit 1 and 0; the PHY address bit [4:2] is force to 0. Force to 01 if
internal PHY is selected
5:0
EROA
PH0,RW EEPROM Word Address or PHY Register Address
6.14 EEPROM & PHY Data Register (EE_PHY_L:0DH EE_PHY_H:0EH)
Bit
Name
Default
Description
7:0
EE_PHY_L
PH0,RW EEPROM or PHY Low Byte Data
This data is made to write low byte of word address defined in Reg. CH to
EEPROM or PHY
7:0
EE_PHY_H
PH0,RW EEPROM or PHY High Byte Data
This data is made to write high byte of word address defined in Reg. CH to
EEPROM or PHY
6.15 Wake up Control Register (0FH)
Bit
Name
Type
Description
7:6
RESERVED
0,RO
Reserved
5
LINKEN
P0,RW
When set, it enables Link Status Change Wake up Event
This bit will not be affected after software reset
4
SAMPLEEN
P0,RW
When set, it enables Sample Frame Wake up Event
This bit will not be affected after software reset
3
MAGICEN
P0,RW
When set, it enables Magic Packet Wake up Event
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
20
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
2
LINKST
P0,RO
1
SAMPLEST
P0,RO
0
MAGICST
P0,RO
This bit will not be affected after software reset
When set, it indicates that Link Change and Link Status Change Event occurred
This bit will not be affected after software reset
When set, it indicates that the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after software reset
When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset
6.16 Physical Address Register (10H~15H)
Bit
Name
Default
7:0
PAB5
E,RW
Physical Address Byte 5
7:0
PAB4
E,RW
Physical Address Byte 4
7:0
PAB3
E,RW
Physical Address Byte 3
7:0
PAB2
E,RW
Physical Address Byte 2
7:0
PAB1
E,RW
Physical Address Byte 1
7:0
PAB0
E,RW
Physical Address Byte 0
(15H)
(14H)
(13H)
(12H)
(11H)
(10H)
6.17 Multicast Address Register (16H~1DH)
Bit
Name
Default
7:0
MAB7
X,RW
Multicast Address Byte 7
7:0
MAB6
X,RW
Multicast Address Byte 6
7:0
MAB5
X,RW
Multicast Address Byte 5
7:0
MAB4
X,RW
Multicast Address Byte 4
7:0
MAB3
X,RW
Multicast Address Byte 3
7:0
MAB2
X,RW
Multicast Address Byte 2
7:0
MAB1
X,RW
Multicast Address Byte 1
7:0
MAB0
X,RW
Multicast Address Byte 0
(1DH)
(1CH)
(1BH)
(1AH)
(19H)
(18H)
(17H)
(16H)
Description
Description
6.18 General purpose control Register (1EH)
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
6:4
GPC64
PH,
General Purpose Control 6~4
111,RO
Define the input/output direction of pins GPIO6~4 respectively.
These bits are all forced to “1”s, so pins GPIO6~4 are output only.
3:1
GPC31
PH,
General Purpose Control 3~1
000,RW Define the input/output direction of pins GPIO 3~1 respectively.
When a bit is set 1, the direction of correspondent bit of General Purpose Register
is output. Other defaults are input
0
GPC0
PH1,RO General Purpose Control 0
This bit defines the input/output direction of pin GPIO0.
These bits are forced to “1”, so pin GPIO0 is output only.
Pin GPIO0 is forced to output for internal PHYceiver power down function.
6.19 General purpose Register (1FH)
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
6:4
GEPIO6-4
PH0,RW General Purpose Data 6~4
These bits are reflect to pin GEPIO6~4 respectively.
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
21
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
3:1
GEPIO3-1
PH0,RW
0
GEPIO0
ET1,RW
General Purpose 3~1
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is reflected to pin GEPIO3-1
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit to be read is reflected from correspondent pins of GEPIO3-1
The GEPIOs are mapped to pins GEPIO3 to GEPIO1 respectively
General Purpose 0
The value of the bit is the output to pin GEPIO0
This bit also defines the power down status of Internal PHYceiver. Driver needs to
clear this bit by writing “0” when it wants internal PHYceiver to be power up. This
default value can be programmed by strap pin GPIO4 or EEPROM. Please refer to
the EEPROM description
6.20 TX SRAM Read Pointer Address Register (22H~23H)
Bit
Name
Default
Description
7:0
TRPAH
PS0,RO
TX SRAM Read Pointer Address High Byte (23H)
7:0
TRPAL
PS0.RO
TX SRAM Read Pointer Address Low Byte (22H)
6.21 RX SRAM Write Pointer Address Register (24H~25H)
Bit
Name
Default
Description
7:0
RWPAH PS,0CH,RO RX SRAM Write Pointer Address High Byte (25H)
7:0
RWPAL
PS,04H.RO RX SRAM Write Pointer Address Low Byte (24H)
6.22 Vendor ID Register (28H~29H)
Bit
Name
Default
7:0
VIDH
PHE,0AH,RO Vendor ID High Byte (29H)
7:0
VIDL
PHE,46H.RO Vendor ID Low Byte (28H)
6.23 Product ID Register (2AH~2BH)
Bit
Name
Default
7:0
PIDH
PHE,90H,RO Product ID High Byte (2BH)
7:0
PIDL
PHE,00H.RO Product ID Low Byte (2AH)
6.24 Chip Revision Register (2CH)
Bit
Name
Default
7:0
CHIPR
12H,RO
CHIP Revision
Description
Description
Description
6.25 Transmit Control Register 2 (2DH)
Bit
Name
Default
Description
7
LED
PH0,RW Led Mode
When set, the LED pins act as led mode 1.
When cleared, the led mode is depending on strap pin or EEPROM setting.
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
22
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6
RLCP
PH0,RW
5
DTU
PH0,RW
4
ONEPM
PH0,RW
3~0
IFGS
PH0,RW
Retry Late Collision Packet
Re-transmit the packet with late-collision
Disable TX Under run Retry
Disable to re-transmit the underruned packet
One Packet Mode
When set, only one packet transmit command can be issued before transmit
completed.
When cleared, at most two packet transmit command can be issued before
transmit completed.
Inter-Frame Gap Setting
0XXX: 96-bit
1000: 64-bit
1001: 72-bit
1010:80-bit
1011:88-bit
1100:96-bit
1101:104-bit
1110: 112-bit
1111:120-bit
6.26 Operation Test Control Register (2EH)
Bit
Name
Default
Description
7~6
SCC
PH0,RW System Clock Control
Set the internal system clock.
00: 50Mhz
01: 20MHz
10: 100MHz
11: 1KHz
In external MII mode, only internal system clock is always 50Mhz.
5
EXTMII
PH0,RW Force to External MII mode
4
SOE
PH0,RW SRAM Output-Enable Always ON
3
SCS
PH0,RW SRAM Chip-Select Always ON
2~0
PHYOP
PH0,RW PHY operation mode
6.27 Special Mode Control Register (2FH)
Bit
Name
Default
7
SM_EN
HPS0,RW Special Mode Enable
6~3
RESERVED HPS0,RO Reserved
2
FLC
HPS0,RW Force Late Collision
1
FB1
HPS0,RW Force Longest Back-off time
0
FB0
HPS0,RW Force Shortest Back-off time
6.28 Early Transmit Control/Status Register (30H)
Bit
Name
Default
7
ETE
HPS0, RW Early Transmit Enable
Enable bits[1:0]
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Description
Description
23
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6
5
4~2
1~0
ETS2
ETS1
RESERVED
ETT
HPS0,RO
HPS0,RO
000,RO
HPS0,RW
Early Transmit Status II (under run)
Early Transmit Status I (under run)
Reserved
Early Transmit Threshold
Start transmit when data write to TX FIFO reach the byte-count threshold
Bit-1 bit-0
----- ---0
0
0
1
1
0
1
1
threshold
------------: 12.5%
: 25%
: 50%
: 75%
6.29 Transmit Check Sum Control Register (31H)
Bit
Name
Default
Description
7~3
RESERVED
0,RO
Reserved
2
UDPCSE
HPS0,RW UDP Checksum Generation Enable
1
TCPCSE
HPS0,RW TCP Checksum Generation Enable
0
IPCSE
HPS0,RW IP Checksum Generation Enable
6.30 Receive Check Sum Control Status Register (32H)
Bit
Name
Default
Description
7
UDPS
HPS0,RO UDP Checksum Status
0: checksum OK, if UDP packet
6
TCPS
HPS0,RO TCP Checksum Status
0: checksum OK, if TCP packet
5
IPS
HPS0,RO IP Checksum Status
0: checksum OK, if IP packet
4
UDPP
HPS0,RO UDP Packet
3
TCPP
HPS0,RO TCP Packet
2
IPP
HPS0,RO IP Packet
1
RCSEN
HPS0,R Receive Checksum Checking Enable
W
When set, the checksum status will store in packet first byte of status header.
0
DCSE
HPS0,R Discard Checksum Error Packet
W
When set, if IP/TCP/UDP checksum field is error, this packet will be discarded.
6.31 External PHYceiver Address Register (33H)
Bit
Name
Default
Description
7
ADR_EN
HPS0,R External PHY Address Enabled
W
When set in external MII mode, the external PHYceiver address is defined at bit
4~0.
6~5
Reserved
HPS0,RO Reserved
4~0
EPHYADR
HPS01,R External PHY Address Bit 4~0
W
The PHY address in external MII mode.
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
24
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.32 General Purpose Control Register 2 (34H)
Bit
Name
Default
Description
7~0
GPC2
HP0,RW General Purpose Control 2
Define the input/output direction of pins SD23~16, which are used as general
purpose pins when none 32-bit mode and external MII mode, respectively.
6.33 General Purpose Register 2 (35H)
Bit
Name
Default
Description
7~0
GPD2
HP0,RW General Purpose Register 2 Data
When the correspondent bit of General Purpose Control Register 2 is set, the value
of the bit is reflected to pin SD23~16
When the correspondent bit of General Purpose Control Register 2 is 0, the value
of the bit to be read is reflected from correspondent pins SD23~16
6.34 General Purpose Control Register 3 (36H)
Bit
Name
Default
Description
7~0
GPC3
HP0,RW General Purpose Control 3
Define the input/output direction of pins SD31~24, which are used as general
purpose pins when none 32-bit mode and external MII mode, respectively.
6.35 General Purpose Register 3 (37H)
Bit
Name
Default
Description
7~0
GPD3
HP0,RW General Purpose Register 3 Data
When the correspondent bit of General Purpose Control Register 3 is set, the value
of the bit is reflected to pin SD31~24
When the correspondent bit of General Purpose Control Register 3 is 0, the value
of the bit to be read is reflected from correspondent pins SD31~24
6.36 Processor Bus Control Register (38H)
Bit
Name
Default
Description
7
Reserved
P0,RW
Reserved
Data Bus Current Driving/Sinking Capability
00: 2mA (default)
01: 4mA
6:5
CURR
P00,RW
10: 6mA
11: 8mA
4
Reserved
P0,RW
Reserved
Enable Schmitt Trigger
3
GPIO
P0,RW
1: Pin 35/36/37 (IOR/IOW/CS#) have Schmitt trigger capability.
2
Reserved
P0,RW
Reserved
Eliminate IOW spike
1
IOW_SPIKE
P0,RW
1: eliminate about 2ns IOW spike
Eliminate IOR spike
0
IOR_SPIKE
P1,RW
1: eliminate about 2ns IOR spike
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
25
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.37 INT Pin Control Register (39H)
Bit
Name
Default
7:2
Reserved
PS0,RO
Reserved
INT Pin Output Type Control
1
INT_TYPE
PET0,RW 1: INT Open-Collector output
0: INT direct output
INT Pin Polarity Control
0
INT_POL
PET0,RW 1: INT active low
0: INT active high
Description
6.38 Monitor Register 1 (40H)
Bit
Name
Default
7
BWIDTH
T0,RO
6
DWIDTH
T0,RO
5
INTOC
ET0,RO
4
INTP
ET0,RO
3
IO16OC
E0,RO
2
IO16P
E0,RO
1
ILEDM
ET0,RO
0
MDIX
ET0,RO
8-bit Data Strap Latch Status
32-bit Data Strap Latch Status
INT Open-Collect Pin Status
INT Polarity Pin Status
IO16/32 Open-Collect Pin Status
IO16/32 Polarity Pin Status
LED Mode Status
MDIX Strap Pin Status
6.39 Monitor Register 2 (41H)
Bit
Name
Default
7~4
RESERVED
0,RO
3
NOEEP
T0,RO
2
EXTMII
T0,RO
1
PHYUP
T0,RO
0
RMII
T0,RO
Description
Reserved
NO Load EEPROM Strap Pin Status
External MII Strap Pin Status
PHY Power-Up Strap Pin Status
Reverse MII strap Pin Status
Description
6.40 System Clock Turn ON Control Register (50H)
Bit
Name
Default
Description
7:1
Reserved
Reserved
Stop Internal System Clock
0
DIS_CLK
P0,W
1: internal system clock turn off, internal PHYceiver also power down
0: internal system clock is ON
6.41 Resume System Clock Control Register (51H)
When the INDEX port set to 51H, the internal system clock is turn ON.
6.42 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)
Bit
Name
Default
Description
7:0
MRCMDX
X,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged. And the DM9010BI starts to pre-fetch the SRAM data
to internal data buffers.
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
26
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.43 Memory Data Read Command without Address Increment Register (F1H)
Bit
Name
Default
Description
7:0
MRCMDX1
X,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged.
6.44 Memory Data Read Command with Address Increment Register (F2H)
Bit
Name
Default
Description
7:0
MRCMD
X,RO
Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit
respectively)
6.45 Memory Data Read address Register (F4H~F5H)
Bit
Name
Default
Description
7:0
MDRAH
PHS0,RW Memory Data Read_ addresses High Byte. It will be set to 0Ch, when IMR bit7 =1
7:0
MDRAL
PHS0,RW Memory Data Read_ address Low Byte
6.46 Memory Data Write Command without Address Increment Register (F6H)
Bit
Name
Default
Description
7:0
MWCMDX
X,WO
Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
6.47 Memory data write command with address increment Register (F8H)
Bit
Name
Default
Description
7:0
MWCMD
X,WO
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1, 2, or 4, depends
on the operator mode. (8-bit, 16-bit,32-bit respectively)
6.48 Memory data write address Register (FAH~FBH)
Bit
Name
Default
Description
7:0
MDRAH
PHS0,RW Memory Data Write_ address High Byte
7:0
MDRAL
PHS0,RW Memory Data Write_ address Low Byte
6.49 TX Packet Length Register (FCH~FDH)
Bit
Name
Default
7:0
TXPLH
PHS0,RW TX Packet Length High byte
7:0
TXPLL
PHS0,RW TX Packet Length Low byte
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Description
27
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.50 Interrupt Status Register (FEH)
Bit
Name
Default
7:6
IOMODE
T0, RO
5
4
3
2
1
0
LNKCHG
UDRUN
ROO
ROS
PT
PR
PHS0,RW/C1
PHS0,RW/C1
PHS0,RW/C1
PHS0,RW/C1
PHS0,RW/C1
PHS0,RW/C1
6.51 Interrupt Mask Register (FFH)
Bit
Name
Default
7
PAR
HPS0,RW
6
5
4
3
2
1
0
RESERVED
LNKCHGI
UDRUNI
ROOI
ROI
PTI
PRI
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
RO
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
Description
Bit 7 Bit 6
0
0
16-bit mode
0
1
32-bit mode
1
0
8-bit mode
1
1
Reserved
Link Status Change
Transmit Under run
Receive Overflow Counter Overflow
Receive Overflow
Packet Transmitted
Packet Received
Description
Enable the SRAM read/write pointer to automatically return to the start address
when pointer addresses are over the SRAM size. Driver needs to set. When
driver sets this bit, REG_F5 will set to 0Ch automatically
Reserved
Enable Link Status Change Interrupt
Enable Transmit Under run Interrupt
Enable Receive Overflow Counter Overflow Interrupt
Enable Receive Overflow Interrupt
Enable Packet Transmitted Interrupt
Enable Packet Received Interrupt
28
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
7. EEPROM Format
name
MAC address
Auto Load Control
Word
0
3
Vendor ID
Product ID
pin control
4
5
6
offset
Description
0~5 6 Byte Ethernet Address
6-7
Bit 1:0=01: Update vendor ID and product ID
Bit 3:2=01: Accept setting of WORD6 [8:0]
Bit 5:4=01: Accept setting of WORD6 [11:9]
Bit 7:6=01: Accept setting of WORD7 [3:0]
Bit 11:10=01: Accept setting of WORD7 [7]
Bit 13:12=01: Accept setting of WORD7 [8]
Bit 15:14=01: Accept setting of WORD7 [14]
8-9
2 byte vendor ID (Default: 0A46H)
10-11 2 byte product ID (Default: 9000H)
12-13 When word 3 bit [3:2] =01, these bits can control the IOR#, IOW# and INT pins
polarity.
Bit0: Reserved
Bit1: IOR# pin is active low when set (default: active low)
Bit2: IOW# pin is active low when set (default: active low)
Bit3: INT pin is active low when set (default: active high)
Bit4: INT pin s open-collected (default: force output)
Bit 8:5: Reserved
Wake-up mode control
7
14-15
RESERVED
RESERVED
RESERVED
RESERVED
8
9
10
11
16-17
18-19
20-21
22-23
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
When word 3 bit [5:4] =01, the I/O base can be re-configured.
Bit11:09: I/O base (default: 300H)
000 : 300H
001 : 310H
010 : 320H
011 : 330H
100 : 340H
101 : 350H
110 : 360H
111 : 370H
Bit15:12: reserved
Bit0: The WAKE pin is active low when set (default: active high)
Bit1: The WAKE pin is in pulse mode when set (default: level mode)
Bit2: magic wakeup event is enabled when set. (default: disable))
Bit3: link change wakeup event is enabled when set (default: disable)
Bit6:4: reserved
Bit7: LED mode 1 (default: 0)
Bit8: internal PHY is enabled after power-on (default: disable)
Bit13:9: reserved
Bit14: 1: HP Auto-MDIX ON, 0: HP Auto-MDIX OFF(default ON)
Bit15: reserved
29
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
8. MII REGISTER DESCRIPTION
ADD Name
15
00 CONTR Reset
OL
0
01 STATUS T4
Cap.
0
02 PHYID1
0
03 PHYID2
04 Auto-Neg. Next
Advertise Page
05 Link Part. LP
Ability
Next
Page
06 Auto-Neg.
Expansio
n
16 Specifie BP
4B5B
d
Config.
17 Specifie 100
FDX
d
Conf/Stat
18
10T
Rsvd
Conf/Stat
14
Loop
back
0
TX FDX
Cap.
1
0
13
12
11
Speed Auto-N Power
select
Enable Down
1
1
0
TX HDX 10 FDX 10 HDX
Cap.
Cap.
Cap.
1
1
1
0
0
0
OUI_LSB
101110
FLP Rcv Remote
Reserved
Ack
Fault
LP
LP
Reserved
Ack
RF
10
Isolate
0
9
8
Restart
Full
Auto-N Duplex
0
1
Reserved
7
Coll.
Test
0
6
5
Pream. Auto-N
Supr.
Compl.
0000
1
0
0
1
1
0
0
Model No.
01010
T4
TX FDX TX HDX 10 FDX 10 HDX
Adv
Adv
Adv
Adv
Adv
LP
LP
LP
LP
LP
T4
TX FDX TX HDX 10 FDX 10 HDX
0
FC
Adv
LP
FC
Reserved
BP
SCR
BP
BP_ADP Reserve
ALIGN
OK
dr
100
HDX
10
FDX
LP
Enable
HBE
Enable
TX
19
PWDOR
20
Specified TSTSE1 TSTSE2 FORCE_ FORCE_
config
TXSD
FEF
JAB
Enable
Remote
Fault
0
0
3
Reserved
2
Next Pg
Able
Reserve Reserve Force Reserve Reserve RPDCTR Reset
d
d
100LNK
d
d
-EN
St. Mch
Pream.
Supr.
Reserved
PHY ADDR [4:0]
Reserved
PDchip
Extd
Cap.
1
1
New Pg LP AutoN
Rcv
Cap.
Sleep
mode
Remote
LoopOut
Auto-N. Monitor Bit [3:0]
Reserved
PD10DR PD100l
V
0
Link Partner Protocol Selector Field
LP Next
Pg Able
Reserve
d
1
000_0000
Auto-N
Link
Jabber
Cap.
Status
Detect
1
0
0
0
0
0
Version No.
0000
Advertised Protocol Selector Field
Pardet
Fault
10 HDX Reserve Reverse Reverse
d
d
d
SQUE
Enable
4
PDcrm
Polarity
Reverse
PDaeq
PDdrv
PDecli
PDeclo
PD10
MDIX_C AutoNeg Mdix_fix Mdix_do MonSel1 MonSel0 Reserve PD_valu
NTL
_dlpbk
Value
wn
d
e
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
<Access Type>:
RO = Read only
RW = Read/Write
Where:
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
30
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
8.1 Basic Mode Control Register (BMCR) - 00
Bit
Bit Name
Default
Description
0.15
Reset
0, RW/SC Reset
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of
one until the reset process is completed
0.14
Loopback
0, RW
Loopback
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead
time" before any valid data appears at the MII receive outputs
0.13
Speed selection
1, RW
Speed Select
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by auto-negotiation.
When auto-negotiation is enabled and bit 12 is set, this bit will return
auto-negotiation selected medium type
0.12
Auto-negotiation
1, RW
Auto-negotiation Enable
enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in
auto-negotiation status
0.11
Power down
0, RW
Power Down
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down state
and while in the power-down state, the PHY should not generate
spurious signals on the MII
1=Power down
0=Normal operation
0.10
Isolate
0,RW
Isolate
Force to 0 in application.
0.9
Restart
0,RW/SC Restart Auto-negotiation
Auto-negotiation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
self-clearing and it will keep returning to a value of 1 until
auto-negotiation is initiated by the DM9010BI. The operation of the
auto-negotiation process will not be affected by the management
entity that clears this bit
0 = Normal operation
0.8
Duplex mode
1,RW
Duplex Mode
1 = Full duplex operation. Duplex selection is allowed when
Auto-negotiation is disabled (bit 12 of this register is cleared). With
auto-negotiation enabled, this bit reflects the duplex capability
selected by auto-negotiation
0 = Normal operation
0.7
Collision test
0,RW
Collision Test
1 = Collision test enabled. When set, this bit will cause the COL
signal to be asserted in response to the assertion of TX_EN in
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
31
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
0.6-0.0
Reserved
0,RO
internal MII interface.
0 = Normal operation
Reserved
Read as 0, ignore on write
8.2 Basic Mode Status Register (BMSR) - 01
Bit
Bit Name
Default
Description
1.15
100BASE-T4
0,RO/P 100BASE-T4 Capable
1 = DM9010BI is able to perform in 100BASE-T4 mode
0 = DM9010BI is not able to perform in 100BASE-T4 mode
1.14
100BASE-TX
1,RO/P 100BASE-TX Full Duplex Capable
full-duplex
1 = DM9010BI is able to perform 100BASE-TX in full duplex mode
0 = DM9010BI is not able to perform 100BASE-TX in full duplex
mode
1.13
100BASE-TX
1,RO/P 100BASE-TX Half Duplex Capable
half-duplex
1 = DM9010BI is able to perform 100BASE-TX in half duplex mode
0 = DM9010BI is not able to perform 100BASE-TX in half duplex
mode
1.12
10BASE-T
1,RO/P 10BASE-T Full Duplex Capable
full-duplex
1 = DM9010BI is able to perform 10BASE-T in full duplex mode
0 = DM9010BI is not able to perform 10BASE-TX in full duplex mode
1.11
10BASE-T
1,RO/P 10BASE-T Half Duplex Capable
half-duplex
1 = DM9010BI is able to perform 10BASE-T in half duplex mode
0 = DM9010BI is not able to perform 10BASE-T in half duplex mode
1.10-1.7
Reserved
0,RO
Reserved
Read as 0, ignore on write
1.6
MF preamble
1,RO
MII Frame Preamble Suppression
suppression
1 = PHY will accept management frames with preamble suppressed
0 = PHY will not accept management frames with preamble
suppressed
1.5
Auto-negotiation
0,RO
Auto-negotiation Complete
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
1.4
Remote fault
0, RO/LH Remote Fault
1 = Remote fault condition detected (cleared on read or by a chip
reset). Fault criteria and detection method is DM9010BI
implementation specific. This bit will set after the RF bit in the
ANLPAR (bit 13, register address 05) is set
0 = No remote fault condition detected
1.3
Auto-negotiation
1,RO/P Auto Configuration Ability
ability
1 = DM9010BI is able to perform auto-negotiation
0 = DM9010BI is not able to perform auto-negotiation
1.2
Link status
0,RO/LL Link Status
1 = Valid link is established (for either 10Mbps or 100Mbps
operation)
0 = Link is not established
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the link status bit to be
cleared and remain cleared until it is read via the management
interface
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
32
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
1.1
Jabber detect
0, RO/LH
1.0
Extended
1,RO/P
capability
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a DM9010BI reset. This bit works only in
10Mbps mode
Extended Capability
1 = Extended register capable
0 = Basic register capable only
8.3 PHY ID Identifier Register #1 (PHYID1) - 02
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9010BI. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a
model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
Default
Description
2.15-2.0
OUI_MSB
<0181h>
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) - 03
Bit
3.15-3.10
Bit Name
OUI_LSB
Default
<101110>,
RO/P
3.9-3.4
VNDR_MDL
<001011>,
RO/P
3.3-3.0
MDL_REV
<0000>,
RO/P
Description
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
Vendor Model Number
Five bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
Model Revision Number
Five bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 4)
8.5 Auto-negotiation Advertisement Register (ANAR) - 04
This register contains the advertised abilities of this DM9010BI device as they will be transmitted to its link partner
during Auto-negotiation.
Bit
4.15
Bit Name
NP
Default
0,RO/P
4.14
ACK
0,RO
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Description
Next page Indication
0 = No next page available
1 = Next page available
The DM9010BI has no next page, so this bit is permanently set to 0
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9010BI's auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the auto-negotiation process. Software
should not attempt to write to this bit.
33
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
4.13
RF
4.12-4.11
Reserved
4.10
FCS
4.9
T4
4.8
TX_FDX
4.7
TX_HDX
4.6
10_FDX
4.5
10_HDX
4.4-4.0
Selector
0, RW
Remote Fault
1 = Local device senses a fault condition
0 = No fault detected
X, RW
Reserved
Write as 0, ignore on read
0, RW
Flow Control Support
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
0, RO/P
100BASE-T4 Support
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
The DM9010BI does not support 100BASE-T4 so this bit is
permanently set to 0
1, RW
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the local device
0 = 100BASE-TX full duplex is not supported
1, RW
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the local device
0 = 100BASE-TX half duplex is not supported
1, RW
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the local device
0 = 10BASE-T full duplex is not supported
1, RW
10BASE-T Support
1 = 10BASE-T half duplex is supported by the local device
0 = 10BASE-T half duplex is not supported
<00001>, RW Protocol Selection Bits
These bits contain the binary encoded protocol selector supported
by this node
<00001> indicates that this device supports IEEE 802.3 CSMA/CD
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05
This register contains the advertised abilities of the link partner when received during Auto-negotiation.
Bit
Bit Name
Default
Description
5.15
NP
0, RO
Next Page Indication
0 = Link partner, no next page available
1 = Link partner, next page available
5.14
ACK
0, RO
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9010BI's auto-negotiation state machine will automatically
control this bit from the incoming FLP bursts. Software should not
attempt to write to this bit
5.13
RF
0, RO
Remote Fault
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
5.12-5.11
Reserved
0, RO
Reserved
Read as 0, ignore on write
5.10
FCS
0, RO
Flow Control Support
1 = Controller chip supports flow control ability by link partner
0 = Controller chip doesn’t support flow control ability by link
partner
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
5.9
T4
5.8
TX_FDX
5.7
TX_HDX
5.6
10_FDX
5.5
10_HDX
5.4-5.0
Selector
0, RO
100BASE-T4 Support
1 = 100BASE-T4 is supported by the link partner
0 = 100BASE-T4 is not supported by the link partner
0, RO
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the link partner
0 = 100BASE-TX full duplex is not supported by the link partner
0, RO
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the link partner
0 = 100BASE-TX half duplex is not supported by the link partner
0, RO
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the link partner
0 = 10BASE-T full duplex is not supported by the link partner
0, RO
10BASE-T Support
1 = 10BASE-T half duplex is supported by the link partner
0 = 10BASE-T half duplex is not supported by the link partner
<00000>, RO Protocol Selection Bits
Link partner’s binary encoded protocol selector
8.7 Auto-negotiation Expansion Register (ANER) - 06
Bit
Bit Name
Default
Description
6.15-6.5
Reserved
0, RO
Reserved
Read as 0, ignore on write
6.4
PDF
0, RO/LH
Local Device Parallel Detection Fault
PDF = 1: A fault detected via parallel detection function.
PDF = 0: No fault detected via parallel detection function
6.3
LP_NP_ABLE
0, RO
Link Partner Next Page Able
LP_NP_ABLE = 1: Link partner, next page available
LP_NP_ABLE = 0: Link partner, no next page
6.2
NP_ABLE
0,RO/P
Local Device Next Page Able
NP_ABLE = 1: DM9010BI, next page available
NP_ABLE = 0: DM9010BI, no next page
DM9010BI does not support this function, so this bit is always 0
6.1
PAGE_RX
0, RO/LH
New Page Received
A new link code word page received. This bit will be automatically
cleared when the register (register 6) is read by management
6.0
LP_AN_ABLE
0, RO
Link Partner Auto-negotiation Able
A “1” in this bit indicates that the link partner supports
Auto-negotiation
8.8 DAVICOM Specified Configuration Register (DSCR) - 16
Bit
Bit Name
Default
Description
16.15
BP_4B5B
0,RW
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
16.14
BP_SCR
0, RW
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
16.13
BP_ALIGN
0, RW
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions (symbol encoder
and scrambler) bypassed
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
16.12
BP_ADPOK
0, RW
16.11
Reserved
RW
16.10
TX
1, RW
16.9
16.8
Reserved
Reserved
0, RO
0, RW
16.7
F_LINK_100
0, RW
16.6
Reserved
0, RW
16.5
Reserved
0, RW
16.4
RPDCTR-EN
1, RW
16.3
SMRST
0, RW
0 = Normal operation
BYPASS ADPOK
Force signal detector (SD) active. This register is for debug only,
not release to customer
1=Forced SD is OK,
0=Normal operation
Reserved
Force to 0 in application
100BASE-TX Mode Control
1 = 100BASE-TX operation
Reserved
Reserved
Force to 0 in application.
Force Good Link in 100Mbps
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Force to 0 in application.
Reserved
Force to 0 in application.
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 = Disable automatic reduced power down
1 = Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
16.2
16.1
MFPSC
SLEEP
1, RW
0, RW
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
16.0
RLOUT
0, RW
machine will be reset
Remote Loop out Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
17.15
Bit Name
100FDX
Default
1, RO
17.14
100HDX
1, RO
17.13
10FDX
1, RO
17.12
10HDX
1, RO
17.11-17. Reserved
9
17.8-17.4 PHYADR[4
:0]
17.3-17.0 ANMB[3:0]
0, RO
1, RW
0, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M full duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
Reserved
Read as 0, ignore on write
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple PHY
entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be written to
these bits.
B3 b2 b1 B0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
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Version: DM9010BI--DS-P01
January 12, 2010
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
Auto-negotiation completed successfully
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
8.10 10BASE-T Configuration/Status (10BTCSR) - 18
Bit
18.15
Bit Name
Reserved
Default
0, RO
18.14
LP_EN
1, RW
18.13
HBE
1,RW
18.12
SQUELCH
1, RW
18.11
JABEN
1, RW
18.10
Reserved
0, RW
18.9-18.1
Reserved
0, RO
18.0
POLR
0, RO
Description
Reserved
Read as 0, ignore on write
Link Pulse Enable
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation
Heartbeat Enable
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the DM9010BI is configured for full duplex operation, this bit will
be ignored (the collision/heartbeat function is invalid in full duplex
mode)
Squelch Enable
1 = Normal squelch
0 = Low squelch
Jabber Enable
Enables or disables the Jabber function when the DM9010BI is in
10BASE-T full duplex or 10BASE-T transceiver Loopback mode
1 = Jabber function enabled
0 = Jabber function disabled
Reserved
Force to 0, in application.
Reserved
Read as 0, ignore on write
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable polarity is
reversed. This bit is automatically set and cleared by 10BASE-T
module
8.11 Power Down Control Register (PWDOR) - 19
Bit
19.15-19.9
Bit Name
Reserved
Description
Reserved
Read as 0, ignore on write
19.8
PD10DRV
0, RW
Vendor power down control test
19.7
PD100DL
0, RW
Vendor power down control test
19.6
PDchip
0, RW
Vendor power down control test
19.5
PDcom
0, RW
Vendor power down control test
19.4
PDaeq
0, RW
Vendor power down control test
19.3
PDdrv
0, RW
Vendor power down control test
19.2
PDedi
0, RW
Vendor power down control test
19.1
PDedo
0, RW
Vendor power down control test
19.0
PD10
0, RW
Vendor power down control test
* When selected, the power down value is control by Register 20.0
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Default
0, RO
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
8.12 (Specified config) Register – 20
Bit
20.15
20.14
20.13
20.12
20.11
20.10
20.9
20.8
20.7
20.6
20.5
20.4
20.3
20.2
20.1
20.0
Bit Name
TSTSE1
TSTSE2
FORCE_TXSD
Description
Vendor test select control
Vendor test select control
Force Signal Detect
1: force SD signal OK in 100M
0: normal SD signal.
FORCE_FEF
0,RW
Vendor test select control
NWAY
0,RW
Auto-negotiation Power Saving Mode
0: save power in auto-negotiation state (Default)
1: full power in auto-negotiation state
TX10M
0,RW
10M Transmit Power Saving Mode
0: full power in 10M mode (Default)
1: save power in 10M mode
Reserved
0,RW
Reserved
Reserved
0,RW
Reserved
MDI/MDIX,RO The polarity of MDI/MDIX value
MDIX_CNTL
1: MDIX mode
0: MDI mode
AutoNeg_dpbk
0,RW
Auto-negotiation Loopback
1: test internal digital auto-negotiation Loopback
0: normal.
Mdix_fix Value
0, RW
MDIX_CNTL force value:
When Mdix_down = 1, MDIX_CNTL value depend on the register
value.
Mdix_down
0,RW
MDIX Down
Manual force MDI/MDIX.
0: Enable HP Auto-MDIX
1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5
MonSel1
0,RW
Vendor monitor select
MonSel0
0,RW
Vendor monitor select
Reserved
0,RW
Reserved
Force to 0, in application.
PD_value
0,RW
Power down control value
Decision the value of each field Register 19.
1: power down
0: normal
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Default
0,RW
0,RW
0,RW
39
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
9. FUNCTIONAL DESCRIPTION
9.1 Host Interface
The host interface is the ISA BUS compatible mode.
There are eight IO bases, which are 300H, 310H,
320H, 330H, 340H, 350H, 360H, and 370H. The IO
base is latched from strap pins or loaded from the
EEPROM.
There are only two addressing ports through the
access of the host interface. One port is the INDEX
port and the other is the DATA port. The INDEX port is
decoded by the pin CMD =0 and the DATA port by the
pin CMD =1. The contents of the INDEX port are the
register address of the DATA port. Before the access
of any register, the address of the register must be
saved in the INDEX port.
9.2 Direct Memory Access Control
The DM9010BI provides DMA capability to simplify
the access of the internal memory. After the
programming of the starting address of the internal
memory and then issuing a dummy read/write
command to load the current data to internal data
buffer, the desired location of the internal memory can
be accessed by the read/write command registers.
The memory’s address will be increased with the size
that equals to the current operation mode (i.e. the
8-bit, 16-bit or 32-bit mode) and the data of the next
location will be loaded into internal data buffer
automatically. It is noted that the data of the first
access (the dummy read/write command) in a
sequential burst should be ignored because that the
data was the contents of the last read/write command.
The internal memory size is 16K bytes. The first
location of 3K bytes is used for the data buffer of the
packet transmission. The other 13K bytes are used for
the buffer of the receiving packets. So in the write
memory operation, when the bit 7 of IMR is set, the
memory address increment will wrap to location 0 if
the end of address (i.e. 3K) is reached. In a similar
way, in the read memory operation, when the bit 7 of
IMR is set, the memory address increment will wrap to
location 0x0C00 if the end of address (i.e. 16K) is
reached.
9.3 Packet Transmission
There are two packets, sequentially named as index I
and index II, can be stored in the TX SRAM at the
same time. The index register 02h controls the
insertion of CRC and pads. Their statuses are
recorded at index registers 03h and 04h respectively.
The start address of transmission is 00h and the
current packet is index I after software or hardware
reset. Firstly write data to the TX SRAM using the
DMA port and then write the byte count to byte_ count
register at index register 0fch and 0fdh. Set the bit 1 of
control register. The DM9010BI starts to transmit the
index I packet. Before the transmission of the index I
packet ends, the data of the next (index II) packet can
be moved to TX SRAM. After the index I packet ends
the transmission, write the byte count data of the
index II to BYTE_COUNT register and then set the bit
1 of control register to transmit the index II packet.
The following packets, named index I, II, I, II, use the
same way to be transmitted.
9.4 Packet Reception
The RX SRAM is a ring data structure. The start
address of RX SRAM is 0C00h after software or
hardware reset. Each packet has a 4-byte header
followed with the data of the reception packet which
CRC field is included. The format of the 4-byte header
is 01h, status, BYTE_COUNT low, and
BYTE_COUNT high. It is noted that the start address
of each packet is in the proper address boundary
which depends on the operation mode (the 8-bit,
16-bit or 32-bit mode).
functional blocks:
9.5 100Base-TX Operation
The block diagram in figure 3 provides an overview of
the functional blocks contained in the transmit section.
The transmitter section contains the following
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
- NRZ to NRZI Converter
- NRZI to MLT-3
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
- MLT-3 Driver
9.5.1 4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data
generated by the MAC Reconciliation Layer into a
5-bit (5B) code group for transmission, see reference
Table 1. This conversion is required for control and
packet data to be combined in code groups. The
4B5B encoder substitutes the first 8 bits of the MAC
preamble with a J/K code-group pair (11000 10001)
upon transmit. The 4B5B encoder continues to
replace subsequent 4B preamble and data nibbles
with corresponding 5B code-groups. At the end of the
transmit packet, upon the deassertion of the Transmit
Enable signal from the MAC Reconciliation layer, the
4B5B encoder injects the T/R code-group pair (01101
00111) indicating the end of frame. After the T/R
code-group pair, the 4B5B encoder continuously
injects IDLEs into the transmit data stream until
Transmit Enable is asserted and the next transmit
packet is detected.
The DM9010BI includes a Bypass 4B5B conversion
option within the 100Base-TX Transmitter for support
of applications like 100 Mbps repeaters which do not
require 4B5B conversion.
9.5.2 Scrambler
The scrambler is required to control the radiated
emissions (EMI) by spreading the transmit energy
across the frequency spectrum at the media
connector and on the twisted pair cable in
100Base-TX operation.
By scrambling the data, the total energy presented to
the cable is randomly distributed over a wide
frequency range. Without the scrambler, energy levels
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
on the cable could peak beyond FCC limitations at
frequencies related to the repeated 5B sequences,
like the continuous transmission of IDLE symbols.
The scrambler output is combined with the NRZ 5B
data from the code-group encoder via an XOR logic
function. The result is a scrambled data stream with
sufficient randomization to decrease radiated
emissions at critical frequencies.
9.5.3 Parallel to Serial Converter
The Parallel to Serial Converter receives parallel 5B
scrambled data from the scrambler, and serializes it
(converts it from a parallel to a serial data stream).
The serialized data stream is then presented to the
NRZ to NRZI encoder block
9.5.4 NRZ to NRZI Encoder
After the transmit data stream has been scrambled
and serialized, the data must be NRZI encoded for
compatibility with the TP-PMD standard, for 100Base
-TX transmission over Category-5 unshielded twisted
pair cable.
9.5.5 MLT-3 Converter
The MLT-3 conversion is accomplished by converting
The data stream output, from the NRZI encoder into
two binary data streams, with alternately phased logic
One event.
9.5.6 MLT-3 Driver
The two binary data streams created at the MLT-3
converter are fed to the twisted pair output driver,
which converts these streams to current sources and
alternately drives either side of the transmit
transformer’s primary winding, resulting in a minimal
current MLT-3 signal. Refer to figure 4 for the block
diagram of the MLT-3 converter.
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
9.5.7 4B5B Code Group
Symbol
Meaning
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
4B code
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
J
K
T
R
H
Idle
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
undefined
0101
0101
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Table 1
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
42
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
9.6 100Base-TX Receiver
The 100Base-TX receiver contains several function
blocks that convert the scrambled 125Mb/s serial data
to synchronous 4-bit nibble data that is then provided
to the MII.
The receive section contains the following functional
blocks:
- Signal Detect
- Digital Adaptive Equalization
- MLT-3 to Binary Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
9.6.1 Signal Detect
The signal detects function meets the specifications
mandated by the ANSI XT12 TP-PMD 100Base-TX
standards for both voltage thresholds and timing
parameters.
9.6.2 Adaptive Equalization
When transmitting data over copper twisted pair cable
at high speed, attenuation based on frequency
becomes a concern. In high speed twisted pair
signaling, the frequency content of the transmitted
signal can vary greatly during normal operation based
on the randomness of the scrambled data stream.
This variation in signal attenuation, caused by
frequency variations, must be compensated for to
ensure the integrity of the received data. In order to
ensure quality transmission when employing MLT-3
encoding, the compensation must be able to adapt to
various cable lengths and cable types depending on
the installed environment. The selection of long cable
lengths for a given implementation requires significant
compensation, which will be over-killed in a situation
that includes shorter, less attenuating cable lengths.
Conversely, the selection of short or intermediate
cable lengths requiring less compensation will cause
serious under-compensation for longer length cables.
Therefore, the compensation or equalization must be
adaptive to ensure proper conditioning of the received
signal independent of the cable length.
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Version: DM9010BI--DS-P01
January 12, 2010
9.6.3 MLT-3 to NRZI Decoder
The DM9010BI decodes the MLT-3 information from
the Digital Adaptive Equalizer into NRZI data. The
relationship between NRZI and MLT-3 data is shown
In figure 4.
9.6.4 Clock Recovery Module
The Clock Recovery Module accepts NRZI data from
the MLT-3 to NRZI decoder. The Clock Recovery
Module locks onto the data stream and extracts the
125 MHz reference clock. The extracted and
synchronized clock and data are presented to the
NRZI to NRZ decoder.
9.6.5 NRZI to NRZ
The transmit data stream is required to be NRZI
encoded for compatibility with the TP-PMD standard
for 100Base-TX transmission over Category-5
unshielded twisted pair cable. This conversion
process must be reversed on the receive end. The
NRZI to NRZ decoder receives the NRZI data stream
from the Clock Recovery Module and converts it to a
NRZ data stream to be presented to the Serial to
Parallel conversion block.
9.6.6 Serial to Parallel
The Serial to Parallel Converter receives a serial data
stream from the NRZI to NRZ converter. It converts
the data stream to parallel data to be presented to the
descrambler.
9.6.7 Descrambler
Because of the scrambling process requires to control
the radiated emissions of transmit data streams, the
receiver must descramble the receive data streams.
The descrambler receives scrambled parallel data
streams from the Serial to Parallel converter, and it
descrambles the data streams, and presents the data
streams to the Code Group alignment block.
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
9.6.8 Code Group Alignment
The Code Group Alignment block receives un-aligned
5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after
the J/K is detected and subsequent data is aligned on
a fixed boundary.
9.9 Carrier Sense
Carrier Sense (CRS) is asserted in half-duplex
operation during transmission or reception of data.
During full-duplex mode, CRS is asserted only during
receive operations.
9.6.9 4B5B Decoder
The 4B5B Decoder functions as a look-up table that
translates incoming 5B code groups into 4B (Nibble)
data. When receiving a frame, the first 2 5-bit code
groups receive the start-of-frame delimiter (J/K
symbols). The J/K symbol pair is stripped and two
nibbles of preamble pattern are substituted. The last
two code groups are the end-of-frame delimiter (T/R
Symbols).
The T/R symbol pair is also stripped from the nibble,
presented to the Reconciliation layer.
9.7 10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant.
When the DM9010BI is operating in 10Base-T mode,
the coding scheme is Manchester. Data processed for
transmit is presented to the MII interface in nibble
format, converted to a serial bit stream, then the
Manchester encoded. When receiving, the bit stream,
encoded by the Manchester, is decoded and
converted into nibble format to present to the MII
interface.
9.8 Collision Detection
For half-duplex operation, a collision is detected when
the transmit and receive channels are active
simultaneously. When a collision is detected, it will be
reported by the COL signal on the MII interface.
Collision detection is disabled in Full Duplex
Operation.
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
9.10 Auto-Negotiation
The objective of Auto-negotiation is to provide a
means to exchange information between linked
devices and to automatically configure both devices to
take maximum advantage of their abilities. It is
important to note that Auto-negotiation does not test
the characteristics of the linked segment. The
Auto-Negotiation function provides a means for a
device to advertise supported modes of operation to a
remote link partner, acknowledge the receipt and
understanding of common modes of operation, and to
reject un-shared modes of operation. This allows
devices on both ends of a segment to establish a link
at the best common mode of operation. If more than
one common mode exists between the two devices, a
mechanism is provided to allow the devices to resolve
to a single mode of operation using a predetermined
priority resolution function.
Auto-negotiation also provides a parallel detection
function for devices that do not support the
Auto-negotiation feature. During Parallel detection
there is no exchange of information of configuration.
Instead, the receive signal is examined. If it is
discovered that the signal matches a technology,
which the receiving device supports, a connection will
be automatically established using that technology.
This allows devices not to support Auto-negotiation
but support a common mode of operation to establish
a link.
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
9.11 Power Reduced Mode
9.11.1 Power Down Mode
The Signal detect circuit is always turned to monitor whether
there is any signal on the media (cable disconnected). The
DM9010BI automatically turns off the power and enters the
Power Reduced mode, whether its operation mode is
N-way or force mode. When enters the Power Reduced
mode, the transmit circuit still sends out fast link pules with
minimum power consumption. If a valid signal is detected
from the media, which might be N-ways fast link pules,
10Base-T normal link pules, or 100Base-TX MLT3 signals,
the device will wake up and resume a normal
operation mode.
The PHY Reg.0.11 can be set high to enter the Power
Down mode, which disables all transmit, receive functions
and MII interface functions, except the MDC/MDIO
management interface.
That can be writing Zero to PHY Reg.16.4 to disable Power
Reduced mode.
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
9.11.2 Reduced Transmit Power Mode
The additional Transmit power reduction can be
gained by designing with 1.25:1 turns ration magnetic
on its TX side and using a 8.5KΩ resistor on BGRES
and AGND pins, and the TXO+/TXO- pulled high
resistors should be changed from 50Ω to 78Ω. This
configuration could be reduced about 20% transmit
power.
45
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
10. DC AND AC ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings (-40°C ~ +85°C)
Symbol
Parameter
DVDD
Supply Voltage
VIN
DC Input Voltage (VIN)
VOUT
DC Output Voltage(VOUT)
Storage Temperature range
TSTG
Ambient Temperature
TA
Lead Temperature
LT
(TL, soldering, 10 sec.).
10.1.1 Operating Conditions
Symbol
Parameter
DVDD
Supply Voltage
PD
100BASE-TX
(Power
10BASE-T TX
Dissipation)
10BASE-T TX (100% utilization)
Min.
-0.3
-0.5
-0.3
-65
-40
-
Max.
3.6
5.5
3.6
+150
+85
+260
Unit
V
V
V
°C
°C
°C
Conditions
Min.
3.135
-------
Typ.
3.300
130
170
160
Max.
3.465
-------
Unit
V
mA
mA
mA
10BASE-T idle
---
60
---
mA
Auto-negotiation
Power Down Mode
Power Down Mode (system clock off)
-------
60
20
6
-------
mA
mA
mA
10.2 DC Electrical Characteristics (VDD = 3.3V)
Symbol
Parameter
Min.
Inputs
VIL
Input Low Voltage
VIH
Input High Voltage
2.0
IIL
Input Low Leakage Current
-1
IIH
Input High Leakage Current
Outputs
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
Receiver
VICM
RX+/RX- Common Mode Input
Voltage
Transmitter
VTD100 100TX+/- Differential Output
1.9
Voltage
VTD10
10TX+/- Differential Output Voltage
4.0
ITD100
100TX+/- Differential Output
│19│
Current
ITD10
10TX+/- Differential Output Current │40│
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Typ.
Conditions
3.3V
3.3V
3.3V,power
saving
3.3V,power
saving
3.3V
3.3V
3.3V
Max.
Unit
Conditions
-
0.8
1
V
V
uA
uA
VIN = 0.0V
VIN = 3.3V
-
0.4
-
V
V
IOL = 4mA
IOH = -4mA
1.8
-
V
100 Ω Termination
Across
2.0
2.1
V
Peak to Peak
5
│20│
5.6
│21│
V
mA
Peak to Peak
Absolute Value
│50│
│56│
mA
Absolute Value
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
10.3 AC Electrical Characteristics & Timing Waveforms
10.3.1 TP Interface
Symbol
Parameter
tTR/F
100TX+/- Differential Rise/Fall Time
tTM
100TX+/- Differential Rise/Fall Time
Mismatch
tTDC
100TX+/- Differential Output Duty Cycle
Distortion
tT/T
100TX+/- Differential Output Peak-to-Peak
Jitter
XOST
100TX+/- Differential Voltage Overshoot
10.3.2 Oscillator/Crystal Timing
Symbol
Parameter
TCKC
TCKC
TPWH
OSC Pulse Width High
TPWL
OSC Pulse Width Low
Min.
3.0
0
Typ.
-
Max.
5.0
0.5
Unit
ns
ns
0
-
0.5
ns
0
-
1.4
ns
0
-
5
%
Min.
39.998
16
16
Typ.
40
20
20
Max.
40.002
24
24
Unit
ns
ns
ns
Conditions
Conditions
50ppm
10.3.3 Power On Reset Timing
T1
PWRST#
T4
Strap pins
T2
EECS
T3
Symbol
T1
T2
T3
T4
Parameter
PWRST# Low Period
Strap pin hold time with PWRST#
PWRST# high to EECS high
PWRST# high to EECS burst end
Min.
1
40
-
Typ.
11.31
--
Max.
3
Unit
ms
ns
us
ms
Conditions
-
Note: The DM9010BI needs the time about 3ms to down load the setting from EEPROM after PWRST# deasserted,
During the period, the processor command (IOR#, IOW#, AEN#) pins are not recognized even no EEPROM present. So,
please note that processor only access DM9010BI after PWRST# deasserted 3ms.
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
47
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
10.3.4 Processor I/O Read Timing
Symbol
T1
T2
T3
T4
T5
T6
T2+T6
T2+T6
T7
T8
Parameter
System Address(SA) valid to IOR# valid
IOR# width
IOR# valid to System Data(SD) valid
IOR# invalid to System Data(SD) bus invalid
IOR# invalid to System Address(SA) invalid
IOR# invalid to next IOR#/IOW# valid
When read DM9010BI register
IOR# valid to next IOR#/IOW# valid
When read DM9010BI memory with F0h register
IOR# valid to next IOR#/IOW# valid
When read DM9010BI memory with F2h register
System Address(SA) valid to IO16,IO32 valid
System Address(SA) invalid to IO16, IO32 invalid
*Note:(The default clk period is 20ns)
1. The IO16 is valid when the SD bus width is 16-bit or
32-bit, and the system address is DATA port (i.e.
CMD is high) and the value of INDEX port is
memory data register index.(ex. F0H, F2H, F6H or
F8H)
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Min.
0
10
Typ.
Max.
0
2
Unit
ns
ns
ns
ns
ns
clk*
4
clk*
1
clk*
3
3
3
3
ns
ns
2. The IO32 is valid when the SD bus width is 32-bit,
the system address is DATA port (i.e. CMD is high)
and the value of INDEX port is memory data
register index(ex. F0H, F2H, F6H or F8H)
48
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
10.3.5 Processor I/O Write Timing
→
T1
→
←
AEN,SA,CMD
←
IOW
SD
→
Symbol
T1
T2
T3
T4
T5
T6
T6
T2+T6
T7
T8
→
←
IO16,IO32
←
←
→
T2
T3
Parameter
System Address(SA) valid to IOW# valid
IOW# width
System Data(SD) setup time
System Data (SD) hold time
IOW# invalid to System Address(SA) invalid
IOW# Invalid to next IOW#/IOR# valid
When write DM9010BI INDEX port
IOW# Invalid to next IOW#/IOR# valid
When write DM9010BI DATA port
IOW# valid to next IOW#/IOR# valid
When write DM9010BI memory
System Address(SA) valid to IO16, IO32 valid
System Address(SA) invalid to IO16, IO32 invalid
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
T5
→
T6
∫∫
←
T4
→
T7
Note:(The default clk period is 20ns)
1. The IO16 is valid when the SD bus width is 16-bit or
32-bit and system address is DATA port (i.e. CMD
is high) and the value of INDEX port is memory
data register index (ex. F0H, F2H, F6H or F8H)
←
Note1.2
→ ←
T8
Min.
0
10
3
3
0
1
Typ.
Max.
Unit
ns
ns
ns
ns
ns
clk*
2
clk*
1
clk*
3
3
ns
ns
2. The IO32 is valid when the SD bus width is 32-bit
and system address is DATA port (i.e. CMD is high)
and the value of INDEX port is memory data
Register index (ex. F0H, F2H, F6H or F8H)
49
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
10.3.6 External MII Interface Transmit Timing
←
T2
→
∫∫
TXCK
∫∫
TXEN
→
T1
←
∫∫
TXD[3:0]
Symbol
T1
T2
Parameter
TXEN,TXD[3:0] Setup Time
TXEN,TXD[3:0] Hold Time
Min.
Typ.
32
8
Max.
Unit
ns
ns
10.3.7 External MII Interface Receive Timing
RXCK
∫∫
RXER,RXDV
→
T1
←
RXD[3:0]
Symbol
T1
T2
Parameter
RXER, RXDV,RXD[3:0] Setup Time
RXER, RXDV,RXD[3:0] Hold Time
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
→
T2
←
∫∫
Min.
5
5
Typ.
Max. Unit
ns
ns
50
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
10.3.8 MII Management Interface Timing
T1
MDC
T2
MDIO(drived by DM9010B)
T4
T3
MDIO (drived by exetrnal MII)
T5
Symbol
T1
T2
T3
T4
T5
Parameter
MDC Frequency
MDIO by DM9010BI Setup Time
MDIO by DM9010BI Hold Time
MDIO by External MII Setup Time
MDIO by External MII Hold Time
Min.
Typ.
2
187
313
Max.
40
40
Unit
MHz
ns
ns
ns
ns
10.3.9 EEPROM Interface Timing
T2
T3
EECS
T1
EECK
T4
EEDO
T6
T5
EEDI
T7
Symbol
T1
T2
T3
T4
T5
T6
T7
Parameter
EECK Frequency
EECS Setup Time
EECS Hold Time
EEDO Setup Time
EEDO Hold Time
EEDI Setup Time
EEDI Hold Time
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Min.
8
8
Typ.
0.375
500
2166
480
2200
Max.
Unit
MHz
ns
ns
ns
ns
ns
51
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
11. APPLICATION NOTES
11.1 Network Interface Signal Routing
Place the transformer as close as possible to the RJ-45
connector. Place all the 50Ω resistors as close as possible
to the DM9010BI RXI± and TXO± pins. Traces routed from
RXI± and TXO± to the transformer should run in close pairs
directly to the transformer. The designer should be careful
not to cross the transmit and receive pairs. As always, vias
should be avoided as much as possible. The network
interface should be void of any signals other than the TXO±
and RXI± pairs between the RJ-45 to the transformer and
the transformer to the DM9010BI.. There should be no
power or ground planes in the area under the network side
of the transformer to include the area under the RJ-45
connector. (Refer to Figure 11-4 and 11-5) Keep chassis
ground away from all active signals. The RJ-45 connector
and any unused pins should be tied to chassis ground
through a resistor divider network and a 2KV bypass
capacitor.
The Band Gap resistor should be placed as physically close
as pins 25 and 26 as possible (refer to Figure 11-1 and
11-2). The designer should not run any high-speed signal
near the Band Gap resistor placement.
11.2 10Base-T/100Base-TX HP Auto-MDIX Application
Figure 11-1 HP Auto-MDIX Application
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
11.3 10Base-T/100Base-TX ( Non HP Auto-MDIX Transformer Application )
Figure 11-2 Non HP Auto-MDIX Transformer Application
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
53
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
11.4 Power Decoupling Capacitors
Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to
the power pads of the DM9010BI (The best placed distance is < 3mm from pin). The recommended decoupling capacitor is
0.1μF or 0.01μF, as required by the design layout.
Figure 11-3 Power Decoupling Capacitors
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
54
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
11.5 Ground Plane Layout
Davicom Semiconductor recommends a single ground
plane approach to minimize EMI. Ground plane partitioning
can cause increased EMI emissions that could make the
network interface card not comply with specific FCC
regulations (part 15). Figure 11-4 shows a recommended
ground layout scheme.
Figure 11-4 Ground Plane Layout
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
55
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
11.6 Power Plane Partitioning
The power planes should be approximately illustrated in Figure 11-5.
Figure 11-5 Power Plane Partitioning
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
11.7 Magnetics Selection Guide
Refer to the following table for 10/100M magnetic
specification requirements. The magnetic which meet
these requirements are available from a variety of
magnetic manufacturers. Designers should test and
qualify all magnetic specifications before using them
in an application. Industrial-temperature range, RoHS
regulations, please contact with your magnetic
vendor, this table only for you reference,
Parameter
Values
Units
Test Condition
Tx / RX turns ratio
1:1 CT / 1:1
-
-
Inductance
350
μH (Min)
-
Insertion loss
1.1
dB ( Max )
1 – 100 MHz
-18
dB ( Min )
1 –30 MHz
-14
dB ( Min )
30 – 60 MHz
-12
dB ( Min )
60 – 80 MHz
Differential to common
mode rejection
-40
dB ( Min )
1 – 60 MHz
-30
dB ( Min )
60 – 100 MHz
Transformer isolation
1500
V
-
Return loss
11.8 Crystal Selection Guide
A crystal can be used to generate the 25MHz
reference clock instead of an oscillator. The crystal
must be a fundamental type, and series-resonant.
Connects to pins X1 and X2, and shunts each crystal
lead to ground with a 22pf capacitor (see figure 11-6).
X1
X2
21
22
25MHz
22pf
AGND
22pf
AGND
Figure 11-6
Crystal Circuit Diagram
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
57
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
11.9 Application of reverse MII
Figure 11-7
Note: When operating DM9010BI at Reverse MII mode, pin 78 is pulled high. At this application, the txclk, col and
crs pins will be changed from input to output.
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
12. PACKAGE INFORMATION
Unit: Inches/mm
LQFP 100L Outline Dimensions
HD
D
75
51
E
F
HE
50
76
100
26
1
25
GD
b
~
~
e
y
A
A1
See Detail F
Seating Plane
D
A2
c
GD
L
L1
Detail F
Symbol
Dimensions In Inches
Dimensions In mm
A
0.063 Max.
1.60 Max.
A1
0.004 ± 0.002
0.1 ± 0.05
A2
0.055 ± 0.002
1.40 ± 0.05
b
0.009 ± 0.002
0.22 ± 0.05
c
0.006 ± 0.002
0.15 ± 0.05
D
0.551 ± 0.005
14.00 ± 0.13
E
0.551 ± 0.005
14.00 ± 0.13
e
0.020 BSC.
0.50 BSC.
F
0.481 NOM.
12.22 NOM.
GD
0.606 NOM.
15.40 NOM.
HD
0.630 ± 0.006
16.00 ± 0.15
HE
0.630 ± 0.006
16.00 ± 0.15
L
0.024 ± 0.006
0.60 ± 0.15
L1
0.039 Ref.
1.00 Ref.
y
0.004 Max.
0.1 Max.
θ
0° ~ 12°
0° ~ 12°
Notes:
1. Dimension D & E do not include resin fins.
2. Dimension GD is for PC Board surface mount pad pitch design reference only.
3. All dimensions are based on metric system.
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
59
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
13. ORDERING INFORMATION
Part Number
DM9010BIEP
Pin Count
100
Package
LQFP(Pb-Free
and
Halogen–Free)
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the described
chip(s) from patent infringement. FURTHER,
DAVICOM MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at any
time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other
information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM for such applications. Please note that
application circuits illustrated in this document are for
reference purposes only.
DAVICOM’s terms and conditions printed on the order
acknowledgment govern all sales by DAVICOM.
DAVICOM will not be bound by any terms inconsistent
with these unless DAVICOM agrees otherwise in
writing. Acceptance of the buyer’s orders shall be
based on these terms.
Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that are the industry’s
best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal, we
have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
products that meet their cost requirements.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently
available and soon to be released products are based
on our proprietary designs and deliver high quality,
high performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact the Sales department at:
Headquarters
Hsin-chu Office:
No.6 Li-Hsin Rd. VI,
Science-based Industrial Park,
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TEL: +886-3-5798797
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MAIL: sales@davicom.com.tw
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WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
60