SN54CDC341 1-LINE TO 8-LINE CLOCK DRIVER SGAS005A – MARCH 1996 – REVISED JULY 1997 D D D D D D J OR W PACKAGE (TOP VIEW) Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight Outputs Distributed VCC and Ground Pins Reduce Switching Noise High-Drive Outputs (– 48-mA IOH, 48-mA IOL) State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Ceramic Flatpacks (W), Ceramic Chip Carriers (FK), and Ceramic (J) 300-mil DIPS VCC 1G 2G A P0 P1 VCC 2Y4 2Y3 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Y1 1Y2 GND 1Y3 1Y4 GND 2Y1 2Y2 GND FK PACKAGE (TOP VIEW) 2G 1G VCC VCC 1Y1 D description 3 2 1 20 19 The SN54CDC341 is a high-performance clockdriver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a low state regardless of the A input. A P0 P1 4 18 5 17 6 16 VCC 2Y4 7 15 8 14 The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND. 1Y2 GND 1Y3 1Y4 GND 2Y3 GND GND 2Y2 2Y1 9 10 11 12 13 The SN54CDC341 is characterized for operation over the full military temperature range of –55°C to 125°C. FUNCTION TABLE INPUTS 1G 2G X L L OUTPUTS A 1Y1 – 1Y4 2Y1 – 2Y4 X L L L L H L L H H L H H L H H L H H H H H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 1 SN54CDC341 1-LINE TO 8-LINE CLOCK DRIVER SGAS005A – MARCH 1996 – REVISED JULY 1997 logic symbol† 1G 2G 2 3 G1 G2 1 1 A 4 1 1 2 2 2 2 19 18 16 15 13 12 9 8 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1G 2G 2 19 3 18 16 15 A 1Y2 1Y3 1Y4 4 13 12 9 8 2 1Y1 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 2Y1 2Y2 2Y3 2Y4 SN54CDC341 1-LINE TO 8-LINE CLOCK DRIVER SGAS005A – MARCH 1996 – REVISED JULY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions (see Note 2) VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level input voltage MAX 4.5 5.5 2 UNIT V V 0.8 V V High-level output current VCC – 48 mA Low-level output current 48 mA Input voltage fclock l k MIN 0 Input clock frequency One output bank loaded 33 Both output banks loaded 25 TA Operating free-air temperature NOTE 2: Unused pins (input or I/O) must be held high or low. –55 125 MHz °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = – 3 mA VOH VCC = 5 V, VCC = 4.5 V, IOH = – 3 mA IOH = – 48 mA VCC = 4.5 V, VCC = 5.5 V, IOL = 48 mA VI = VCC or GND VOL II IO‡ ICC VCC = 5.5 V, VO = 2.5 V VCC = 5.5 V,, VI = VCC or GND IO = 0,, MIN MAX UNIT –1.2 V 2.5 V 3 2 – 50 • V ±1 µA – 200 mA Outputs high 3.5 Outputs low 33 Ci VI = 2.5 V or 0.5 V ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 0.5 mA pF 3 SN54CDC341 1-LINE TO 8-LINE CLOCK DRIVER SGAS005A – MARCH 1996 – REVISED JULY 1997 switching characteristics, CL = 50 pF (see Figures 1 and 2) VCC = 5 V, TA = 25°C MIN TYP MAX VCC = 4.5 V to 5.5 V, TA = –55°C to 125°C MIN MAX PARAMETER FROM (INPUT) TO (OUTPUT) PACKAGE tPLH tPHL A Y All tPLH tPHL G Y All J 1.8 1.9 A Y W 0.7 1.9 FK 0.6 0.8 tsk(o) k( ) G A Y Y tsk(p) k( ) tsk(pr)† G Y A or G Y 2.3 6.7 1.8 7 3.6 6.3 3.3 7 1.6 4.1 1.3 4.7 2.3 4.4 1.8 4.9 J 0.9 0.9 W 0.5 1.2 FK 0.6 0.7 J 1.7 1.7 W 1.4 1.7 FK 1.7 2.1 J 1 1 W 0.6 1.3 FK 1.3 1.8 1.2 1.2 † tsk(pr) is guaranteed across the full voltage and temperature range but is measured only at 25C, VCC = 5 V, using the A inputs. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • UNIT ns ns ns ns ns ns ns SN54CDC341 1-LINE TO 8-LINE CLOCK DRIVER SGAS005A – MARCH 1996 – REVISED JULY 1997 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pF (see Note A) 500 Ω LOAD CIRCUIT 3V Input (see Note B) 1.5 V 1.5 V 0V tPLH Output tPHL 2V 1.5 V 0.8 V 1.5 V 0.8 V tr VOH VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 1. Load Circuit and Voltage Waveforms A 1G 2G 1Yn tPLH1 tPHL1 tPLH2 tPHL2 2Yn NOTES: A. Output skew, tsk(o), is calculated as the greater of: – The difference between the fastest and slowest of tPLHn (n = 1, 2) – The difference between the fastest and slowest of tPHLn (n = 1, 2) B. Pulse skew, tsk(p), is calculated as the greater of | tPLHn – tPHLn | (n = 1, 2). C. Process skew, tsk(pr), is calculated as the greater of: – The difference between the fastest and slowest of tPLHn (n = 1, 2) across multiple devices under identical operating conditions – The difference between the fastest and slowest of tPHLn (n = 1, 2) across multiple devices under identical operating conditions Figure 2. Waveforms for Calculation of tsk(o), tsk(p), tsk(pr) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 5 SN54CDC341 1-LINE TO 8-LINE CLOCK DRIVER SGAS005A – MARCH 1996 – REVISED JULY 1997 MECHANICAL INFORMATION FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 B A MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 25 5 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. 6 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • SN54CDC341 1-LINE TO 8-LINE CLOCK DRIVER SGAS005A – MARCH 1996 – REVISED JULY 1997 MECHANICAL INFORMATION J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE 14 PIN SHOWN PINS ** 14 16 18 20 A MAX 0.310 (7,87) 0.310 (7,87) 0.310 (7,87) 0.310 (7,87) A MIN 0.290 (7,37) 0.290 (7,37) 0.290 (7,37) 0.290 (7,37) B MAX 0.785 (19,94) 0.785 (19,94) 0.910 (23,10) 0.975 (24,77) B MIN 0.755 (19,18) 0.755 (19,18) C MAX 0.280 (7,11) 0.300 (7,62) 0.300 (7,62) 0.300 (7,62) C MIN 0.245 (6,22) 0.245 (6,22) 0.245 (6,22) 0.245 (6,22) DIM B 14 8 C 1 7 0.065 (1,65) 0.045 (1,14) 0.100 (2,54) 0.070 (1,78) 0.020 (0,51) MIN 0.930 (23,62) A 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.100 (2,54) 0°– 15° 0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20) 4040083/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL-STD-1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, and GDIP1-T20 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 7 SN54CDC341 1-LINE TO 8-LINE CLOCK DRIVER SGAS005A – MARCH 1996 – REVISED JULY 1997 MECHANICAL INFORMATION W (R-GDFP-F20) CERAMIC DUAL FLATPACK Base and Seating Plane 0.300 (7,62) 0.245 (6,22) 0.006 (0,15) 0.004 (0,10) 0.100 (2,54) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.320 (8,13) 0.265 (6,73) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 20 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.540 (13,72) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 10 11 1.040 (26,42) 0.745 (18,92) 4040180-4 / B 03/95 NOTES: A. B. C. D. E. 8 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL-STD-1835 GDFP2-F20 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SNJ54CDC341FK OBSOLETE LCCC FK 20 TBD Call TI Call TI SNJ54CDC341J OBSOLETE CDIP J 20 TBD Call TI Call TI SNJ54CDC341W OBSOLETE CFP W 20 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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