ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC www.ti.com SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 4242-VPK Small-Footprint and Low-Power Triple and Quad Channels Digital Isolators Check for Samples: ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC FEATURES APPLICATIONS • • 1 2 • • • • • • • • • Maximum Signaling Rate: 50 Mbps (with 5V Supplies) Robust Design With Integrated Noise Filter Default Output Low Option (Suffix F) Low Power Consumption, Typical ICC per Channel (with 3.3 V Supplies): – ISO7131: 1.5 mA at 1 Mbps, 2.6 mA at 25 Mbps – ISO7140: 1 mA at 1 Mbps, 2.3 mA at 25 Mbps – ISO7141: 1.3 mA at 1 Mbps, 2.6 mA at 25 Mbps Low Propagation Delay: 23 ns Typical (3.3 V Supplies) Wide Temperature Range: –40°C to 125°C 50 kV/µs Transient Immunity, Typical Long Life with SiO2 Isolation Barrier Operates From 2.7 V, 3.3 V and 5 V Supply and Logic Levels Small QSOP-16 Package General-Purpose Isolation – Industrial Fieldbus – Profibus – Modbus™ – DeviceNet Data Buses – RS-232, RS-485 – Serial Peripheral Interface SAFETY AND REGULATORY APPROVALS • 2500 VRMS Isolation for 1 minute per UL 1577 (Approved) 4242 VPK Isolation per DIN EN 60747-5-2 (VDE 0884 Teil 2), 566 VPK Working Voltage (Approved) CSA Component Acceptance Notice 5A (Approval Pending) IEC 60950-1 and IEC 61010-1 End Equipment Standards (Approval Pending) GB 4943.1-2011 and GB 8898:2011 CQC Certification (Approval Pending) • • • • DESCRIPTION ISO7131, ISO7140, and ISO7141 provide galvanic isolation up to 2500 VRMS for 1 minute per UL and 4242 VPK per VDE. ISO7131 has three channels with two forward and one reverse-direction channels. ISO7140 and ISO7141 are quad-channel isolators; ISO7140 has four forward, ISO7141 has three forward and one reversedirection channels. These devices are capable of 50 Mbps maximum data rate with 5V supplies and 40Mbps maximum data rate with 3.3V or 2.7V supplies, with integrated filters on the inputs for noise-prone applications. The suffix F indicates that default output state is low; otherwise, the default output state is high (see Table 1). Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The devices have TTL input thresholds and can operate from 2.7 V, 3.3 V, and 5 V supplies. All inputs are 5V tolerant when supplied from a 2.7V or 3.3V supply. PIN CONFIGURATIONS (TOP VIEW) ISO7131 ISO7140 ISO7141 VCC1 1 16 VCC2 VCC1 1 16 VCC2 VCC1 1 16 GND1 2 15 GND2 GND1 2 15 GND2 GND1 2 15 GND2 INA INB 3 14 OUTA 3 14 OUTA 14 OUTA 13 OUTB 4 13 OUTB INA INB 3 4 INA INB 4 13 OUTB OUTC 5 12 INC INC 5 12 OUTC INC 5 12 OUTC NC 6 11 NC IND 6 11 OUTD OUTD 6 11 IND EN1 7 10 EN2 NC 7 10 EN EN1 7 10 EN2 GND1 8 9 GND1 8 9 GND1 8 9 GND2 GND2 VCC2 GND2 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Modbus is a trademark of Gould Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. FUNCTION TABLE (1) INPUT VCC PU (1) OUTPUT VCC PU OUTPUT (OUTx) INPUT (INx) OUTPUT ENABLE (ENx) ISO71xxCC ISO71xxFCC H H or open H H L H or open L L X L Z Z Open H or open H L H or open H L PD PU X PD PU X L Z Z PU PD X X Undetermined Undetermined PU = Powered Up (VCC ≥ 2.7 V); PD = Powered Down (VCC ≤ 2.1 V); X = Irrelevant; H = High Level; L = Low Level; Z = High Impedance AVAILABLE OPTIONS PRODUCT RATED ISOLATION INPUT THRESHOLD DEFAULT OUTPUT MAX DATA RATE and INPUT FILTER ISO7131CC CHANNEL DIRECTION ORDERING NUMBER 2 forward, 1 reverse ISO7131CCDBQR (reel) High ISO7140CCDBQ (tube) ISO7140CC ISO7140FCC 4242 VPK (1) 1.5-V TTL (CMOS compatible) ISO7141CC Low 50 Mbps, with noise filter integrated 4 forward, 0 reverse 2 ISO7140FCCDBQ (tube) ISO7141CCDBQ (tube) 3 forward, 1 reverse (1) ISO7140CCDBQR (reel) ISO7140FCCDBQR (reel) High ISO7141FCC ISO7131CCDBQ (tube) Low ISO7141CCDBQR (reel) ISO7141FCCDBQ (tube) ISO7141FCCDBQR (reel) See the REGULATORY INFORMATION section for detailed Isolation Ratings. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC www.ti.com SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 ABSOLUTE MAXIMUM RATINGS (1) PARAMETER VALUE Supply voltage (2) VCC1, VCC2 Input voltage INx, ENx Output voltage OUTx Output current IO –0.5 V to 6 V –0.5 V to 6 V –0.5 V to VCC+ 0.5 V ±15 mA Human-body model Electrostatic discharge Field-induced charged device model Maximum junction temperature TJ Storage temperature TSTG (1) (2) ESDA / JEDEC JS-001-2012 ±4 kV All pins JEDEC JESD22-C101E ±1.5 kV 150°C –65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values. RECOMMENDED OPERATING CONDITIONS PARAMETER VCC1, VCC2 IOH MIN Supply voltage 2.7 High-level output current (VCC ≥ 3.0 V) –4 High-level output current (VCC < 3.0 V) –2 TYP MAX 5.5 UNIT V mA mA IOL Low-level output current 4 VIH High-level input voltage 2 VCC mA V VIL Low-level input voltage 0 0.8 V tui Input pulse duration (VCC ≥ 4.5V) 20 tui Input pulse duration (VCC < 4.5V) 25 1 / tui Signaling rate (VCC ≥ 4.5V) 1 / tui Signaling rate (VCC < 4.5V) TJ Junction temperature TA Ambient temperature –40 ns ns 0 50 Mbps 0 40 Mbps –40 136 °C 125 °C 25 THERMAL INFORMATION THERMAL METRIC (1) ISO7131, ISO714x DBQ (16 Pins) UNIT θJA Junction-to-ambient thermal resistance 104.5 °C/W θJC(top) Junction-to-case(top) thermal resistance 57.8 °C/W θJB Junction-to-board thermal resistance 46.8 °C/W ψJT Junction-to-top characterization parameter 18.3 °C/W ψJB Junction-to-board characterization parameter 46.4 °C/W θJC(bottom) Junction-to-case(bottom) thermal resistance n/a °C/W PD Device power dissipation 150 mW (1) VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF Input a 25-MHz, 50% duty cycle square wave For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 3 ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS IOH = –4 mA; see Figure 1 VCCx (1) IOH = –20 μA; see Figure 1 VCCx (1) VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 4 (1) MIN TYP – 0.5 4.8 – 0.1 5 MAX UNIT V IOL = 4 mA; see Figure 1 0.2 0.4 IOL = 20 μA; see Figure 1 0 0.1 V 450 mV 10 μA –10 25 75 kV/μs VCCx is the supply voltage, VCC1 or VCC2, for the output channel that is being measured. SWITCHING CHARACTERISTICS VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER tPLH, tPHL PWD tsk(o) (1) Pulse width distortion |tPHL – tPLH| (2) tsk(pp) Propagation delay time Channel-to-channel output skew time (3) Output signal rise time tf Output signal fall time tPHZ, tPLZ Disable propagation delay, high/low-to-high impedance output tPZH, tPZL Enable propagation delay, high impedance-to-high/low output tfs Fail-safe output delay time from input data or power loss tGR Input glitch rejection time (3) 4 See Figure 1 MIN TYP 12 19 MAX UNIT 35 3 Same-direction channels 2 Opposite-direction channels 4 Part-to-part skew time tr (1) (2) TEST CONDITIONS ns 12 2 See Figure 1 ns 2 See Figure 2 See Figure 3 6 10 5 10 ns 9.5 μs 11 ns Also known as pulse skew tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals, and loads. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC www.ti.com SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 SUPPLY CURRENT VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS MIN TYP MAX 2.2 3.7 UNIT ISO7131 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V AC signal: All channels switching with square-wave clock input; CL = 15 pF 50 Mbps 3.7 5 2.2 3.7 3.7 5 3.4 4.8 4.9 6.6 4.9 6.6 6.8 9 7.1 10 10.5 13 0.6 1.2 4.6 7 0.6 1.3 mA ISO7140 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF 50 Mbps 4.8 7 1.4 2.2 6.9 9.2 2.7 3.9 10.3 13.5 4.7 6.5 15.6 21 2.5 4.2 mA ISO7141 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V, AC signal: All channels switching with square wave clock input; CL = 15 pF 50 Mbps Copyright © 2013, Texas Instruments Incorporated 4.2 7 2.5 4.2 4.2 7 3.8 5.3 6.2 9.6 5.6 7.5 9.2 13 8.4 11.2 14 18.5 Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC mA 5 ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS IOH = –4 mA; see Figure 1 VCCx IOH = –20 μA; see Figure 1 VCCx (1) VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 4 (1) MIN (1) TYP – 0.5 3 – 0.1 3.3 MAX V IOL = 4 mA; see Figure 1 0.2 0.4 IOL = 20 μA; see Figure 1 0 0.1 425 V mV 10 –10 25 UNIT 50 μA kV/μs VCCx is the supply voltage, VCC1 or VCC2, for the output channel that is being measured. SWITCHING CHARACTERISTICS VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(o) (2) tsk(pp) Channel-to-channel output skew time (3) Output signal rise time tf Output signal fall time tPHZ, tPLZ Disable propagation delay, from high/low to high-impedance output tPZH, tPZL Enable propagation delay, from highimpedance to high/low output tfs Fail-safe output delay time from input data or power loss tGR Input glitch rejection time (3) 6 See Figure 1 MIN TYP MAX 15 23 45 UNIT 3 Same-direction Channels 2 Opposite-direction Channels 4 Part-to-part skew time tr (1) (2) TEST CONDITIONS ns 19 See Figure 1 2.5 ns 2.5 6.5 15 6.5 15 See Figure 2 ns 8 μs 12.5 ns See Figure 3 Also known as pulse skew tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC www.ti.com SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 SUPPLY CURRENT VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS MIN TYP MAX 1.9 2.7 2.6 3.8 1.9 2.7 2.6 3.8 2.4 3.5 3.5 4.7 3.2 4.6 4.7 6.2 5 7 7 9 0.3 0.7 3.6 5.2 0.4 0.8 3.7 5.3 0.9 1.4 5.1 6.8 1.7 2.4 7.3 10 2.4 3.7 9.4 13 2 3.1 3.2 4.9 2 3.1 3.2 4.9 2.8 3.8 4.5 6.1 4 5.2 6.4 8.3 UNIT ISO7131 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps mA ISO7140 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V, AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps mA ISO7141 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V, AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps Copyright © 2013, Texas Instruments Incorporated 5 8 8.2 11.6 Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC mA 7 ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS IOH = –2 mA; see Figure 1 VCC (1) IOH = –20 μA; see Figure 1 VCC (1) VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 4 (1) MIN TYP – 0.3 2.5 – 0.1 2.7 MAX UNIT V IOL = 4 mA; see Figure 1 0.2 0.4 IOL = 20 μA; see Figure 1 0 0.1 V 350 mV 10 μA -10 25 50 kV/μs MIN TYP MAX 15 27 50 VCCx is the supply voltage, VCC1 or VCC2, for the output channel that is being measured. SWITCHING CHARACTERISTICS VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.) PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(o) (2) tsk(pp) Channel-to-channel output skew time (3) Output signal rise time tf Output signal fall time tPHZ, tPLZ Disable propagation delay, from high/low to highimpedance output tPZH, tPZL Enable propagation delay, from high-impedance to high/low output tfs Fail-safe output delay time from input data or power loss tGR Input glitch rejection time (3) 8 See Figure 1 UNIT 3 Same-direction Channels 2 Opposite-direction Channels 4 Part-to-part skew time tr (1) (2) TEST CONDITIONS ns 22 3 See Figure 1 ns 3 9 15 9 15 See Figure 2 ns See Figure 3 8.5 μs 14 ns Also known as pulse skew tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals, and loads. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC www.ti.com SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 SUPPLY CURRENT VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS MIN TYP MAX 1.2 2.4 2.3 3.3 1.2 2.4 2.3 3.3 2.1 3 2.9 4 3 3.8 4 5.2 4.2 5.3 5.8 7 0.2 0.4 3.2 4.7 0.2 0.5 3.4 4.8 0.6 1 4.5 6.3 1.2 1.8 6.2 8 1.8 2.6 8 11 1.6 2.6 2.8 4.1 1.6 2.6 2.8 4.1 2.3 3.2 3.8 5 3.3 4.2 5.4 6.8 4.3 5.8 6.9 9.2 UNIT ISO7131 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps mA ISO7140 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V, AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps mA ISO7141 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V, AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC mA 9 ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 www.ti.com ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator NOTE A 50 W VI VCC1 VI VCC/2 OUT VCC/2 0V tPHL tPLH VO CL NOTE B VOH 90% VO 50% 10% tf tr 50% VOL A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the input-generator signal. It is not needed in an actual application. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching-Characteristics Test Circuit and Voltage Waveforms VCC VCC ISOLATION BARRIER 0V R L = 1 k W ± 1% IN Input Generator VI OUT EN VO 0V tPLZ tPZL VO CL VCC/2 VCC/2 VCC 0.5 V 50% VOL NOTE B VI 50 W ISOLATION BARRIER NOTE A IN 3V Input Generator NOTE A VI VCC OUT VO VCC/2 VI VCC/2 0V EN CL NOTE B 50 W tPZH R L = 1 k W ± 1% VO VOH 50% 0.5 V tPHZ A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. 0V Figure 2. Enable/Disable Propagation Delay-Time Test Circuit and Waveform 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC www.ti.com SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 PARAMETER MEASUREMENT INFORMATION (continued) VI IN = 0 V (Devices without suffix F) IN = VCC (Devices with suffix F) A. IN VCC ISOLATION BARRIER VCC 2.7 V VI OUT 0V t fs VO fs high CL NOTE A VO VOH 50% fs low V OL CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Failsafe Delay-Time Test Circuit and Voltage Waveforms VCC1 VCC2 IN S1 ISOLATION BARRIER C = 0.1 mF ±1% GND1 C = 0.1 mF ±1% OUT CL NOTE A Pass/Fail Criterion – the output must remain stable. VOH or VOL GND2 VTEST A. CL = 15pF and includes instrumentation and fixture capacitance within ±20%. Figure 4. Common-Mode Transient Immunity Test Circuit Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 11 ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 www.ti.com DEVICE INFORMATION INSULATION AND SAFETY-RELATED SPECIFICATIONS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIOTM Maximum transient overvoltage per DIN EN 60747-5-2 (VDE 0884 Teil 2) 4242 VPK VIORM Maximum working voltage per DIN EN 60747-5-2 (VDE 0884 Teil 2) 566 VPK VTEST = VISO, t = 60 sec (qualification) 2500 VRMS VTEST = 1.2 * VISO, t = 1 sec (100% production) 3000 VRMS Isolation Voltage per UL 1577 VISO VPR Input-to-output test voltage After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 679 Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial discharge < 5 pC 906 Method b1, 100% production test, VPR = VIORM x 1.875, t = 1 s, Partial discharge < 5 pC VPK 1061 L(I01) Minimum air gap (clearance) Shortest terminal to terminal distance through air 3.7 mm L(I02) Minimum external tracking (creepage) Shortest terminal to terminal distance across the package surface 3.7 mm Minimum internal gap (internal clearance) Distance through the insulation 0.014 mm Pollution degree Tracking resistance (comparative tracking index) CTI RIO (1) CIO (1) CI (1) (2) 2 DIN IEC 60112 / VDE 0303 Part 1 Isolation Resistance, Input to Output (2) ≥400 V VIO = 500 V, TA < 100oC >1012 o Ω >1011 VIO = 500 V, 100 C ≤ TA ≤ max Barrier capacitance, input to output VI = 0.4 sin (2πft), f = 1 MHz 2.3 pF Input capacitance VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 2.8 pF All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. spacer NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. Table 2. IEC 60664-1 RATINGS TABLE PARAMETER Basic Isolation Group Installation classification 12 TEST CONDITIONS SPECIFICATION Material Group Submit Documentation Feedback II Rated mains voltage ≤ 150 VRMS I–IV Rated mains voltage ≤ 300 VRMS I–III Rated mains voltage ≤ 400 VRMS I–II Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC www.ti.com SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 REGULATORY INFORMATION VDE UL Certified according to DIN EN 60747-5-2 CSA Recognized under 1577 Approved under CSA Component Certified according to GB 4943.1Component Recognition Program Acceptance Notice 2011 and GB 8898:2011 Basic Insulation Maximum Transient Overvoltage, 4242 VPK Single protection, 2500 VRMS Maximum Working Voltage, 566 VPK File number: 40016131 (1) CQC File number: E181974 (1) Reinforced Insulation per CSA 60950-1-03 and IEC 60950-1 (2nd Ed.), 150 VRMS maximum working voltage Basic Insulation per CSA 609501-03 and IEC 60950-1 (2nd Ed.), 380 VRMS maximum working voltage Reinforced Insulation per CSA 61010-1-04 and IEC 61010-1 (2nd Edition), 150 VRMS maximum working voltage Basic Insulation, Altitude ≤ 5000m, Tropical Climate, 250 VRMS maximum working voltage File number: 220991 (approval pending) Report Number: Pending Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577. IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER IS TS Safety input, output, or supply current TEST CONDITIONS DBQ-16 MIN TYP MAX θJA = 104.5°C/W, VI = 5.5V, TJ = 150°C, TA = 25°C 217 θJA = 104.5°C/W, VI = 3.6V, TJ = 150°C, TA = 25°C 332 θJA = 104.5°C/W, VI = 2.7V, TJ = 150°C, TA = 25°C 443 Maximum case temperature 150 UNIT mA °C Safety Limiting Current – mA The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 500 450 400 350 300 250 200 150 100 50 0 VCC1 = VCC2 = 2.7V VCC1 = VCC2 = 3.6V VCC1 = VCC2 = 5.5V 0 50 100 150 200 Case Temperature – oC Figure 5. DBQ-16 θJC Thermal Derating Curve Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 13 ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 VCC1 www.ti.com 2 mm max. from 2 mm max. from VCC2 VCC2 VCC1 ISO7131 0.1 mF GND1 INA 0.1 mF 1 16 2 15 3 14 OUTA OUTB INB 4 13 OUTC 5 12 NC EN1 GND2 INC NC 6 11 7 10 8 9 EN2 GND1 GND 2 VCC1 2 mm max. from 2 mm max. from VCC1 VCC2 VCC2 ISO7140 0.1 mF GND1 0.1 mF 1 16 GND2 2 15 INA 3 14 OUTA INB 4 13 OUTB INC 5 12 OUTC IND 6 11 NC OUTD EN 7 10 8 9 GND 2 GND1 Figure 6. Typical Application Circuits for ISO7131 and ISO7140 VCC1 2 mm max. from 2 mm max. from VCC1 VCC2 VCC2 ISO7141 0.1 mF 0.1 mF 1 16 2 15 3 14 OUTA INB 4 13 OUTB INC 5 12 OUTC GND1 INA OUTD EN1 6 11 7 10 8 9 GND2 IND EN2 GND1 GND 2 Figure 7. Typical Application Circuit for ISO7141 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC www.ti.com SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 Note: For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide. ISO71xxFCC Input VCC1 VCC1 Output 500Q IN VCC2 7.5 uA 8Q OUT 13Q ISO71xxCC Input VCC1 VCC1 VCC1 7.5 uA 500Q IN Figure 8. Device I/O Schematics Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 15 ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS 12.00 ICC2 5VV ICC2 at 5 ICC2 3.3VV ICC2 at 3.3 ICC1 at 5 ICC1 5VV ICC1 at 3.3 ICC1 3.3VV 16 Supply Current (mA) 10.00 Supply Current (mA) 18 ICC1 3.3VV ICC1 atat3.3 ICC2 atat3.3 ICC2 3.3VV ICC1 atat5 5VV ICC1 ICC2 atat5 5VV ICC2 8.00 6.00 4.00 14 12 10 8 6 4 2.00 2 0.00 0 0 10 20 30 40 50 Data Rate (Mbps) 60 0 40 50 60 C001 Figure 10. ISO7140 SUPPLY CURRENT FOR ALL CHANNELS vs DATA RATE 5.00 High-Level Output Voltage (V) Supply Current (mA) 12 30 6.00 ICC2 5VV ICC2 at 5 ICC2 at 3.3 ICC2 3.3VV ICC1 at 5 ICC1 5VV ICC1 at 3.3 ICC1 3.3VV 14 20 Data Rate (Mbps) Figure 9. ISO7131 SUPPLY CURRENT FOR ALL CHANNELS vs DATA RATE 16 10 C001 10 8 6 4 2 4.00 3.00 2.00 1.00 3.3V V VVCC 3.3 CC atat 0.00 VVCC 5 5V V CC atat 0 ±1.00 0 10 20 30 40 50 Data Rate (Mbps) 60 ±15 2.00 Low-Level Output Voltage (V) VCC 3.3VV V CC atat3.3 V VCC CC atat55VV 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0 5 10 Low-Level Output Current (mA) Figure 13. LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 16 Submit Documentation Feedback 0 ±5 C002 Figure 12. HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 15 C003 Power Supply Under Voltage Threshold (V) Figure 11. ISO7141 SUPPLY CURRENT FOR ALL CHANNELS vs DATA RATE 1.75 ±10 High-Level Output Current (mA) C001 2.48 VCC Rising V CC Rising 2.46 V VCC Falling CC Falling 2.44 2.42 2.40 2.38 2.36 2.34 ±50 0 50 100 150 Free-Air Temperature (C) C004 Figure 14. VCC UNDERVOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC www.ti.com SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 1.2 25 1 Pk-Pk Output Jitter (ns) Propagation Delay Time (ns) TYPICAL CHARACTERISTICS (continued) 30 20 15 10 ttpLH 3.3 3.3VV pLH atat ttpHL 3.3 3.3VV pHL atat ttpLH 5 5VV pLH atat ttpHL 5 5VV pHL atat 5 0 ±50 0 50 100 0.8 0.6 0.4 0.2 Output Jitter at 5 V Output Jitter at 3.3 V 0 150 Free-Air Temperature (C) C005 Figure 15. PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 0 20 40 Data Rate (Mbps) 60 C006 Figure 16. OUTPUT JITTER vs DATA RATE Input Glitch Rejection Time (ns) 18 16 14 12 10 8 6 4 ttGR 2.7VV GR atat2.7 ttGR 3.3VV GR atat3.3 ttGR GR atat55VV 2 0 ±50 0 50 100 150 Free-Air Temperature (C) C007 Figure 17. INPUT GLITCH REJECTION vs FREE-AIR TEMPERATURE Figure 18. TYPICAL EYE DIAGRAM AT 40 MBPS, PRBS 216 - 1, 2.7-V OPERATION Figure 19. TYPICAL EYE DIAGRAM AT 40 MBPS, PRBS 216 - 1, 3.3-V OPERATION Figure 20. TYPICAL EYE DIAGRAM AT 50 MBPS, PRBS 216 - 1, 5-V OPERATION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 17 ISO7131CC, ISO7140CC, ISO7140FCC ISO7141CC, ISO7141FCC SLLSE83E – APRIL 2013 – REVISED SEPTEMBER 2013 www.ti.com REVISION HISTORY Changes from Original (April 2013) to Revision A Page • Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device. ............................... 4 • Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device. ............................... 6 • Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device. ............................... 8 • Added Figure 11 ................................................................................................................................................................. 16 Changes from Revision A (June 2013) to Revision B • Page Changed device ISO7141CC From: Product Preview To: Released in the Product Status table ........................................ 1 Changes from Revision B (June 2013) to Revision C Page • Changed Feature From: ISO7140: TBD at 1 Mbps, TBD at 25 Mbps To: ISO7140: 1 mA at 1 Mbps, 2.3 mA at 25 Mbps ..................................................................................................................................................................................... 1 • Changed the SAFETY and REGULATORY APPROVALS .................................................................................................. 1 • Added text to the Description: "All inputs are 5V tolerant when supplied from a 2.7V or 3.3V supply." .............................. 1 • Deleted the Product Status table .......................................................................................................................................... 1 • Changed the AVAILABLE OPTIONS table ........................................................................................................................... 2 • Changed the ABSOLUTE MAXIMUM RATINGS table ......................................................................................................... 3 • Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. ............................................................. 4 • Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values ....................................................................... 5 • Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. ............................................................. 6 • Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values ....................................................................... 7 • Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. ............................................................. 8 • Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values ....................................................................... 9 • Changed Figure 9 X-axis scale ........................................................................................................................................... 16 Changes from Revision C (July 2013) to Revision D Page • Added Safety List item "GB 4943.1-2011 and GB 8898:2011 CQC Certification (Approval Pending)" ............................... 1 • Deleted "Product Preview" From the AVAILABLE OPTIONS table ...................................................................................... 2 • Changed the REGULATORY INFORMATION, added column for CQC ............................................................................ 13 • Added Figure 10 ................................................................................................................................................................. 16 Changes from Revision D (August 2013) to Revision E Page • Changed From: 2500 VRMS Isolation for 1 minute per UL 1577 (Approval Pending) To: (Approved) .................................. 1 • Added note1 to the AVAILABLE OPTIONS table ................................................................................................................. 2 • Changed From: Basic Insulation To: Basic Insulation, Altitude ≤ 5000m, Tropical Climate, 250 VRMS maximum working voltage in the Regulatory Information table ........................................................................................................... 13 • Changed File number: E181974 (approval pending) To: File number: E181974 in the Regulatory Information table ...... 13 • Changed Figure 5 ............................................................................................................................................................... 13 • Changed the title of Figure 18, Figure 19, and Figure 19 to include "PRBS 216 - 1" ......................................................... 17 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) ISO7131CCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7131CC ISO7131CCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7131CC ISO7140CCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140CC ISO7140CCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140CC ISO7140FCCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140FC ISO7140FCCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140FC ISO7141CCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141CC ISO7141CCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141CC ISO7141FCCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141FC ISO7141FCCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141FC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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