SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 D D D D D D D EPIC (Enhanced-Performance Implanted CMOS) Process High On-Off Output-Voltage Ratio Low Crosstalk Between Switches Individual Switch Controls Extremely Low Input Current ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, and Standard Plastic (N) and Ceramic (J) DIPs SN54LV4066A . . . J OR W PACKAGE SN74LV4066A . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) 1A 1B 2B 2A 2C 3C GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 4C 4A 4B 3B 3A description This quadruple silicon-gate CMOS analog switch is designed for 2-V to 5.5-V VCC operation. These switches are designed to handle both analog and digital signals. Each switch permits signals with amplitudes up to 5.5 V (peak) to be transmitted in either direction. Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. The SN54LV4066A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV4066A is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each switch) INPUT CONTROL (C) SWITCH L OFF H ON Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 logic symbol† 1C 1A 2C 2A 3C 3A 4C 4A 13 1 X1 1 1 2 1B 5 3 4 2B 6 9 8 3B 12 10 11 4B † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) A VCC VCC B C One of Four Switches 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Switch I/O voltage range, VIO (see Note 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Control-input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA I/O diode current, IIOK (VIO < 0 or VIO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA On-state switch current, IT (VIO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 4) VCC VIH Supply voltage High level input voltage, High-level voltage control inputs VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V SN54LV4066A SN74LV4066A MIN 2‡ MIN 2‡ MAX 5.5 1.5 5.5 UNIT V 1.5 0.7 0.7 VCC 0.7 0.7 0.7 VCC 0.7 VCC VCC VCC = 2 V VCC = 2.3 V to 2.7 V MAX VCC VCC 0.5 V 0.5 0.3 0.3 VCC 0.3 0.3 0.3 VCC 0.3 VCC VCC VCC VCC VIL Low level input voltage, voltage control inputs Low-level VI VIO Control input voltage 0 5.5 0 5.5 V Input/output voltage 0 0 V ∆t/∆v Input transition rise or fall rate ns/V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 VCC 200 0 VCC 200 0 100 0 100 VCC = 4.5 V to 5.5 V 0 20 0 20 V TA Operating free-air temperature –55 125 –40 85 °C ‡ With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. Only digital signals should be transmitted at these low supply voltages. NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TA = 25°C TYP MAX MIN MAX SN74LV4066A MIN MAX UNIT IT = –1 mA, VI = VCC or GND, GND VC = VIH (see Figure 1) 2.3 V 38 180 225 225 3V 29 150 190 190 4.5 V 21 75 100 100 IT = –1 1 mA, VI = VCC to GND, VC = VIH 2.3 V 143 500 600 600 3V 57 180 225 225 4.5 V 31 100 125 125 Difference in on-state on state resistance between switches IT = –1 1 mA, VI = VCC to GND, VC = VIH 2.3 V 6 30 40 40 3V 3 20 30 30 4.5 V 2 15 20 20 II Control input current 5.5 V ±0.1 ±1 ±1 µA Isoff Off-state switch leakage current VI = VCC or GND VI = VCC and VO = GND, or VI = GND and VO = VCC, VC = VIL (see Figure 2) 5.5V ±0.1 ±1 ±1 µA Ison On-state switch leakage current VI = VCC or GND, VC = VIH (see Figure 3) 5.5 V ±0.1 ±1 ±1 µA ICC Supply current VI = VCC or GND 5.5 V 20 20 µA Cic Control input capacitance 1.5 pF Cio Switch input/output capacitance 5.5 pF Cf Feedthrough capacitance 0.5 pF Ron Ron(p) ( ) ∆Ron On-state O t t switch it h resistance P k on-state t t Peak resistance PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 SN54LV4066A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Ω Ω Ω SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TA = 25°C TYP MAX SN54LV4066A MIN MAX SN74LV4066A MIN MAX UNIT tPLH, tPHL Propagation delay time A or B B or A CL = 15 pF, (see Figure 4) 1.2 10 16 16 ns tPZH, tPZL Switch turn-on time C A or B CL = 15 pF, RL = 1 kΩ (see Figure 5) 3.3 15 20 20 ns tPLZ, tPHZ Switch turn-off time C A or B CL = 15 pF, RL = 1 kΩ (see Figure 5) 6 15 23 23 ns tPLH, tPHL Propagation delay time A or B B or A CL = 50 pF, (see Figure 4) 2.6 12 18 18 ns tPZH, tPZL Switch turn-on time C A or B CL = 50 pF, RL = 1 kΩ (see Figure 5) 4.2 25 32 32 ns tPLZ, tPHZ Switch turn-off time C A or B CL = 50 pF, RL = 1 kΩ (see Figure 5) 9.6 25 32 32 ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS TA = 25°C MIN TYP MAX SN54LV4066A MIN MAX SN74LV4066A MIN MAX UNIT tPLH, tPHL Propagation delay time A or B B or A CL = 15 pF, (see Figure 4) 0.8 6 10 10 ns tPZH, tPZL Switch turn-on time C A or B CL = 15 pF, RL = 1 kΩ (see Figure 5) 2.3 11 15 15 ns tPLZ, tPHZ Switch turn-off time C A or B CL = 15 pF, RL = 1 kΩ (see Figure 5) 4.5 11 15 15 ns tPLH, tPHL Propagation delay time A or B B or A CL = 50 pF, (see Figure 4) 1.5 9 12 12 ns tPZH, tPZL Switch turn-on time C A or B CL = 50 pF, RL = 1 kΩ (see Figure 5) 3 18 22 22 ns tPLZ, tPHZ Switch turn-off time C A or B CL = 50 pF, RL = 1 kΩ (see Figure 5) 7.2 18 22 22 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TA = 25°C TYP MAX SN54LV4066A MIN SN74LV4066A MAX MIN MAX UNIT tPLH, tPHL Propagation delay time A or B B or A CL = 15 pF, (see Figure 4) 0.3 4 7 7 ns tPZH, tPZL Switch turn-on time C A or B CL = 15 pF, RL = 1 kΩ (see Figure 5) 1.6 7 10 10 ns tPLZ, tPHZ Switch turn-off time C A or B CL = 15 pF, RL = 1 kΩ (see Figure 5) 3.2 7 10 10 ns tPLH, tPHL Propagation delay time A or B B or A CL = 50 pF, (see Figure 4) 0.6 6 8 8 ns tPZH, tPZL Switch turn-on time C A or B CL = 50 pF, RL = 1 kΩ (see Figure 5) 2.1 12 16 16 ns tPLZ, tPHZ Switch turn-off time C A or B CL = 50 pF, RL = 1 kΩ (see Figure 5) 5.1 12 16 16 ns analog switch characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER Frequency response F (switch on) Crosstalk C t lk (between any switches) Crosstalk (control input to signal output) F dth h attenuation tt ti Feedthrough (switch off) Sine-wave distortion FROM (INPUT) A or B A or B C A or B A or B TO (OUTPUT) B or A B or A A or B B or A B or A TEST CONDITIONS VCC TA = 25°C MIN TYP MAX CL = 50 pF, RL = 600 Ω, fin = 1 MH MHz ((sine i wave)) 20log10(VO/VI) = –3 dB (see Figure 6) 2.3 V 30 3V 35 4.5 V 50 CL = 50 pF, F, RL = 600 Ω, fin = 1 MHz (sine wave) (see Figure 7) 2.3 V –45 3V –45 4.5 V –45 CL = 50 pF, F, RL = 600 Ω, fin = 1 MHz (square wave) (see Figure 8) 2.3 V 15 3V 20 4.5 V 50 CL = 50 pF, F, RL = 600 Ω, fin = 1 MHz (see Figure 9) 2.3 V –40 CL= 50 pF, F, RL = 10 kΩ, fin = 1 kHz (sine wave) (see Figure 10) VI = 2 Vp-p VI = 2.5 Vp-p VI = 4 Vp-p 3V –40 4.5 V –40 2.3 V 0.1 3V 0.1 4.5 V 0.1 UNIT MHz dB mV dB operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP UNIT 4.5 pF SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION VCC VC = VIH VCC VI = VCC or GND VO (ON) GND R ON + V 10– V I –3 O W 1 mA V VI – VO Figure 1. On-State Resistance Test Circuit VCC VC = VIL VCC VI A (OFF) VO GND Condition 1: VI = 0, VO = VCC Condition 2: VI = VCC, VO = 0 Figure 2. Off-State Switch Leakage-Current Test Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION VCC VC = VIH VCC A VI Open (ON) GND VI = VCC or GND Figure 3. On-State Leakage-Current Test Circuit VCC VC = VIH VCC VI VO (ON) 50 Ω CL GND TEST CIRCUIT tr tf VI A or B 90% 50% 10% VCC 90% 50% 10% 0V tPLH VO B or A tPHL VOH 50% 50% VOL VOLTAGE WAVEFORMS Figure 4. Propagation Delay Time, Signal Input to Signal Output 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION VCC 50 Ω VC VCC VI S1 VO RL = 1 kΩ S2 TEST S1 S2 tPZL tPZH tPLZ tPHZ GND VCC GND VCC VCC GND VCC GND CL GND TEST CIRCUIT VCC VC VCC 50% 50% 0V 0V tPZL tPZH ≈ VCC VO VOL VOH 50% 50% ≈0V (tPZL, tPZH) VCC VC VCC 50% 50% 0V 0V tPLZ tPHZ ≈ VCC VO VOL VOH VOL + 0.3 V VOH – 0.3 V ≈0V (tPLZ, tPHZ) VOLTAGE WAVEFORMS Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION VCC VCC 0.1 µF fin VI VCC (ON) VO GND 50 Ω RL = 600 Ω CL = 50 pF VCC/2 Figure 6. Frequency Response (Switch On) VCC VC = VCC fin 50 Ω VCC (ON) VI 0.1 µF 600 Ω VO1 GND RL = 600 Ω CL = 50 pF VCC/2 VI VCC VC = GND VCC (OFF) 600 Ω VO2 GND RL = 600 Ω CL = 50 pF VCC/2 Figure 7. Crosstalk Between Any Two Switches VCC 50 Ω VC VCC VO GND 600 Ω VCC/2 RL = 600 Ω CL = 50 pF VCC/2 Figure 8. Crosstalk (Control Input – Switch Output) 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV4066A, SN74LV4066A QUADRUPLE BILATERAL ANALOG SWITCHES SCLS427A – APRIL 1999 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION VCC VC = GND 0.1 µF fin 50 Ω VI VCC (OFF) VO GND 600 Ω RL = 600 Ω CL = 50 pF VCC/2 VCC/2 Figure 9. Feedthrough Attenuation (Switch Off) VCC VC = VCC 10 µF fin 600 Ω VI 10 µF VCC (ON) GND VO RL = 10 kΩ CL = 50 pF VCC/2 Figure 10. Sine-Wave Distortion POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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