PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT MC-45D16CD641KS 16 M-WORD BY 64-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM) Description The MC-45D16CD641KS is a 16,777,216 words by 64 bits DDR synchronous dynamic RAM module on which 8 pieces of 128M DDR SDRAM: µPD45D128164 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features • 16,777,216 words by 64 bits organization • Clock frequency Part number /CAS latency Clock frequency Module type (MAX.) MC-45D16CD641KS-C75 MC-45D16CD641KS-C80 CL = 2.5 133 MHz DDR SDRAM CL = 2 100 MHz SO DIMM CL = 2.5 125 MHz Design specification CL = 2 100 MHz Rev.1.0 compliant • Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge • Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK • Quad internal banks operation • Possible to assert random column address in every clock cycle • Programmable Mode register set /CAS latency (2, 2.5) Burst length (2, 4, 8) Wrap sequence (Sequential / Interleave) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • 2.5 V ± 0.2 V Power supply for VDD • 2.5 V ± 0.2 V Power supply for VDDQ • SSTL_2 compatible with all signals • 4,096 refresh cycles / 64 ms • Burst termination by Precharge command and Burst stop command • 200-pin dual in-line memory module (Pin pitch = 0.6 mm) • Unbuffered type • Serial PD The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0187N10 (Ver. 1.0) Date Published August 2001 (K) Printed in Japan C Elpida Memory, Inc. 2001 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. Ordering Information Part number MC-45D16CD641KS-C75 Clock frequency (MAX.) 133 MHz Package 200-pin Dual In-line Memory Module 8 pieces of µPD45D128164G5 (Rev. K) (Socket Type) MC-45D16CD641KS-C80 125 MHz Edge connector: Gold plated 31.75 mm height 2 Mounted devices Preliminary Data Sheet E0187N10 (10.16 mm (400) TSOP (II)) Pin Configuration 200-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) /xxx indicates active low signal. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD NC NC VSS NC NC VDD NC NC VSS VSS VDD VDD CKE0 NC A11 A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /S1 NC VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 NC DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD NC NC VSS NC NC VDD NC NC VSS CK2 /CK2 VDD CKE1 NC NC A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /S0 NC VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 A0 - A11 : Address Inputs [Row: A0 - A11, Column: A0 - A9] BA0, BA1 : SDRAM Bank Select DQ0 - DQ63 : Data Inputs/Outputs CK0 - CK2 : Clock Input (positive line of differential pair) /CK0 - /CK2 : Clock Input (negative line of differential pair) CKE0 : Clock Enable Input /S0, /S1 : Chip Select Input /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQS0 - DQS7 : Low Data Strobe DM(0 - 7) / DQS(9 - 16) : Low Data Masks / High Data Strobe SA0 - SA2 : Address Input for EEPROM SDA : Serial Data I/O for PD SCL : Clock Input for PD VDD : Power Supply VSS : Ground VDDID : VDD Identification Flag VDDQ : Power Supply for DQ and DQS VREF : Input Reference VDDSPD : Power supply for EEPROM NC : No Connection /RESET : Reset Input Preliminary Data Sheet E0187N10 3 Block Diagram /S1 /S0 RS DQS0 LDQS /S LDQS RS /S DQS4 LDM DM0 8 LDM 8 I/O0 to I/O7 RS DQS1 RS DM1 8 DM4 RS DQ0 to DQ7 UDQS I/O0 to I/O7 D0 UDM UDQS LDQS D4 DQS5 UDM DM5 I/O8 to I/O15 /S LDQS DQS3 RS DM3 8 DQS6 LDM DM6 8 I/O0 to I/O7 I/O0 to I/O7 UDQS UDQS D1 UDM I/O8 to I/O15 I/O8 to I/O15 /S LDQS LDM LDM DQ48 to DQ55 I/O0 to I/O7 I/O0 to I/O7 RS D5 DQS7 D3 UDQS UDQS UDM UDM DM7 8 D7 I/O8 to I/O15 UDM UDM I/O8 to I/O15 I/O8 to I/O15 RS DQ56 to DQ63 Serial PD A0 to AN SDRAMs (D0 to D7) SCL SCL /RAS SDRAMs (D0 to D7) SA0 A0 /CAS SDRAMs (D0 to D7) SA1 A1 /WE SDRAMs (D0 to D7) CKE0 SA2 SDRAMs (D0 to D3) A2 CKE1 SDRAMs (D4 to D7) SPD VREF SDRAMs (D0 to D7) VDD SDRAMs (D0 to D7), VDD and VDDQ SDA SDA WP CK0 /CK0 4 loads CK1 /CK1 4 loads CK2 /CK2 0 loads SDRAMs (D0 to D7), SPD Notes : Open /S RS SDRAMs (D0 to D7) VSS D6 RS I/O8 to I/O15 VDDSPD 1. DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. VDDID strap connections: (for memory device VDD, VDDQ) Strap out (open): VDD = VDDQ Strap in (closed): VDD ≠ VDDQ Remarks 1. The value of all resistors of DQs, DQSs, DM/DQSs is 22 Ω.± 5% 2. D0 – D7: µPD45D128164 (2M words × 16 bits × 4 banks) 4 UDQS UDM LDQS BA0 to BA1 VDDID D2 RS /S RS DQ24 to DQ31 I/O0 to I/O7 RS LDM RS I/O0 to I/O7 RS DQ40 to DQ47 RS DQ16 to DQ23 LDM UDQS RS 8 LDM RS 8 RS DM2 /S RS I/O8 to I/O15 DQS2 LDQS RS DQ32 to DQ39 RS DQ8 to DQ15 /S LDQS RS RS Preliminary Data Sheet E0187N10 Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 1 ms and then, execute Power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Rating Unit VDD, VDDQ –0.5 to +3.6 V Voltage on input pin relative to VSS VT –0.5 to +3.6 V Short circuit output current IO 50 mA Power dissipation PD 12 W Storage temperature Tstg –55 to +125 °C Voltage on power supply pin relative to VSS Caution Symbol Condition Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply voltage Symbol Condition MIN. TYP. MAX. Unit 2.3 2.5 2.7 V 2.5 VDD Supply voltage for DQ, DQS VDDQ 2.3 Input reference voltage VREF 0.49 × VDDQ 2.7 V 0.51 × VDDQ V Termination voltage VTT VREF − 0.04 VREF + 0.04 V High level dc input voltage VIH (DC) VREF + 0.15 VDD + 0.3 V Low level dc input voltage VIL (DC) −0.3 VREF − 0.15 V Input differential voltage (CLK and /CLK) VID (DC) 0.36 VDDQ + 0.6 V Input crossing point voltage (CLK and /CLK) VIX 0.5 × VDDQ–0.2 0.5 × VDDQ+0.2 V Operating ambient temperature TA 0 70 °C VREF Capacitance (TA = 25 °C, f = 100 MHz) Parameter Input capacitance Data input/output capacitance Symbol Test condition MIN. TYP. MAX. Unit pF CI1 A0 - A11, BA0, BA1, /RAS, /CAS, /WE TBD TBD CI2 CK0 - CK2, /CK0 - /CK2 TBD TBD CI3 CKE0 TBD TBD CI4 /S0, /S1 TBD TBD DM(0-7) / DQS(9-16), TBD TBD TBD TBD CI/O1 pF DQS0 - DQS7 CI/O2 DQ0 - DQ63 Preliminary Data Sheet E0187N10 5 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted) Parameter Operating current (ACT-PRE) Operating current Symbol IDD0 IDD1 (ACT-READ-PRE) Test condition /CAS Grade latency tRC = tRC(MIN.), tCK = tCK (MIN.), One bank, Active-precharge, DQ, DM and DQS inputs changing twice per clock cycle, Address and control inputs changing once per clock cycle tRC = tRC(MIN.), tCK = tCK (MIN.), One CL = 2 bank, Active-read-precharge, IO = 0 mA, Burst length = 2, CL = 2.5 Address and control inputs changing once per clock cycle MIN. MAX. Unit -C75 920 mA -C80 840 -C75 980 -C80 920 -C75 1020 -C80 960 mA Notes 1 Precharge power down standby current IDD2P CKE ≤ VIL(MAX.), tCK = tCK(MIN.), All banks idle, Power down mode Idle standby current IDD2N CKE ≥ VIH(MIN.), tCK = tCK(MIN.), /CS ≥ VIH(MIN.), All banks idle, Address and other control inputs changing once per clock cycle 400 mA Active power down standby current IDD3P CKE ≤ VIL(MAX.), tCK = tCK(MIN.), One bank active, Power down mode 400 mA Active standby current IDD3N /CS ≥ VIH(MIN.), CKE ≥ VIH(MIN.), tCK = tCK(MIN.), tRC = tRAS(MAX.), One bank, Active-precharge, DQ, DM and DQS inputs changing twice per clock cycle, Address and other control inputs changing once per clock cycle 560 mA Operating current IDD4R tCK = tCK(MIN.), Continuous burst read, Burst length = 2, IO = 0mA, One bank active, Address and control inputs changing once per clock cycle -C75 1080 mA 2 -C80 1080 mA 2 (Burst read) Operating current IDD4W (Burst write) tCK = tCK(MIN.), Continuous burst write, Burst length = 2, One bank active, Address and control inputs changing once per clock cycle CBR (Auto) refresh current IDD5 tRFC = tRFC(MIN.) Self refresh current IDD6 CKE ≤ 0.2 V CL = 2 80 mA CL = 2.5 -C75 1340 -C80 1280 -C75 1040 -C80 1040 CL = 2 CL = 2.5 -C75 1300 -C80 1240 -C75 1360 -C80 1280 16 mA mA Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. 2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output open. DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test condition MIN. MAX. Unit Notes Input leakage current II(L) VI = 0 to 3.6 V, all other pins not under test = 0 V −5 5 µA Output leakage current IO(L) DOUT is disabled, VO = 0 to VDDQ + 0.3 V −5 5 µA Output high current IOH VOUT = VDDQ − 0.43 V −15.2 mA Output low current IOL VOUT = 0.35 V 15.2 mA 6 Preliminary Data Sheet E0187N10 AC Characteristics (Recommended Operating Conditions unless otherwise noted) Test Conditions Parameter Symbol Value Unit Input Reference voltage (Input timing measurement reference level) VREF VDDQ x 0.5 V Termination voltage (Output timing measurement reference level) VTT VREF V High level ac input voltage VIH(ac) VREF + 0.31 V Low level ac input voltage VIL(ac) VREF − 0.31 V Input differential voltage (CK0 - CK2 and /CK0 - /CK2) VID(ac) 0.7 V Input signal slew rate SLEW 1 V/ns Notes 1 2 Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level. 2. Slew rate is to be maintained in the VIL (ac) to VIH(ac) range of the input signal swing. SLEW = (VIH(ac)VIL(ac))/ ∆t VTT RT = 50 Ω Output CLOAD = 30 pF Preliminary Data Sheet E0187N10 7 Synchronous Characteristics Parameter Clock cycle time Symbol CL = 2.5 tCK CL = 2 -C75 (PC266B) -C80 (PC200) MIN. MAX. MIN. MAX. 7.5 15 8 15 10 15 10 15 Unit ns CLK high-level width tCH 0.45 0.55 0.45 0.55 tCK CLK low-level width tCL 0.45 0.55 0.45 0.55 tCK DQ output access time from CLK, /CLK tAC –0.75 0.75 –0.8 0.8 ns DQS output access time from CLK, /CLK tDQSCK –0.75 0.75 –0.8 0.8 ns DQS-DQ skew (for DQS and associated DQ signals) tDQSQ –0.5 0.5 –0.6 0.6 ns DQS-DQ skew (for DQS and all DQ signals) tDQSQA –0.5 0.5 –0.6 0.6 ns Data out low-impedance time from CLK, /CLK tLZ –0.75 0.75 –0.8 0.8 ns Data out high-impedance time from CLK, /CLK tHZ –0.75 0.75 –0.8 0.8 ns Half clock period tHP tCH, tCL DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP – 0.75 tHP – 1 ns DQ and DM input setup time tDS 0.5 0.6 ns DQ and DM input hold time tDH 0.5 0.6 ns tDIPW 1.75 2 ns DQS write preamble setup time tWPRES 0 0 ns DQS write preamble tWPRE 0.25 0.25 tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK DQS input high pulse width tDQSH 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 tCK DQS falling edge to CLK setup time tDSS 0.2 0.2 tCK DQS falling edge hold time from CLK tDSH 0.2 0.2 tCK Address and control input setup time tIS 0.9 1.1 ns Address and control input hold time tIH 0.9 1.1 ns Address and control input pulse width tIPW 2.2 2.5 ns Internal write to read command delay tWTR 1 1 tCK DQ and DM input pulse width (for each input) tCH, tCL Remark These specifications are applied to the monolithic device. 8 Preliminary Data Sheet E0187N10 ns Note Asynchronous Characteristics Parameter Symbol -C75(PC266B) MIN. MAX. -C80(PC200) MIN. Unit MAX. ACT to REF/ACT command period (operation) tRC 65 70 ns REF to REF/ACT command period (refresh) tRFC 75 80 ns ACT to PRE command period tRAS 45 PRE to ACT command period tRP 20 20 ns ACT to READ/WRITE delay tRCD 20 20 ns ACT(one) to ACT(another) command period tRRD 15 15 ns Write recovery time tWR 15 15 ns Auto precharge write recovery time + precharge time tDAL 35 35 ns Mode register set command cycle time tMRD 15 15 ns Exit self refresh to command tXSNR 75 Refresh time (4,096 refresh cycles) tREF 120,000 Preliminary Data Sheet E0187N10 50 120,000 80 64 ns ns 64 ms 9 Serial PD Byte No. (1/2) Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 1 0 0 0 0 0 0 0 Notes 0 Defines the number of bytes written into serial PD memory 128 bytes 1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes 2 Fundamental memory type 07H 0 0 0 0 0 1 1 1 DDR SDRAM 3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows 4 Number of columns 09H 0 0 0 0 1 0 0 1 9 columns 5 Number of banks 02H 0 0 0 0 0 0 1 0 2 banks 6 Data width 40H 0 1 0 0 0 0 0 0 64 bits 7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0 8 Voltage interface 04H 0 0 0 0 0 1 0 0 SSTL_2 9 CL = 2.5 Cycle time -C75 75H 0 1 1 1 0 1 0 1 7.5 ns -C80 80H 1 0 0 0 0 0 0 0 8 ns 10 11 CL = 2.5 Access time -C75 75H 0 1 1 1 0 1 0 1 0.75 ns -C80 80H 1 0 0 0 0 0 0 0 0.8 ns 00H 0 0 0 0 0 0 0 0 None DIMM configuration type 12 Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal 13 SDRAM width 10H 0 0 0 1 0 0 0 0 x8 14 Error checking SDRAM width 00H 0 0 0 0 0 0 0 0 None 15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock 16 Burst length supported 0EH 0 0 0 0 1 1 1 0 2, 4, 8 17 Number of banks on each SDRAM 04H 0 0 0 0 0 1 0 0 4 banks 18 /CAS latency supported 0CH 0 0 0 0 1 1 0 0 2, 2.5 19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0 20 /WE latency supported 02H 0 0 0 0 0 0 1 0 1 21 SDRAM module attributes 20H 0 0 1 0 0 0 0 0 Differential Clock 22 SDRAM device attributes : General 00H 0 0 0 0 0 0 0 0 VDD ± 0.2 V 23 CL = 2 Cycle time -C75 A0H 1 0 1 0 0 0 0 0 10 ns -C80 A0H 1 0 1 0 0 0 0 0 10 ns 24 CL = 2 Access time -C75 75H 0 1 1 1 0 1 0 1 0.75 ns -C80 80H 1 0 0 0 0 0 0 0 0.8 ns 25-26 27 -C75 50H 0 1 0 1 0 0 0 0 20 ns -C80 50H 0 1 0 1 0 0 0 0 20 ns 0 0 1 1 1 1 0 0 15 ns 28 tRRD(MIN.) -C75 3CH -C80 3CH 0 0 1 1 1 1 0 0 15 ns 29 tRCD(MIN.) -C75 50H 0 1 0 1 0 0 0 0 20 ns -C80 50H 0 1 0 1 0 0 0 0 20 ns -C75 2DH 0 0 1 0 1 1 0 1 45 ns -C80 32H 0 0 1 1 0 0 1 0 50 ns 10H 0 0 0 1 0 0 0 0 64M bytes 30 31 10 tRP(MIN.) tRAS(MIN.) Module bank density Preliminary Data Sheet E0187N10 (2/2) Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes 32 Command and address signal -C75 90H 1 0 0 1 0 0 0 0 0.9 ns input setup time -C80 B0H 1 0 1 1 0 0 0 0 1.1 ns 33 Command and address -C75 90H 1 0 0 1 0 0 0 0 0.9 ns signal input hold time -C80 B0H 1 0 1 1 0 0 0 0 1.1 ns Data signal input setup time -C75 50H 0 1 0 1 0 0 0 0 0.5 ns -C80 60H 0 1 1 0 0 0 0 0 0.6 ns -C75 50H 0 1 0 1 0 0 0 0 0.5 ns -C80 60H 0 1 1 0 0 0 0 0 0.6 ns 00H 0 0 0 0 0 0 0 0 -C75 94H 1 0 0 1 0 1 0 0 -C80 1AH 0 0 0 1 1 0 1 0 00H 0 0 0 0 0 0 0 0 34 35 Data signal input hold time 36-61 62 SPD revision 63 Checksum for bytes 0 - 62 64-71 72 73-90 91 Manufacture’s JEDEC ID code Manufacturing location Manufacture’s P/N Revision Code 93-94 Manufacturing date 95-99 Assembly serial number 100-127 Mfg specific Timing Chart Refer to the µPD45D128442, 45D128842, 45D128164 Data sheet (E0030N). Preliminary Data Sheet E0187N10 11 Package Drawing 67.60 Unit: mm 63.60 11.55 18.45 3.80 (DATUM -A-) 4x Full R 4.00 199 1 6.00 20.0 31.75 Component area (Front) A 11.40 2.15 47.40 B 2.45 4.20 1.00 ± 0.10 4.20 1.50 2.15 47.40 11.40 2.45 2 200 R0.50 ± 0.20 R0.50 ± 0.20 2x φ 1.80 4.00 ± 0.10 Component area (Back) (DATUM -A-) Detail A 2.00 Min. Detail B (DATUM -A-) 0.60 0.45 ± 0.03 1.80 1.00 ± 0.10 12 0.25 Max 2.55 4.00 ± 0.10 FULL R Preliminary Data Sheet E0187N10 CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0107 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Preliminary Data Sheet E0187N10 13 The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107