SN54HC266, SN74HC266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-DRAIN OUTPUTS SCLS135C – DECEMBER 1982 – REVISED MAY 1997 D SN54HC266 . . . J OR W PACKAGE SN74HC266 . . . D OR N PACKAGE (TOP VIEW) Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 1A 1B 1Y 2Y 2A 2B GND description The ’HC266 are composed of four independent 2-input exclusive-NOR gates and feature open-drain outputs. They perform the Boolean function Y = A ⊗ B or Y = AB + AB in positive logic. The SN54HC266 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC266 is characterized for operation from –40°C to 85°C. L L B L H H L L L H H H 13 3 12 4 11 5 10 6 9 7 8 1B 1A NC VCC 4B 1Y NC 2Y NC 2A OUTPUT Y H 2 VCC 4B 4A 4Y 3Y 3B 3A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3Y 2B GND NC 3A 3B INPUTS 14 SN54HC266 . . . FK PACKAGE (TOP VIEW) FUNCTION TABLE A 1 NC – No internal connection logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 1 =1 2 3 1Y 5 4 6 2Y 8 10 9 3Y 12 11 13 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages. logic diagram, each gate (positive logic) A B Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC266, SN74HC266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-DRAIN OUTPUTS SCLS135C – DECEMBER 1982 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions SN54HC266 VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage Output voltage tt Input transition (rise and fall) time TA SN74HC266 MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC VCC = 2 V VCC = 4.5 V 0 1000 0 1000 0 500 0 500 VCC = 6 V 0 400 0 400 –55 125 –40 85 Operating free-air temperature V V 0 VCC = 4.5 V VCC = 6 V UNIT V V V ns °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH TEST CONDITIONS VI = VIH or VIL, VO = VCC IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 Ci VCC MIN TA = 25°C TYP MAX MIN MAX SN74HC266 MIN MAX 6V 0.01 0.5 10 5 UNIT µA 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 2 40 20 µA 10 10 10 pF 6V 2 V to 6 V 3 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2 SN54HC266 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V SN54HC266, SN74HC266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-DRAIN OUTPUTS SCLS135C – DECEMBER 1982 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) PARAMETER tPLH TO (OUTPUT) A or B tPHL Y A or B Y tt Y VCC MIN TA = 25°C TYP MAX SN54HC266 MIN SN74HC266 MAX MIN MAX 2V 60 125 190 155 4.5 V 13 25 38 31 6V 10 23 32 26 2V 60 100 150 125 4.5 V 13 20 30 25 6V 10 17 25 21 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate No load TYP 35 UNIT pF PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ From Output Under Test VCC Test Point Input tPLH In-Phase Output LOAD CIRCUIT Input 50% 10% 90% tr 50% 0V CL = 50 pF (see Note A) 90% 50% 90% 10% tPHL VCC 50% 10% 0 V tPHL Out-of-Phase Output 90% tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES tPLH 50% 10% 10% VOH 50% 10% V OL tf VOH VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 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