FMP1617DA0(7) CMOS LPRAM Document Title 1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM Revision History Revision No. History Draft date Remark 0.0 Initial Draft Aug. 25th, 2009 Preliminary 0.1 Revised ISB1 (110uA Æ 100uA) Nov. 25th, 2009 Preliminary 0.2 Removed Page Write Operation Jul. 21st, 2010 Final 1 Revision 0.2 Jul. 2010 FMP1617DA0(7) CMOS LPRAM 1M x 16 bit Super Low Power and Low Voltage Full CMOS RAM FEATURES • Process Technology : Full CMOS • Organization : 1M x 16 • Power Supply Voltage : 2.7~3.3V • Three state output and TTL Compatible • Separated I/O power(VCCQ) & Core power(VCC) • Operating Temperature Ranges: Special (-10’C to +60’C) Commercial (0’C to +70’C) Extended (-25’C to +85’C) Industrial (-40’C to +85’C) •Package Type : 48-FBGA-6.00x8.00 mm2 FMP1617DA0(7)-HxxX : Pb-Free & Halogen Free • Dual CS & Page Mode FMP1617DA0 : Dual CS FMP1617DA7 : Page mode with Dual CS • Page read/write operation by 16 words PRODUCT FAMILY Power Dissipation Operating Voltage (V) ICC1 Speed Product Family f = 1MHz Min. Typ. Max. FMP1617DA0(7)-H60E FMP1617DA0(7)-H70E 2.7 60ns 70ns 3.3 3.0 ISB1 (CMOS Standby Current) ICC2 f = fmax Typ. Max. Typ. Max. Typ. Max. 1.5mA 3mA 15mA 12mA 20mA 70uA 100uA 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. H=FBGA(Pb-Free & Halogen Free), W=WAFER 3. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) PIN DESCRIPTION 1 2 3 4 5 6 A /LB /OE A0 A1 A2 CS2 B I/O9 /UB A3 A4 /CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VCC E VCCQ I/O13 DNU A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 A19 A12 A13 WE I/O8 H A18 A8 A9 A10 A11 NC FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. VCC VSS Row Addresses I/O1~I/O8 Row select Data cont Memory array I/O Circuit Column select Data cont I/O9~I/O16 Data cont 48-FBGA : Top View(Ball Down) Column Addresses Name Function Name Function CS2 /CS Low Power Modes VCC Core Power Chip Select Input VCCQ I/O Power /CS /OE Output Enable Input VSS Ground /OE /WE Write Enable Input /UB Upper Byte(I/O9~16) A0~A19 Address Inputs /LB Lower Byte(I/O 1~8) I/O1~I/O16 Data Inputs/Outputs DNU Do Not Use /WE Control Logic /UB /LB CS2 2 Revision 0.2 Jul. 2010 FMP1617DA0(7) CMOS LPRAM PRODUCT LIST Part Name Function FMP1617DA0(7)-H60E FMP1617DA0(7)-H70E 60ns, VCC=3.0V, VCCQ=3.0V 70ns, VCC=3.0V, VCCQ=3.0V 1. H=FBGA(Pb-Free & Halogen Free), W=WAFER 2. Operating Temperature Range: S (-10’C~60’C), C(0’C~70’C), E(-25’C~85’C), I (-40’C~85’C) FUNCTIONAL DESCRIPTION /CS1 CS2 /OE /WE /LB /UB I/O1-8 I/O9-16 Mode Power X X X X 1) H X High-Z High-Z Deselect/Power-down Standby X1) L X1) X1) X1) X1) High-Z High-Z Deselect/Power-down Standby X1) X1) X1) X1) H H High-Z High-Z Deselect/Power-down Standby H H H L X High-Z High-Z Output Disabled Active H H H X1) L High-Z High-Z Output Disabled Active L H Dout High-Z Lower Byte Read Active H L High-Z Dout Upper Byte Read Active L L Dout Dout Word Read Active L H Din High-Z Lower Byte Write Active H L High-Z Din Upper Byte Write Active L L Din Din Word Write Active L 1) 1) L L 1) H H X 1) L 1) 1) 1. X means don’t care.(Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to VSS Symbol Ratings VIN, VOUT -0.5 to VCC+0.3V V VCC -0.2 to 3.6 V PD 1.0 W TSTG -65 to 150 ’C Voltage on VCC supply relative to VSS Power Dissipation Storage temperature Unit 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS FMP1617DA0(7) Item Supply voltage I/O operating voltage (VCCQ ≤ VCC) Symbol Unit Min Typ Max VCC 2.7 3.0V 3.3 V VCCQ 2.7 3.0V 3.3 V Ground VSS 0 0 0 V Input high voltage VIH 0.8VCCQ VCCQ VCC+0.21) V Input low voltage VIL -0.2 0 0.2VCCQ V 2) Note : 1. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 2. Undershoot : -1.0V in case of pulse width≤20ns. 3. Overshoot and undershoot are sampled, not 100% tested. 3 Revision 0.2 Jul. 2010 FMP1617DA0(7) CAPACITANCE1) CMOS LPRAM (f=1MHz , TA=25’C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Min Max Unit Input leakage current Item Symbol ILI VIN=VSS to VCC Test Conditions -1 1 uA Output leakage current ILO /CS=VIH, CS2=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC -1 1 uA ICC1 Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, CS2=VIH, VIN≤0.2V or VIN≥VCC-0.2V - 3 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, CS2=VIH, VIN=VIL or VIH - 20 mA Output low voltage VOL IOL=0.5mA 0.2VCCQ V Output high voltage VOH IOH=-0.5mA Standby Current(TTL) ISB /CS=VIH, CS2=VIH, Other inputs=VIH or VIL - 0.3 mA Standby Current(CMOS) ISB1 /CS≥VCC-0.2V, CS2≥VCC-0.2V, Other inputs=0~VCC - 100 uA Average operating current 0.8VCCQ V Operating Range Device Range Ambient Temperature FMP1617DA0(7)-XxxS Special -10℃ to +60℃ FMP1617DA0(7)-XxxC Commercial 0℃ to +70℃ FMP1617DA0(7)-XxxE Extended -25℃ to +85℃ FMP1617DA0(7)-XxxI Industrial -40℃ to +85℃ VCC VCCQ 2.7V to 3.3V 2.7V to VCC AC Input/Output Reference Waveform VCCQ Input 1 VCCQ/2 2 VCCQ/23 Output Test Points VSS NOTE: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. AC Output Load Circuit Test Point 50Ω DUT VCCQ/2 30pF 4 Revision 0.2 Jul. 2010 FMP1617DA0(7) CMOS LPRAM AC CHARACTERISTICS(VCC=2.7V~3.3V) Speed Bins Parameter List Read Cycle Time Symbol 60ns 70ns Units Min Max Min Max tRC 60 20k 70 20k ns Address Access Time tAA - 60 - 70 ns Chip Select to Output tCO - 60 - 70 ns Output Enable to Valid Output tOE - 25 - 25 ns /UB, /LB Access Time tBA - 60 - 70 ns Chip Select to Low-Z Output tLZ 10 - 10 - ns /UB, /LB Enable to Low-Z Output tBLZ 10 - 10 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns Read Chip Disable to High- Z Output Write tHZ 0 5 0 5 ns /UB, /LB Disable to High- Z Output tBHZ 0 5 0 5 ns Output Disable to High- Z Output tOHZ 0 5 0 5 ns Output Hold from Address Change tOH 5 - 5 - ns Write Cycle Time tWC 60 20k 70 20k ns Chip Select to End of Write tCW 50 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 50 - 60 - ns /UB, /LB Valid to End of Write tBW 50 - 60 - ns Write Pulse Width tWP 50 - 50 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z Page tWHZ 0 5 0 5 ns Data to Write Time Overlap tDW 20 - 20 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns Page Mode Cycle Time tPC 20 - 25 - ns Page Mode Address Access Time tPAA - 20 - 25 ns Maximum Cycle Time tMRC - 20k - 20k ns /CS High Pulse Width tCP 10 - 10 - ns 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. 5 Revision 0.2 Jul. 2010 FMP1617DA0(7) CMOS LPRAM Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 150us with /CS=CS2=VIH Standby Mode State machines Power On /CS1=VIH Wait min.150us Initial State /CS1=VIL, CS2=VIH /UB or/and /LB=VIL Active Mode /CS1=VIL CS2=VIH /CS1=VIH (or/and /UB=/LB=VIH) CS2=VIH Standby Mode Standby Mode Characteristics Mode Memory Cell Data Standby Current(uA) Wait Time(us) Standby Valid 100 (ISB1) 0 6 Revision 0.2 Jul. 2010 FMP1617DA0(7) READ CYCLE (1) CMOS LPRAM (Address controlled,/CS=/OE=VIL, CS2=/WE=VIH, /UB or/and /LB=VIL) tRC Address tAA tOH Data Out READ CYCLE (2) Previous Data Valid Data Valid (CS2=/WE=VIH) tRC Address tOH tAA tCO /CS tHZ tBA /UB, /LB tBHZ tOE /OE tOLZ Data Out tOHZ tBLZ tLZ High-Z Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. PAGE READ CYCLE (CS2=/WE=VIH, 16 words access) tMRC tRC tPC tPC tPC tPC tPC tPC tPC A0~A3 tAA A4~A19 tOH tCO /CS tHZ tBA /UB, /LB tBHZ tOE /OE tOLZ tBLZ Data Out High-Z tPAA tPAA Data Valid Data Valid tPAA tPAA tPAA tPAA tPAA tOHZ tLZ Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 4. In case page address skew is over 3ns, tPAA will be out of spec. 7 Revision 0.2 Jul. 2010 FMP1617DA0(7) WRITE CYCLE (1) CMOS LPRAM (/WE controlled, CS2=VIH) tWC Address tCW(2) tWR(4) /CS tAW tBW /UB, /LB tWP(1) /WE tAS(3) tDW Data in tWHZ Data Out WRITE CYCLE (2) tDH Data Valid High-Z High-Z tOW Data Undefined (/CS controlled, CS2=VIH) tWC Address tAS(3) tWR(4) tCW(2) /CS tAW tBW /UB, /LB tWP(1) /WE tDW Data in Data Out WRITE CYCLE (3) tDH Data Valid High-Z High-Z (/UB, /LB controlled, CS2=VIH) tWC Address tWR(4) tCW(2) /CS tAW tBW /UB, /LB tAS(3) tWP(1) /WE tDW Data in Data Out tDH Data Valid High-Z High-Z 1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 8 Revision 0.2 Jul. 2010 FMP1617DA0(7) CMOS LPRAM PACKAGE DIMENSION Unit : millimeters 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View Bottom View A1 INDEX MARK B B1 B 0.05 0.05 6 5 4 3 2 1 A B C #A1 C C C1 D C1/2 E F G H B/2 0.25/Typ. E2 D A Y 0.85/Typ. E Detail A E1 0.30 Side View C - Min Typ A - 0.75 Max - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.30 0.35 0.40 E - 1.10 1.20 E1 - 0.85 - E2 0.20 0.25 0.30 Y - - 0.08 9 NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) Revision 0.2 Jul. 2010