FUJITSU SEMICONDUCTOR DATA SHEET DS04-27241-1E ASSP for Power Supply Applications (Secondary battery) DC/DC Converter IC for Charging Li-ion Battery MB39A114 ■ DESCRIPTION The MB39A114 is a DC/DC converter IC of pulse width modulation (PWM) type for charging, capable of independently controlling the output voltage and output current. It is suitable for down conversion. MB39A114 can dynamically control the secondary battery’s charge current by detecting a voltage drop in an AC adapter to keep its power constant (dynamically-controlled charging) . This IC can easily set the charge current value, making it ideal for use as a built-in charging device in products such as notebook PC. ■ FEATURES • • • • Built-in constant current control circuit in 2-system. Analog control of charge current value is possible. (+INE1 terminal and +INE2 terminal) Built-in AC adapter detection function (When VCC is lower than the battery voltage +0.2 V, output is fixed in the off.) Constant voltage control state detection function (CVM terminal) enables prevention of mis-detection for full charge. • Built-in overvoltage detection function (OVP terminal) of charge voltage (Continued) ■ PACKAGE 24-pin plastic SSOP (FPT-24P-M03) MB39A114 (Continued) • Wide range of operating power-supply voltage range : 8 V to 25 V • Built-in output setting resistor • Built-in switching function (SEL terminal) of output setting voltage 16.8 V or 12.6 V • Output voltage setting accuracy : ± 0.74% (Ta = −10 °C to +85 °C) • Built-in high accuracy current detection amplifier : ± 5% (At the input voltage difference of 100 mV) , ± 15% (At the input voltage difference of 20 mV) • Output voltage setting resistor is open to enable prevention of invalidity current at IC standby (ICC = 0 µA Typ). • Oscillation frequency range : 100 kHz to 500 kHz • Built-in current detection Amp with wide in-phase input voltage range : 0 V to VCC • Built-in soft-start function independent of loads • Built-in standby current function : 0 µA (Typ) • Built-in totem-pole type output stage supporting Pch MOS FET devices. 2 MB39A114 ■ PIN ASSIGNMENT (TOP VIEW) −INC2 1 24 +INC2 OUTC2 2 23 GND +INE2 3 22 CS −INE2 4 21 VCC CVM 5 20 OUT VREF 6 19 VH FB12 7 18 OVP −INE1 8 17 RT +INE1 9 16 −INE3 OUTC1 10 15 FB3 SEL 11 14 CTL −INC1 12 13 +INC1 (FPT-24P-M03) 3 MB39A114 ■ PIN DESCRIPTION 4 Pin No. Symbol I/O Description 1 −INC2 I Current detection amplifier (Current Amp2) inverted input terminal 2 OUTC2 O Current detection amplifier (Current Amp2) output terminal 3 +INE2 I Error amplifier (Error Amp2) non-inverted input terminal 4 −INE2 I Error amplifier (Error Amp2) inverted input terminal 5 CVM O Open drain type output terminal of constant voltage control state detection comparator (CV Comp.) 6 VREF O Reference voltage output terminal 7 FB12 O Error amplifier (Error Amp1, Error Amp2) output terminal 8 −INE1 I Error amplifier (Error Amp1) inverted input terminal 9 +INE1 I Error amplifier (Error Amp1) non-inverted input terminal 10 OUTC1 O Current detection amplifier (Current Amp1) output terminal 11 SEL O Charge voltage setting switch terminal (3 cell or 4 cell) “H” level in SEL terminal : charge voltage setting 16.8 V (4 Cell) “L” level in SEL terminal : charge voltage setting 12.6 V (3 Cell) 12 −INC1 I Current detection amplifier (Current Amp1) inverted input terminal 13 +INC1 I Current detection amplifier (Current Amp1) non-inverted input terminal 14 CTL I Power-supply control terminal Setting the CTL terminal at “L” level places the IC in the standby mode. 15 FB3 O Error amplifier (Error Amp3) output terminal 16 −INE3 I Error amplifier (Error Amp3) inverted input terminal 17 RT Triangular wave oscillation frequency setting resistor connection terminal 18 OVP O Open drain type output terminal overvoltage detection comparator (OV Comp.) 19 VH O Power supply terminal for FET drive circuit (VH = VCC − 6 V) 20 OUT O External FET gate drive terminal 21 VCC Power supply terminal for reference power supply, control circuit and output circuit 22 CS Soft-start capacitor connection terminal 23 GND Ground terminal 24 +INC2 I Current detection amplifier (Current Amp2) non-inverted input terminal MB39A114 ■ BLOCK DIAGRAM <CV Comp.> − −INE1 5 CVM + 8 2.6 V OUTC1 10 +INC1 13 −INC1 12 +INE1 9 −INE2 4 OUTC2 2 +INC2 24 −INC2 1 +INE2 3 FB12 7 <Current Amp 1> + VREF ×20 − <OV Comp.> + <Error Amp 1> 18 OVP − − + + 1.4 V 0.2 V + − <UV Comp.> − <Current Amp 2> + ×20 − −INC2 (VO) <Error Amp 2> 21 VCC <PWM Comp.> − + + + + − <OUT> Drive 20 OUT VREF <Error Amp 3> R1 −INE3 16 R2 −2.5 V −1.5 V − + + VH VCC − 6 V 19 VH Bias Voltage UVLO 4.2 V/3.15 V VREF UVLO FB3 15 SEL 11 <SOFT> H : 4Cell L : 3Cell 4.2 V bias VREF VCC 10 µA <OSC> 500 kHz CS <REF> <CTL> 14 CTL 22 CT 45 pF 17 RT VREF 5.0 V 6 VREF 23 GND 5 MB39A114 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Rating Unit Min Max 28 V 60 mA Power supply voltage VCC Output current IOUT Peak output current IOUT Duty ≤ 5% (t = 1/fosc × Duty) 700 mA Power dissipation PD Ta ≤ +25 °C 740* mW −55 +125 °C Storage temperature TSTG VCC terminal * : The packages are mounted on the dual-sided epoxy board (10 cm × 10 cm) . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 6 MB39A114 ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions Value Unit Min Typ Max 8 25 V Power supply voltage VCC Reference voltage output current IREF −1 0 mA VH terminal output current IVH 0 30 mA VINE −INE1 to −INE3, +INE1, +INE2 terminal 0 5 V VINC +INC1, +INC2, −INC1, −INC2 terminal 0 VCC V CTL terminal input voltage VCTL 0 25 V Output current IOUT −45 +45 mA Peak output current IOUT −600 +600 mA CVM terminal output voltage VCVM 0 25 V Input voltage VCC terminal Duty = 5% (t = 1/fosc × Duty) CVM terminal output current ICVM 0 1 mA OVP terminal output voltage VOVP 0 25 V OVP terminal output current IOVP 0 1 mA SEL terminal input voltage VSEL 0 25 V Oscillation frequency fosc 100 300 500 kHz Timing resistor RT 27 47 130 kΩ Soft-start capacitor CS 0.022 1.0 µF VH terminal capacitor CVH 0.1 1.0 µF Reference voltage output capacitor CREF 0.1 1.0 µF Ta −30 +25 +85 °C Operating ambient temperature WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 7 MB39A114 ■ ELECTRICAL CHARACTERISTICS Parameter 6 Ta = +25 °C 4.975 5.000 5.025 V VREF2 6 Ta = −10 °C to +85 °C 4.963 5.000 5.037 V Input stability Line 6 VCC = 8 V to 25 V 3 10 mV Load stability Load 6 VREF = 0 mA to −1 mA 1 10 mV Ios 6 VREF = 1 V −50 −25 −12 mA VTLH 6 VREF = 2.6 2.8 3.0 V VTHL 6 VREF = 2.4 2.6 2.8 V Hysteresis width VH 6 0.2* V Charge current ICS 22 −14 −10 −6 µA fosc 20 RT = 47 kΩ 270 300 330 kHz ∆f/fdt 20 Ta = −30 °C to +85 °C 1* % 1 5 mV Output current at short circuit Under voltage lockout protection circuit block [UVLO] Soft start block [SOFT] Threshold voltage Oscillation Triangular wave frequency oscillator block Frequency [OSC] temperature stability Input offset voltage Input bias current Error amplifier block [Error Amp1, Error Amp2] Symbol Pin No. VREF1 Output voltage Reference voltage block [REF] (VCC = 19 V, VREF = 0 mA, Ta = +25 °C) Value Conditions Unit Min Typ Max VIO 3, 4, 8, 9 FB12 = 2 V IB 3, 4, 8, 9 −100 −30 nA In-phase input voltage range VCM 3, 4, 8, 9 0 VCC − 1.8 V Voltage gain AV 7 DC 100* dB Frequency bandwidth BW 7 AV = 0 dB 1.3* MHz VFBH 7 4.8 5.0 V VFBL 7 0.8 0.9 V ISOURCE 7 FB12 = 2 V −120 −60 µA ISINK 7 FB12 = 2 V 2.0 4.0 mA Output voltage Output source current Output sink current * : Standard design value (Continued) 8 MB39A114 Parameter Symbol Pin No. Voltage gain AV 15 DC 100* dB Frequency bandwidth BW 15 AV = 0 dB 1.3* MHz VFBH 15 4.8 5.0 V VFBL 15 0.8 0.9 V ISOURCE 15 FB3 = 2 V −120 −60 µA ISINK 15 FB3 = 2 V 2.0 4.0 mA VTH1 1 SEL = 5 V, FB3 = 2 V, Ta = +25 °C 16.716 16.800 16.884 V VTH2 1 SEL = 5 V, FB3 = 2 V, Ta = −10 °C to +85 °C 16.676 16.800 16.924 V VTH3 1 SEL = 0 V, FB3 = 2 V, Ta = +25 °C 12.537 12.600 12.663 V VTH4 1 SEL = 0 V, FB3 = 2 V, Ta = −10 °C to +85 °C 12.507 12.600 12.694 V IIN 1 −INC2 = 16.8 V 84 150 µA IINL 1 VCC = 0 V, −INC2 = 16.8 V 1 µA R1 1, 16 105 150 195 kΩ R2 16 35 50 65 kΩ VON 11 +INE3 = 4.2 V (4 Cell setting) 2 25 V VOFF 11 +INE3 = 3.15 V (3 Cell setting) 0 0.8 V ISELH 11 SEL = 5 V 50 100 µA ISELL 11 SEL = 0 V 0 1 µA 1, 12, +INC1 = +INC2 = 13, 24 −INC1 = −INC2 = 3 V to VCC −3 +3 mV +INC1 = +INC2 = 3 V to VCC, ∆VIN = −100 mV 20 30 µA Output voltage Output source current Output sink current Error amplifier block [Error Amp3] (VCC = 19 V, VREF = 0 mA, Ta = +25 °C) Value Conditions Unit Min Typ Max Threshold voltage Input current Input resistance SEL input voltage Input current Input offset voltage Current detection amplifier block [Current Amp1, Input current Current Amp2] VIO I + INCH 13, 24 I − INCH 12 +INC1 = 3 V to VCC, ∆VIN = −100 mV 0.1 0.2 µA I + INCL 13, 24 +INC1 = +INC2 = 0 V, ∆VIN = −100 mV −180 −120 µA I − INCL 1, 12 +INC1 = +INC2 = 0 V, ∆VIN = −100 mV −195 −130 µA * : Standard design value (Continued) 9 MB39A114 (VCC = 19 V, VREF = 0 mA, Ta = +25 °C) Parameter Value Min Typ Max Unit 2, 10 +INC1 = +INC2 = 3 V to VCC, ∆VIN = −100 mV 1.9 2.0 2.1 V VOUTC2 2, 10 +INC1 = +INC2 = 3 V to VCC, ∆VIN = −20 mV 0.34 0.40 0.46 V VOUTC3 2, 10 +INC1 = +INC2 = 0 V, ∆VIN = −100 mV 1.8 2.0 2.2 V VOUTC4 2, 10 +INC1 = +INC2 = 0 V, ∆VIN = −20 mV 0.2 0.4 0.6 V VCM 1, 12, 13, 24 0 VCC V AV 2, 10 +INC1 = +INC2 = 3 V to VCC, ∆VIN = −100 mV 19 20 21 V/V BW 2, 10 AV = 0 dB 2* MHz VOUTCH 2, 10 4.7 4.9 V VOUTCL 2, 10 20 200 mV ISOURCE 2, 10 OUTC1 = OUTC2 = 2 V −2 −1 mA ISINK 2, 10 OUTC1 = OUTC2 = 2 V 150 300 µA VTL 7, 15 Duty cycle = 0% 1.4 1.5 V VTH 7, 15 Duty cycle = 100% 2.5 2.6 V ISOURCE 20 OUT = 13 V, Duty ≤ 5% (t = 1/fosc × Duty) − 400* mA ISINK 20 OUT = 19 V, Duty ≤ 5% (t = 1/fosc × Duty) 400* mA ROH 20 OUT = − 45 mA 6.5 9.8 Ω ROL 20 OUT = 45 mA 5.0 7.5 Ω Rise time tr1 20 OUT = 3300 pF 50* ns Fall time tf1 20 OUT = 3300 pF 50* ns VTLH 21 VCC = , −INC2 = 16.8 V 17.2 17.4 17.6 V VTHL 21 VCC = , −INC2 = 16.8 V 16.8 17.0 17.2 V VH 21 0.4* V Current In-phase input detection voltage range amplifier block [Current Amp1, Voltage gain Current Amp2] Frequency bandwidth Output voltage Output source current Output sink current Threshold voltage Output source current Output block [OUT] Conditions VOUTC1 Current detection voltage PWM comparator block [PWM Comp.] Symbol Pin No. Output sink current Output ON resistor Threshold AC adaptor voltage detection block Hysteresis [UV Comp.] width * : Standard design value (Continued) 10 MB39A114 (Continued) Parameter VTLH 5 FB3 = 2.6 2.7 2.8 V VTHL 5 FB3 = 2.5 2.6 2.7 V VH 5 0.1* V CMV terminal output leak current ILEAK 5 CVM = 25 V 0 1 µA CVM terminal output ON resistor RON 5 CVM = 1 mA 200 400 Ω VTLH 18 FB3 = 1.3 1.4 1.5 V VTHL 18 FB3 = 1.2 1.3 1.4 V VH 18 0.1* V ILEAK 18 OVP = 25 V 0 1 µA RON 18 OVP = 1 mA 200 400 Ω VON 14 IC operating state 2 25 V VOFF 14 IC standby staet 0 0.8 V ICTLH 14 CTL = 5 V 100 150 µA ICTLL 14 CTL = 0 V 0 1 µA Output voltage VH 19 VCC = 8 V to 25 V, VH = 0 mA to 30 mA Standby current ICCS 21 CTL = 0 V 0 10 µA Power supply current ICC 21 CTL = 5 V 5 7.5 mA Threshold voltage Constant voltage control state detection block [CV Comp.] Hysteresis width Threshold voltage Hysteresis width Overvoltage detection block OVP terminal output leak [OV Comp.] current OVP terminal output ON resistor Control block [CTL] CTL input voltage Input current Bias voltage block [VH] General Symbol Pin No. (VCC = 19 V, VREF = 0 mA, Ta = +25 °C) Value Conditions Unit Min Typ Max VCC − 6.5 VCC − 6.0 VCC − 5.5 V * : Standard design value 11 MB39A114 ■ TYPICAL CHARACTERISTICS CTL terminal Input Current, Reference Voltage vs. CTL terminal Input Voltage CTL terminal input current ICTL (µ µA) 6 5 4 3 2 Ta = +25 °C CTL = 5 V 1 0 0 5 10 15 20 1000 900 800 700 600 500 400 300 200 100 0 VREF ICTL 0 25 Power supply voltage VCC (V) 4 3 Ta = +25 °C CTL = 5 V VREF = 0 mA 0 5 10 15 20 25 Power supply voltage VCC (V) Reference voltage VREF (V) Reference voltage VREF (V) 5 0 10 15 20 25 Reference Voltage vs. Load Current 6 1 5 CTL terminal input voltage VCTL (V) Reference voltage vs. Power Supply voltage 2 10 9 8 7 6 5 4 3 2 1 0 Ta = +25 °C VCC = 19 V VREF = 0 mA Reference voltage VREF (V) Power supply current ICC (mA) Power Supply Current vs. Power Supply Voltage 6 Ta = +25 °C VCC = 19 V CTL = 5 V 5 4 3 2 1 0 0 5 10 15 20 25 30 35 Load current IREF (mA) Reference voltage VREF (V) Reference Voltage vs. Operating Ambient Temperature 5.08 VCC = 19 V CTL = 5 V VREF = 0 mA 5.06 5.04 5.02 5.00 4.98 4.96 4.94 4.92 −40 −20 0 20 40 60 80 100 Operating ambient temperature Ta ( °C) (Continued) 12 MB39A114 Triangular Wave Oscillation Frequency vs. Power Supply Voltage Triangular Wave Oscillation Frequency vs. Operating Ambient Temperature 340 320 Triangular wave oscillation frequency fosc (kHz) Ta = +25 °C CTL = 5 V RT = 47 kΩ 330 310 300 290 280 270 260 5 10 15 20 25 VCC = 19 V CTL = 5 V RT = 47 kΩ 330 320 310 300 290 280 270 260 −40 −20 0 20 40 60 80 100 Operating ambient temperature Ta ( °C) Power supply voltage VCC (V) Triangular Wave Oscillation Frequency vs. Timing Resistor 1000 Triangular wave oscillation frequency fosc (kHz) 0 Ta = +25 °C VCC = 19 V CTL = 5 V 100 10 10 100 1000 Timing resistor RT (kΩ Ω) Error Amplifier Threshold Voltage vs. Ambient Temperature Error amplifier threshold voltage VTH (V) Triangular wave oscillation frequency fosc (kHz) 340 4.25 VCC = 19 V CTL = 5 V 4.24 4.23 4.22 4.21 4.20 4.19 4.18 4.17 4.16 4.15 −40 −20 0 20 40 60 80 100 Ambient temperature Ta ( °C) (Continued) 13 MB39A114 Error Amplifier Gain, Phase vs. Frequency Ta = +25 °C VCC = 19 V 180 40 ϕ 10 AV 0 0 −10 −90 −20 240 kΩ 90 Phase ϕ (deg) 20 10 kΩ 1 µF − + Gain AV (dB) 30 IN 8 2.4 kΩ (4) 9 10 kΩ (3) 7 + + −30 OUT CS Error Amp1 (Error Amp2) −180 −40 100 1k 10 k 100 k 1M 10 M Frequency f (Hz) Error Amplifier Gain, Phase vs. Frequency Ta = +25 °C VCC = 19 V 180 40 30 0 0 −10 −90 −20 10 kΩ 1 µF + Gain AV (dB) 10 AV 240 kΩ 90 Phase ϕ (deg) ϕ 20 10 kΩ − 15 + + OUT Error Amp3 −30 CS 4.2 V −180 −40 100 16 2.4 kΩ IN 1k 10 k 100 k 1M 10 M Frequency f (Hz) Current Detection Amplifier Gain, Phase vs. Frequency 180 40 AV 10 ϕ 0 0 −10 −90 −20 10 kΩ 1 µF IN 10 kΩ VCC = 19 V 13 + (24) 12 − (1) 10 (2) OUT 12.6 V Current Amp1 (Current Amp2) −30 −180 −40 100 Phase ϕ (deg) 90 20 + Gain AV (dB) 30 1k 10 k 100 k 1M 10 M Frequency f (Hz) (Continued) 14 MB39A114 (Continued) Power dissipation PD (mW) Power Dissipation vs. Operating Ambient Temperature 800 740 700 600 500 400 300 200 100 0 −40 −20 0 20 40 60 80 100 Operating ambient temperature Ta ( °C) 15 MB39A114 ■ FUNCTIONAL DESCRIPTION 1. DC/DC Converter Block (1) Reference voltage block (REF) The reference voltage circuit generator uses the voltage supplied from the VCC terminal (pin 21) to generate a temperature compensated stable voltage (5.0 V Typ) used as the reference supply voltage for the internal circuits of the IC. It is also possible to supply the load current of up to 1 mA to external circuits as a output reference voltage through the VREF terminal (pin 6) . (2) Triangular wave oscillator block (OSC) The triangular wave oscillator block has built-in capacitor for frequency setting, and generates the triangular wave oscillation waveform by connecting the freguency setting resistor with the RT terminal (pin 17) . The triangular wave is input to the PWM comparator circuits on the IC. (3) Error amplifier block (Error Amp1) The error amplifier (Error Amp1) detects voltage drop of the AC adapter and outputs a PWM control signal. Also, by connecting feedback resistor and capacitor between FB12 terminal (pin 7) and −INE1 terminal (pin 8), it is possible to set the desired level of loop gain, to provide stabilized phase compensation to the system. The CS terminal (pin 22) can be connected to a soft-start capacitor to prevent rush currents at startup. The soft start time is detected by the error amplifier, which provides a constant soft-start time independent of output load. (4) Error amplifier block (Error Amp2) The amplifier detects output signal from the current detection amplifier (Current Amp 2) . This is amplifier providing PWM control signal by comparing to +INE2 terminal (pin3), and it is used to control the charging current. Also, by connecting feedback resistor and capacitor between FB12 terminal (pin 7) and −INE2 terminal (pin 4) , it is possible to set the desired level of loop gain, to provide stabilized phase compensation to the system. The CS terminal (pin 22) can be connected to a soft-start capacitor to prevent rush currents at startup. The soft start time is detected by the error amplifier, which provides a constant soft-start time independent of output load. (5) Error amplifier block (Error Amp3) The error amplifier (Error Amp3) detects output voltage of the DC/DC converter and outputs a PWM control signal. Output voltage become 16.8 V if the SEL terminal is set in “H” level, and become 12.6 V if it sets in “L” level . Also, by connecting feedback resistor and capacitor between FB3 terminal (pin 15) and −INE3 terminal (pin 16) , it is possible to set the desired level of loop gain, to provide stabilized phase compensation to the system. The CS terminal (pin 22) can be connected to a soft-start capacitor to prevent rush currents at startup. The soft start time is detected by the error amplifier, which provides a constant soft-start time independent of output load. (6) Current detection amplifier block (Current Amp1) The current detection amplifier (Current Amp1) detects a voltage drop which occurs between both ends of the output sense resistor (RS) due to the flow of the charge current, using the +INC1 terminal (pin 13) and −INC1 terminal (pin 12) . Then it outputs the signal amplified by 20 times to the error amplifier (Error amp1) at the next stage. 16 MB39A114 (7) Current detection amplifier block (Current Amp2) The current detection amplifier (Current Amp2) detects a voltage drop which occurs between both ends of the output sense resistor (RS) due to the flow of the charge current, using the +INC2 terminal (pin 24) and −INC2 terminal (pin 1) . Then it outputs the signal amplified by 20 times to the error amplifier (Error Amp2) at the next stage. (8) PWM comparator block (PWM Comp.) The PWM comparator circuit is a voltage-pulse width converter that controls the output duty of the error amplifier (Error Amp.1 to Error Amp.3) according to the output voltage. It is compared between triangular wave voltage generated in triangular wave oscillator and error amplifier output voltage and during intervals when the triangular wave voltage is lower than the error amplifier output voltage, an external output transistor is switched on. (9) Output block (OUT) The output circuit uses a totem-pole configuration and is capable of driving an external P-ch MOS FET device. For the output “L” level, set the output amplitude to 6 V (Typ) using the voltage generated by the bias voltage block (VH) . This results in higher conversion efficiency and suppressing the withstand voltage of the connected external transistor even in a wide range of input voltages. (10) Power control (CTL) Setting the CTL terminal (14 pin) low places the IC in the standby mode. (Power supply current 10 µA max at standby mode.) CTL function table CTL Power L OFF (Standby) H ON (Active) (11) Bias voltage block (VH) The bias voltage circuit outputs VCC − 6 V (Typ) as the minimum potential of the output circuit. In the standby mode, this circuit outputs the potential equal to VCC. 2. Protection Function (1) Under voltage lockout protection circuit (UVLO) The transient state, which occurs when the power supply (VCC) is turned on, a momentary decrease in supply voltage or internal reference voltage (VREF), may cause the control IC to malfunction, resulting in breakdown or degradation of the system. To prevent such malfunctions, under voltage lockout protection circuit detects a internal reference voltage drop and fixes the OUT terminal (pin 20) at the “H” level. The system restores voltage supply when the internal reference voltage reaches the threshold voltage of the under voltage lockout protection circuit. Protection circuit (UVLO) operation function table. At UVLO operating (VREF voltage is lower than UVLO threshold voltage.) OUT CS CVM OVP H L H H 17 MB39A114 (2) AC adapter detection block (UV Comp.) This block detects that power-supply voltage (VCC) is lower than the battery voltage +0.2 V (Typ) , and OUT terminal (pin 18) is fixed at the High level. The system restores voltage supply when the supply voltage reaches the threshold voltage of the AC adapter detection block. Protection circuit (UV Comp.) operation function table. At UV Comp. operating (VCC voltage is lower than UV Comp. threshold voltage.) OUT CS H L 3. Soft start Function Soft start block (SOFT) Connecting a capacitor to the CS terminal (pin 22) prevents rush currents from flowing upon activation of the power supply. Using the error amplifier to detect a soft start allows to soft-start at constant setting time intervals independent of the output load of the DC/DC converter. 4. Detection Function (1) Constant voltage control state detection block. (CV Comp.) Error amplifier (Error Amp3) detects the voltage at FB3 terminal (pin 15) falling to or below 2.6 V (Typ) and outputs the Low level to the constant voltage control state detection block output terminal (CVM, pin 5) . (2) Overvoltage state detection block (OV Comp.) Error amplifier (Error Amp3) detects the voltage at FB3 terminal (pin 15) falling to or below 1.3 V (Typ) and outputs the High level to the overvoltage detection block output terminal (OVP, pin 18) . 5. Switching function Output voltage switching function block (SEL) The charge voltage is set in 16.8 V or 12.6 V by SEL terminal (pin 11) . SEL function table SEL DC/DC output setting voltage 18 H 16.8 V L 12.6 V MB39A114 ■ SETTING THE CHARGING VOLTAGE The setting of the charging voltage is switched to 3 cell or 4 cell by the SEL terminal. As for the charge voltage, the SEL terminal becomes 16.8 V at “H” level. It become 12.6 V at “L” level. Charging voltage of battery : VO VO (V) = (150 kΩ + 50 kΩ) /50 kΩ × 4.20 V = 16.8 (SEL = H) VO (V) = (150 kΩ + 50 kΩ) /50 kΩ × 3.15 V = 12.6 (SEL = L) VO B −INC2 1 R3 −INE3 150 kΩ − 16 R4 CS <Error Amp3> 50 kΩ + + 22 SEL 11 3.15 V 4.2 V ■ SETTING THE CHARGING CURRENT The charging current value (output limit current value) is set at the +INE2 terminal (pin 3) . If a current exceeding the set value attempts to flow, the charge voltage drops according to the set current value. Battery charge current setting voltage : +INE2 +INE2 (V) = 20 × I1 (A) × RS (Ω) ■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY The triangular wave oscillation frequency can be set by connecting a timing resistor (RT ) to the RT terminal (pin 17) . Triangular wave oscillation frequency : fosc fosc (kHz) =: 14100/RT (kΩ) 19 MB39A114 ■ SETTING THE SOFT START TIME (1) Setting constant voltage mode soft start To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors (CS ) to the CS terminal (pin 22). When CTL terminal (pin 14) is “H” levels and IC is activated (VCC ≥ UVLO threshold voltage), Q2 becomes off and the external soft-start capacitors (CS) connected to CS terminal are charged at 10 µA. The error amplifier output (FB3 terminal (pin 15) ) is determined by comparison between the lower voltage of the two non-inverted input terminal voltage (internal reference voltage 4.2 V (Typ) , CS terminal voltages) and the inverted input terminal voltage (−INE3 terminal (pin 16) voltage). The FB3 is decided for the soft-start period (CS terminal voltage < 4.2 V) by the comparison between −INE3 terminal voltage and CS terminal voltage. The DC/DC converter output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor externally connected to the CS terminal is charged. The soft-start time is obtained from the following formula : Soft start time : ts (time until output voltage 100%) ts (s) =: 0.42 × CS (µF) =: 4.9 V CS terminal voltage =: 4.2 V Internal reference voltage in Error Amp block =: 0 V Soft-start time : ts VREF 10 µA 10 µA FB3 15 −INE3 16 CS − + + 22 Error Amp3 4.2 V CS Q2 Soft start circuit 20 UVLO MB39A114 (2) Setting constant current mode soft-start To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors (CS ) to the CS terminal (pin 22). When CTL terminal (pin 14) is “H” levels and IC activated (VREF ≥ UVLO threshold voltage), Q2 becomes off and the external soft-start capacitors (CS) connected to CS terminal are charged at 10 µA. The error amplifier1 output (FB12 terminal (pin 7) ) is determined by comparison between the lower voltage of the two non-inverted input terminal voltage (+INE1 terminal (pin 9) voltage, CS terminal voltages) and the inverted input terminal voltage (−INE1 terminal (pin 8) voltage). The FB12 is decided for the soft-start period (CS terminal voltage < +INE1) by the comparison between −INE1 terminal voltage and CS terminal voltage. The DC/DC converter output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor externally connected to the CS terminal is charged. The error amplifier2 output (FB12 terminal (pin 7) ) is determined by comparison between the lower voltage of the two non-inverted input terminal voltage (+INE2 terminal (pin 3) voltage, CS terminal voltages) and the inverted input terminal voltage (−INE2 terminal (pin 4) voltage). The FB12 is decided for the soft-start period (CS terminal voltage < +INE2) by the comparison between −INE2 terminal voltage and CS terminal voltage. The DC/DC converter output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor externally connected to the CS terminal is charged. The soft-start time is obtained from the following formula : Soft start time : ts (time until output voltage 100%) ts (s) =: +INE1 (+INE2) /10 µA × CS (µF) CS terminal voltage =: 4.9 V +INE1 (+INE2) Comparison voltage with Error Amp1block −INE1 voltage (comparison voltage with Error Amp2 block −INE2 voltage) =: 0 V Soft-start time : ts 21 MB39A114 VREF 10 µA FB12 −INE1 −INE2 CS 10 µA 7 Error Amp1 (Error Amp2) 8 4 − + + 22 +INE1 CS +INE2 9 3 Q2 Soft start circuit 22 UVLO MB39A114 ■ SETTING THE DYNAMICALLY-CONTROLLED CHARGING With an external resistor connected to +INE1 terminal (pin 9) , dynamically-controlled charging mode to reduce the charge current to keep AC adapter power constant when the partial potential point A of AC adapter voltage (VCC) become lower the −INE1 terminal voltage. Dynamically-controlled charging setting voltage : Vth Vth (V) = (R1 + R2) /R2 × −INE1 <Error Amp1> −INE1 A VCC R1 +INE1 8 − 9 + R2 23 MB39A114 ■ ABOUT CONSTANT VOLTAGE CONTROL STATE DETECTION/ OVERVOLTAGE DETECTION TIMING CHART In the constant voltage control state, the CVM terminal (pin 5) of the constant voltage control state detection block (CV Comp.) outputs the “L” level when the voltage at the FB3 terminal (pin 15) of the error amplifier (Error Amp3) becomes 2.6 V (Typ) or less. When the DC/DC converter output voltage enters the state of the overvoltage higher than a setting voltage, the voltage at FB3 terminal (pin 15) of the error amplifier (Error Amp3) becomes 1.3 V (Typ) or less. As a result, the OVP terminal (pin 18) of the overvoltage detection block (OVComp.) outputs the “H” level. Both of the CVM terminal and the OVP terminal are open-drain output forms : Error Amp3 FB3 2.6 V CV Comp. VTHL 2.5 V Error Amp2 Error Amp1 FB12 1.5 V 1.3 V OV Comp. VTHL CV Comp. CVM OV Comp. OVP OUT Constant current control 24 Constant voltage control Overvoltage State MB39A114 ■ ABOUT THE OPERATION TIMING CHART Error Amp2 Error Amp1 FB12 2.5 V Error Amp3 FB3 1.5 V Current Amp2 OUTC2 OUT Constant voltage control Constant current control AC adapter dynamicallycontrolled charging 25 MB39A114 ■ PROCESSING WITHOUT USING OF THE CURRENT AMP1 AND AMP2 When Current Amp is not used, connect the +INC1 terminal (pin 13), and −INC1 terminal (pin 12) to VREF, and be short-circuited of +INC2 terminal (pin 24) and −INC2 terminal (pin 1) , and then leave OUTC1 terminal (pin 10) and OUTC terminal (pin 2) open. • Connection when Current Amp is not used VO “Open” 12 −INC1 +INC1 13 1 −INC2 +INC2 24 10 OUTC1 2 OUTC2 6 VREF ■ PROCESSING WITHOUT USING OF THE ERROR AMP1 AND AMP2 When Error Amp is not used, leave FB12 terminal (pin 7) open and connect the −INE1 terminal (pin 8) and −INE2 terminal (pin 4) to GND, and connect +INE1 terminal (pin 9) and +INE2 terminal (pin 3) to VREF. • Connection when Error Amp is not used “Open” 26 9 3 +INE1 +INE2 8 4 −INE1 −INE2 7 FB12 6 VREF GND 23 MB39A114 ■ PROCESSING WITHOUT USING OF THE CS TERMINAL When soft-start function is not used, leave the CS terminal (pin 22) open. • Connection when no soft-start time is specified “Open” CS 22 27 MB39A114 ■ I/O EQUIVALENT CIRCUIT Reference voltage block Control block VCC 21 + − CTL 14 6 VREF ESD protection element 33.1 kΩ 37.8 kΩ 51 kΩ ESD protection element 12.35 kΩ GND 23 GND Soft start block VREF (5.0 V) Triangular wave oscillator block Error amplifier block (Error Amp1) VCC VCC VREF (5.0 V) 22 CS 1.3 V + − −INE1 8 7 FB12 CS 17 RT GND GND GND 9 +INE1 Error amplifier block (Error Amp3) Error amplifier block (Error Amp2) VCC VCC VREF (5.0 V) VREF (5.0 V) −INE2 4 −INE3 16 FB12 CS GND CS 4.2 V 15 FB3 GND 3 +INE2 Current detection amplifier block (Current Amp1) Current detection amplifier block (Current Amp2) VCC VCC +INC1 13 +INC2 24 10 OUTC1 GND 2 OUTC2 GND 12 −INC1 1 −INC1 (Continued) 28 MB39A114 (Continued) PWM comparator block Output block VCC AC adapter detection block VCC VCC −INC2 FB12 20 OUT CT VREF (5.0 V) FB3 VH GND GND GND Overvoltage detection block Constant voltage control state detection block VCC VCC VREF (5.0 V) 5 CVM VREF (5.0 V) 18 OVP FB3 FB3 GND GND Bias voltage block Output voltage switching function block VCC SEL 11 85 kΩ 19 VH 97 kΩ GND GND 29 MB39A114 ■ APPLICATION EXAMPLE D2 VIN (8 to 25 V) R4 180 kΩ R5 330 kΩ R6 30 kΩ R10 120 kΩ <CV Comp.> − C8 10000 pF −INE1 CVM 5 + 8 2.6 V R7 22 kΩ R11 30 kΩ OUTC1 +INC1 −INC1 +INE1 −INE2 C10 4700 pF R9 10 kΩ R8 100 kΩ OUTC2 +INC2 A −INC2 B R12 30 kΩ FB12 R13 20 kΩ R16 200 kΩ +INE2 Q2 10 13 12 <Current Amp 1> + VREF −×20 − + + 1.4 V 0.2 V + <UV Comp.> − 4 <Current Amp 2> 2 1 OVP 18 − 9 24 <OV Comp.> + <Error Amp 1> + −×20 −INC2 (VO) <Error Amp 2> VCC 21 <PWM Comp.> − + + + + − C12 0.1 µF <OUT> 3 Drive C1 4.7 µF C2 4.7 µF A OUT B Q1 20 7 R14 1 kΩ R15 120 Ω I1 L1 VREF VH <Error Amp 3> SW −INE3 R1 16 R2 C6 1500 pF R3 330 kΩ SEL VH −2.5 V −1.5 V − + + VCC − 6 V Bias Voltage 15 11 <SOFT> 4.2 V bias VREF VCC 10 µA CS + D1 VREF UVLO H : 4Cell L : 3Cell CTL <OSC> 500 kHz <REF> <CTL> 22 C11 0.022 µF VREF 5.0 V CT 45 pF 17 6 RT VREF 23 GND R2 47 kΩ C9 0.1 µF 15 µH 19 UVLO 4.2 V/3.15 V FB3 30 C7 0.1 µF 14 C3 22 µF R27 100 kΩ VO Q3 R1 0.033 Ω C4 4.7 µF Battery MB39A114 ■ PARTS LIST COMPONENT ITEM SPECIFICATION VENDOR PARTS No. Q1, Q3 Q2 Pch FET Nch FET VDS = −30 V, ID = −7.0 A VDS = 30 V, ID = 1.4 A NEC SANYO µPA2714GR MCH3401 D1, D2 Diode VF = 0.42 V (Max) , At IF = 3 A ROHM RB053L-30 L1 Inductor 15 µH 3.6 A, 50 mΩ SUMIDA CDRH104R-150 C1, C2, C4 C3 C6 C7, C9 C8 C10 C11 C12 Ceramics Condenser OS-CONTM Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser Ceramics Condenser 4.7 µF 22 µF 1500 pF 0.1 µF 0.01 µF 4700 pF 0.022 µF 0.1 µF 25 V 20 V 50 V 50 V 50 V 50 V 50 V 50 V TDK SANYO TDK TDK TDK TDK TDK TDK C3225JB1E475K 20SVP22M C1608JB1H152K C1608JB1H104K C1608JB1H103K C1608JB1H472K C1608JB1H223K C1608JB1H104K R1 R2 R3, R5 R4 R6 R7 R8 R9 R10 R11, R12 R13 R14 R15 R16 R27 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 33 mΩ 47 kΩ 330 kΩ 180 kΩ 30 kΩ 22 kΩ 100 kΩ 10 kΩ 120 kΩ 30 kΩ 20 kΩ 1 kΩ 120 Ω 200 kΩ 100 kΩ 1% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% KOA ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm ssm SL1TTE33LOF RR0816P-473-D RR0816P-334-D RR0816P-184-D RR0816P-303-D RR0816P-223-D RR0816P-104-D RR0816P-103-D RR0816P-124-D RR0816P-303-D RR0816P-203-D RR0816P-102-D RR0816P-121-D RR0816P-204-D RR0816P-104-D Note : NEC SANYO ROHM SUMIDA TDK KOA ssm OS-CON : NEC Corporation : SANYO Electric Co., Ltd. : ROHM CO., LTD. : Sumida Corporation : TDK Corporation : KOA Corporation : SUSUMU CO., LTD. is a trademark of SANYO Electric Co., Ltd. 31 MB39A114 ■ SELECTION OF COMPONENTS • Pch MOS FET The P-ch MOS FET for switching use should be rated for at least +20% more than the input voltage. To minimize continuity loss, use a FET with low RDS(ON) between the drain and source. For high input voltage and high frequency operation, on-cycle switching loss will be higher so that power dissipation must be considered. In this application, the NEC µPA2714GR is used. Continuity loss, on/off switching loss and total loss are determined by the following formulas. The selection must ensure that peak drain current does not exceed rated values. Continuity loss : Pc = ID2 × RDS (ON) × Duty PC On-cycle swiching loss : PS (ON) = PS (ON) VD (Max) × ID × tr × fosc 6 Off-cycle switching loss : PS (OFF) PS (OFF) = VD (Max) × ID (Max) × tf × fosc 6 Total loss : PT = PC + PS (ON) + PS (OFF) PT Example : Using the µPA2714GR 16.8 V setting Input voltage VIN (Max) = 25 V, output voltage VO = 16.8 V, drain current ID = 3 A, oscillation frequency fosc = 300 kHz, L = 15 µH, drain-source on resistance RDS (ON) =: 18 mΩ, tr =: 15 ns, tf =: 42 ns Drain current (Max) : ID (Max) ID (Max) = Io + = 3+ VIN (Max) − Vo 2L 25 − 16.8 2 × 15 × 10 − 6 tON × 1 300 × 103 × 0.672 =: 3.6 A Drain current (Min) : ID (Min) ID (Min) = Io − = 3− =: 2.4 A 32 VIN (Max) − Vo 2L 25 − 16.8 2 × 15 × 10−6 tON × 1 300 × 103 × 0.672 MB39A114 PC = ID2 × RDS (ON) × Duty = 32 × 0.018 × 0.672 =: 0.109 W PS (ON) = = VD × ID × tr × fosc 6 25 × 3 × 15 × 10−9 × 300 × 103 6 =: 0.056 W PS (OFF) = = VD × ID (Max) × tf × fosc 6 25 × 3.6 × 42 × 10−9 × 300 × 103 6 =: 0.189 W PT = PC + PS (ON) + PS (OFF) =: 0.109 + 0.056 + 0.189 =: 0.354 W The above power dissipation figures for the µPA2714GR are satisfied with ample margin at 2.0 W. 12.6 V setting Input voltage VIN (Max) = 22 V, output voltage VO = 12.6 V, drain current ID = 3 A, oscillation frequency fosc = 300 kHz, L = 15 µH, drain-source on resistance RDS (ON) =: 18 mΩ, tr =: 15 ns, tf =: 42 ns Drain current (Max) : ID (Max) ID (Max) = Io + = 3+ VIN (Max) − Vo 2L 22 − 12.6 2 × 15 × 10 −6 ton × 1 300 × 103 × 0.572 × 0.572 =: 3.6 A Drain current (Min) : ID (Min) ID (Min) = Io − = 3− VIN (Max) − Vo 2L 22 − 12.6 2 × 15 × 10−6 tON × 1 300 × 103 =: 2.4 A 33 MB39A114 PC = ID2 × RDS (ON) × Duty = 32 × 0.018 × 0.572 =: 0.093 W PS (ON) = = VD × ID × tr × fosc 6 22 × 3 × 15 × 10−9 × 300 × 103 6 =: 0.050 W PS (OFF) = = VD × ID (Max) × tf × fosc 6 22 × 3.6 × 42 × 10−9 × 300 × 103 6 =: 0.166 W PT = PC + PS (ON) + PS (OFF) =: 0.093 + 0.050 + 0.166 =: 0.309 W The above power dissipation figures for the µPA2714GR are satisfied with ample margin at 2.0 W. • Inductor In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor, but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous operation and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value, which will enable continuous operation under light loads. Note that if the inductance value is too high, however, direct current resistance (DCR) is increased and this will also reduce efficiency. The inductance must be set at the point where efficiency is greatest. Note also that the DC superimposition characteristics become worse as the load current value approaches the rated current value of the inductor, so that the inductance value is reduced and ripple current increases, causing loss of efficiency. The selection of rated current value and inductance value will vary depending on where the point of peak efficiency lies with respect to load current. Inductance values are determined by the following formulas. The L value for all load current conditions is set so that the peak to peak value of the ripple current is 1/2 the load current or less. Inductance value : L L≥ 34 2 (VIN − Vo) Io tON MB39A114 16.8 V output Example) 2 (VIN (Max) − Vo) L≥ Io ≥ ≥ 2 × (25 − 16.8) 3 tON 300 × 103 × 0.672 12.2 µH 12.6 V output Example) 2 (VIN (Max) − Vo) L≥ Io ≥ 1 × tON 2 × (22 − 12.6) × 3 1 × 300 × 103 0.572 ≥ 12.0 µH Inductance values derived from the above formulas are values that provide sufficient margin for continuous operation at maximum load current, but at which continuous operation is not possible at light loads. It is therefore necessary to determine the load level at which continuous operation becomes possible. In this application, the SUMIDA CDRH104R-150 is used. The following formula is available to obtain the load current as a continuous current condition when 15 µH is used. The value of the load current satisfying the continuous current condition : Io Io ≥ Vo 2L tOFF Example) Using the CDRH104R-150 15 µH (tolerance ± 30%) , rated current = 3.6 A 16.8 V output Vo Io ≥ tOFF 2L ≥ 16.8 2 × 15 × 10 −6 × 1 300 × 103 × (1 − 0.672) × (1 − 0.572) ≥ 0.61 A 12.6 V output Vo Io ≥ tOFF 2L ≥ 12.6 2 × 15 × 10−6 × 1 300 × 103 ≥ 0.60 A 35 MB39A114 To determine whether the current through the inductor is within rated values, it is necessary to determine the peak value of the ripple current as well as the peak-to-peak values of the ripple current that affect the output ripple voltage. The peak value and peak-to-peak value of the ripple current can be determined by the following formulas. Peak Value : IL VIN − Vo IL ≥ Io + tON 2L Peak-to-peak Value : ∆IL ∆IL = VIN − Vo tON L Example) Using the CDRH104R-150 15 µH (tolerance ± 30%) , rated current = 3.6 A Peak Value 16.8 V output IL ≥ Io + ≥ 3+ VIN − Vo tON 2L 25 − 16.8 × 2 × 15 × 10−6 1 300 × 103 × 0.672 ≥ 3.6 A 12.6 V output IL ≥ Io + ≥ 3+ VIN − Vo 2L tON 22 − 12.6 × 2 × 15 × 10−6 1 300 × 103 ≥ 3.6 A Peak-to-peak Value 16.8 V output VIN − Vo tON ∆IL = L = 25 − 16.8 15 × 10 =: 1.22 A 36 −6 × 1 300 × 103 × 0.672 × 0.572 MB39A114 12.6 V output VIN − Vo ∆IL = L tON 22 − 12.6 = 15 × 10 −6 =: × 1 300 × 103 × 0.572 1.2 A • Flyback diode Shottky barrier diode (SBD) is generally used for the flyback diode when the reverse voltage to the diode is less than 40V. The SBD has the characteristics of higher speed in terms of faster reverse recovery time, and lower forward voltage, and is ideal for achieving high efficiency. As long as the DC reverse voltage is sufficiently higher than the input voltage, and the mean current flowing during the diode conduction time is within the mean output current level, and as the peak current is within the peak surge current limits, there is no problem. In this application the ROHM RB053L-30 are used. The diode mean current and diode peak current can be obtained by the following formulas. Diode mean current : IDi IDi ≥ Io × (1 − Vo VIN ) Diode peak current : IDip IDip ≥ (Io + Vo 2L tOFF) Example) Using the RB053L-30 VR (DC reverse voltage) = 30 V, mean output current = 3.0 A, peak surge current = 70 A, VF(forward voltage) = 0.42 V, at IF = 3.0 A 16.8 V output IDi ≥ Io × ≥ 3 ≥ (1 − Vo VIN ) × (1 − 0.672) 0.984 A 12.6 V output IDi ≥ Io × ≥ 3 (1 − Vo VIN ) × (1 − 0.572) ≥ 1.284 A 37 MB39A114 16.8 V output IDip ≥ Vo (Io + ≥ 2L tOFF) 3.6 A 12.6 V output IDip ≥ Vo (Io + ≥ tOFF) 2L 3.6 A • Smoothing capacitor The smoothing capacitor is an indispensable element for reducing ripple voltage in output. In selecting a smoothing capacitor, it is essential to consider equivalent series resistance (ESR) and allowable ripple current. Higher ESR means higher ripple voltage, so that to reduce ripple voltage it is necessary to select a capacitor with low ESR. However, the use of a capacitor with low ESR can have substantial effects on loop phase characteristics, and therefore requires attention to system stability. Care should be also taken to use a capacity with sufficient margin for allowable ripple current. This application uses the 20SVP22M (OS-CONTM : SANYO) . The ESR, capacitance value, and ripple current can be calculated from the following formulas. Equivalent series resistance : ESR ESR ≤ ∆Vo − ∆IL 1 2πfCL Capacitance value : CL CL ≥ ∆IL 2πf (∆Vo − ∆IL × ESR) Ripple current : ICLrms ICLrms ≥ (VIN − Vo) tON 2√3L Example) Using the 20SVP22M Rated voltage = 20 V, ESR = 60 mΩ, maximum allowable ripple current = 1450 mArms Equivalent series resistance 16.8 V output ∆Vo 1 ESR ≤ − ∆IL 2πfCL ≤ ≤ 38 0.168 1.22 114 mΩ − 1 2π × 300 × 103 × 22 × 10−6 MB39A114 12.6 V output ∆Vo ESR ≤ ∆IL − 0.126 ≤ − 1.2 1 2πfCL 1 2π × 300 × 103 × 22 × 10−6 ≤ 80 mΩ Capacitance value 16.8 V output CL ≥ ≥ ∆IL 2πf (∆Vo − ∆IL × ESR) 1.22 2π × 300 × 10 × (0.168 − 1.22 × 0.06) 3 ≥ 6.8 µF 12.6 V output CL ≥ ≥ ∆IL 2πf (∆Vo − ∆IL × ESR) 1.2 2π × 300 × 10 × (0.126 − 1.2 × 0.06) 3 ≥ 11.8 µF Ripple current 16.8 V output (VIN − Vo) tON ICLrms ≥ 2√3L ≥ (25 − 16.8) × 0.672 2√3 × 15 × 10−6 × 300 × 103 ≥ 707 mArms 12.6 V output (VIN − Vo) tON ICLrms ≥ 2√3L ≥ (22 − 12.6) × 0.572 2√3 × 15 × 10−6 × 300 × 103 ≥ 690 mArms 39 MB39A114 ■ REFERENCE DATA Conversion efficiency vs. Charging current (constant voltage mode) 100 98 Effciency η (%) 96 94 92 90 88 Ta = +25 °C VAC = 19 V VBATT = 12.6 V setting η = (VBATT × IBATT) / (VAC × IAC) VBATT conversion 86 84 82 80 0.01 0.1 1 10 IBATT (A) Conversion efficiency vs. Charging voltage (constant current mode) 100 98 Effciency η (%) 96 94 92 90 88 Ta = +25 °C VAC = 19 V IBATT = 3 A setting η = (VBATT × IBATT) / (VAC × IAC) VBATT conversion 86 84 82 80 0 2 4 6 8 10 12 14 VBATT (V) BATT voltage vs. BATT charging current (12.6 V setting) 18 16 VBATT (V) 14 Ta = +25 °C VAC = 19 V VBATT = 12.6 V setting 12 D.C.C. Mode 10 8 Dead Battery Mode 6 4 2 0 0.0 D.C.C. Mode : Dynamically-controlled charging 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IBATT (A) (Continued) 40 MB39A114 Conversion efficiency vs. Charging current (constant voltage mode) 100 98 Effciency η (%) 96 94 92 90 88 Ta = +25 °C VAC = 19 V VBATT = 16.8 V setting η = (VBATT × IBATT) / (VAC × IAC) VBATT conversion 86 84 82 80 0.01 0.1 1 10 IBATT (A) Conversion efficiency vs. Charging voltage (constant current mode) 100 98 Effciency η (%) 96 94 92 90 88 Ta = +25 °C VAC = 19 V IBATT = 3 A setting η = (VBATT × IBATT) / (VAC × IAC) VBATT conversion 86 84 82 80 0 2 4 6 8 10 12 14 16 VBATT (V) BATT voltage vs. BATT charging current (16.8 V setting) 18 16 D.C.C. Mode VBATT (V) 14 12 Dead Battery Mode 10 8 6 4 2 0 0.0 Ta = +25 °C VAC = 19 V VBATT = 16.8 V setting D.C.C. Mode : Dynamically-controlled charging 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 IBATT (A) (Continued) 41 MB39A114 Switching waveform at constant voltage mode (12.6 V setting) OUT (V) 15 VAC = 19 V CV mode IBATT = 1.5 A VBATT = 12.6 V setting VD (V) 20 10 5 0 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 (µs) Switching waveform at constant current mode (12.6 V setting at 10 V) OUT (V) 15 VAC = 19 V CC mode IBATT = 3 A setting VBATT = 10 V VD (V) 20 10 5 0 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 (µs) (Continued) 42 MB39A114 Switching waveform at constant voltage mode (16.8 V setting) OUT (V) 15 VAC = 19 V CV mode IBATT = 1.5 A VBATT = 16.8 V setting VD (V) 20 10 5 0 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 (µs) Switching waveform at constant current mode (16.8 V setting at 10 V) OUT (V) 15 VAC = 19 V CC mode IBATT = 3 A setting VBATT = 10 V VD (V) 20 10 5 0 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 (µs) (Continued) 43 MB39A114 Soft start operating waveform at constant voltage mode (12.6 V setting) (1) VAC = 19 V CV mode RL = 20 Ω VBATT = 12.6 V setting VO (V) 20 15 10 5 VO 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Soft start operating waveform at constant voltage mode (12.6 V setting) (2) CVM (V) 6 VAC = 19 V CV mode RL = 20 Ω VBATT = 12.6 V setting 4 2 CVM 0 OVP (V) 5 OVP 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 44 MB39A114 Discharge operating waveform at constant voltage mode (12.6 V setting) (1) VAC = 19 V CV mode RL = 20 Ω VBATT = 12.6 V setting VO (V) 20 15 10 5 VO 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Discharge operating waveform at constant voltage mode (12.6 V setting) (2) CVM (V) 6 VAC = 19 V CV mode RL = 20 Ω VBATT = 12.6 V setting 4 2 CVM 0 OVP (V) 5 OVP 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 45 MB39A114 Soft start operating waveform at constant current mode (12.6 V setting) (1) VAC = 19 V CC mode RL = 3.33 Ω VBATT = 12.6 V setting VO (V) 20 15 10 5 VO 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Soft start operating waveform at constant current mode (12.6 V setting) (2) CVM (V) 6 VAC = 19 V CC mode RL = 3.33 Ω VBATT = 12.6 V setting 4 2 CVM 0 OVP (V) 5 OVP 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 46 MB39A114 Discharge operating waveform at constant current mode (12.6 V setting) (1) VAC = 19 V CC mode RL = 3.33 Ω VBATT = 12.6 V setting VO (V) 20 15 10 5 VO 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Discharge operating waveform at constant current mode (12.6 V setting) (2) CVM (V) 6 VAC = 19 V CC mode RL = 3.33 Ω VBATT = 12.6 V setting 4 2 CVM 0 OVP (V) 5 0 OVP CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 47 MB39A114 Soft start operating waveform at constant voltage mode (16.8 V setting) (1) VAC = 19 V CV mode RL = 20 Ω VBATT = 16.8 V setting VO (V) 20 15 10 5 VO 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Soft start operating waveform at constant voltage mode (16.8 V setting) (2) CVM (V) 6 VAC = 19 V CV mode RL = 20 Ω VBATT = 16.8 V setting 4 2 CVM 0 OVP (V) 5 OVP 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 48 MB39A114 Discharge operating waveform at constant voltage mode (16.8 V setting) (1) VAC = 19 V CV mode RL = 20 Ω VBATT = 16.8 V setting VO (V) 20 15 10 5 VO 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Discharge operating waveform at constant voltage mode (16.8 V setting) (2) CVM (V) 6 VAC = 19 V CV mode RL = 20 Ω VBATT = 16.8 V setting 4 2 CVM 0 OVP (V) 5 OVP 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 49 MB39A114 Soft start operating waveform at constant current mode (16.8 V setting) (1) VAC = 19 V CC mode RL = 3.33 Ω VBATT = 16.8 V setting VO (V) 20 15 10 5 VO 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Soft start operating waveform at constant current mode (16.8 V setting) (2) CVM (V) 6 VAC = 19 V CC mode RL = 3.33 Ω VBATT = 16.8 V setting 4 2 CVM 0 OVP (V) 5 OVP 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) (Continued) 50 MB39A114 (Continued) Discharge operating waveform at constant current mode (16.8 V setting) (1) VAC = 19 V CC mode RL = 3.33 Ω VBATT = 16.8 V setting VO (V) 20 15 10 5 VO 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) Discharge operating waveform at constant current mode (16.8 V setting) (2) CVM (V) 6 VAC = 19 V CC mode RL = 3.33 Ω VBATT = 16.8 V setting 4 2 CVM 0 OVP (V) 5 OVP 0 CTL (V) 5 CTL 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 (ms) 51 MB39A114 ■ USAGE PRECAUTIONS • Printed circuit board ground lines should be set up with consideration for common impedance. • Take appropriate static electricity measures. • Containers for semiconductor materials should have anti-static protection or be made of conductive material. • After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. • Work platforms, tools, and instruments should be properly grounded. • Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground. • Do not apply negative voltages. • The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause abnormal operation. ■ ORDERING INFORMATION Part number MB39A114PFV 52 Package 24-pin plastic SSOP (FPT-24P-M03) Remarks MB39A114 ■ PACKAGE DIMENSION Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) . Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 24-pin plastic SSOP (FPT-24P-M03) 0.17±0.03 (.007±.001) *17.75±0.10(.305±.004) 24 13 *2 5.60±0.10 7.60±0.20 (.220±.004) (.299±.008) INDEX Details of "A" part +0.20 1.25 –0.10 +.008 .049 –.004 (Mounting height) 0.25(.010) 1 "A" 12 0~8˚ +0.08 0.65(.026) 0.24 –0.07 +.003 .009 –.003 0.13(.005) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.10(.004) C 2003 FUJITSU LIMITED F24018S-c-4-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. 53 MB39A114 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0405 FUJITSU LIMITED Printed in Japan