GS7025 PRO-LINX™ Serial Digital Receiver Key Features Description • SMPTE 259M-C compliant (270Mb/s) • Automatic cable equalization (typically greater than 350m of high-quality cable) • Serial data outputs muted and serial clock remains active when input data is lost • Operation independent of SAV/EAV sync signals • Signal strength indicator output The GS7025 provides automatic cable equalization and high-performance clock and data recovery for serial digital signals. The GS7025 receives either single-ended or differential serial digital data and outputs differential clock and retimed data signals at PECL levels (800mV). The onboard cable equalizer provides up to 35dB of gain at 135MHz, which typically results in equalization of greater than 350m of high-quality cable at 270Mb/s. • Carrier detect with programmable threshold level • Power savings mode (output serial clock disable) • Large IJT, typically 0.56UI beyond loop bandwidth • Robust lock detect The GS7025 requires only one external resistor to set the VCO centre frequency and provides adjustment free operation. Applications Cable equalization plus clock and data recovery for all high speed serial digital interface applications involving SMPTE 259M-C. The GS7025 has dedicated pins to indicate signal strength, carrier detect, and LOCK. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. In addition, the GS7025 provides an 'Output Eye Monitor Test' (OEM_TEST) for diagnostic testing of signal integrity after equalization, prior to re-slicing. The serial clock outputs can be disabled to reduce power. The GS7025 operates from a single +5V or -5V supply. A/D DDI COSC ANALOG DIGITAL MUX DDI LOCK CARRIER DETECT PHASELOCK HARMONIC LOGIC MUTE SDO SDI + SDI -- FREQUENCY ACQUISITION VARIABLE GAIN EQ STAGE SDO CLK_EN PHASE DETECTOR SCO SCO OEM_TEST EYE MONITOR AUTO EQ CONTROL + AGC CAP CD_ADJ SSI/CD CHARGE PUMP LF+ LFS LF- VCO CBG RVCO GS7025 Functional Block Diagram GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 www.gennum.com 1 of 23 Revision History Version ECR PCN Date 7 152762 − October 2009 Changes and/or Modifications Converted document to new format. Changed Part Numbers in 5.3 Ordering Information. Contents Key Features........................................................................................................................................................1 Applications.........................................................................................................................................................1 Description...........................................................................................................................................................1 Revision History .................................................................................................................................................2 1. Pin Out...............................................................................................................................................................3 1.1 GS7025 Pin Assignment .................................................................................................................3 1.2 GS7025 Pin Descriptions ................................................................................................................4 2. Electrical Characteristics ............................................................................................................................5 2.1 Absolute Maximum Ratings ..........................................................................................................5 2.2 DC Electrical Characteristics ........................................................................................................5 2.3 AC Electrical Characteristics ........................................................................................................6 2.4 Typical Performance Curves ........................................................................................................8 3. Detailed Description.................................................................................................................................. 10 3.1 Cable Equalizer .............................................................................................................................. 10 3.1.1 Signal Strength Indication/Carrier Detect ................................................................ 10 3.1.2 Carrier Detect Threshold Adjust................................................................................... 11 3.1.3 Output Eye Monitor Test................................................................................................. 11 3.2 Reclocker .......................................................................................................................................... 12 3.2.1 Phase Locked Loop (PLL) ................................................................................................. 12 3.2.2 Frequency Acquisition..................................................................................................... 13 3.2.3 Logic Circuit ........................................................................................................................ 14 3.2.4 Locking.................................................................................................................................. 14 3.2.5 Output Data Muting.......................................................................................................... 16 3.2.6 Clock Enable........................................................................................................................ 16 3.2.7 Stressful Data Patterns..................................................................................................... 16 3.3 I/O Description ............................................................................................................................... 16 3.3.1 High Speed Analog Inputs (SDI/SDI)........................................................................... 16 3.3.2 High Speed Outputs (SDO/SDO and SCO/SCO)...................................................... 18 4. Application Information .......................................................................................................................... 19 4.1 Typical Application Circuit ........................................................................................................ 19 5. Package & Ordering Information .......................................................................................................... 20 5.1 Package Dimensions ..................................................................................................................... 20 5.2 Solder Reflow Profiles .................................................................................................................. 21 5.3 Ordering Information ................................................................................................................... 21 GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 2 of 23 1. Pin Out DDI COSC 40 39 38 37 36 35 34 VEE LOCK 41 VCC SSI/CD 42 CLK_EN A/D 43 VEE MOD 44 OEM_TEST VCC_75 1.1 GS7025 Pin Assignment 1 33 VEE DDI 2 32 SDO VCC_75 3 31 SDO VCC 4 30 VEE VEE 5 GS7025 29 SCO SDI 6 TOP VIEW 28 SCO SDI 7 27 VEE VCC 8 26 nc VEE 15 16 17 18 19 20 21 22 RVCO CBG VCC 14 RVCO_RTN nc 13 VEE 23 12 LF- 11 LFS AGC- LF+ RSV1 VEE nc 24 VCC 25 10 AGC+ 9 CD_ADJ Figure 1-1: GS7025 Pin Out GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 3 of 23 1.2 GS7025 Pin Descriptions Table 1-1: GS7025 Pin Descriptions Pin Number Name Type 1, 2 DDI/DDI I Digital data inputs (Differential ECL/PECL). 3, 44 VCC_75 I Power supply connection for internal 75Ω pullup resistors connected to DDI/DDI. 4, 8, 13, 22, 35 VCC I Most positive power supply connection. 5, 9, 14, 18, 27, 30, 33, 34, 37 VEE I Most negative power supply connection. 6, 7 SDI/SDI I Differential analog data inputs. 10 CD_ADJ I Carrier detect threshold adjust. 11, 12 AGC-, AGC+ I External AGC capacitor. Vcommon mode = 2.7V typ. 15, 16, 17 LF+, LFS, LF- I Loop filter component connection. 19 RVCO_RTN I RVCO Return. Frequency setting resistor return connection. 20 RVCO I Frequency setting resistor connection. 21 CBG I Internal bandgap voltage filter capacitor. 23, 25, 26 nc - No connect - Do not connect to power or ground. Leave floating. 24 RSV1 I Reserved pin 1. Always set HIGH. 28, 29 SCO/SCO O Serial clock output. SCO/SCO are differential current mode outputs and require external 75Ω pullup resistors. 31, 32 SDO/SDO O Equalized and reclocked serial digital data outputs. SDO/SDO are differential current mode outputs and require external 75Ω pullup resistors. 36 CLK_EN I Clock enable. When HIGH, the serial clock outputs are enabled. 38 COSC I Timing control capacitor for internal system clock. 39 LOCK O Lock indication. When HIGH, the GS7025 is locked. LOCK is an open collector output and requires an external 10kΩ pullup resistor. 40 SSI/CD O Signal strength indicator/Carrier detect. 41 A/D I Analog/Digital select. 42 MOD I 270 Mb/s modulus select - always set HIGH. 43 OEM_TEST O Output ‘Eye’ monitor test. Single-ended current mode output that requires an external 50Ω pullup resistor. This feature is recommended for debugging purposes only. If enabled during normal operation, the maximum operating temperature is rated to 60°C. For maximum cable length performance the OEM_TEST must be disabled. GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 Description 4 of 23 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Value Supply Voltage (VS) 5.5V Input Voltage Range (any input) VCC + 0.5 to VEE - 0.5V Operating Temperature Range 0°C ≤ TA ≤ 70°C Storage Temperature Range -65°C ≤ TS ≤ 150°C Lead Temperature (soldering, 10 sec) 260°C Moisture Sensitivity Level 3 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VCC = 5.0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF Parameter Condition Min Typical1 Max Units 4.75 5 5.25 V 3 CLK_EN = 0 - 115 - mA 9 CLK_EN = 1 - 125 - mA 3 - 2.4 - V 3 VEE+(VDIFF/2) 0.4 to 4.6 VCC-(VDIFF/2) V 200 800 2000 mV 3 - 3 - V 3 - 2.1 - V 3 Supply Voltage Supply Current SDI Common Mode Voltage DDI/DDI Common Mode Input Voltage Range DDI/DDI Differential Input Drive SSI/CD Output Current HIGH, Om Note s 2 Test Level 3 ΙOH = -10µA HIGH, 300m ΙOH = -10µA OEM_TEST Bias Potential 50Ω - 4.75 - V A/D Input Voltage HIGH 2.3 - - V LOW - - 0.8 GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 4 3 3 5 of 23 Table 2-1: DC Electrical Characteristics VCC = 5.0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF Parameter RSV1, IN _ENABLE Input Voltage CLK_EN Input Voltage LOCK Output Low Voltage 1. 2. 3. 4. 5. 6. 7. 8. 9. Min Typical1 Max Units HIGH 2.0 - - V 3 LOW - - 0.8 HIGH 2.5 - - V 3 LOW - - 0.8 0.25 0.4 V 26 55 µA IOL = 500µA CLK_EN Source Current 1. 2. 3. 4. Condition LOW, VIL =0V - Note s 3 Test Level 1 1 NOTES: TYPICAL - measured on characterization board. VDIFF is the differential input signal swing. LOCK is an open collector output and requires an external pullup resistor. If OEM_TEST is permanently enabled, operating temperature range is limited from 0°C to 60°C inclusive. TEST LEVELS: Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. Production test at room temperature and nominal supply voltage. QA sample test. Calculated result based on Level 1,2, or 3. Not tested. Guaranteed by design simulations. Not tested. Based on characterization of nominal parts. Not tested. Based on existing design/characterization data of similar product. Indirect test. 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VCC = 5.0V, VEE = 0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF Parameter Condition Serial Data Rate Maximum Equalizer Gain Min Typical1 Max Units Note s Test Level SDI - 270 (only) - Mb/s 3 @ 135MHz - 35 - dB 6 270Mb/s, 300m (Belden 8281) - 300 - ps p-p 2, 7 9 270Mb/s - 185 - ps p-p 2, 6 4 270Mb/s - 462 - ps p-p 2, 6 3 (see Figure 3) Additive Jitter [Pseudorandom (2 23 -1)] Intrinsic Jitter [Pseudorandom (2 Intrinsic Jitter 23 -1)] [Pathological (SDI checkfield)] GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 6 of 23 Table 2-2: AC Electrical Characteristics VCC = 5.0V, VEE = 0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF Parameter Min Typical1 Max Units Note s Test Level 270Mb/s 0.40 0.56 - UI p-p 3, 6 9 tswitch < 0.5µs, 270Mb/s - 1 - µs 4 7 0.5µs< tswitch <10ms - 1 - ms tswitch > 10 ms - 4 - ms SDO Mute Time 0.5 1 2 µs 5 7 SDO to SCO Synchronization -200 0 200 ps 7 75Ω DC load 600 800 1000 mV p-p 1 20%-80% 200 300 400 ps 7 SDI/SDI Input Resistance - 10 - kΩ 7 6 SDI/SDI Input Capacitance - 1.0 - pF 7 6 Carrier Applied - 3 - µs 7, 8 6 Carrier Removed - 30 - Input Jitter Tolerance Lock Time Synchronous Switch SDO, SCO Output Signal Swing SDO, SCO Rise & Fall Times Carrier Detect Response Time 1. 2. 3. 4. 5. 6. 7. 8. 1. 2. 3. 4. 5. 6. 7. 8. 9. Condition NOTES: TYPICAL - measured on characterization board. Characterized 6 sigma RMS. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz). Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie. line 10 switching for component NTSC). Carrier Loss Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is removed. Using the DDI input, A/D=0. Using the SDI input, A/D=1. Carrier Detect Response Time refers to the response of the SSI/CD output from a logic high to a logic low state when the input signal is removed or amplitude drops below the threshold set by the CD_ADJ pin. SSI/CD pin loading CL<50pF, RL=open cct. TEST LEVELS: Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. Production test at room temperature and nominal supply voltage. QA sample test. Calculated result based on Level 1,2, or 3. Not tested. Guaranteed by design simulations. Not tested. Based on characterization of nominal parts. Not tested. Based on existing design/characterization data of similar product. Indirect test. GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 7 of 23 2.4 Typical Performance Curves (VS = 5V, TA = 25°C unless otherwise shown) BELDEN 8281 CABLE DATA TEKTRONIX GigaBERT 1400 TRANSMITTER GS9028 CABLE DRIVER DATA CHARACTERIZATION BOARD TEKTRONIX GigaBERT 1400 ANALYZER CLOCK TRIGGER Figure 2-1: Test Setup for Figure 2-5 and Figure 2-6 SSI/CD OUTPUT VOLTAGE (V) 5.00 4.50 4.00 3.50 3.00 2.50 0 50 100 150 200 250 300 350 400 450 500 CABLE LENGTH (m) Figure 2-2: SSI/CD Voltage vs. Cable Length (Belden 8281) (CD_ADJ = 0V) 50 45 40 GAIN (dB) 35 30 25 20 15 10 5 0 1 10 100 1000 FREQUENCY (MHz) Figure 2-3: Equalizer Gain vs. Frequency GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 8 of 23 5.0 CD_ADJ VOLTAGE (V) 4.5 4.0 3.5 3.0 2.5 2.0 200 250 300 350 400 CABLE LENGTH (m) Figure 2-4: Carrier Detect Adjust Voltage Threshold Characteristics 450 400 JITTER (ps p-p) 350 (Characterized) 300 250 200 270Mb/s 150 100 50 0 0 50 100 150 200 250 300 350 400 CABLE LENGTH (m) Figure 2-5: Typical Additive Jitter vs. Input Cable Length (Belden 8281)Pseudorandom (223-1) Figure 2-6: Intrinsic Jitter (223 - 1 Pattern) 270Mb/s GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 9 of 23 0.600 0.550 270Mb/s 0.500 IJT (UI) 0.450 0.400 0.350 0.300 0.250 0.200 0 10 20 30 40 50 60 70 TEMPERATURE (C°) Figure 2-7: Typical IJT vs. Temperature (VCC = 5.0V) (Characterized) GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 10 of 23 3. Detailed Description The GS7025 Serial Digital Receiver is a bipolar integrated circuit, containing a built-in cable equalizer and reclocker. Serial digital signals are applied to either the analog SDI/SDI or digital DDI/DDI inputs. Signals applied to the SDI/SDI inputs are equalized and then passed to a multiplexer. Signals applied to the DDI/DDI inputs bypass the equalizer, and go directly to the multiplexer. The analog/digital select pin (A/D) determines which signal is then passed to the reclocker. Packaged in a 44 pin MQFP, the receiver operates from a single 5V supply at a data rate of 270Mb/s. Typical power consumption is 600mW. 3.1 Cable Equalizer The automatic cable equalizer is designed to equalize a serial digital data rate of 270Mb/s. The serial data signal is connected to the input pins (SDI/SDI) either differentially or single-endedly. The input signal passes through a variable gain equalizing stage, whose frequency response closely matches the inverse cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The gain stage provides up to 35dB of gain at 135MHz which typically results in equalization of greater than 350m of Belden 8281 cable at 270Mb/s. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by an external differential AGC filter capacitor (AGC+/AGC-) providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is DC-restored, effectively restoring the logic threshold of the equalized signal to its corrective level irrespective of shifts due to AC-coupling. 3.1.1 Signal Strength Indication/Carrier Detect The GS7025 incorporates an analog Signal Strength Indicator/Carrier Detect (SSI/CD) output indicating both the presence of a carrier and the amount of equalization applied to the signal. The voltage output of this pin versus cable length (signal strength) is shown in Figure 2-2 and Figure 3-1. With 0m of cable (800mV input signal levels), the SSI/CD output voltage is approximately 4.5V. As the cable length increases, the SSI/CD voltage decreases linearly providing accurate correlation between the SSI/CD voltage and cable length. GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 11 of 23 SSI/CD OUTPUT VOLTAGE (V) 5 4 3 CD_ADJ CONTROL RANGE 2 1 0 0 50 100 150 200 250 300 350 400 450 500 CABLE LENGTH (m) Figure 3-1: SSI/CD Voltage vs. Cable Length When the signal strength decreases to the level set at the “Carrier Detect Threshold Adjust” pin, the SSI/CD voltage goes to a logic “0” state (0.8 V) and can be used to drive other TTL/CMOS compatible logic inputs. When loss of carrier is detected, the SDO/SDO outputs are muted (set to a known static state). Additional SSI/CD output source current can be obtained in applications with a pull-up resistor. An external 5kΩ pull-up resistor with less than 50pf capacitor loading is recommended. 3.1.2 Carrier Detect Threshold Adjust Carrier Detect Threshold Adjust is designed applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The GS7025 solves this problem with a user adjustable threshold which meets the unique conditions that exist in each application. Override and internal default settings are provided to give the user total flexibility. The threshold level at which loss of carrier is detected is adjustable via external resistors at the CD_ADJ pin (see Figure 2-4). The control voltage at the CD_ADJ pin is set by a simple resistor divider circuit (see Figure 4-1: GS7025 Typical Application Circuit). The threshold level is adjustable from 200m to 350m. By default (no external resistors), the threshold is typically 320m. In noisy environments, it is not recommended to leave this pin floating. Connecting this pin to VEE disables the SDO/SDO muting function and allows for maximum possible cable length equalization. 3.1.3 Output Eye Monitor Test The GS7025 also provides an 'Output Eye Monitor Test' (OEM_TEST) which allows the verification of signal integrity after equalization, prior to re-slicing. The OEM_TEST pin is an open collector current output that requires an external 50Ω pullup resistor. When the pullup resistor is not used, the OEM_TEST block is disabled and the internal OEM_TEST circuit is powered down. The OEM_TEST provides a 100mVp-p signal when driving a 50Ω oscilloscope input. Due to additional power consumed by this diagnostic circuit, it is not recommended for continuous operation. GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 12 of 23 NOTE: For maximum cable length performance the OEM_TEST block should be disabled. 3.2 Reclocker The reclocker receives a differential serial data stream from the internal multiplexer. It locks an internal clock to the incoming data. It outputs the differential PECL retimed data signal on SDO/SDO. It outputs the recovered clock on SCO/SCO. The timing between the output and clock signals is shown in Figure 3-2. SDO SCO 50% Figure 3-2: Output and Clock Signal Timing The reclocker contains three main functional blocks: the Phase Locked Loop, Frequency Acquisition, and Logic Circuit. 3.2.1 Phase Locked Loop (PLL) The Phase Locked Loop locks the internal PLL clock to the incoming data rate. A simplified block diagram of the PLL is shown in Figure 3-3 below. The main components are the VCO, the phase detector, the charge pump, and the loop filter. DDI/DDI 2 PHASE DETECTOR INTERNAL PLL CLOCK CHARGE PUMP LFS LF+ RLF CLF1 VCO LF- RVCO LOOP FILTER CLF2 Figure 3-3: Simplified Block Diagram of the PLL GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 13 of 23 3.2.1.1 VCO The VCO is a differential low phase noise, factory trimmed oscillator that provides increased immunity to PCB noise and precise control of the VCO centre frequency. The VCO has a pull range of ±15% about the centre frequency. A single low-impedance external resistor, RVCO, sets the VCO centre frequency. The low-impedance RVCO minimizes thermal noise and reduces the PLL's sensitivity to PCB noise. The recommended RVCO value for SMPTE 259M-C applications is 365Ω. When the input data stream is removed for an excessive period of time (see AC electrical characteristics table), the VCO frequency can drift from the 270Mb/s centre frequency to the limits shown in Table 3-1. Table 3-1: Frequency Drift Range Frequency Min (%) Max(%) 270Mb/s lock -13 28 3.2.1.2 Phase Detector The phase detector compares the phase of the PLL clock with the phase of the incoming data signal and generates error correcting timing pulses. The phase detector design provides a linear transfer function which maximizes the input jitter tolerance of the PLL. 3.2.1.3 Charge Pump The charge pump takes the phase detector output timing pulses and creates a charge packet that is proportional to the system phase error. A unique differential charge pump design insures that the output phase does not drift when data transitions are sparse. This makes the GS7025 ideal for SMPTE 259M-C applications where pathological signals have data transition densities of 0.05. 3.2.1.4 Loop Filter The loop filter integrates the charge pump packets and produces a VCO control voltage. The loop filter is comprised of three external components which are connected to pins LF+, LFS, and LF-. The loop filter design is fully differential giving the GS7025 increased immunity to PCB board noise. The loop filter components are critical in determining the loop bandwidth and damping of the PLL. Recommended values for SMPTE 259M-C applications are shown in the GS7025 Typical Application Circuit. No further changes from the recommended GS7025 loop filter components are necessary. For more information on choosing loop filter component values, refer to the PLL DESIGN GUIDELINES section of the GS9025A data sheet. GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 14 of 23 3.2.2 Frequency Acquisition The core PLL is able to lock if the incoming data rate and the PLL clock frequency are within the PLL capture range (which is slightly larger than the loop bandwidth). To assist the PLL to lock, the GS7025 uses a frequency acquisition circuit. The frequency acquisition circuit sweeps the VCO control voltage so that the VCO frequency changes from -10% to +10% of the centre frequency. Figure 3-4 shows a typical sweep waveform. tsys tswp VLF A Tcycle Tcycle = tswp + tsys Figure 3-4: Typical Sweep Waveform The VCO frequency starts at point A and sweeps up attempting to lock. If lock is not established during the up sweep, the VCO is then swept down. The probability of locking within one cycle period is greater than 0.999. If the system does not lock within one cycle period, it attempts to lock in the subsequent cycle. The average sweep time, (tswp) is determined by the loop filter component (CLF1) and the charge pump current (ICP): 4CLF1 t SWP = ------------3I CP The nominal sweep time is approximately 121μs when CLF1 = 15nF and ICP = 165μA (RVCO = 365Ω). An internal system clock determines tsys (see Section 3.2.3 Logic Circuit). 3.2.3 Logic Circuit The GS7025 is controlled by a finite state logic circuit which is clocked by an asynchronous system clock. That is, the system clock is completely independent of the incoming data rate. The system clock runs at low frequencies, relative to the incoming data rate, and thus reduces interference to the PLL.The period of the system clock is set by the COSC capacitor and is: 4 t sys = 9.6 × 10 × C OSC [ seconds ] The recommended value for tsys is 450μs (COSC = 4.7nF) GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 15 of 23 3.2.4 Locking The GS7025 indicates valid lock when the following three conditions are satisfied: 1. Input data is detected. 2. The incoming data signal and the PLL clock are phase locked. 3. The system is not locked to an integer-multiple harmonic of a 270Mb/s SMPTE 259M-C signal. The GS7025 defines the presence of input data when at least one data transition occurs every 1μs. The GS7025 assumes that it is NOT locked to a harmonic if the pattern ‘101’ or ‘010’ (in the reclocked data stream) occurs at least once every tsys/3 seconds. Using the recommended component values, this corresponds to approximately 150μs. In a harmonically locked system, all bit cells are double clocked and the above patterns become ‘110011’ and ‘001100’, respectively. 3.2.4.1 Lock Time Synchronous switching refers to the case where the input data is changed from one source to another source which is at the same data rate (but different phase). When input data to the GS7025 is removed, the GS7025 latches the current state. Therefore, when data is reapplied, the GS7025 begins the lock procedure at the previous locked data rate. As a result, in synchronous switching applications, the GS7025 locks very quickly. The nominal lock time depends on the switching time and is summarized in Table 3-2. Table 3-2: Lock Time Switching Time Lock Time <0.5µs 10µs 0.5µs - 10ms 2tsys >10ms 2Tcycle + 2tsys To acquire lock, the frequency acquisition circuit may have to sweep over an entire cycle depending on initial conditions. Maximum lock time is 2Tcycle + 2tsys. The nominal value of Tcycle for the GS7025 operating in a typical SMPTE 259M-C application is approximately 1.3ms. The GS7025 has a dedicated LOCK output (pin 39) indicating when the device is locked. Note: In synchronous switching applications where the switching time is less than 0.5μs, the LOCK output is not de-asserted and the data outputs are not muted. 3.2.4.2 DVB-ASI Design Note: For DVB-ASI applications having significant instances of few bit transitions or when only K28.5 idle bits are transmitted, the wide-band PLL in the GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 16 of 23 GS7025 may lock at 243MHz being the first 27MHz sideband below 270MHz. In this case, when normal bit density signals are transmitted, the PLL will correctly lock onto the proper 270MHz carrier. 3.2.5 Output Data Muting The GS7025 internally mutes the SDO and SDO outputs when the device is not locked. When muted, SDO/SDO are latched providing a logic state to the subsequent circuit and avoiding a condition where noise could be amplified and appear as data. The output data muting timing is shown in Figure 3-5. NO DATA TRANSITIONS DDI LOCK SDO VALID DATA OUTPUTS MUTED VALID DATA Figure 3-5: Output Data Muting Timing 3.2.6 Clock Enable When CLK_EN is HIGH, the GS7025 SCO/SCO outputs are enabled. When CLK_EN is LOW, the SCO/SCO outputs are placed in a high-impedance state and float to VCC. Disabling the clock outputs results in a power savings of 10%. It is recommended that the CLK_EN input be hard wired to the desired state. For applications which do not require the clock output, connect CLK_EN to Ground and connect the SCO/SCO outputs to VCC. 3.2.7 Stressful Data Patterns All PLL's are susceptible to stressful data patterns which can introduce bit errors in the data stream. PLL's are most sensitive to patterns which have long run lengths of 0's or 1's (low data transition densities for a long period of time). The GS7025 is designed to operate with low data transition densities such as the SMPTE 259M-C pathological signal (data transition density = 0.05). 3.3 I/O Description 3.3.1 High Speed Analog Inputs (SDI/SDI) SDI/SDI are high-impedance inputs which accept differential or single-ended input drive. Figure 3-6 shows the recommended interface when a single-ended serial digital signal is used. GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 17 of 23 75 10nF 113 10nF SDI 75 GS7025 SDI Figure 3-6: High Speed Digital Inputs (DDI/DDI) DDI/DDI are high-impedance inputs which accept differential or single-ended input drive. Two conditions must be observed when interfacing to these inputs: 1. Input signal amplitudes are between 200 and 2000mV. 2. The common mode input voltage range is as specified in Table 2-1: DC Electrical Characteristics. Commonly used interface examples are shown in Figure 3-7, Figure 3-8 & Figure 3-9. Figure 3-7 illustrates the simplest interface to the GS7025 digital inputs. In this example, the driving device generates the PECL level signals (800mV amplitudes) having a common mode input range between 0.4 and 4.6V. This scheme is recommended when the trace lengths are less than 1in. The value of the resistors depends on the output driver circuitry. DDI ZO GS7025 DDI Figure 3-7: Digital Inputs - simple interface When trace lengths become greater than 1in, controlled impedance traces should be used. The recommended interface is shown in Figure 3-8. In this case, a parallel resistor (RLOAD) is placed near the GS7025 inputs to terminate the controlled impedance trace. The value of RLOAD should be twice the value of the characteristic impedance of the trace. In addition, place series resistors (RSOURCE) near the driving chip to serve as source terminations. They should be equal to the value of the trace impedance. Assuming 800mV output swings at the driver, RLOAD = 100Ω, RSOURCE = 50Ω and ZO = 50Ω. DDI DDI GS7025 Figure 3-8: Digital Inputs - controlled impedance interface Figure 3-9 shows the recommended interface when the GS7025 digital inputs are driven single-endedly. In this case, the input must be AC-coupled and a matching resistor (Zo) must be used. GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 18 of 23 RSOURCE ZO DDI RLOAD RSOURCE GS7025 DDI ZO Figure 3-9: Digital Inputs - single-ended input interface When the DDI and the DDI inputs are not used, saturate one input of the differential amplifier for improved noise immunity. To saturate, connect either pins 44 and 1 or pins 2 and 3 to VCC. Leave the other pair floating. 3.3.2 High Speed Outputs (SDO/SDO and SCO/SCO) SDO/SDO and SCO/SCO are current mode outputs that require external pullup resistors (see Figure 3-10). To calculate the output sink current, use the following relationship: Output Sink Current = Output Signal Swing / Pullup Resistor A diode can be placed between Vcc and the pullup resistors to reduce the common mode voltage by approximately 0.7V. When the output traces are longer than 1in, controlled impedance traces should be used. The pullup resistors should be placed at the end of the output traces as they terminate the trace in its characteristic impedance (75Ω). VCC GS7025 75 75 75 75 SDO SDO SCO SCO VCC Figure 3-10: High-speed Outputs with External Pullups GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 19 of 23 4. Application Information 4.1 Typical Application Circuit VCC 10k VCC VCC VCC VCC VCC VCC 41 40 39 38 37 36 35 34 OEM_TEST MOD A/D SSI/CD LOCK COSC VEE CLK_EN VCC VEE SDO 32 VCC 3 VCC_75 SDO 31 VCC 4 VCC 5 VEE 6 SDI SCO 28 7 SDI VEE 27 10n VCC nc 26 9 VEE nc 25 10 CD_ADJ 11 AGC- 15 16 17 18 All resistors in ohms, all capacitors in microfarads, unless otherwise stated. 100p VCC 1.8k 15n 19 VCC VEE 14 CBG LF- 13 20 21 22 365 (1%) VCC nc 23 RVCO LFS 12 RVCO_RTN LF+ 270 24 VEE 8 VCC 100k Pot (Optional) SCO 29 AGC+ 75 10n VCC To GS9020 VEE 30 GS7025 TOP VIEW VCC 4 x 75 see Note 2 33 DDI 75 Power supply decoupling capacitors are not shown. VEE 2 75 VCC 42 DDI see Note 1 37.5 43 1 from GS9024 15nH 44 VCC_75 4n7 VCC 0.1µ 0.1µ 3.3p NOTES 1. It is recommended that the DDI/DDI input are not driven when the SDI/SDI inputs are being used. This minimizes crosstalk between the DDI/DDI and SDI/SDI inputs and maximizes performance. 2. These resistors are not needed if the internal pull-up resistors on the GS9020 are used. 3. It is recommended that for new designs VCO components should be returned to the RVCO_RTN pin for improved ground bounce immunity. Figure 4-1: GS7025 Typical Application Circuit GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 20 of 23 5. Package & Ordering Information 5.1 Package Dimensions 13.20 ±0.25 10.00 ±0.10 10.00 ±0.10 13.20 ±0.25 PIN 1 0.80 BSC 0.45 MAX 0.30 MIN 5° to 16° 0.20 MIN 0° MIN 2.20 MAX 1.85 MIN 7° MAX 0° MIN 2.55 MAX 0.23 MAX. 0.35 MAX 0.15 MIN All dimensions in millimetres 44 pin MQFP GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 0.3 MAX. RADIUS 5° to 16° 0.88 NOM. 0.13 MIN. RADIUS 1.60 REF 21 of 23 5.2 Solder Reflow Profiles The GS7025 is available in a Pb-free package. It is recommended that the Pb-free package be soldered with Pb-free paste using the reflow profile shown in Figure 5-1. Temperature 60-150 sec. 20-40 sec. 260°C 250°C 3°C/sec max 217°C 6°C/sec max 200°C 150°C 25°C Time 60-180 sec. max 8 min. max Figure 5-1: Maximum Pb-free Solder Reflow Profile 5.3 Ordering Information GS7025 Part Number Package Temperature Range GS7025-CQME3 44 pin MQFP Tray 0°C to 70°C GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 22 of 23 DOCUMENT IDENTIFICATION CAUTION DATA SHEET ELECTROSTATIC SENSITIVE DEVICES The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION GENNUM CORPORATE HEADQUARTERS Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055 4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada E-mail: [email protected] www.gennum.com OTTAWA SNOWBUSH IP - A DIVISION OF GENNUM GERMANY 232 Herzberg Road, Suite 101 Kanata, Ontario K2K 2A1 Canada 439 University Ave. Suite 1700 Toronto, Ontario M5G 1Y8 Canada Hainbuchenstraße 2 80935 Muenchen (Munich), Germany Phone: +49-89-35831696 Phone: +1 (613) 270-0458 Phone: +1 (416) 925-5643 Fax: +49-89-35804653 Fax: +1 (613) 270-0429 Fax: +1 (416) 925-0581 E-mail: [email protected] CALGARY E-mail: [email protected] 3553 - 31st St. N.W., Suite 210 Calgary, Alberta T2L 2K7 Canada Web Site: http://www.snowbush.com Phone: +1 (403) 284-2672 UNITED KINGDOM North Building, Walden Court Parsonage Lane, Bishop’s Stortford Hertfordshire, CM23 5DB United Kingdom MEXICO 288-A Paseo de Maravillas Jesus Ma., Aguascalientes Mexico 20900 NORTH AMERICA WESTERN REGION 691 South Milpitas Blvd., Suite #200 Milpitas, CA 95035 United States Phone: +1 (408) 934-1301 Fax: +1 (408) 934-1029 Phone: +1 (416) 848-0328 E-mail: [email protected] JAPAN KK NORTH AMERICA EASTERN REGION Fax: +44 1279 714171 Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo, 160-0023 Japan INDIA Phone: +81 (03) 3349-5501 #208(A), Nirmala Plaza, Airport Road, Forest Park Square Bhubaneswar 751009 India Fax: +81 (03) 3349-5505 Web Site: http://www.gennum.co.jp KOREA Phone: +91 (674) 653-4815 TAIWAN Fax: +91 (674) 259-5733 6F-4, No.51, Sec.2, Keelung Rd. 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All rights reserved. www.gennum.com GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 23 of 23 23