TI TMS470R1VF288

TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
O
High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
– 24-MHz System Clock (48-MHz Pipeline)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– Three Inter-Integrated Circuit (I2C) Modules
– Multi-Master and Slave Interfaces
– Up to 400 Kbps (Fast Mode)
– 7- and 10-Bit Address Capability
O
High-End Timer Lite (HET)
– 12 Programmable I/O Channels:
– 12 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 64-Instruction Capacity
O
Operating Features
– Low-Power Modes: STANDBY and HALT
– Industrial/Automotive Temperature Ranges
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
O
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Digital Watchdog (DWD) Timer
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– Interrupt Expansion Module (IEM)
– System Integrity and Failure Detection
– ICE Breaker
12-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 μs Minimum Sample/Conversion Time
– Calibration Mode and Self-Test Features
O
Flexible Interrupt Handling
Expansion Bus Module (EBM) (PGE only)
– Supports 8- and 16-Bit Expansion Bus
Memory Interface Mappings
– 42 I/O Expansion Bus Pins
O
Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
O
50 Dedicated General-Purpose I/O (GIO) Pins
and 43 Additional Peripheral I/Os (PGE)
O
Frequency-Modulated Zero-Pin Phase-Locked
Loop (FMZPLL)-Based Clock Module With
Prescaler
– Multiply-by-8 Internal FMZPLL Option
– ZPLL Bypass Mode
O
14 Dedicated General-Purpose I/O (GIO) Pins
and 43 Additional Peripheral I/Os (PZ)
O
Sixteen External Interrupts
Compatible ROM Device (Planned)
On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1(1) (JTAG) Test-Access
Port
O
O
O
O
Integrated Memory
– 288K-Byte Program Flash
– Two Banks With 8 Contiguous Sectors
– 16K-Byte Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
O
O
Ten Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Two Serial Communication Interfaces (SCIs)
– 224 Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
– Two Standard CAN Controllers (SCC)
– 16-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
– Class II Serial Interface B (C2SIb)
– Normal 10.4 Kbps and 4X Mode 41.6 Kbps
O
PRODUCT PREVIEW
O
O
144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
O
100-Pin Plastic Low-Profile Quad Flatpack
(PZ Suffix)
O
Development System Support Tools Available
– Code Composer Studio™ Integrated
Development Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
1 The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
Copyright © 2005, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic
data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue
these products without notice.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
1
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
74
73
75
78
77
76
82
81
80
79
85
84
83
86
94
93
92
91
90
89
88
87
95
97
96
99
98
100
102
101
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
57
56
55
54
53
52
51
50
131
49
48
47
46
45
44
43
42
41
40
39
38
37
132
133
134
135
136
137
138
139
140
141
142
36
34
35
32
33
30
31
24
25
26
27
28
29
22
23
21
SPI1SCS
SPI1ENA
GIOG[4]
SPI1CLK
SPI1SIMO
GIOG[3]
SPI1SOMI
GIOG[2]
HET[6]
GIOG[1]
HET[7]
HET[8]
VCC
VSS
HET[18]
TMS2
TMS
HET[20]
HET[22]
GIOG[0]
C2SILPN
C2SIRX
GIOD[5]
C2SITX
VCCIO
VSSIO
GIOD[4]
I2C3SCL
I2C3SDA
GIOD[3]
VCC
OSCOUT
OSCIN
VSS
GIOD[2]
AWD
18
19
20
143
144
1
PRODUCT PREVIEW
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
GIOC[4]
GIOC[3]
RST
VSS
VCC
TEST
GIOH[5]/INT[13]
GIOC[2]
GIOA[4]/INT[4]
GIOC[1]
VSS
VCC
VCCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
GIOC[0]
GIOA[0]/INT[1]/ECLK
VCCIO
VSSIO
GIOH[0]/INT[8]
GIOG[7]
GIOA[0]/INT0
GIOG[6]
GIOG[5]
TRST
71
70
69
68
67
66
65
64
63
62
61
60
59
58
16
17
ADIN[3]
72
109
110
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADREFHI
ADREFLO
VCCAD
VSSAD
ADIN[4]
106
105
104
103
108
107
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
GIOF[7]
GIOF[6]
GIOA[5]/INT[5]
PLLDIS
GIOF[5]
I2C2SCL
I2C2SDA
GIOF[4]
VCC
VSS
GIOF[3]
GIOF[2]
I2C1SCL
I2C1SDA
VCCIO
VSSIO
CAN1STX
CAN1SRX
GIOF[1]
CLKOUT
GIOF[0]
GIOA[7]/INT[7]
GIOA[6]/INT[6]
GIOE[7]
TCK
TDO
TDI
HET[0]
TMS470R1VF288 144-PIN PGE PACKAGE (TOP VIEW) (without Expansion Bus)
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
HET[1]
HET[2]
GIOE[6]
VCCIO
VSSIO
GIOE[5]
HET[3]
HET[4]
GIOE[4]
HET[5]
SPI2SCS
GIOE[3]
SPI2ENA
SPI2SIMO
GIOE[2]
SPI2SOMI
SPI2CLK
CAN2STX
CAN2SRX
VCC
VSS
SCI2CLK
SCI2RX
SCI2TX
SCI1CLK
GIOE[1]
SCI1RX
SCI1TX
GIOE[0]
GIOB[0]
GIOD[0]
GIOH[1]/INT[9]
GIOH[2]/INT[10]
GIOD[1]
GIOH[3]/INT[11]
GIOH[4]/INT[12]
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
109
110
EBADDR[22]/EBADDR[14]
GIOA[0]/INT[0]
139
140
141
EBADDR[20]/EBADDR[12]
142
EBADDR[19]/EBADDR[11]
143
144
74
73
75
78
77
76
82
81
80
79
85
84
83
86
94
93
92
91
90
89
88
87
95
97
96
99
98
100
102
101
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
57
56
55
54
53
52
51
50
131
49
48
47
46
45
44
43
42
41
40
39
38
37
132
133
134
HET[1]
HET[2]
EBDATA[6]
VCCIO
VSSIO
EBDATA[5]
HET[3]
HET[4]
EBDATA[4]
HET[5]
SPI2SCS
EBDATA[3]
SPI2ENA
SPI2SIMO
EBDATA[2]
SPI2SOMI
SPI2CLK
CAN2STX
CAN2SRX
VCC
VSS
SCI2CLK
SCI2RX
SCI2TX
SCI1CLK
EBDATA[1]
SCI1RX
SCI1TX
EBDATA[0]
DMAREQ[0]
EBADDR[0]
EBADDR[23]/EBADDR[15]
EBADDR[24]/EBADDR[16]
EBADDR[1]
EBADDR[25]/EBADDR[17]
EBADDR[26]/EBADDR[18]
36
34
35
32
33
30
31
26
27
28
29
24
25
22
23
21
18
19
20
16
17
8
9
10
11
12
13
14
15
2
3
4
5
6
7
135
136
137
138
1
TRST
71
70
69
68
67
66
65
64
63
62
61
60
59
58
SPI1SCS
SPI1ENA
EBADDR[18]/EBADDR[10]
SPI1CLK
SPI1SIMO
EBADDR[17]/EBADDR[9]
SPI1SOMI
EBADDR[16]/EBADDR[8]
HET[6]
EBADDR[15]/EBADDR[7]
HET[7]
HET[8]
VCC
VSS
HET[18]
TMS2
TMS
HET[20]
HET[22]
EBADDR[14]/EBADDR[6]
C2SILPN
C2SIRX
EBADDR[5]
C2SITX
VCCIO
VSSIO
EBADDR[4]
I2C3SCL
I2C3SDA
EBADDR[3]
VCC
OSCOUT
OSCIN
VSS
EBADDR[2]
AWD
EBADDR[21]/EBADDR[13]
72
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
3
PRODUCT PREVIEW
ADREFHI
ADREFLO
VCCAD
VSSAD
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
EBCS[6]
EBCS[5]
RST
VSS
VCC
TEST
EBHOLD
EBWR[1]
GIOA[4]/INT[4]
EBWR[0]
VSS
VCC
VCCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
EBOE
GIOA[0]/INT1/ECLK
VCCIO
VSSIO
106
105
104
103
108
107
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
EBDAAR[13]/EBDATA[15]
EBADDR[12]/EBDATA[14]
GIOA[5]/INT[5]
PLLDIS
EBADDR[11]/EBDATA[13]
I2C2SCL
I2C2SDA
EBADDR[10]/EBDATA[12]
VCC
VSS
EBADDR[9]/EBDATA[11]
EBADDR[8]/EBDATA[10]
I2C1SCL
I2C1SDA
VCCIO
VSSIO
CAN1STX
CAN1SRX
EBADDR[7]/EBDATA[9]
CLKOUT
EBADDR[6]/EBDATA[8]
GIOA[7]/INT[7]
GIOA[6]/INT[6]
EBDATA[7]
TCK
TDO
TDI
HET[0]
TMS470R1VF288 144-PIN PGE PACKAGE (TOP VIEW) (with Expansion Bus)
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
TDI
HET[0]
TDO
TCK
GIOA[6]/INT[6]
CLKOUT
GIOA[7]/INT[7]
CAN1SRX
I2C1SDA
CAN1STX
VSS
I2C1SCL
I2C2SDA
VCC
I2C2SCL
PLLDIS
ADEVT
GIOA[5]/INT[5]
ADIN[11]
ADIN[10]
ADIN[9]
ADIN[8]
ADIN[7]
ADIN[6]
ADIN[5]
TMS470R1VF288 100-PIN PZ PACKAGE (TOP VIEW)
VCCIO
VSSAD
79
47
VSSIO
ADIN[4]
80
46
HET[3]
ADIN[3]
ADIN[2]
81
45
HET[4]
82
44
HET[5]
ADIN[1]
83
43
SPI2SCS
ADIN[0]
84
42
SPI2ENA
PORRST
85
41
SPI2SIMO
RST
86
40
SPI2SOMI
TEST
87
39
SPI2CLK
GIOH[5]/INT[13]
88
38
CAN2STX
GIOA[4]/INT[4]
89
37
CAN2SRX
VSS
90
36
SCI2CLK
VCC
91
35
SCI2RX
VCCP
92
34
SCI2TX
FLTP2
93
33
SCI1CLK
GIOA[3]/INT[3]
94
32
SCI1RX
GIOA[2]/INT[2]
95
31
SCI1TX
GIOA[1]/INT[1]/ECLK
96
30
GIOB[0]
VCCIO
97
29
GIOH[1]/INT[9]
VSSIO
98
28
GIOH[2]/INT[10]
GIOA[0]/INT[0]
99
27
GIOH[3]/INT[11]
100
26
GIOH[4]/INT[12]
4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
AWD
VSS
OSCIN
VCC
OSCOUT
I2C3SDA
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSSIO
9
I2C3SCL
8
VCCIO
7
C2SITX
6
C2SIRX
5
C2SILPN
4
HET[22]
3
HET[20]
2
TMS
1
TMS2
TRST
HET[18]
48
HET[8]
78
HET[7]
HET[2]
VCCAD
HET[6]
ADREFLO
SPI1SOMI
HET[1]
49
SPI1SIMO
50
77
SPI1CKL
76
SPI1SCS
ADREFHI
SPI1ENA
PRODUCT PREVIEW
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
description
The TMS470R1VF288(1) devices are members of the Texas Instruments TMS470R1x family of generalpurpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The VF288 microcontroller offers
high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting
in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU
views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VF288 utilizes the
big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining
low costs. The VF288 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The VF288 devices contain the following:
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
ARM7TDMI 16/32-Bit RISC CPU
TMS470R1x system module (SYS) with 470+ enhancements
288K-byte flash
16K-byte SRAM
Frequency-modulated zero-pin phase-locked loop (FMZPLL) clock module
Digital watchdog (DWD) timer
Analog watchdog (AWD) timer
Enhanced real-time interrupt (RTI) module
Interrupt expansion module (IEM)
Memory security module (MSM)
JTAG security module
Two serial peripheral interface (SPI) modules
Two serial communications interface (SCI) modules
Two standard CAN controllers (SCC)
Three inter-integrated circuit (I2C) modules
Class II Serial Interface B (C2SIb) module
10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
High-end timer lite (HET) controlling 12 I/Os
External Clock Prescale (ECP)
Expansion Bus Module (EBM)
Up to 93 I/O pins (PGE only), up to 57 I/O (PZ only)
PRODUCT PREVIEW
O
The functions performed by the 470+ system module (SYS) include:
Address decoding
O
Memory protection
O
Memory and peripherals bus supervision
O
Reset and abort exception management
O
Prioritization for all internal interrupt sources
O
Device clock control
O
Parallel signature analysis (PSA)
O
The enhanced real-time interrupt (RTI) module on the VF288 has the option to be driven by the oscillator clock.
The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the
watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral
select assignment, interrupt priority, and a device memory map. For a more detailed functional description of
the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).
1 Throughout the remainder of this document, the TMS470R1VF288 shall be referred to as either the full device name or VF288.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
5
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
description (continued)
The VF288 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. When
in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. For more detailed information
on the flash, see the flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature
number SPNU213).
The memory security module (MSM) and JTAG security module prevent unauthorized access and visibility to
on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code. For more information, see the TMS470R1x Memory Security Module Reference Guide (literature number SPNU246) and the
TMS470R1x JTAG Security Module Reference Guide (literature number SPNU245).
PRODUCT PREVIEW
The VF288 device has ten communication interfaces: two SPIs, two SCIs, two SCCs, a C2SI, and three I2Cs.
The SPI provides a convenient method of serial interaction for high-speed communications between similar
shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC
uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with
robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating
in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIb allows the VF68x to transmit and receive messages on a class II network
following an SAE Standard J1850 Class B Data Communication Network Interface standard. The I2C module
is a multi-master communication module providing an interface between the VF288 microcontroller and an I2Ccompatible device via the I2C serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more
detailed functional information on the SPI, SCI, and CAN peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197). For more detailed functional information on the I2C, see
the TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223). For more detailed
functional information on the C2SI, see the TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide
(literature number SPNU214).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and
an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well
suited for applications requiring multiple sensor information and drive actuators with complex and accurate
time pulses. The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a
standard HET. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199). The VF288 HET peripheral contains the XOR-share feature.
This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to
output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see
the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).
The VF288 device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be
converted individually or can be grouped by software for sequential conversion sequences. There are three
separate groupings, two of which can be triggered by an external event. Each sequence can be converted once
when triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
description (continued)
The frequency-modulated zero-pin phase-locked loop (FMZPLL) clock module contains a phase-locked loop,
a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the
FMZPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMZPLL
provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK),
real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other VF288
device modules. For more detailed functional information on the FMZPLL, see the TMS470R1x FrequencyModulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide (literature number SPNU221).
NOTE
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system
clock from an external resonator/crystal reference.
The VF288 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
7
PRODUCT PREVIEW
The expansion bus module (EBM) is a standalone module that supports the multiplexing of the GIO functions
and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module
(EBM) Reference Guide (literature number SPNU222).
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
device characteristics
The VF288 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1 identifies all
the characteristics of the VF288 device except the SYSTEM and CPU, which are generic.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470R1VF288
COMMENTS FOR VF288
MEMORY
For the number of memory selects on this device, see the TMS470VF288 Memory Selection Assignment table (Table 2).
Pipeline/Non-Pipeline
Flash is pipeline-capable
INTERNAL
MEMORY
288K-Byte Flash
16K-Byte SRAM
Memory Security Module (MSM)
JTAG Security Module
The VF288 RAM is implemented in one 16K array selected by two
memory-select signals (see the TMS470R1VF288 Memory Selection
Assignment table, Table 2).
PERIPHERALS
PRODUCT PREVIEW
For the device-specific interrupt priority configurations, see the Interrupt Priority Table (Table 5). And for the 1K peripheral address ranges and
their peripheral selects, see the VF288 Peripherals, System Module, and Flash Base Addresses table (Table 3).
CLOCK
FMZPLL
Expansion Bus
EBM
GENERAL-PURPOSE
I/Os
50 I/O (PGE Suffix)
14 I/O (PZ Suffix)
Frequency-modulated zero-pin PLL has no external loop filter pins.
Expansion bus module with 42 pins. Supports 8- and 16-bit memories.
See Table 6 for details.
In the PGE package, Port A has eight (8) external pins, Port B has only
one (1) external pin, Port C has five (5) external pins, Port D has six (6)
external pins, Ports E, F, and G each have eight (8) external pins, and
Port H has six (6) external pins.
In the PZ package, Port A has eight (8) external pins, Port B has only
one (1) external pin, and Port H has five (5) external pins.
8
ECP
YES
SCI
2 (3-pin)
CAN
(HECC and/or SCC)
2 SCC
SPI
(5-pin, 4-pin or 3-pin)
2 (5-pin)
C2SIb
1
I2C
3
HET with
XOR Share
12 I/O
HET RAM
64-Instruction Capacity
MibADC
10-bit, 12-channel
64-word FIFO
CORE VOLTAGE
1.8 V
I/O VOLTAGE
3.3 V
PINS
144
100
PACKAGES
PGE
PZ
POST OFFICE BOX 1443
Two standard CAN controllers
The high-resolution (HR) SHARE feature allows even-numbered HR
pins to share the next higher odd-numbered HR pin structures. This HR
sharing is independent of whether or not the odd pin is available
externally. If an odd pin is available externally and shared, then the odd
pin can only be used as a general-purpose I/O. For more information on
HR SHARE, see theTMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
Both the logic and registers for a full 16-channel MibADC are present.
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
functional block diagram
External Pins
FLTP2
FLASH
(288K Bytes)
2 Banks
8 Sectors
OSCIN
Memory
Security
Module
(MSM)
RAM
(16K Bytes)
FMZPLL
OSCOUT
Crystal
VCCP
External Pins
PLLDIS
ADIN[11:0]
CPU Address/Data Bus
MibADC
64-Word
FIFO
TMS470R1x CPU
TCK
VSSAD
TDI
TDO
TMS2
DMA Controller
16 Channels
AWD
Interrupt Expansion
Module (IEM)
TEST
Digital
Watchdog
(DWD)
PORRST
CLKOUT
Analog
Watchdog
(AWD)
HET
64 Words
Expansion Address/Data Bus
TMS470R1x SYSTEM MODULE
with Enhanced RTI Module(A)
RST
ADREFLO
VCCAD
ICE Breaker
TMS
ADREFHI
SCC1
HET [0:8;18,20,22]
CAN1TX
PRODUCT PREVIEW
TRST
ADEVT
CAN1RX
SCC2
CAN2TX
CAN2RX
SCI1CLK
SCI1
SCI1TX
SCI1RX
SCI2CLK
SCI2
SCI2TX
SCI2RX
HECC
I2C3
I2C3SDA
I2C3SCL
I2C2
I2C2SDA
I2C2SCL
C2SI
SPI2
SPI1
ECP
GIO/EBM(B)
I2C1
I2C1SDA
A.
B.
GIOA[0]/INT[0]
GIOA[7:2]/INT[7:2]
GIOB[0]
GIOC[4:0](B)
GIOD[5:0](B)
GIOE[7:0](B)
GIOF[7:0](B)
GIOG[7:0](B)
GIOH[5:0/INT[13:8](B)
GIOA[1]/INT[1]/ECLK
C2SITX
C2SIRX
C2SILPN
SPI2SCS
SPI2ENA
SPI2SIMO
SPI2SOMI
SPI2CLK
SPI1SCS
SPI1ENA
SPI1SIMO
SPI1SOMI
SPI1CLK
I2C1SCL
The Enhanced RTI module is the System Module with two extra bits to disable the FMZPLL while in STANDBY mode.
GIOC[4:0], GIOD[5:0], GIOE[5:0], GIOF[7:0], and GIOH[0], which are muxed with EBM, are not available on the PZ package. See Table
6 for EBM to GIO mapping.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
9
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
Terminal Functions
TERMINAL
NAME
PZ
PGE
HET[0]
51
73
HET[1]
50
72
HET[2]
49
71
HET[3]
46
66
HET[4]
45
65
HET[5]
44
63
HET[6]
6
9
HET[7]
7
11
INPUT
VOLT-
OUTPUT
CUR-
AGE(1)(2)
RENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
PRODUCT PREVIEW
HIGH-END TIMER (HET)
Timer input capture or output compare. The HET[8:0,18,20,22]
applicable pins can be programmed as general-purpose input/
output (GIO) pins. All are high-resolution pins.
3.3-V
The high-resolution (HR) SHARE feature allows even HR pins to
share the next higher odd HR pin structures. This HR sharing is
independent of whether or not the odd pin is available externally.
If an odd pin is available externally and shared, then the odd pin
can only be used as a general-purpose I/O. For more information
on HR SHARE, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
2mA -z
HET[8]
8
12
HET[18]
9
15
HET[20]
12
18
HET[22]
13
19
CAN1SRX
58
83
5V tolerant
4mA
CAN1STX
59
84
3.3-V
2mA -z
SCC1 transmit pin or GIO pin
CAN2SRX
37
54
5V tolerant
4mA
SCC2 receive pin or GIO pin
CAN2STX
38
55
3.3-V
STANDARD CAN CONTROLLER (SCC)
SCC1 receive pin or GIO pin
2mA -z
SCC 2 transmit pin or GIO pin
CLASS II SERIAL INTERFACE (C2SIB)
C2SIbLPN
14
21
3.3-V
2mA -z
C2SIb module loopback enable pin or GIO pin
C2SIbRX
15
22
5V tolerant
4mA
C2SIb module receive data input pin or GIO pin
C2SIbTX
16
24
3.3-V
2mA -z
C2SIb module transmit data output pin or GIO pin
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/INT[0]
99
141
GIOA[1]/INT[1]/
ECLK
96
136
GIOA[2]/INT[2]
95
134
GIOA[3]/INT[3]
94
133
GIOA[4]/INT[4]
89
127
GIOA[5]/INT[5]
67
98
GIOA[6]/INT[6]
55
78
GIOA[7]/INT[7]
56
79
GIOB[0]/
EBDMAREQ[0]
30
43
GIOC[0]/EBOE
–
135
GIOC[1]/EBWR[0]
–
128
GIOC[2]/EBWR[1]
–
126
GIOC[3]/EBCS[5]
–
120
GIOC[4]/EBCS[6]
–
119
General-purpose input/output pins. GIOA[7:0]/INT[7:0] are
interrupt-capable pins.
5V tolerant
3.3-V
4mA
2mA -z
GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clockout function of the external clock prescale (ECP) module.
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0],
GIOG[7:0], AND GIOH[5:0] are multiplexed with the expansion
IPD (20 μA) bus module.
See Table 6.
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
Terminal Functions (Continued)
TERMINAL
NAME
PZ
PGE
GIOD[0]/EBADDR[0]
–
42
GIOD[1]/EBADDR[1]
–
39
GIOD[2]/EBADDR[2]
–
35
GIOD[3]/EBADDR[3]
–
30
GIOD[4]/EBADDR[4]
–
27
GIOD[5]/EBADDR[5]
–
23
GIOE[0]/EBDATA[0]
–
44
GIOE[1]/EBDATA[1]
–
47
GIOE[2]/EBDATA[2]
–
58
GIOE[3]/EBDATA[3]
–
61
GIOE[4]/EBDATA[4]
–
64
GIOE[5]/EBDATA[5]
–
67
GIOE[6]/EBDATA[6]
–
70
GIOE[7]/EBDATA[7]
–
77
GIOF[0]/EBADDR[6]/
EBDATA[8]
–
80
GIOF[1]/EBADDR[7]/
EBDATA[9]
–
82
GIOF[2]/EBADDR[8]/
EBDATA[10]
–
89
GIOF[3]/EBADDR[9]/
EBDATA[11]
–
90
GIOF[4]/EBADDR[10]/
EBDATA[12]
–
93
GIOF[5]/EBADDR[11]/
EBDATA[13]
–
96
GIOF[6]/EBADDR[12]/
EBDATA[14]
–
99
GIOF[7]/EBADDR[13]/
EBDATA[15]
–
100
GIOG[0]/EBADDR[14]/
EBADDR[6]
–
20
GIOG[1]/EBADDR[15]/
EBADDR[7]
–
10
GIOG[2]/EBADDR[16]/
EBADDR[8]
–
8
GIOG[3]/EBADDR[17]/
EBADDR[9]
–
6
GIOG[4]/EBADDR[18]/
EBADDR[10]
–
3
GIOG[5]/EBADDR[19]/
EBADDR[11]
–
143
GIOG[6]/EBADDR[20]/
EBADDR[12]
–
142
INPUT
VOLT-
OUTPUT
CUR-
AGE(1)(2)
RENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
3.3-V
2mA -z
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0],
GIOG[7:0], AND GIOH[5:0] are multiplexed with the expansion
IPD (20 μA) bus module.
See Table 6.
GIOG[7]/EBADDR[21]/
–
140
EBADDR[13]
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
11
PRODUCT PREVIEW
GENERAL-PURPOSE I/O (GIO) (CONTINUED)
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
Terminal Functions (Continued)
TERMINAL
NAME
PZ
PGE
INPUT
VOLT-
OUTPUT
CUR-
AGE(1)(2)
RENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
GENERAL-PURPOSE I/O (GIO) (CONTINUED)
GIOH[0]/EBADDR[22]/
EBADDR[14]/INT[8]
–
139
GIOH[1]/EBADDR[23]/
EBADDR[15]/INT[9]
29
41
GIOH[2]/EBADDR[24]/
EBADDR[16]/INT[10]
28
40
GIOH[3]/EBADDR[25]/
EBADDR[17]/INT[11]
27
38
GIOH[4]/EBADDR[26]/
EBADDR[18]/INT[12]
26
37
GIOH[5]/EBHOLD/INT[13]
88
3.3-V
2mA
IPD
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0],
GIOG[7:0], AND GIOH[5:0] are multiplexed with the
expansion bus module.
GIOH[5:0]/INT[13:8] are interrupt-capable pins.
125
PRODUCT PREVIEW
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
ADEVT
68
101
ADIN[0]
84
117
ADIN[1]
83
116
ADIN[2]
82
115
ADIN[3]
81
114
ADIN[4]
80
113
ADIN[5]
75
108
ADIN[6]
74
107
ADIN[7]
73
106
ADIN[8]
72
105
ADIN[9]
71
104
ADIN[10]
70
103
3.3-V
2mA -z
3.3-V
MibADC event input. Can be programmed as a GIO pin.
MibADC analog input pins
ADIN[11]
69
102
ADREFHI
76
109
ADREFLO
77
110
GND REF
MibADC module low-voltage reference input
VCCAD
78
111
3.3-V PWR
MibADC analog supply voltage
VSSAD
79
112
GND
3.3-V REF
MibADC module high-voltage reference input
MibADC analog ground reference
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1CLK
3
4
SPI1 clock. SPI1CLK can be programmed as a GIO pin.
SPI1ENA
2
2
SPI1 chip enable. Can be programmed as a GIO pin.
SPI1SCS
1
1
SPI1 slave chip select. Can be programmed as a GIO pin.
5V tolerant
4mA
SPI1SIMO
4
5
SPI1 data stream. Slave in/master out. Can be
programmed as a GIO pin.
SPI1SOMI
5
7
SPI1 data stream. Slave out/master in. Can be
programmed as a GIO pin.
SPI2CLK
39
56
SPI2ENA
42
60
SPI2SCS
43
62
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2 clock. Can be programmed as a GIO pin.
5V tolerant
4mA
SPI2 chip enable. Can be programmed as a GIO pin.
SPI2 slave chip select. Can be programmed as a GIO pin.
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
Terminal Functions (Continued)
TERMINAL
NAME
PZ PGE
INPUT
VOLT-
OUTPUT
CUR-
AGE(1)(2)
RENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
SERIAL PERIPHERAL INTERFACE 2 (SPI2) (CONTINUED)
SPI2SIMO
41
59
SPI2SOMI
40
57
I2C1SDA
60
87
I2C1 serial data pin or GIO pin
I2C1SCL
61
88
I2C1 serial clock pin or GIO pin
5V tolerant
SPI2 data stream. Slave in/master out. Can be programmed as a GIO pin.
4mA
SPI2 data stream. Slave out/master in. Can be programmed as a GIO pin.
INTER-INTEGRATED CIRCUIT (I2C)
I2C2SDA
64
94
I2C2SCL
65
95
5V tolerant
I2C2 serial data pin or GIO pin
4mA
I2C2 serial clock pin or GIO pin
I2C3SDA
20
29
I2C3 serial data pin or GIO pin
I2C3SCL
19
28
I2C3 serial clock pin or GIO pin
OSCIN
23
33
OSCOUT
22
32
PLLDIS
66
97
3.3-V
SCI1CLK
33
48
3.3-V
SCI1RX
32
46
5V tolerant
4mA
SCI1 data receive. SCI1RX can be programmed as a GIO pin.
SCI1TX
31
45
3.3-V
2mA -z
SCI1 data transmit. SCI1TX can be programmed as a GIO pin.
FREQUENCY-MODULATED ZERO-PIN PHASE-LOCKED LOOP (FMZPLL)
1.8-V
Crystal connection pin or external clock input
External crystal connection pin
IPD (20 μA)
Enable/disable the FMZPLL. The FMZPLL can be bypassed and the
oscillator becomes the system clock.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
2mA -z
SCI1 clock. SCI1CLK can be programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2CLK
36
51
3.3-V
2mA -z
SCI2RX
35
50
5V tolerant
4mA
SCI2 clock. SCI2CLK can be programmed as a GIO pin.
SCI2 data receive. SCI2RX can be programmed as a GIO pin.
SCI2TX
34
49
3.3-V
2mA -z
SCI2 data transmit. SCI2TX can be programmed as a GIO pin.
SYSTEM MODULE (SYS)
CLKOUT
57
81
3.3-V
PORRST
85
118
3.3-V
RST
86
121
3.3-V
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output
of SYSCLK, ICLK, or MCLK.
8mA
4mA
IPD (20 μA)
Input master chip power-up reset. External VCC monitor circuitry must
assert a power-on reset.
IPU (20 μA)
Bidirectional reset. The internal circuitry can assert a reset, and an external
system reset can assert a device reset.
On this pin, the output buffer is implemented as an open drain (drives low
only).
To ensure an external reset is not arbitrarily generated, TI recommends
that an external pullup resistor be connected to this pin.
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
AWD
25
36
3.3-V
8mA
Analog watchdog reset. The AWD pin provides a system reset if the WD
KEY is not written in time by the system, providing an external RC network
circuit is connected. If the user is not using AWD, TI recommends that this
pin be connected to ground or pulled down to ground by an external
resistor.
For more details on the external RC network circuit, see the TMS470R1x
System Module Reference Guide (literature number SPNU189) and the
application note Analog Watchdog Resistor, Capacitor and Discharge
Interval Selection Constraints (literature number SPNA005).
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
13
PRODUCT PREVIEW
2mA
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
Terminal Functions (Continued)
TERMINAL
NAME
PZ PGE
INPUT
VOLT-
OUTPUT
CUR-
AGE(1)(2)
RENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
PRODUCT PREVIEW
TEST/DEBUG (T/D)
IPD (20 μA) Test clock. TCK controls the test hardware (JTAG).
TCK
54
76
TDI
52
74
8mA
IPU (20 μA)
TDO
53
75
8mA
Test data out. TDO outputs serial data from the test instruction register,
IPD (20 μA) test data register, identification register, and programmable test address
(JTAG).
TEST
87
124
TMS
11
17
TMS2
10
16
TRST
100 144
Test data in. TDI inputs serial data to the test instruction register, test data
register, and programmable test address (JTAG).
IPD (20 μA)
Test enable. Reserved for internal use only. TI recommends that this pin
be connected to ground or pulled down to ground by an external resistor.
8mA
IPU (20 μA)
Serial input for controlling the state of the CPU test access port (TAP)
controller (JTAG).
8mA
IPU (20 μA)
Serial input for controlling the second TAP. TI recommends that this pin
be connected to VCCIO or pulled up to VCCIO by an external resistor.
3.3-V
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)
IPD (20 μA) Boundary-Scan Logic. TI recommends that this pin be pulled down to
ground by an external resistor.
FLASH
FLTP2
93
132
NC
VCCP
92
131 3.3-V PWR
21
13
63
31
91
53
–
92
–
123
–
130
17
25
48
69
–
86
97
137
90
14
–
34
–
52
–
91
62
122
24
129
18
26
47
68
–
85
98
138
Flash test pad 2. For proper operation, this pin must not be connected
[no connect (NC)].
NC
Flash external pump voltage (3.3 V)
SUPPLY VOLTAGE CORE (1.8 V)
VCC
1.8-V
PWR
Core logic supply voltage
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
VCCIO
3.3-V
PWR
Digital I/O supply voltage
SUPPLY GROUND CORE
VSS
GND
Core supply ground reference
SUPPLY GROUND DIGITAL I/O
VSSIO
GND
Digital I/O supply ground reference
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
VF288 DEVICE-SPECIFIC INFORMATION
memory
Figure 1 shows the memory map of the VF288 device.
0xFFFF_FFFF
System Module Control Registers
(512K Bytes)
0xFFF8_0000
0xFFF7_FFFF
Reserved
HET
Reserved
SPI1
Reserved
Peripheral Control Registers
(512K Bytes)
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4021
0xFFE8_4020
0xFFE8_4000
SCI2
Reserved
Flash Control Registers
SCI1
Reserved
MibADC
Reserved
ECP
MPU Control Registers
Reserved
EBM
Reserved (1 MByte)
GIO
HECC
HECC RAM
0xFFE0_0000
0x7FFF_FFFF
RAM
(16K Bytes)
Program
and
Data Area
0xFFFF_FD00
0xFFFF_FC00
0xFFFF_F700
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F500
0xFFF7_F400
0xFFF7_F000
0xFFF7_EF00
0xFFF7_ED00
0xFFF7_EC00
0xFFF7_E200
SCC2
SCC1
Reserved
0xFFF7_E000
SCC2 RAM
0xFFF7_DE00
Reserved
SCC1 RAM
0xFFF7_DC00
Reserved
I2C3
0xFFF7_DA00
I2C2
0xFFF7_D900
I2C1
0xFFF7_D800
Reserved
FLASH
(288K Bytes)
2 Banks
SPI2
0xFFF7_D400
Reserved
C2SIb
Reserved
Reserved
FIQ
IRQ
HET RAM
(1K Byte)
0x0000_0024
0x0000_0023
0x0000_0000
0xFFFF_FFFF
Reserved
Data Abort
Exception, Interrupt, and
Reset Vectors
Prefetch Abort
Software Interrupt
Undefined Instruction
0xFFF7_C800
0xFFF0_0000
0x0000_0023
0x0000_0020
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
Reset
0x0000_0000
A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B. The CPU registers are not a part of the memory map.
Figure 1. TMS470R1VF288 Memory Map
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
15
PRODUCT PREVIEW
SYSTEM with PSA, CIM, RTI, DEC,
DMA, MMC, DWD
IEM
MSM
Reserved
Memory (4G Bytes)
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
memory selects
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array’s starting (base) address, size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple
of the decoded block size. The decoded block size for the flash memory on this device is 0x00200000. For
more information on how to control and configure these memory select registers, see the bus structure and
memory sections of the TMS470R1x System Module Reference Guide (literature number SPNU189).
For the memory selection assignments and the memory selected, see Table 2.
PRODUCT PREVIEW
Table 2. TMS470R1VF288 Memory Selection Assignment
MEMORY
SELECT
MEMORY SELECTED
(ALL INTERNAL)
0 (fine)
FLASH/ROM
1 (fine)
FLASH/ROM
2 (fine)
RAM
3 (fine)
RAM
4 (fine)
HET RAM
5 (coarse)
6 (coarse)
MEMORY
STATIC MEM
CTL REGISTER
MPU
MSM
MEMORY BASE ADDRESS REGISTER
NO
YES
MFBAHR0 and MFBALR0
NO
YES
MFBAHR1 and MFBALR1
YES
YES
MFBAHR2 and MFBALR2
YES
YES
MFBAHR3 and MFBALR3
1K
NO
NO
MFBAHR4 and MFBALR4
SMCR1
CS[5]/GIOC[3]
128MB (x8)
1MB (x16)
NO
NO
MCBAHR2 and MCBALR2
SMCR5
CS[6]/GIOC[4]
128MB (x8)
1MB (x16)
NO
NO
MCBAHR3 and MCBALR3
SMCR6
SIZE(1)
288K
16K(2)
1 x8 refers to size of memory in 8-bits; x16 refers to size of memory in 16-bits.
2 The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in
the memory-base address register.
JTAG security module
The VF288 device includes a JTAG security module to provide maximum security to the memory contents. The
visible unlock code can be chosen to be in the OTP sector or in the first bank of the user-programmable memory.
For the VF288, the visible unlock code is in the OTP sector at address 0x0000_01F8.
memory security module
The VF288 device also includes a memory security module (MSM) to provide additional security and flexibility
to the memory contents’ protection. The password for unlocking the MSM is located in the four words just before
the flash protection keys (see page 17).
RAM
The VF288 device contains 16K-bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This VF288 RAM is implemented in one 16K array selected
by two memory-select signals. This VF288 configuration imposes an additional constraint on the memory map
for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the multiples
of the size of the physical RAM (i.e., 16K for the VF288 device). The VF288 RAM is addressed through memory
selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion
of the SYS module and memory protection, see the memory section of the TMS470R1x System Module
Reference Guide (literature number SPNU189).
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
F05 Flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the flash read and flash program and erase sections following.
flash protection keys
The VF288 device provides flash protection keys. These four 32-bit protection keys prevent program/erase/
compaction operations from occurring until after the four protection keys have been matched by the CPU loading
the correct user keys into the FMPKEY control register. The protection keys on the VF288 are located in the
last 4 words of the first 8K sector. For more detailed information on the flash protection keys and the FMPKEY
control register, see the Optional Quadruple Protection Keys and Programming the Protection Keys portions
of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
flash read
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
flash pipeline mode
When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz (versus a system
clock frequency of 24 MHz in normal mode). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the Flash can be read with no wait
states when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).
NOTE
After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a "0"). In other words, the
VF288 device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the Flash
configuration mode bit (GBLCTRL.4) will override pipeline mode.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
17
PRODUCT PREVIEW
The VF288 flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000
to 0xFFE0_0000. The Flash is addressed through memory selects 0 and 1.
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
flash program and erase
PRODUCT PREVIEW
The VF288 device Flash contains one 32K-byte memory array (or bank) and one 256K-byte bank, for a total
of 288K-bytes of Flash, and consists of eight sectors. These eight sectors are sized as follows:
SECTOR
NO.
SEGMENT
LOW ADDRESS
OTP
2K Bytes
0x0000_0000
0x0000_07FF
0
8K Bytes
0x0000_0000
0x0000_1FFF
1
8K Bytes
0x0000_2000
0x0000_3FFF
2
8K Bytes
0x0000_4000
0x0000_5FFF
3
8K Bytes
0x0000_6000
0x0000_7FFF
0
64K Bytes
0x0004_0000
0x0004_FFFF
1
64K Bytes
0x0005_0000
0x0005_FFFF
2
64K Bytes
0x0006_0000
0x0006_FFFF
3
64K Bytes
0x0007_0000
0x0007_FFFF
HIGH ADDRESS
MEMORY ARRAYS
(OR BANKS)
BANK0
(32K Bytes)
BANK1
(256K Bytes)
The minimum size for an erase operation is one sector. The maximum size for a program operation is one
16-bit word.
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
Execution can occur from one bank while programming/erasing any or all sectors of another bank. However,
execution can not occur from any sector within a bank that is being programmed or erased.
NOTE
When the OTP sector is enabled, the rest of the flash memory is disabled. The OTP memory can only
be read or programmed from code executed out of RAM.
For more detailed information on Flash program and erase operations, see the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
HET RAM
The VF288 device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
peripheral selects and base addresses
The VF288 device uses ten of the sixteen peripheral selects to decode the base addresses of the peripherals.
These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used
by the SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 3.
Table 3. VF288 Peripherals, System Module, and Flash Base Addresses
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
PERIPHERAL SELECTS
SYSTEM
0xFFFF_FFCC
0xFFFF_FFFF
N/A
RESERVED
0xFFFF_FF70
0xFFFF_FFCB
N/A
DWD
0xFFFF_FF60
0xFFFF_FF6F
N/A
PSA
0xFFFF_FF40
0xFFFF_FF5F
N/A
CIM
0xFFFF_FF20
0xFFFF_FF3F
N/A
RTI
0xFFFF_FF00
0xFFFF_FF1F
N/A
DMA
0xFFFF_FE80
0xFFFF_FEFF
N/A
DEC
0xFFFF_FE00
0xFFFF_FE7F
N/A
RESERVED
0xFFFF_FD80
0xFFFF_FDFF
N/A
MMC
0xFFFF_FD00
0xFFFF_FD7F
N/A
IEM
0xFFFF_FC00
0xFFFF_FCFF
N/A
RESERVED
0xFFFF_FB00
0xFFFF_FBFF
N/A
RESERVED
0xFFFF_FA00
0xFFFF_FAFF
N/A
DMA CMD BUFFER
0xFFFF_F800
0xFFFF_F9FF
N/A
MSM
0xFFFF_F700
0xFFFF_F7FF
N/A
RESERVED
0xFFF8_0000
0xFFFF_F6FF
N/A
RESERVED
0xFFF7_FD00
0xFFF7_FFFF
HET
0xFFF7_FC00
0xFFF7_FCFF
RESERVED
0xFFF7_F900
0xFFF7_FBFF
SPI1
0xFFF7_F800
0xFFF7_F8FF
RESERVED
0xFFF7_F600
0xFFF7_F7FF
SCI2
0XFFF7_F500
0XFFF7_F5FF
SCI1
0xFFF7_F400
0xFFF7_F4FF
RESERVED
0xFFF7_F100
0xFFF7_F3FF
MibADC
0xFFF7_F000
0xFFF7_F0FF
ECP
0xFFF7_EF00
0xFFF7_EFFF
RESERVED
0xFFF7_EE00
0xFFF7_EEFF
EBM
0xFFF7_ED00
0xFFF7_EDFF
GIO
0xFFF7_EC00
0xFFF7_ECFF
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
PRODUCT PREVIEW
CONNECTING MODULE
PS[0]
PS[1]
PS[2]
PS[3]
PS[4]
19
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
Table 3. VF288 Peripherals, System Module, and Flash Base Addresses (Continued)
PRODUCT PREVIEW
CONNECTING MODULE
20
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
HECC
0xFFF7_EA00
0xFFF7_EBFF
RESERVED
0xFFF7_E800
0xFFF7_E9FF
HECC RAM
0xFFF7_E600
0xFFF7_E7FF
RESERVED
0xFFF7_E400
0xFFF7_E5FF
RESERVED
0xFFF7_E300
0xFFF7_E3FF
SCC2
0xFFF7_E200
0xFFF7_E2FF
RESERVED
0xFFF7_E100
0xFFF7_E1FF
SCC1
0xFFF7_E000
0xFFF7_E0FF
RESERVED
0xFFF7_DF00
0xFFF7_DFFF
SCC2 RAM
0xFFF7_DE00
0xFFF7_DEFF
RESERVED
0xFFF7_DD00
0xFFF7_DDFF
PERIPHERAL SELECTS
PS[5]
PS[6]
PS[7]
PS[8]
SCC1 RAM
0xFFF7_DC00
0xFFF7_DCFF
RESERVED
0xFFF7_DB00
0xFFF7_DBFF
I2C3
0xFFF7_DA00
0xFFF7_DAFF
I2C2
0xFFF7_D900
0xFFF7_D9FF
I2C1
0xFFF7_D800
0xFFF7_D8FF
RESERVED
0xFFF7_D500
0xFFF7_D7FF
SPI2
0xFFF7_D400
0xFFF7_D4FF
RESERVED
0xFFF7_CC00
0xFFF7_D3FF
RESERVED
0xFFF7_C900
0xFFF7_CBFF
C2SIb
0xFFF7_C800
0xFFF7_C8FF
RESERVED
0xFFF7_C000
0xFFF7_C7FF
PS[14] - PS[15]
RESERVED
0xFFF0_0000
0xFFF7_BFFF
N/A
Flash Control Registers
0xFFE8_8000
0xFFE8_BFFF
N/A
PS[9]
PS[10]
PS[11] - PS[12]
PS[13]
RESERVED
0xFFF8_4024
0xFFF8_7FFF
N/A
MPU CONTROL REGISTERS
0xFFE8_4000
0xFFE8_4023
N/A
RESERVED
0xFFF8_0000
0xFFF8_3FFF
N/A
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
direct-memory access (DMA)
The direct-memory access (DMA) controller transfers data to and from any specified location in the VF288
memory map (except for restricted memory locations like the system control registers area). The DMA manages
up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The
DMA controller is connected to both the CPU and peripheral busses, enabling these data transfers to occur in
parallel with CPU activity and thus maximizing overall system performance.
Although the DMA controller has two possible configurations, for the VF288 device, the DMA controller configuration is 32 control packets and 16 channels.
For the VF288 DMA request hardwired configuration, see Table 4.
Table 4. DMA Request Lines Connections(1)
DMA REQUEST INTERRUPT SOURCES
DMA CHANNEL
EBM
Expansion Bus DMA request
EBDMAREQ0
DMAREQ[0]
SPI1
SPI1 end-receive
SPI1DMA0
DMAREQ[1]
DMAREQ[2]
SPI1
SPI1 end-transmit
SPI1DMA1
MibADC/I2C1
ADC EV/I2C1 read
MibADCDMA0/I2C1DMA0
DMAREQ[3]
MibADC/SCI1
ADC G1/SCI1 end-receive
MibADCDMA1/SCI1DMA0
DMAREQ[4]
MibADC/SCI1
DMAREQ[5]
ADC G2/SCI1 end-transmit
MibADCDMA2/SCI1DMA1
I2C1
I2C1 write
I2C1DMA1
DMAREQ[6]
SPI2
SPI2 end-receive
SPI2DMA0
DMAREQ[7]
DMAREQ[8]
SPI2 end-transmit
SPI2DMA1
I2C2/C2SIb
SPI2
I2C2 read end-receive/C2SIb end-receive
I2C2DMA0/C2SIDMA0
DMAREQ[9]
I2C2/C2SIb
I2C2 write end-transmit/C2SIb end-transmit I2C2DMA1/C2SIDMA1
DMAREQ[10]
I2C3
I2C3 read
I2C3DMA0
DMAREQ[11]
I2C3
I2C3 write
I2C3DMA1
DMAREQ[12]
SCI2
SCI2 end-receive
SCI2DMA0
DMAREQ[14]
SCI2
SCI2 end-transmit
SCI2DMA1
DMAREQ[15]
RESERVED
DMAREQ[13]
1 For DMA channels with more than one assigned request source, only one of the sources listed can be the DMA request generator in a given
application. The device has software control to ensure that there are no conflicts between requesting modules.
Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate
periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,
and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
O
Non-request mode (used when transferring from memory to memory)
O
Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access
(DMA) Controller Reference Guide (literature number SPNU194).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
21
PRODUCT PREVIEW
MODULES
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
interrupt priority (IEM to CIM)
Interrupt requests originating from the VF288 peripheral modules (i.e., SPI1 or SPI2; SCI1 or SCI2; RTI; etc.)
are assigned to channels within the 48-channel interrupt expansion module (IEM) where, via programmable
register mapping, these channels are then mapped to the 32-channel central interrupt manager (CIM) portion
of the SYS module.
Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel
between sources.
The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the CIM to be of either type:
O
Fast interrupt request (FIQ)
O
Normal interrupt request (IRQ)
The CIM prioritizes interrupts. The precedences of request channels decrease with ascending channel order
in the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their
associated modules, see Table 5.
PRODUCT PREVIEW
Table 5. Interrupt Priority (IEM and CIM)
MODULES
INTERRUPT SOURCES
DEFAULT CIM
INTERRUPT LEVEL/
CHANNEL
IEM
CHANNEL
SPI1
SPI1 end-transfer/overrun
0
0
RTI
COMP2 interrupt
1
1
RTI
COMP1 interrupt
2
2
RTI
TAP interrupt
3
3
SPI2
SPI2 end-transfer/overrun
4
4
GIO
GIO interrupt A
5
5
RESERVED
HET
I2C1
HET interrupt 1
6
7
7
I2C1 interrupt
8
8
SCI1 or SCI2 error interrupt
9
9
SCI1
SCI1 receive interrupt
10
10
C2SIb
SCI1/SCI2
C2SIb interrupt
11
11
I2C2
I2C2 interrupt
12
12
SCC2
SCC2 interrupt A
13
13
SCC1
SCC1 interrupt A
14
14
RESERVED
MibADC
MibADC end event conversion
15
15
16
16
SCI2
SCI2 receive interrupt
17
17
DMA
DMA interrupt 0
18
18
I2C3
I2C3 interrupt
19
19
SCI1
SCI1 transmit interrupt
20
20
SW interrupt (SSI)
21
21
22
22
HET interrupt 2
23
23
SCC2
SCC2 interrupt B
24
24
SCC1
SCC1 interrupt B
25
25
System
RESERVED
HET
22
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
interrupt priority (IEM to CIM) (continued)
Table 5. Interrupt Priority (IEM and CIM) (Continued)
SCI2
INTERRUPT SOURCES
DEFAULT CIM
INTERRUPT LEVEL/
CHANNEL
IEM
CHANNEL
SCI2 transmit interrupt
26
26
MibADC end Group 1 conversion
27
27
DMA
DMA Interrupt 1
28
28
GIO
GIO interrupt B
29
29
MibADC end Group 2 conversion
30
30
31
31
MibADC
MibADC
RESERVED
RESERVED
31
32-37
HECC
HECC interrupt A
31
38
HECC
HECC interrupt B
31
39
31
40-47
RESERVED
For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module (IEM)
Reference Guide (literature number SPNU211). For more detailed functional information on the CIM, see the
TMS470R1x System Module Reference Guide (literature number SPNU189).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
23
PRODUCT PREVIEW
MODULES
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
expansion bus module (EBM)
The expansion bus module (EBM) is a standalone module used to bond out both general-purpose input/output
pins and expansion bus interface pins. This module supports the multiplexing of the GIO functions and the
expansion bus interface functions. The module also supports 8- and 16- bit expansion bus memory interface
mappings, as well as mapping of the following expansion bus signals:
O
27-bit address bus (EBADDR[26:0]) for x8, 19-bit address bus (EBADDR[18:0]) for x16
O
8- or 16-bit data bus (EBDATA[7:0] or EBDATA[15:0])
O
2 write strobes (EBWR[1:0])
O
2 memory chip selects (EBCS[6:5])
O
1 output enable (EBOE)
O
1 external hold signal for interfacing to slow memories (EBHOLD)
O
1 DMA request line (EBDMAREQ[0])
PRODUCT PREVIEW
Table 6 shows the multiplexing of I/O signals with the expansion bus interface signals. The mapping of these
pins varies depending on the memory mode.
Table 6. Expansion Bus Mux Mapping(1)
EXPANSION BUS MODULE PINS(2)
GIO
X8
X16
GIOB[0]
EBDMAREQ[0]
EBDMAREQ[0]
GIOC[0]
EBOE
EBOE
GIOC[2:1]
EBWR[1:0]
EBWR[1:0]
GIOC[4:3]
EBCS[6:5]
EBCS[6:5]
GIOD[5:0]
EBADDR[5:0]
EBADDR[5:0]
GIOE[7:0]
EBDATA[7:0]
EBDATA[7:0]
GIOF[7:0]
EBADDR[13:6]
EBDATA[15:8]
GIOG[7:0]
EBADDR[21:14]
EBADDR[13:6]
GIOH[4:0]
EBADDR[26:22]
EBADDR[18:14]
GIOH[5]
EBHOLD
EBHOLD
1 These mappings are controlled by the EBM mux control registers B-H (EBMXCRB - EBMXCRH) and the EBM control register 1 (EBMCR1).
For GPIO functions, use GIODIRx, GIODINx, GIODOUTx, GIODSETx, and GIODCLRx. For more detailed information, see the TMS470R1x
General-Purpose Input/Output (GIO) Reference Guide (literature number SPNU192) and the TMS470R1x Expansion Bus Module (EBM)
Reference Guide (literature number SPNU222).
2 X8 refers to size of memory in 8-bits; X16 refers to size of memory in 16-bits.
Table 7 lists the names of the expansion bus interface signals and their functions.
Table 7. Expansion Bus Pins
24
PIN
DESCRIPTION
EBDMAREQ
Expansion bus DMA request
EBOE
Expansion bus pin enable
EBWR
Expansion bus write strobe. EBWR[1] controls EBDATA[15:8] and EBWR[0]
controls EBDATA[7:0]
EBCS
Expansion bus chip select
EBADDR
Expansion bus address pin
EBDATA
Expansion bus data pin
EBHOLD
Expansion bus hold. An external device may assert this signal to add wait states
to an expansion bus transaction.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The VF288 MibADC module can function in two modes: compatibility mode, where its programmer’s model is
compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by interrupts
or by the DMA.
MibADC event trigger enhancements
The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.
O
Both group 1 and the event group can be configured for event-triggered operation, providing up to two
event-triggered groups.
O
The trigger source and polarity can be selected individually for both group 1 and the event group from the
options identified in Table 8.
SOURCE SELECT BITS FOR G1 OR EVENT
(G1SRC[1:0] or EVSRC[1:0])
SIGNAL PIN NAME
EVENT1
00
ADEVT
EVENT2
01
HET18
EVENT3
10
Reserved
EVENT4
11
Reserved
EVENT #
For group 1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0])
in the AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC.[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
25
PRODUCT PREVIEW
Table 8. MibADC Event Hookup Configuration
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
JTAG interface
There are two main test access ports (TAPs) on the VF748C device:
O
TMS470R1x CPU TAP
O
Device TAP for factory test
Some of the JTAG pins are shared among these two TAPs. The hookup is illustrated in Figure 2.
PRODUCT PREVIEW
TSM470R1x CPU
TCK
TCK
TRST
TRST
TMS
TMS
TDI
TDI
TDO
Factory TEST
TCK
TRST
TMS2
TMS
TDI
TDO
Figure 2. JTAG Interface
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TDO
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
development system support
Texas Instruments provides extensive hardware and software development support tools for the TMS470R1x
family. These support tools include:
Code Composer Studio™ Integrated Development Environment (IDE)
–
–
–
O
Optimizing C compiler
–
–
–
–
–
–
–
O
Provides extensive macro capability
Allows high-speed operation
Allows extensive control of the assembly process using assembler directives
Automatically resolves memory references as C and assembly modules are combined
TMS470R1x CPU Simulator
–
–
–
O
Supports high-level language programming
Full implementation of the standard ANSI C language
Powerful optimizer that improves code-execution speed and reduces code size
Extensive run-time support library included
TMS470R1x control registers easily accessible from the C program
Interfaces C functions and assembly functions easily
Establishes comprehensive, easy-to-use tool set for the development of high-performance
microcontroller applications in C/C++
Assembly language tools (assembler and linker)
–
–
–
–
O
Fully integrated suite of software development tools
Includes Compiler/Assembler/Linker, Debugger, and Simulator
Supports Real-Time analysis, data visualization, and open API
Provides capability to simulate CPU operation without emulation hardware
Allows inspection and modifications of memory locations
Allows debugging programs in C or assembly language
XDS emulation communication kits
–
Allows high-speed JTAG communication to the TMS470R1x emulator or target board
For more information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio is a trademark of Texas Instruments.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
27
PRODUCT PREVIEW
O
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
documentation support
Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types
of documentation available include: data sheets with design specifications; complete user’s guides for all
devices and development support tools; and hardware and software applications. Useful reference documentation includes:
PRODUCT PREVIEW
O
O
28
User’s Guides
–
TMS470R1x 32-Bit RISC Microcontroller Family User’s Guide (literature number SPNU134)
–
TMS470R1x C/C++ Compiler User’s Guide (literature number SPNU151)
–
TMS470R1x Code Generation Tools Getting Started Guide (literature number SPNU117)
–
TMS470R1x C Source Debugger User’s Guide (literature number SPNU124)
–
TMS470R1x Assembly Language Tools User’s Guide (literature number SPNU118)
–
TMS470R1x System Module Reference Guide (literature number SPNU189)
–
TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)
–
TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
–
TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
–
TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
–
TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199)
–
TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
–
TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide
(literature number SPNU206)
–
TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
–
TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214)
–
TMS470R1x Frequency-Modulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide
(literature number SPNU221)
–
TMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222)
–
TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223)
Application Reports:
–
Analog Watchdog Resistor, Capacitor and Discharge Interval Selection Constraints
(literature number SPNA005)
–
F05/C05 Power Up Reset and Power Sequencing Requirements (literature number SPNA009)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
device numbering conventions
Figure 3 illustrates the numbering and symbol nomenclature for the TMS470R1x family.
TMS 470 R1 V F 28 8 PGE A
Prefix: TMS = Standard Prefix for Fully Qualified Devices
Family:
470 = TMS470 RISC-Embedded Microcontroller Family
V = 1.8-V Core Voltage
CPU Type:
Device Type:
Program Memory Size
C
F
L
B
R
=
=
=
=
=
Masked ROM
Flash
ROM-less
System Emulator for Development Tools
RAM
R1 = ARM7TDMI CPU
28 = ’28 Devices Containing the Following Modules:
– FMZPLL Clock
– 16K-Byte Static RAM
– 1K-Byte HET RAM (64 Instructions)
– Digital Watchdog (DWD)
– Interrupt Expansion Module (IEM)
– Memory Security Module (MSM)
– High-End Lite (HET)
– Real-Time Interrupt (RTI)
– 10-Bit, 12-Input Multi-buffered Analog-to-Digital
Converter (MibADC)
– Two Serial Peripheral Interface (SPI) Modules
– Two Serial Communications Interface (SCI) Modules
– Three Inter-Integrated Circuit (I2C) Modules
– Class II Serial Interface B (C2SIb) Module
– Standard Controller Area Network (CAN) [SCC]
– External Clock Prescaler (ECP)
8 = 0
PRODUCT PREVIEW
Program Memory Types:
– No on-chip program memory
1–5 – 1 to < 128K Bytes
6–B – 128K Bytes to < 1M Bytes
C–F – > 1M Bytes
Operating Free-Air
Temperature Ranges:
A =
T =
Q =
–40°C to 85°C
–40°C to 105°C
–40°C to 125°C
Package: PGE = 144-Pin Plastic Low-Profile Quad Flatpack (LQFP)
PZ = 100-Pin Plastic Low-Profile Quad Flatpack (LQFP)
Figure 3. TMS470R1x Family Nomenclature
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
29
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
device identification code register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash
device, and an assigned device-specific part number (see Table 9). The VF288 device identification code
register value is 0x095F.
Table 9. TMS470 Device ID Bit Allocation Register
BIT 31
30
29
28
27
26
25
23
22
21
20
19
18
17
BIT 16
6
5
4
3
2
1
BIT 0
Reserved
FFFF_FFF0
BIT 15
LEGEND:
For bits 3–15:
For bits 0–2:
PRODUCT PREVIEW
24
14
13
12
11
10
9
8
7
VERSION
TF
R/F
PART NUMBER
1
1
1
R-K
R-K
R-K
R-K
R-1
R-1
R-1
R = Read only, -K = Value constant after RESET
R = Read only, -1 = Value after RESET
Transmission Request Reset Register (CANTRR) Field Descriptions
Bit
Name
Value
Description
31–16
Reserved
Reads are undefined and writes have no effect.
15–12
VERSION
Silicon version (revision) bits
These bits identify the silicon version of the device.
11
TF
Technology family bit
This bit distinguishes the technology family core power supply:
10
0
3.3 V for F10/C10 devices
1
1.8 V for F05/C05 devices
ROM/Flash bit
This bit distinguishes between ROM and Flash devices:
R/F
0
Flash device
1
ROM device
9–3
PART NUMBER
Device-specific part number bits
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the VF288 device is 0101011.
2–0
1 Mandatory
High
Bits 2, 1, and 0 are tied high by default.
30
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
device part numbers
Table 10 lists all the available TMS470R1VF288 devices.
Table 10. Device Part Number
DEVICE PART
NUMBER
PROGRAM MEMORY
ROM
FLASH
EEPROM
PACKAGE TYPE
100-PIN
LQFP
TEMPERATURE RANGES
144-PIN
LQFP
−40°C TO 85°C
X
TMS470R1VF288PGEA
X
X
TMS470R1VF288PGEQ
X
X
TMS470R1VF288PZA
X
X
TMS470R1VF288PZQ
X
X
TMS470R1VF288PGEAR
X
TMS470R1VF288PGEQR
X
TMS470R1VF288PZAR
X
X
TMS470R1VF288PZQR
X
X
−40°C TO 105°C
−40°C TO 125°C
X
X
X
X
X
X
X
X
PRODUCT PREVIEW
X
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
31
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
absolute maximum ratings over operating free-air temperature range(1)
Supply voltage ranges: VCC (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.5 V
Supply voltage ranges: VCCIO , VCCAD , VCCP (flash pump)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Input voltage range: All 5 V tolerant input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.0 V
All other input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Input clamp current: All 5 V tolerant pins, PORRST, TRST, TEST and TCK (VI < 0) . . . . . . . . . . . . . −20mA(3)
ADIN[0:11] IIK (VI < 0 or VI > VCCAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±10 mA
All other pins IIK (VI < 0 or VI > VCCIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Operating free-air temperature ranges, TA: A version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
PRODUCT PREVIEW
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
1 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2 All voltage values are with respect to their associated grounds.
3 These pins do not have an internal clamp diode to a positive supply voltage.
device recommended operating conditions(4)
MIN
NOM
MAX
UNIT
1.71
2.05
V
VCC
Digital logic supply voltage (Core)
VCCIO
Digital logic supply voltage (I/O)
3
3.6
V
VCCAD
ADC supply voltage
3
3.6
V
VCCP
Flash pump supply voltage
3
3.6
V
VSS
Digital logic supply ground
VSSAD
ADC supply ground
TA
Operating free-air temperature
TJ
Operating junction temperature
0
A version
Q version
4 All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
V
− 0.1
0.1
V
− 40
85
°C
− 40
125
°C
− 40
150
°C
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
electrical characteristics over recommended operating free-air temperature range(1)
VIL
TEST CONDITIONS
Low-level input voltage
All
− 0.3
inputs(2)
VIH
High-level input voltage
All inputs
Vth
Input threshold voltage
AWD only(3)
VOL
Low-level output voltage(4)
VOH
High-level output voltage(4)
IIC
Input clamp current (I/O pins)(5)
2
1.35
IOL = IOL MAX
IOH = IOH MIN
IOH = 50 μA
0.8 VCCIO
−1
1
VI = VCCIO
5
40
RST
2
–40
–5
VI = VCCIO
−1
1
No pullup or pulldown
−1
1
VI = VSS
−1
1
VI = VCCIO
−1
1
VI = 5 V
0.5
20
1
40
mA
μA
μA
8
4
VOL = VOL MAX
(6)
All other 3.3 V I/O
2
5 V tolerant
4
CLKOUT, TDI, TDO,
TMS, TMS2
RST
V
V
VCCIO − 0.2
IIH Pulldown
VI = 5.5 V
High-level output
current
V
V
0.2
CLKOUT, AWD, TDI,
TDO, TMS, TMS2
V
1.8
−2
Input current (5 V tolerant input pins)
IOH
0.8
VCCIO + 0.3
VI < VSSIO − 0.3 or VI > VCCIO + 0.3
VI = VSS
UNIT
V
VI = VSS
All other pins
Low-level output
current
MAX
IIL Pulldown
IIH Pullup
IOL
TYP
0.2 VCCIO
IOL = 50 μA
Input current (3.3 V input pins) IIL Pullup
II
MIN
0.15
Input hysteresis
mA
−8
VOH = VOH MIN
−4
All other 3.3 V I/O
−2
5 V tolerant
−4
(6)
mA
1 Source currents (out of the device) are negative while sink currents (into the device) are positive.
2 This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 40.
3 These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
4 VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
5 Parameter does not apply to input-only or output-only pins.
6 Some of the 2 mA buffers on this device are zero-dominant buffers, as indicated by a -z in the Output Current column of the Terminal Functions
table. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the resulting value
will always be low.
7 For Flash banks/pumps in sleep mode.
8 ICC in halt mode is linear between 30C and 85C.
9 I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
33
PRODUCT PREVIEW
PARAMETER
Vhys
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
electrical characteristics over recommended operating free-air temperature range(1) (continued)
PARAMETER
TEST CONDITIONS
VCC digital supply current (operating mode)
ICC
VCC digital supply current (standby mode)(7)
MAX
UNIT
SYSCLK = 24 MHz, VCC = 2.05 V
MIN
90
mA
TYP
SYSCLK = 48 MHz, VCC = 2.05 V
115
mA
A version (85°C)
OSCIN = 4 MHz, VCC = 2.05 V
750
μA
Q version (125°C)
OSCIN = 4 MHz, VCC = 2.05 V
1.25
mA
30
μA
TA = 30°C, VCC = 2.05 V
A version (85°C), VCC = 2.05 V
160
μA
Q version (125°C), VCC = 2.05 V
550
μA
No DC load, VCCIO = 3.6 V(9)
15
mA
No DC load, VCCIO = 3.6 V
(9)
10
μA
VCCIO digital supply current (halt mode)
No DC load, VCCIO = 3.6 V
(9)
5
μA
VCCAD supply current (operating mode)
All frequencies, VCCAD = 3.6 V
25
mA
VCC digital supply current (halt mode)
(7)(8)
VCCIO digital supply current (operating mode)
PRODUCT PREVIEW
ICCIO
ICCAD
ICCP
VCCIO digital supply current (standby mode)
VCCAD supply current (standby mode)
No DC load, VCCAD = 3.6 V
10
μA
VCCAD supply current (halt mode)
VCCAD = 3.6 V
5
μA
VCCP = 3.6 V read operation
60
mA
VCCP = 3.6 V program and erase
70
mA
10
μA
5
μA
VCCP pump supply current
(9)
VCCP = 3.6 V standby mode
operation(7)
VCCP = 3.6 V halt mode operation(7)
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
1 Source currents (out of the device) are negative while sink currents (into the device) are positive.
2 This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 40.
3 These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
4 VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
5 Parameter does not apply to input-only or output-only pins.
6 Some of the 2 mA buffers on this device are zero-dominant buffers, as indicated by a -z in the Output Current column of the Terminal Functions
table. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the resulting value
will always be low.
7 For Flash banks/pumps in sleep mode.
8 ICC in halt mode is linear between 30°C and 85°C.
9I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CL
IOH
Where: IOL
= IOL MAX for the respective pin(A)
IOH
= IOH MIN for the respective pin(A)
VLOAD = 1.5 V
PRODUCT PREVIEW
CL
= 150-pF typical load-circuit capacitance(B)
NOTES: A. For these values, see the "electrical characteristics over recommended operating free-air temperature range" table.
B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 4. Test Load Circuit
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
35
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten
the symbols, some of the pin names and other related terminology have been abbreviated as follows:
CM
CO
ER
ICLK
M
OSC, OSCI
OSCO
P
R
R0
R1
Compaction, CMPCT
CLKOUT
Erase
Interface clock
Master mode
OSCIN
OSCOUT
Program, PROG
Ready
Read margin 0, RDMRGN0
Read margin 1, RDMRGN1
RD
RST
RX
S
SCC
SIMO
SOMI
SPC
SYS
TX
Read
Reset, RST
SCInRX
Slave mode
SCInCLK
SPInSIMO
SPInSOMI
SPInCLK
System clock
SCInTX
r
su
t
v
w
rise time
setup time
transition time
valid time
pulse duration (width)
PRODUCT PREVIEW
Lowercase subscripts and their meanings are:
a
c
d
f
h
access time
cycle time (period)
delay time
fall time
hold time
The following additional letters are used with these meanings:
36
H
High
X
L
V
Low
Valid
Z
POST OFFICE BOX 1443
Unknown, changing, or don’t care
level
High impedance
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
external reference resonator/crystal oscillator clock option
The oscillator is enabled by connecting the appropriate fundamental 4–10 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 5a. The oscillator is a singlestage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.8 V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 5b.
C1(A)
OSCOUT
Crystal
OSCIN
C2(A)
OSCOUT
External
Clock Signal
(toggling 0–1.8 V)
(a)
PRODUCT PREVIEW
OSCIN
(b)
A. The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 5. Crystal/Clock Connection
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
37
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
FMZPLL and clock specifications
timing requirements for FMZPLL circuits enabled or disabled
MIN
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
tw(OSCIL)
tw(OSCIH)
f(OSCRST)
TYP
4
MAX
UNIT
10
MHz
100
ns
Pulse duration, OSCIN low
15
ns
Pulse duration, OSCIN high
15
ns
OSC FAIL frequency
(1)
53
kHz
1 Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal
to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number
SPNU189).
switching characteristics over recommended operating conditions for clocks(1)(2)(3)
TEST CONDITIONS(3)
PRODUCT PREVIEW
PARAMETER
f(SYS)
System clock frequency(4)
f(CONFIG)
System clock frequency - Flash config mode
f(ICLK)
Interface clock frequency
f(ECLK)
External clock output frequency for ECP module
Cycle time, system clock
tc(CONFIG)
Cycle time, system clock - flash config mode
tc(ECLK)
Cycle time, interface clock
Cycle time, ECP module external clock output
MAX
UNIT
48
MHz
24
MHz
24
MHz
Pipeline mode enabled
25
MHz
Pipeline mode disabled
tc(SYS)
tc(ICLK)
MIN
Pipeline mode enabled
Pipeline mode disabled
24
MHz
Pipeline mode enabled
25
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
20.8
ns
Pipeline mode disabled
41.6
ns
41.6
ns
Pipeline mode enabled
40
ns
Pipeline mode disabled
41.6
ns
Pipeline mode enabled
40
ns
Pipeline mode disabled
41.6
ns
1 f(SYS) = M × f(OSC) / R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the CLKDIVPRE
[2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the GLBCTRL register
(GLBCTRL.3).
f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits
in the SYS module.
2 f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
3 Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
4 Flash Vread must be set to 5V to achieve maximum system clock frequency.
38
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
FMZPLL and clock specifications (continued)
switching characteristics over recommended operating conditions for external clocks
(see Figure 6 and Figure 7)(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
(4)
SYSCLK or MCLK
1
tw(COL)
Pulse duration, CLKOUT low
ICLK: X is even or 1(5)
ICLK: X is odd and not
0.5tc(ICLK) – tf
1(5)
Pulse duration, CLKOUT high ICLK: X is even or 1(5)
ICLK: X is odd and not
0.5tc(ICLK) – tr
1(5)
4
tw(EOL)
tw(EOH)
Pulse duration, ECLK low
0.5tc(ECLK) – tf
0.5tc(ECLK) – tf
N is odd and X is even
Pulse duration, ECLK high
N is odd and X is odd and not 1
0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tr
N is odd and X is even
0.5tc(ECLK) – tr
N is odd and X is odd and not 1
ns
0.5tc(ICLK) – 0.5tc(SYS) – tr
N is even and X is even or odd
3
ns
0.5tc(SYS) – tr
SYSCLK or MCLK
tw(COH)
UNIT
0.5tc(ICLK) + 0.5tc(SYS) – tf
(4)
2
MAX
0.5tc(SYS) – tf
ns
ns
PRODUCT PREVIEW
NO.
0.5tc(ECLK) – 0.5tc(SYS) – tr
1 X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.
2 N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
3 CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
4 Clock source bits are selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).
5 Clock source bits are selected as ICLK (CLKCNTL.[6:5] = 01 binary).
2
CLKOUT
1
Figure 6. CLKOUT Timing Diagram
4
ECLK
3
Figure 7. ECLK Timing Diagram
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
39
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
RST and PORRST timings
timing requirements for PORRST (see Figure 8)
MIN
PRODUCT PREVIEW
NO.
MAX
UNIT
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and
become active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VCCIOPORH
VCCIO high supply level when PORRST must remain active during power up and
become active during power down
VIL
Low-level input voltage after VCCIO > VCCIOPORH
VIL(PORRST)
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
3
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
5
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
6
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
0.6
1.5
V
V
1.1
2.75
V
V
0.2 VCCIO
V
0.5
V
7
tsu(PORRST)f
Setup time, PORRST active before VCC ≤ VCCPORH during power down
8
μs
8
th(PORRST)rio
Hold time, PORRST active after VCCIO > VCCIOPORH
1
ms
9
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
10
tsu(PORRST)fio
Setup time, PORRST active before VCCIO ≤ VCCIOPORH during power down
0
ns
11
tsu(VCCIO)f
Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL
0
ns
VCCP/VCCIO
VCCIOPORH
VCCIOPORH
VCCIO
8
VCC
VCC
VCCPORH
6
VCCIOPORL
VCC
VCCP/VCCIO
PORRST
11
VCCPORH
7
6
10
7
VCCPORL
VCCPORL
VCCIOPORL
5
3
VIL(PORRST)
9
VIL
VIL
VIL
VIL(PORRST)
VIL
Figure 8. PORRST Timing Diagram
switching characteristics over recommended operating conditions for RST(1)
PARAMETER
tv(RST)
tfsu
MIN
4112tc(OSC)
Valid time, RST active after PORRST inactive
8tc(SYS)
Valid time, RST active (all others)
Flash start up time, from RST inactive to fetch of first instruction from Flash (Flash pump
stabilization time)
670tc(OSC)
MAX
UNIT
ns
ns
1 Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load
capacitance" table.
40
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
JTAG scan interface timing (JTAG clock specification 10-MHz and 50-pF load on TDO output)
MIN
NO.
MAX
UNIT
1
tc(JTAG)
Cycle time, JTAG low and high period
50
ns
2
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
3
th(TCKr -TDI/TMS)
Hold time, TDI, TMS after TCKr
15
ns
4
th(TCKf -TDO)
Hold time, TDO after TCKf
10
ns
5
td(TCKf -TDO)
Delay time, TDO valid after TCK fall (TCKf)
45
ns
TCK
1
1
TMS
TDI
2
PRODUCT PREVIEW
3
TDO
4
5
Figure 9. JTAG Scan Timings
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
41
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
output timings
switching characteristics for output timings versus load capacitance (CL) (see Figure 10)
MIN
PARAMETER
tr
tf
PRODUCT PREVIEW
tr
tf
tr
tf
tr
tf
Rise time, AWD, CLKOUT, TDI, TDO, TMS, TMS2
Fall time, AWD, CLKOUT, TDI, TDO, TMS, TMS2
Rise time, RST
Fall time, RST
Rise time,4mA, 5 V tolerant pins
Fall time, 4mA, 5 V tolerant pins
0.5
2.5
CL= 50 pF
1.5
5.0
CL = 100 pF
3.0
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL= 50 pF
1.5
5.0
CL = 100 pF
3.0
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
3
10
CL = 50 pF
3.5
12
CL = 100 pF
7
21
CL = 150 pF
9
28
CL = 15 pF
2
8
CL = 50 pF
2.5
9
8
25
CL = 150 pF
11
35
CL = 15 pF
2.5
10
CL = 100 pF
Rise time, all other output pins
Fall time, all other output pins
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
tr
tf
80%
Output
20%
VCC
80%
20%
Figure 10. CMOS-Level Outputs
42
POST OFFICE BOX 1443
MAX UNIT
CL = 15 pF
• HOUSTON, TEXAS 77251-1443
0
ns
ns
ns
ns
ns
ns
ns
ns
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
input timings
timing requirements for input timings(1) (see Figure 11)
MIN
tpw
tc(ICLK) + 10
Input minimum pulse width
MAX
UNIT
ns
1 tc(ICLK) = interface clock cycle time = 1/f(ICLK)
tpw
Input
80%
20%
VCC
80%
20%
0
PRODUCT PREVIEW
Figure 11. CMOS-Level Inputs
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
43
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
flash timings
timing requirements for program flash(1)(2)
tprog(16-bit)
Half word (16-bit) programming time
tprog(Total)
288K-byte programming
terase(sector)
Sector erase time
twec
Write/erase cycles
MIN
TYP
MAX
UNIT
4
16
200
μs
2
8
s
5
15
time(3)
1000
10000
s
cycles
tfp(RST)
Flash pump settling time from RST to SLEEP
134tc(SYS)
ns
tfp(SLEEP)
Initial flash pump settling time from SLEEP to STANDBY
134tc(SYS)
ns
tfp(STANDBY)
Initial flash pump settling time from STANDBY to ACTIVE
67tc(SYS)
ns
1 For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
PRODUCT PREVIEW
2 Flash program/erase is specified only at the temperature range of 25°C to 85°C (A version), or 25°C to 125°C (Q version).
3 The 288K-byte programming time includes overhead of state machine.
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
SPIn master mode timing parameters
SPIn master mode external timing parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)(1)(2)(3)(see Figure 12)
1
2(5)
3(5)
4
MAX
100
256tc(ICLK)
Cycle time, SPInCLK
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid
(clock polarity = 0)
10
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid
(clock polarity = 1)
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)
tc(SPC)M – 5 – tf
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)
tc(SPC)M – 5 – tr
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
6
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
4
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
4
6(5)
7(5)
MIN
tc(SPC)M
(5)
5(5)
(4)
UNIT
ns
PRODUCT PREVIEW
NO.
1 The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
2 tc(ICLK) = interface clock cycle time = 1/f(ICLK)
3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
4 When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
5 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
45
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
PRODUCT PREVIEW
7
SPInSOMI
Master In Data
Must Be Valid
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0)
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
SPIn master mode timing parameters (continued)
SPIn master mode external timing parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)(1)(2)(3) (see Figure 13)
1
2(5)
tc(SPC)M
Cycle time, SPInCLK
tw(SPCH)M
(4)
MIN
MAX
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0) at 85°C
0.5tc(SPC)M – 10
4(5) t
v(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0) at 125°C
0.5tc(SPC)M – 12
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid (clock polarity = 1)
0.5tc(SPC)M – 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – 5 – tf
3(5)
5(5)
6(5)
7(5)
tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity = 0)
6
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low (clock polarity = 1)
6
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0)
4
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1)
4
UNIT
ns
PRODUCT PREVIEW
NO.
1 The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
2 tc(ICLK) = interface clock cycle time = 1/f(ICLK)
3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
4 When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
5 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
47
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
PRODUCT PREVIEW
7
SPInSOMI
Master In Data
Must Be Valid
Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 1)
48
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
SPIn slave mode timing parameters
SPIn slave mode external timing parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)(1)(2)(3)(4)(see Figure 14)
1
2(6)
3(6)
(5)
MIN
MAX
100
256tc(ICLK)
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid (clock
polarity = 0)
6 + tr
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid (clock
polarity = 1)
6 + tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
tc(SPC)S – 6 – tf
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low (clock
polarity = 0)
6
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high (clock
polarity = 1)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 0)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
6
4(6)
5(6)
6(6)
7(6)
UNIT
ns
PRODUCT PREVIEW
NO
1 The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
2 If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
4 tc(ICLK) = interface clock cycle time = 1/f(ICLK)
5 When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
6 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
49
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
6
PRODUCT PREVIEW
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
50
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
SPIn slave mode timing parameters (continued)
SPIn slave mode external timing parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)(1)(2)(3)(4)(see Figure 15)
1
2(6)
3(6)
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
MIN
MAX
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SOMI-SPCL)S
Valid time, SPInCLK low after SPInSOMI data valid (clock
polarity = 1)
0.5tc(SPC)S – 6 – tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
0.5tc(SPC)S – 6 – tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high (clock
polarity = 0)
6
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low (clock
polarity = 1)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 1)
6
4(6)
5(6)
6(6)
7
(5)
(6)
UNIT
ns
PRODUCT PREVIEW
NO
1 The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
2 If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
4 tc(ICLK) = interface clock cycle time = 1/f(ICLK)
5 When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
6 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
51
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
PRODUCT PREVIEW
7
SPInSIMO
SPISIMO Data Must
Be Valid
Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
52
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
SCIn isosynchronous mode timings — internal clock
timing requirements for internal clock SCIn isosynchronous mode(1)(2)(3) (see Figure 16)
(BAUD + 1)
IS ODD AND BAUD ≠ 0
UNIT
MIN
MAX
MIN
MAX
2tc(ICLK)
224tc(ICLK)
3tc(ICLK)
(224 –1) tc(ICLK)
1
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCL)
Pulse duration,
SCInCLK low
0.5tc(SCC) – tf
0.5tc(SCC) + 5
0.5tc(SCC) +0.5tc(ICLK) – tf 0.5tc(SCC) +0.5tc(ICLK)
ns
3
tw(SCCH)
Pulse duration,
SCInCLK high
0.5tc(SCC) – tr
0.5tc(SCC) + 5
0.5tc(SCC) –0.5tc(ICLK) – tr 0.5tc(SCC) –0.5tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK
high to SCInTX valid
5
tv(TX)
Valid time, SCInTX data
after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX
before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data
- tc(ICLK) + tf + 20
after SCInCLK low
10
10
ns
ns
tc(SCC) – 10
tc(SCC) – 10
ns
tc(ICLK) + tf + 20
tc(ICLK) + tf + 20
ns
- tc(ICLK) + tf + 20
ns
PRODUCT PREVIEW
(BAUD + 1)
IS EVEN OR BAUD = 0
NO.
1 BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
2 tc(ICLK) = interface clock cycle time = 1/f(ICLK)
3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
1
3
2
SCICLK
5
4
SCITX
Data Valid
6
7
SCIRX
NOTE :
Data Valid
Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
53
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
SCIn isosynchronous mode timings — external clock
timing requirements for external clock SCIn isosynchronous mode(1)(2) (see Figure 17)
MIN
NO.
(3)
MAX
1
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCH)
Pulse duration, SCInCLK high
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
3
tw(SCCL)
Pulse duration, SCInCLK low
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
2tc(ICLK) + 12 + tr
ns
8tc(ICLK)
5
tv(TX)
Valid time, SCInTX data after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data after SCInCLK low
ns
2tc(SCC)–10
0
2tc(ICLK) + 10
PRODUCT PREVIEW
1
2
3
SCICLK
5
4
SCITX
Data Valid
6
7
SCIRX
NOTE :
Data Valid
Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
ns
ns
1 tc(ICLK) = interface clock cycle time = 1/f(ICLK)
2 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
3 When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK)
54
UNIT
ns
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
I2C timing
Table 11 below assumes testing over recommended operating conditions.
Table 11. I2C Signals (SDA and SCL) Switching Characteristics(1)
STANDARD
FAST MODE
MODE
UNIT
MIN MAX
MIN MAX
tc(I2CCLK)
Cycle time, I2C module clock
75
tc(SCL)
Cycle time, SCL
10
2.5
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START condition)
4.7
0.6
μs
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated START condition)
4
0.6
μs
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
μs
tw(SCLH)
Pulse duration, SCL high
4
0.6
μs
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
250
100
th(SDA-SCLL)
Hold time, SDA valid after SCL low
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
For I2C bus devices
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition)
tw(SP)
Cb
150
0 3.45(2)
0
4.7
1.3
4.0
0.6
0
Pulse duration, spike (must be suppressed)
(3)
75
400
Capacitive load for each bus line
150
ns
ns
0.9
μs
μs
μs
50
ns
400
pF
1 The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
2 The maximum th(SDA-SCLL) for I2C bus devices needs only be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal.
3 Cb = The total capacitance of one bus line in pF.
SDA
tsu(SDA-SCLH)
tw(SDAH)
tw(SCLL)
tr(SCL)
tw(SP)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
Stop
tf(SCL)
th(SDA-SCLL)
Start
th(SCLL-SDAL)
tsu(SCLH-SDAL)
Repeated
Start
Stop
NOTE:A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
NOTE:The maximum th(SDA-SCLL) needs only be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal.
NOTE:A Fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device
does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH).
NOTE:Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
Figure 18. I2C Timings
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
55
PRODUCT PREVIEW
PARAMETER
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
standard CAN controller (SCC) mode timings
dynamic characteristics for the CANSTX and CANSRX pins
MIN
PARAMETER
td(CANSTX)
Delay time, transmit shift register to CANSTX pin(1)
td(CANSRX)
Delay time, CANSRX pin to receive shift register
MAX
UNIT
15
ns
5
ns
1 These values do not include rise/fall times of the output buffer.
expansion bus timing parameters, –40°C ≤ TJ ≤ 150°C, 3.0 V ≤ VCC ≤ 3.6 V
(see figure 19 and figure 20)
PRODUCT PREVIEW
NO.
MIN
PARAMETER
1
tc(CO)
Cycle time, CLKOUT
2
td(COH-EBADV)
Delay Time, CLKOUT high to EBADDR valid
3
th(COH-EBADIV)
Hold Time, EBADDR invalid after CLKOUT high
4
td(COH-EBOE)
Delay Time, CLKOUT high to EBOE fall
5
th(COH-EBOEH)
Hold Time, EBOE rise after CLKOUT high
6
td(COL-EBWR)
Delay Time, CLKOUT low to write strobe (EBWR) low
7
th(COL-EBWRH)
Hold Time, EBWR high after CLKOUT low
8
tsu(EBRDATV-COH)
Setup time, EBDATA valid before CLKOUT high (READ)(2)
Hold time, EBDATA invalid after CLKOUT high (READ)
MAX UNIT
20.8
ns
26
(– 8)
ns
15
2
9
th(COH-EBRDATIV)
10
td(COL-EBWDATV)
Delay time, CLKOUT low to EBDATA valid
11
th(COL-EBWDATIV)
Hold time, EBDATA invalid after CLKOUT low (WRITE)
ns
ns
ns
17
ns
3
ns
25
ns
(– 6)
(WRITE)(3)
ns
19
(– 12)
ns
ns
SECONDARY TIMES
12
td(COH-EBCS0)
Delay, CLKOUT high to EBCS0 fall
13
th(COH-EBCS0H)
Hold, EBCS0 rise after CLKOUT high
14
tsu(COH-EBHOLDL)
15
tsu(COH-EBHOLDH)
Setup time, EBHOLD low to CLKOUT
6
high(2)
Setup time, EBHOLD high to CLKOUT
high(2)
2 Setup time is the minimum time under worst case conditions. Data with less setup time will not work.
3 Valid after CLKOUT goes low for write cycles.
56
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
20
ns
21
ns
25
ns
25
ns
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
expansion bus module timing
1
CLKOUT
3
2
Valid
EBADDR
9
8
Valid
EBDATA
4
5
EBOE
12
13
EBCS0
15
14
PRODUCT PREVIEW
EBHOLD
1 Hold State
Figure 19. Expansion Memory Signal Timing - Reads
1
CLKOUT
2
3
Valid
EBADDR
11
10
Valid
EBDATA
6
7
EBWR
12
12
EBCS0
14
15
EBHOLD
1 Hold State
Figure 20. Expansion Memory Signal Timing - Writes
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
57
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
high-end timer (HET) timings
minimum PWM output pulse width:
This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale
factor (hr) which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns
minimum input pulses we can capture:
The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the
HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which
is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns
PRODUCT PREVIEW
NOTE
Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is,
the captured value gives the number of HRP clocks inside the pulse.)
Abbreviations:
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
58
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
multi-buffered A-to-D converter (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on
VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to
ADREFLO unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bits (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Assured
Output conversion code . . . . . . . . . . . . . . . . . . . . . . . 00h to 3FFh [00 for VAI ≤ADREFLO; 3FF for VAI ≥ ADREFHI]
MibADC recommended operating conditions(1)
ADREFLO
MIN
MAX
UNIT
A-to-D high -voltage reference source
VSSAD
VCCAD
V
A-to-D low-voltage reference source
VSSAD
VCCAD
V
VSSAD − 0.3
VCCAD + 0.3
V
VAI
Analog input voltage
IAIC
Analog input clamp current(2)
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
−2
2
mA
1 For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table.
2 Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
operating characteristics over full ranges of recommended operating conditions(1)(2)
PARAMETER
Ri
DESCRIPTION/CONDITIONS
Analog input resistance
MIN
Analog input capacitance
See Figure 21
IAIL
Analog input leakage current
See Figure 21
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which specified
accuracy is maintained
ADREFHI − ADREFLO
EDNL
Differential nonlinearity error
EINL
ETOT
MAX
250
UNIT
500
Ω
Conversion
10
pF
Sampling
30
pF
See Figure 21
Ci
TYP
–1
3
1
μA
5
mA
3.6
V
Difference between the actual step width and the
ideal value. (See Figure 22)
±2
LSB
Integral nonlinearity error
Maximum deviation from the best straight line through
the MibADC. MibADC transfer characteristics,
excluding the quantization error.
(See Figure 23)
±2
LSB
Total error/Absolute accuracy
Maximum value of the difference between an analog
value and the ideal midstep value.
(See Figure 24)
±2
LSB
1 VCCAD = ADREFHI
2 1 LSB = (ADREFHI – ADREFLO)/210 for the MibADC
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
59
PRODUCT PREVIEW
ADREFHI
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
multi-buffered A-to-D converter (MibADC) (continued)
External
Rs
MibADC
Input Pin
Ri
Sample Switch
Parasitic
Capacitance
Vsrc
Sample
Capacitor
Rleak
Ci
PRODUCT PREVIEW
Figure 21. MibADC Input Equivalent Circuit
multi-buffer ADC timing requirements
MIN
NOM
MAX
UNIT
μs
tc(ADCLK)
Cycle time, MibADC clock
td(SH)
Delay time, sample and hold time
1
μs
td(C)
Delay time, conversion time
0.55
μs
td(SHC)(1)
Delay time, total sample/hold and conversion time
1.55
μs
0.05
1 This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for more details,
see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
60
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
multi-buffered A-to-D converter (MibADC) (continued)
The differential nonlinearity error shown in Figure 22 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
0 ...
0.
.. 100
0 ...
0.
.. 011
Differential
Linearity Error (1/2 LSB)
1 LSB
0 ...
0.
.. 010
0 ...
0.
.. 001
Differential Linearity
Error (–1/2 LSB)
1 LSB
0 ...
0.
.. 000
0
1
2
3
4
Analog Input Value (LSB)
5
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
Figure 22. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in Figure 23 (sometimes referred to as linearity error) is the deviation of
the values on the actual transfer function from a straight line.
0 ... 111
Digital Output Code
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(– 1/2 LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
0 ... 001
At Transition
001/010 (– 1/4 LSB)
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 23. Integral Nonlinearity (INL) Error
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
61
PRODUCT PREVIEW
Digital Output Code
0 ... 101
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
multi-buffer A-to-D converter (MibADC) (continued)
The absolute accuracy or total error of an MibADC as shown in Figure 24 is the maximum value of the difference
between an analog value and the ideal midstep value.
0 ... 111
Digital Output Code
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
PRODUCT PREVIEW
0 ... 001
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 24. Absolute Accuracy (Total) Error
62
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
144
0,13 NOM
37
1
PRODUCT PREVIEW
0,50
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°-7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 11
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
PARAMETER
°C/W
RΘJA
43
RΘJC
5
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
63
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
MECHANICAL DATA
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
PRODUCT PREVIEW
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°-7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
64
PARAMETER
°C/W
RΘJA
48
RΘJC
5
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
List of Figures
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
PRODUCT PREVIEW
TMS470R1VF288 144-Pin PGE Package (TOP VIEW) (without Expansion Bus)
TMS470R1VF288 144-Pin PGE Package (TOP VIEW) (with Expansion Bus)
TMS470R1VF288 100-Pin PZ Package (TOP VIEW)
Functional Block Diagram
Figure 1. TMS470R1VF288 Memory Map
Figure 2. JTAG Interface
Figure 3. TMS470R1x Family Nomenclature
Figure 4. Test Load Circuit
Figure 5. Crystal/Clock Connection
Figure 6. CLKOUT Timing Diagram
Figure 7. ECLK Timing Diagram
Figure 8. PORRST Timing Diagram
Figure 9. JTAG Scan Timings
Figure 10. CMOS-Level Outputs
Figure 11. CMOS-Level Inputs
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0)
Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock
Figure 18. I2C Timings
Figure 19. Expansion Memory Signal Timing - Reads
Figure 20. Expansion Memory Signal Timing - Writes
Figure 21. MibADC Input Equivalent Circuit
Figure 22. Differential Nonlinearity (DNL)
Figure 23. Integral Nonlinearity (INL) Error
Figure 24. Absolute Accuracy (Total) Error
Mechanical Data
Mechanical Data
65
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS095E – JULY 2004 – REVISED DECEMBER 2005
List of Tables
Device Characteristics
TMS470R1VF288 Memory Selection Assignment
VF288 Peripherals, System Module, and Flash Base Addresses
DMA Request Lines Connections
Interrupt Priority (IEM and CIM)
Expansion Bus Mux Mapping
Expansion Bus Pins
MibADC Event Hookup Configuration
TMS470 Device ID Bit Allocation Register
Device Part Number
I2C Signals (SDA and SCL) Switching Characteristics
PRODUCT PREVIEW
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
66
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
TMS470R1VF288
16/32-BIT RISC FLASH MICROCONTROLLER
REVISION HISTORY
REVISION HISTORY
REV
E
DATE
12/05
NOTES
Updates:
Page 44, temperature condition removed from twec parameter.
Page 44, note #2 revised.
Page 56, expansion bus timing parameters updated.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
67
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without
notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is
current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order
acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
application s using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is
an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.
Resale of TI products or services with statements different form or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Interface
Logic
Power Mgmt
Microcontrollers
Mailing Address:
Applications
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
Audio
Automotive
Broadband
Digital Control
Military
Optical Networking
Security
Telephony
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright © 2005, Texas Instruments Incorporated