January 5, 2012 Quad Class D Spatial Array General Description Features The LM48901 is a quad Class D amplifier that utilizes Texas Instruments’ proprietary spatial sound processor to create an enhanced sound stage for portable multimedia devices. The Class D output stages feature Texas Instruments’ edge rate control (ERC) PWM architecture that significantly reduces RF emissions while preserving audio quality and efficiency. The LM48901’s flexible I2S interface is compatible with standard serial audio interfaces. A stereo differential-input ADC gives the device the ability to process analog stereo audio signals. The LM48901 is configured through an I2C compatible interface and is capable of delivering 2.8W/channel of continuous output power into an 4Ω load with less than 10% THD+N. A 2.1 mode pairs two output drivers in parallel, increasing current drive for 4Ω loads. Output short circuit and thermal overload protection prevent the device from being damaged during fault conditions. Superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. The LM48901 is available in space saving microSMD and LLP packages. ■ ■ ■ ■ Key Specifications ■ SNR (A-Weighted) 87dBA (typ) ■ ■ ■ ■ ■ ■ Spatial Sound Processing I2S Compatible Input Differential-Input Stereo ADC Edge Rate Control Reduces EMI while Preserving Audio Quality and Efficiency Paralleled Output Mode Short Circuit and Thermal Overload Protection Minimum external components Click and Pop suppression Micro-power shutdown Available in space-saving micro SMD and LLP packages Applications ■ ■ ■ ■ ■ ■ ■ Laptops Tablets Desktop Computers Sound Bars Multimedia Devices MP3 Player Accessories Docking Stations ■ Output Power/channel, PVDD = 5V RL = 8Ω, THD+N ≤10% 1.7W (typ) RL = 4Ω, THD+N ≤10% 2.8W (typ) ■ THD+N 0.06% (typ) ■ Efficiency/Channel 89% (typ) ■ PSRR at 217Hz 71dB (typ) ■ Shutdown current 1μA (typ) Boomer® is a registered trademark of National Semiconductor Corporation. © 2012 Texas Instruments Incorporated 301692 SNAS520C www.ti.com LM48901 Quad Class D Spatial Array LM48901 LM48901 Typical Application 30169203 FIGURE 1. Typical Audio Amplifier Application Circuit www.ti.com 2 LM48901 30169209 FIGURE 2. Channel Audio Amplifier Application Circuit Only OUT2 and OUT3 can be configured in parallel. OUT1 and OUT4 cannot be configured in parallel. 3 www.ti.com LM48901 Connection Diagrams micro SMD Package 36–Bump micro SMD Marking 301692a5 Top View XY = Date code TT = Die traceability G = Boomer Family 02 = LM48901RL 30169202 Top View Order Number LM48901RL See NS Package Number RLA36JSA SQ Package 30169201 Top View Order Number LM48901SQ See NS Package Number SQA32A www.ti.com 4 LM48901 Ordering Information Ordering Information Table Package Package Drawing Number Transport Media MSL Level Green Status n LM48901RL 36–bump microSMD RLA36JSA 250 units on tape and reel 1 RoHS & no Sb/Br LM48901RLX 36–bump microSMD RLA36JSA 1000 units on tape and reel 1 RoHS & no Sb/Br LM48901SQ 32–pin LLP SQA32A 1000 units on tape and reel 1 RoHS & no Sb/Br LM48901SQE 32–pin LLP SQA32A 250 units on tape and reel 1 RoHS & no Sb/Br LM48901SQX 32–pin LLP SQA32A 4500 units on tape and reel 1 RoHS & no Sb/Br Order Number TABLE 1. Pin Descriptions BUMP PIN NAME DESCRIPTION A1 1 OUT4+ Channel 4 Non-Inverting Output A2, A5 2, 7 PVDD Class D Power Supply A3 4 OUT3+ Channel 3 Non-Inverting Output. Connect to OUT2+ in Parallel Mode. A4 5 OUT2+ Channel 2 Non-Inverting Output. Connect to OUT3+ in Parallel Mode. A6 8 OUT1+ Channel 1 Non-Inverting Output B1 31 OUT4- Channel 4 Inverting Output B2, B5 9, 32 PGND Power Ground B3 3 OUT3- Channel 3 Inverting Output. Connect to OUT2- in Parallel Mode. B4 6 OUT2- Channel 2 Inverting Output. Connect to OUT3- in Parallel Mode. B6 10 OUT1- Channel 1 Inverting Output C1 29 IOVDD Digital Interface Power Supply C2 28 DVDD Digital Power Supply C3 30 DGND Digital Ground C4 11 AGND1 Modulator Analog Ground C5 — AVDD3 ADC Reference Power Supply C6 12 AVDD1 Modulator Analog Power Supply. Set to same voltage as PVDD for maximum headroom. D1 27 SHDN Active Low Shutdown. Connect to VDD for normal operation. D2 26 I2C_EN I2C Enable Input D3 30 IOGND Digital Interface Ground D4 — AGND2 ADC Analog Ground D5 — PLLVDD PLL Power Supply D6 13 AVDD2 ADC Analog Power Supply E1 25 I2C_EX I2C Enable Output E2 23 WS I2S Word Select Input E3 20 SDA I2C Serial Data Input E4 18 INR- Right Channel Inverting Analog Input E5 15 INL- Left Channel Inverting Analog Input E6 14 REF ADC Reference Bypass F1 24 MCLK Master Clock F2 22 SCLK Serial Clock Input F3 21 SDIO I2S Serial Data Input/Output F4 19 SCL I2C Clock Input F5 17 INR+ Right Channel Non-Inverting Analog Input F6 16 INL+ Left Channel Non-Inverting Analog Input 5 www.ti.com LM48901 Absolute Maximum Ratings (Note 1, Note Thermal Resistance 2) θJA (LLP) 26°C/W θJC (LLP) 2.6°C/W θJA (microSMD) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. 26°C/W Operating Ratings Supply Voltage Temperature Range TMIN ≤ TA ≤ TMAX Supply Voltage AVDD, PVDD, PLVDD, IOVDD(Note 1) 6.0V Supply Voltage, DVDD (Note 1) 2.2V Storage Temperature −65°C to + 150°C −0.3V to VDD + 0.3V Input Voltage Power Dissipation (Note 3) Internally limited ESD Susceptibility (Note 4) 2000V ESD Susceptibility (Note 5) 150V Junction Temperature 150°C −40°C ≤ TA ≤ +85°C 2.7V ≤ AVDD ≤ 5.5V AVDD 2.7V ≤ PVDD ≤ 5.5V PVDD 2.7V ≤ PLLVDD ≤ 5.5V PLLVDD 1.62V ≤ IOVDD ≤ 5.5V IOVDD 1.62V ≤ DVDD ≤ 1.98V DVDD Electrical Characteristics PVDD = AVDD = 5V, IOVDD = PLLVDD = 3.3V, DVDD = 1.8 (Note 2, Note 8) The following specifications apply for AV = 0dB, CREF = 4.7µF, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C. LM48901 Symbol Parameter Conditions Min (Note 8) Typ (Note 7) Max (Note 8) Units (Limits) AVDD Analog Supply Voltage Range (Note 9) 2.7 5.5 V PVDD Amplifier Supply Voltage Range (Note 9) 2.7 5.5 V PLLVDD PLL Supply Voltage Range 2.7 5.5 V IOVDD Interface Supply Voltage Range 1.62 5.5 V DVDD Digital Supply Voltage Range 1.98 V LM48901RL 1.62 17.5 21 mA LM48901SQ 19.2 22.3 mA 8.25 mA AIDD Analog Quiescent Supply Current PIDD Amplifier Quiescent Supply Current RL = 8Ω 5.25 PLLIDD PLL Quiescent Supply Current LM48901RL 1.5 DIDD Quiescent Digital Power Supply Current ISD Shutdown Current (Analog, Amplifier and PLL Supplies) DISTBY Digital Standby Current DISD Digital Shutdown Current VOS Differential Output Offset Voltage VIN = 0 TWU Wake-up Time fSW Switching Frequency www.ti.com Shutdown Enabled Shutdown Enabled –17 Power Up (Device Initialization) mA 5.5 6.2 mA 1 5 μA 30 μA 2 μA 0 150 17 mV ms From Shutdown 30 ms fS = 48kHz 384 kHz 6 Parameter Conditions Min (Note 8) Typ (Note 7) Max (Note 8) Units (Limits) RL = 4Ω, THD+N = 10% f = 1kHz, 22kHz BW VDD = 5V 2.8 W VDD = 3.6V 1.4 W VDD = 5V 2.2 W VDD = 3.6V 1.2 W RL = 4Ω, THD+N = 1% f = 1kHz, 22kHz BW PO Output Power/Channel RL = 8Ω, THD+N = 10% f = 1kHz, 22kHz BW VDD = 5V 1.7 W VDD = 3.6V 825 mW 1.3 W 650 mW VDD = 5V 3.2 W VDD = 3.6V 1.6 W VDD = 5V 2.5 W VDD = 3.6V 1.2 W 0.06 % RL = 8Ω, THD+N = 1% f = 1kHz, 22kHz BW VDD = 5V 1.0 VDD = 3.6V RL = 4Ω, THD+N = 10%, f = 1kHz, 22kHz BW PO THD+N Output Power (Parallel Mode) (Note 10) RL = 4Ω, THD+N = 1%, f = 1kHz, 22kHz BW Total Harmonic Distortion + Noise PO = 500mW, f = 1kHz, RL = 8Ω VRIPPLE = 200mVP-P sine, Inputs AC GND, CIN = 1μF PSRR Power Supply Rejection Ratio (ADC Path) fRIPPLE = 217Hz, Applied to PVDD 67 dB fRIPPLE = 217Hz, Applied to DVDD 54 dB fRIPPLE = 1kHz, Applied to PVDD 66 dB fRIPPLE = 1kHz, Applied to DVDD 54 dB fRIPPLE = 10kHz, Applied to PVDD 57 dB fRIPPLE = 10kHz, Applied to DVDD 52 dB fRIPPLE = 217Hz, Applied to PVDD 71 dB fRIPPLE = 217Hz, Applied to DVDD 58 dB fRIPPLE = 1kHz, Applied to PVDD 69 dB fRIPPLE = 1kHz, Applied to DVDD 57 dB fRIPPLE = 10kHz, Applied to PVDD 70 dB fRIPPLE = 10kHz, Applied to DVDD 55 dB VRIPPLE = 1VP-P, fRIPPLE = 217Hz, AV = 0dB 60 dB VDD = 5V, PO = 1.1W 89 % VDD = 3.6V, PO = 400mW 87 % VDD = 5V, PO = 1.1W 87 % VDD = 3.6V, PO = 400mW 86 % ADC Input, PO = 1W 85 dB I2S Input, PO = 1W 87 dB VRIPPLE = 200mVP-P sine, Inputs –120dBFS PSRR Power Supply Rejection Ratio (I2S Path) CMRR Common Mode Rejection Ratio η Efficiency/Channel η SNR Efficiency Signal-to-Noise-Ratio 7 www.ti.com LM48901 LM48901 Symbol LM48901 LM48901 Symbol Parameter CMVR Common Mode Input Voltage Range εOS Output Noise XTALK Conditions Min (Note 8) Max (Note 8) Units (Limits) 5 V Inputs AC GND, A-weighted, AV = 0dB 130 μV I2S Input 72 μV 75 dB Crosstalk I2C Interface Characteristics Typ (Note 7) (Note 1, Note 2) The following specifications apply for RPU = 1kΩ to IOVDD, unless otherwise specified. Limits apply for TA = 25°C. LM48901 Symbol Parameter Conditions VIH Logic Input High Threshold SDA, SCL Min (Note 7) Typ (Note 6) 0.7*IOVDD VIL Logic Input Low Threshold SDA, SCL VOL Logic Output Low Threshold SDA, ISDA = 3.6mA IOH Logic Output High Current SDA, SCL 1 2 3 Units V 300 SCL Frequency Hold Time (repeated START Condition) Max (Note 7) mV 0.35 V 2 uA 400 kHz 0.6 µs Clock Low Time 1.3 µs Clock High Time 600 ns 4 Setup Time for Repeated START condition 600 ns 5 Data Hold Time 6 Data Setup Time 7 SDA Rise Time 300 ns 8 SDA Fall Time 300 ns 9 Setup Time for STOP Condition 600 ns 10 Bus Free Time Between STOP and START Condition 1.3 µs Output 300 900 100 ns ns I2S Timing Characteristics (Note 2, Note 8) The following specifications apply for DVDD = 1.8V, unless otherwise specified. Limits apply for TA = 25°C. LM48901 Symbol Parameter Conditions Min (Note 7) Typ (Note 6) Max (Note 7) Units (Limits) tMCLKL MCLK Pulse Width Low 16 ns tMCLKH MCLK Pulse Width High 16 ns tMCLKY MCLK Period 27 ns tBCLKR SCLK rise time 3 ns tBCLKCF SCLK fall time 3 ns tBCLKDS SCLK Duty Cycle 50 % TDL LRC Propagation Delay from SCLK falling edge TDST DATA Setup Time to SCLK Rising Edge 10 ns TDHT DATA Hold Time from SCLK Rising Edge 10 ns www.ti.com 10 8 ns Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX − TA) / θJA or the given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model, applicable std. JESD22-A114C. Note 5: Machine model, applicable std. JESD22-A115-A. Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 7: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 8: RL is a resistive load in series with two inductors to simulate an actual speaker load. For RL = 8Ω, the load is 15μH+8Ω+15μH. For RL = 4Ω, the load is 15μH+4Ω+15μH. Note 9: Maintain PVDD and AVDD at the same voltage potential. Note 10: Only OUT2 and OUT3 can be configured in Parallel Mode. 9 www.ti.com LM48901 Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. LM48901 Typical Performance Characteristics THD+N vs FREQUENCY VDD = 3.6V, POUT = 500mW, RL = 8Ω, ADC Input THD+N vs FREQUENCY VDD = 5V, POUT = 925 mW, RL = 8Ω, ADC Input 30169220 30169221 THD+N vs FREQUENCY VDD = 3.6V, POUT = 7505 mW, RL = 4Ω, ADC Input THD+N vs FREQUENCY VDD = 5V, POUT = 1.3W, RL = 4Ω, ADC Input 30169223 30169222 THD+N vs FREQUENCY VDD = 3.6V, POUT = 900mW, RL = 4Ω, ADC Input THD+N vs FREQUENCY VDD = 3.6V, POUT = 450mW, RL = 8Ω, I2S Input 30169224 www.ti.com 30169226 10 LM48901 THD+N vs FREQUENCY VDD = 5V, POUT = 950mW, RL = 8Ω, I2S Input THD+N vs FREQUENCY VDD = 3.6V, POUT = 750mW, RL = 4Ω, I2S Input 30169227 30169282 THD+N vs FREQUENCY VDD = 5V, POUT = 1.65W, RL = 4Ω, I2S Input THD+N vs FREQUENCY VDD = 3.6V, POUT = 850mW, RL = 4Ω, I2S Input 30169283 30169284 THD+N vs FREQUENCY VDD = 5V, POUT = 1.8W, RL = 4Ω, I2S Input THD+N vs OUTPUT POWER RL = 8Ω, f = 1kHz, ADC Input 30169210 30169285 11 www.ti.com LM48901 THD+N vs OUTPUT POWER RL = 4Ω, f = 1kHz, ADC Input, Single channel THD+N vs OUTPUT POWER RL = 8Ω, f = 1kHz, ADC Input 30169211 30169212 THD+N vs OUTPUT POWER RL = 4Ω, f = 1kHz, ADC Input, All channels THD+N vs OUTPUT POWER RL = 4Ω, f = 1kHz, ADC Input, Parallel mode 30169213 30169214 THD+N vs OUTPUT POWER RL = 8Ω, f = 1kHz, I2S Input, Single mode THD+N vs OUTPUT POWER RL = 4Ω, f = 1kHz, I2S Input, Single channel 30169215 www.ti.com 30169216 12 LM48901 THD+N vs OUTPUT POWER RL = 8Ω, f = 1kHz, I2S Input, All channels THD+N vs OUTPUT POWER RL = 4Ω, f = 1kHz, I2S Input, All channels 30169217 30169218 THD+N vs OUTPUT POWER RL = 4Ω, f = 1kHz, I2S Input, All channels THD+N vs OUTPUT POWER RL = 4Ω, f = 1kHz, I2S Input, Parallel mode 30169218 30169219 EFFICIENCY vs OUTPUT POWER RL = 8Ω, f = 1kHz, ADC Input, All channels EFFICIENCY vs OUTPUT POWER RL = 4Ω, f = 1kHz, ADC Input, All channels 30169286 30169287 13 www.ti.com LM48901 POWER DISSIPATION vs OUTPUT POWER RL = 8Ω, f = 1kHz, ADC Input POWER DISSIPATION vs OUTPUT POWER RL = 4Ω, f = 1kHz, ADC Input 30169288 30169289 OUTPUT POWER vs SUPPLY VOLTAGE RL = 4Ω, f = 1kHz, ADC Input, Single mode OUTPUT POWER vs SUPPLY VOLTAGE RL = 4Ω, f = 1kHz, ADC Input, Parallel mode 30169290 30169291 OUTPUT POWER vs SUPPLY VOLTAGE RL = 8Ω, f = 1kHz, ADC Input, Single channel PSRR vs FREQUENCY PVDD = 5V, VRIPPLE = 200mVP-P, RL = 8Ω, ADC Mode, ADC input = AC GND 30169292 301692a8 www.ti.com 14 LM48901 PSRR vs FREQUENCY DVDD = 1.8V, VRIPPLE = 200mVP-P, RL = 8Ω, ADC Mode, ADC input = AC GND PSRR vs FREQUENCY PVDD = 5V, VRIPPLE = 200mVP-P, RL = 8Ω, I2S mode, I2S input = –120dBFS 301692a9 301692b0 PSRR vs FREQUENCY DVDD = 1.8V, VRIPPLE = 200mVP-P, RL = 8Ω, I2S mode, I2S input = –120dBFS PSRR vs FREQUENCY VRIPPLE = 200mVP-P, RL = 8Ω, ADC mode 301692b1 30169297 SUPPLY CURRENT vs SUPPLY VOLTAGE (PVDD) RL = Open, ADC mode, All channels enabled SUPPLY CURRENT vs SUPPLY VOLTAGE (AVDD) RL = Open 30169299 30169298 15 www.ti.com LM48901 SUPPLY CURRENT vs SUPPLY VOLTAGE (PLVDD) ADC mode, All channels enabled SUPPLY CURRENT vs SUPPLY VOLTAGE (DVDD) RL = Open 301692a0 301692a1 SHUTDOWN CURRENT vs SUPPLY VOLTAGE SHUTDOWN CURRENT vs SUPPLY VOLTAGE (DVDD) 301692a2 301692a3 OUTPUT NOISE VS FREQUENCY PVDD = 5V, RL = 8Ω, ADC mode, ADC Input = AC GND OUTPUT NOISE VS FREQUENCY DVDD = 1.8V, RL = 8Ω, I2S mode, I2S Input = –120dBFS 301692b7 www.ti.com 301692b8 16 I2C COMPATIBLE INTERFACE The LM48901 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock and data lines are bi-directional (open drain). The LM48901 can communicate at clock rates up to 400kHz. Figure 3 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48901 is a transmit/receive device, and can act 30169240 FIGURE 3. I2C Timing Diagram 30169241 FIGURE 4. Start and Stop Diagram 17 www.ti.com LM48901 as the I2C master, generating the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition Figure 4. Due to the number of data registers, the LM48901 employs a page mode scheme. Each data write consists of 7, 8 bit data bytes, device address (1 byte), 16 bit register address (2 bytes), and 32 bit register data (4 bytes). Each byte is followed by an acknowledge pulse Figure 5. Single byte read and write commands are ignored. The LM48901 device address is 0110000X. Application Information LM48901 Once the master device registers the ACK bit, the first 8-bit register address word is sent, MSB first [15:8]. Each data bit should be stable while SCL is HIGH. After the first 8-bit register address is sent, the LM48901 sends another ACK bit. Upon receipt of acknowledge, the second 8-bit register address word is sent [7:0], followed by another ACK bit. The register data is sent, 8-bits at a time, MSB first in the following order [7:0], [15:8], [23:16], [31:24]. Each 8-bit word is followed by an ACK, upon receipt of which the successive 8-bit word is sent. Following the acknowledgement of the last register data word [31:24], the master issues a STOP bit, allowing SDA to go high while SDA is high. WRITE SEQUENCE The example write sequence is shown in Figure 5. The START signal, the transition of SDA from HIGH to LOW while SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus. The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0 indicating the master is writing to the LM48901). The data is latched in on the rising edge of the clock. Each address bit must be stable while SDA is HIGH. After the R/W\ bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48901 receives the correct address, the device pulls the SDA line low, generating and acknowledge bit (ACK). 30169205 FIGURE 5. Example I2C Write Sequence LM48901. Upon receipt of the acknowledge, the second 8-bit register address word is sent [7:0], followed by another ACK bit. Following the acknowledgement of the last register address, the master initiates a REPEATED START, followed by the 7-bit device address, followed by R/W = 1 (R/W = 1 indicating the master wants to read data from the LM48901). The LM48901 sends an ACK, followed by the selected register data. The register data is sent, 8-bits at a time, MSB first in the following order [7:0], [15:8], [23:16], [31:24]. Each 8-bit word is followed by an ACK, upon receipt of which the successive 8-bit word is sent. Following the acknowledgement of the last register data word [31:24], the master issues a STOP bit, allowing SDA to go high while SDA is high. READ SEQUENCE The example read sequence is shown in Figure 6. The START signal, the transition of SDA from HIGH to LOW while SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus. The 7-bit device address is written to the bus, followed by the R/W = 0. After the R/W bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48901 receives the correct address, the device pulls the SDA line low, generating and acknowledge bit (ACK). Once the master device registers the ACK bit, the first 8-bit register address word is sent, MSB first [15:8], followed by and ACK from the 30169206 FIGURE 6. Example I2C Read Sequence www.ti.com 18 301692b4 FIGURE 7. I2S Normal Input Format 301692b5 FIGURE 8. I2S Left Justified Input Format 301692b6 FIGURE 9. I2S Right Justified Input Format 19 www.ti.com LM48901 Mode, the audio data format is similar to the Normal Mode, without the delay between the LSB and the change in I2S_WS. In Right Justified Mode, the audio data MSB is transmitted after a delay of a preset number of bits. I2S DATA FORMAT The LM48901 supports three I2S formats: Normal Mode Figure 7, Left Justified Mode Figure 8, and Right Justified Mode Figure 9. In Normal Mode, the audio data is transmitted MSB first, with the unused bits following the LSB. In Left Justified LM48901 configuration settings, and a 48-bit wide Audio Sample Space that holds the current audio data sampled from either the ADCs or the I2S interface, organized as shown in Figure 10. MEMORY ORGANIZATION The LM48901 memory is organized into three main regions: a 32-bit wide Coefficient Space that holds the spatial coefficients, a 32-bit wide Register Space that holds the device 30169207 FIGURE 10. LM48901 Memory Organization Register 1 (0x504h) = 1 to enable Debug mode. The Coefficient Memory Space is organized as follows. COEFFICIENT MEMORY The device must be in Debug mode in order to write to the Coefficient memory. Set Bit 7 (DBG_ENABLE) in Filter Debug TABLE 2. Coefficient Memory Space REGISTER ADDRESS REGISTER CONTENTS (31:16) (15:0) 0x000h - 0x0FFh 256x16 bit Array Taps (Right Input to OUT4) 256x16 bit Array Taps (Left Input to OUT4) 0x100h - 0x1FFh 256x16 bit Array Taps (Right Input to OUT3) 256x16 bit Array Taps (Left Input to OUT3) 0x200h - 0x2FFh 256x16 bit Array Taps (Right Input to OUT2) 256x16 bit Array Taps (Left Input to OUT2) 0x300h - 0x3FFh 256x16 bit Array Taps (Right Input to OUT1) 256x16 bit Array Taps (Left Input to OUT1) 0x400h - 0x47Eh (EVEN) C2 128x16 bit Prefilter Taps (Right to Right) C0 128x16 bit Prefilter FIR Taps (Left to Left) 0x441h - 0x47Fh (ODD) C3 128x16 bit Prefilter Taps (Right to Left) C1 128x16 bit Prefilter FIR Taps (Left to Right) www.ti.com 20 LM48901 CONTROL REGISTERS TABLE 3. Register Map Register Name FILTER CONTROL FILTER COMP1 Register Address Default Value 0x500h [7:0] 0xFFh 0x500h [15:8] 0xFFh 0x500h [23:16] 0xE4h 0x500h [31:24] 0x31h 0x501h [7:0] 0x00h 0x501h [15:8] 0x00h 0x501h [23:16] 0x00h ARRAY_COMP_SELECT 0x501h [31:24] 0x00h UNUSED 0x502h [7:0] FILTER COMP2 FILTER DEBUG0 FILTER DEBUG1 FILTER STATS 7 6 5 4 3 2 1 0 ARRAY_TAP UNUSED PRE_TAP CH4_SEL ARRAY_ ENABLE PRE_ ENABLE CH3_SEL ARRAY_ BYPASS CH2_SEL PRE_ BYPASS UNUSED G1_GAIN UNUSED COMP_TH POST_GAIN UNUSED G1_GAIN 0x00h 0x00h 0x502h [23:16] 0x00h 0x502h [31:24] 0x00h 0x503h [7:0] 0xFFh DBG_DATA [7:0] 0x503h [15:8] 0xFFh DBG_DATA [15:8] 0x503h [23:16] 0xFFh DBG_DATA [23:16] 0x503h [31:24] 0xFFh DBG_ STEP 0x504h [7:0] 0xFFh DBG_ ENABLE 0x504h [15:8] 0xFFh UNUSED 0x504h [23:16] 0xFFh UNUSED 0x504h [31:24] 0xFFh UNUSED 0x505h [7:0] 0x00h 0x505h [15:8] 0x80h 0x505h [23:16] 0x00h 0x505h [31:24] 0x80h POST_GAIN UNUSED G1_GAIN UNUSED POST_GAIN UNUSED COMP_RATIO UNUSED STEP_ ENABLE UNUSE D UNUSED COUNT1_MODE CLEAR COMP_RATIO COMP_TH COUNT1_MODE CLEAR COMP_RATIO COMP_TH 0x502h [15:8] UNUSED CH1_SEL UNUSED 21 FILTER_ SELECT ACC_ADDR CH_SEL COUNT2_MODE CH_SEL COUNT2_MODE www.ti.com LM48901 Register Name FILTER TAP (READONLY) ACCUML DEBUG (READONLY) ACCUMH DEBUG (READONLY) DBG SAT (READONLY) STAT PCNT1 (READONLY) STAT PCNT2 (READONLY) www.ti.com Register Address Default Value 0x508h [7:0] 0x7Fh TAP_LENGTH 0x508h [15:8] 0x00h UNUSED 0x508h [23:16] 0x00h UNUSED 0x508h [31:24] 0x00h UNUSED 0x509h [7:0] 0x00h DBG_ACCL [7:0] 0x509h [15:8] 0x00h DBG_ACCL [15:8] 0x509h [23:16] 0x00h DBG_ACCL [23:16] 0x509h [31:24] 0x00h DBG_ACCL [31:24] 0x50Ah [7:0] 0x00h DBG_ACCH 0x50Ah [15:8] 0x00h BDG_ACCH 0x50Ah [23:16] 0x00h UNUSED 0x50Ah [31:24] 0x00h UNUSED 0x50Bh [7:0] 0x00h DBG_SAT [7:0] 0x50Bh [15:8] 0x00h DBG_SAT [15:8] 0x50Bh [23:16] 0x00h DBG_SAT [23:16] 0x50Bh [31:24] 0x00h UNUSED 0x50Ch [7:0] 0x00h COUNT [7:0] 0x50Ch [15:8] 0x00h COUNT [15:8] 0x50Ch [23:16] 0x00h COUNT [23:16] 0x50Ch [31:24] 0x00h 0x50Dh [7:0] 0x00h COUNT [7:0] 0x50Dh [15:8] 0x00h COUNT [15:8] 0x50Dh [23:16] 0x00h COUNT [23:16] 0x50Dh [31:24] 0x00h 7 6 5 OVF 4 3 COUNT [30:24] OVF COUNT [30:24] 22 2 1 0 STAT ACNT1 (READONLY) STAT ACNT2 (READONLY) SYS CONFIG CL REG0 CL REG1 E2_ OFFSET Register Address Default Value 0x50Eh [7:0] 0x00h COUNT [7:0] 0x50Eh [15:8] 0x00h COUNT [15:8] 0x50Eh [23:16] 0x00h COUNT [23:16] 0x50Eh [31:24] 0x00h 0x50Fh [7:0] 0x00h COUNT [7:0] 0x50Fh [15:8] 0x00h COUNT [15:8] 0x50Fh [23:16] 0x00h COUNT [23:16] 0x50Fh [31:24] 0x00h OVF COUNT [30:24] 0x530h [7:0] 0x30h CONFIG _CLK_ ENABLE DEVICE_ID 0x530h [15:8] 0x00h ALTID_ ENABLE ALT_DEVICE_ID 0x530h [23:16] 0x8Ch CL_ ENABLE 0x530h [31:24] 0x00h 0x531h [7:0] 0x00h TRANS_LENGTH [7:0] 0x531h [15:8] 0x10h TRANS_LENGTH [15:8] 0x531h [23:16] 0x00h REG_START_ADDR [7:0] 0x531h [31:24] 0x00h REG_START_ADDR [16:8] 0x532h [7:0] 0x00h E2_START_ADDR [7:0] 0x532h [15:8] 0x00h E2_START_ADDR [15:8] 0x532h [23:16] 0x00h UNUSED 0x532h [31:24] 0x00h UNUSED 0x533h [7:0] 0x00h 0x533h [15:8] 0x00h UNUSED 0x533h [23:16] 0x00h UNUSED 0x533h [31:24] 0x00h UNUSED 7 6 5 4 OVF 3 2 1 0 CL_W CL_REQ COUNT [30:24] UNUSED CL_PAGE MBIST1_ MBIST0_ ENABLE ENABLE UNUSED UNUSED E2_OFFSET 23 www.ti.com LM48901 Register Name LM48901 Register Name I2C_EnXT MBIST STAT (READONLY) DELAY ENABLE & CLOCKS DIGITAL MIXER ANALOG www.ti.com Register Address Default Value 7 6 0x534h [7:0] 0x00h I2C _EnXT UNUSED 0x534h [15:8] 0x00h UNUSED 0x534h [23:16] 0x00h UNUSED 0x534h [31:24] 0x00h UNUSED 0x538h [7:0] 0x7Fh 0x538h [15:8] 0x80h UNUSED 0x538h [23:16] 0x00h UNUSED 0x538h [31:24] 0x80h UNUSED 0x520h [7:0] 0x06h 0x520h [15:8] 0x00h 0x520h [23:16] 0x20h 0x520h [31:24] 0x09h 5 4 3 2 1 0 E2NXT_OFFSET UNUSED MBIST_EN MBIST_GO MBIST_DONE POWER_UP_DELAY [7:0] POWER_UP_DELAY [15:8] DEGLITCH_DELAY STATE_DELAY VREF_ DELAY 0x521h [7:0] 0x00h 0x521h [15:8] 0x00h 0x521h [23:16] 0x00h 0x521h [31:24] 0x00h 0x522h [7:0] 0x33h 0x522h [15:8] 0x33h 0x522h [23:16] 0x00h 0x522h [31:24] 0x00h 0x523h [7:0] 0x00h 0x523h [15:8] 0x00h 0x523h [23:16] 0x00h UNUSED 0x523h [31:24] 0x00h UNUSED UNUSED UNUSED QSA_ CLK_ STOP PULSE FORCE ENABLE PCM_ HIFI I2S_CLK MCLK_RATE CLK_SEL ADC_ SYNC UNUSED UNUSED ZERO_ CROSS MUTE ADC_LVL I2S_LVL UNUSED I2SB_ON I2SA_ON I2SB_TX_SEL I2SA_TX_SEL ADC_DS 2 I S_DSP P OUT3_SEL OUT2_SEL OUT1_SEL OUT4_SEL BYPASS _MOD AUTO _SD ADC TRIM UNUSED 24 ZERO _DIG ZERO_ ANA PARALLEL SE_MOD PMC_ TEST TSD_DIS ANA_LVL SCKT _DIS TST_SHT I2S PORT ADC TRIM CO-EF FICIENT READBACK (READONLY) READBACK (READONLY) Register Address Default Value 0x524h [7:0] 0x01h 0x524h [15:8] 0x00h 0x524h [23:14] 0x00h 0x524h [31:24] 0x00h UNUSED MONO_SYNC_WIDTH SYNC_RATE 0x525h [7:0] 0x00h TX_BIT TX_WIDTH RX_WIDTH 0x525h [15:8] 0x02h RX_ RX_ A/µLAW COMPAN D RX_MSB_POSITION RX _MODE 0x525h [23:16] 0x02h TX_ TX_ A/µLAW COMPAN D TX_MSB_POSITION TX _MODE 0x525h [31:24] 0x00h UNUSED 0x526h [7:0] 0x00h ADC_COMP_COEFF_C0 [7:0] 0x526h [15:8] 0x00h ADC_COMP_COEFF_C0 [15:8] 0x526h [23:14] 0x00h ADC_COMP_COEFF_C1 [7:0] 0x526h [31:24] 0x00h ADC_COMP_COEFF_C1 [15:8] 0x527h [7:0] 0x00h ADC_COMP_COEFF_C2 [7:0] 0x527h [15:8] 0x00h ADC_COMP_COEFF_C2 [15:8] 0x528h [7:0] 0x00h 0x528h [15:8] 0x00h 0x528h [23:14] 0x00h SPARE 0x528h [31:24] 0x00h UNUSED 0x529h [7:0] 0x00h 0x529h [15:8] 0x00h SPARE 0x529h [23:14] 0x00h UNUSED 0x529h [31:24] 0x00h UNUSED 7 6 SYNC_ MODE 5 STEREO_ CLOCK_ SYNC_ PHASE PHASE 4 3 SYNC _MS CLK_MS UNUSED 2 1 TX_ RX_ ENABLE ENABLE 0 STEREO HALF_CYCLE_DIVIDER SYNTH_ DENOM UNUSED I2SL _LVL CLIP UNUSED UNUSED I2SR _LVL CLIP ADCL _LVL CLIP THERMAL SHORT4 UNUSED SYNTH_NUM ADCR _LVL CLIP SHORT3 ADCL_ ADCR_ CLIP CLIP SHORT2 SHORT1 CE_STATE FILTER CONTROL REGISTER (0x500h) Configures the LM48901 Array and Pre-Array filters (Spatial Engine). The Filter Control Register sets the length of the Array and Pre-Array filter taps, and selects the filter channel source for each audio output. Set PRE_BYPASS and ARRAY_BYPASS to 1 to bypass the Spatial Engine, disabling the spatial effect without modifying the coefficients. Set PRE_ENABLE and ARRAY_ENABLE 25 www.ti.com LM48901 Register Name LM48901 to 1 to enable the Spatial Engine. Set PRE_ENABLE and ARRAY_ENABLE to 0 to disable the spatial engine. Disabling the Spatial Engine does not affect the register contents. Disable the Spatial Engine during coefficient programming. TABLE 4. Filter Control Register BIT NAME 7:0 ARRAY_TAP 14:8 PRE_TAP 15 UNUSED VALUE DESCRIPTION Array Filter Tap Length Pre-filter Tap Length. Pre-filter tap length should be less than or equal to the Array filter tap length Channel 1 Output Routing Selection 17:16 CH1_SEL 00 Array Filter Channel 0 Output Select 01 Array Filter Channel 1 Output Select 10 Array Filter Channel 2 Output Select 11 Array Filter Channel 3 Output Select Channel 2 Output Routing Selection 19:18 CH2_SEL 00 Array Filter Channel 0 Output Select 01 Array Filter Channel 1 Output Select 10 Array Filter Channel 2 Output Select 11 Array Filter Channel 3 Output Select Channel 3 Output Routing Selection 21:20 CH3_SEL 00 Array Filter Channel 0 Output Select 01 Array Filter Channel 1 Output Select 10 Array Filter Channel 2 Output Select 11 Array Filter Channel 3 Output Select Channel 4 Output Routing Selection 23:22 27:24 UNUSED 28 PRE_BYPASS 29 30 31 www.ti.com CH4_SEL ARRAY_BYPASS PRE_ENABLE ARRAY_ENABLE 00 Array Filter Channel 0 Output Select 01 Array Filter Channel 1 Output Select 10 Array Filter Channel 2 Output Select 11 Array Filter Channel 3 Output Select 0 Pre-Array filter not bypassed 1 Pre-Array filter bypassed 0 Array filter not bypassed 1 Array filter bypassed 0 Pre-Array filter disabled. Disable the Pre-Array Filter during filter and coefficient programming. Disabling the Pre-Array Filter does not affect the device memory contents. 1 Pre-Array filter enabled 0 Array filter disabled. Disable the Array Filter during filter and coefficient programming. Disabling the Array Filter does not affect the device memory contents. 1 Array filter enabled 26 LM48901 COMPRESSOR CONTROL REGISTER 1 (FILTER COMP1) (0x501h) TABLE 5. Compressor Control Register BIT NAME VALUE DESCRIPTION Pre-Filter Compressor Threshold 4:0 COMP_TH 00000 0 00001 0.3125 00010 0.0625 - - 10000 0.5 - - 11000 0.75 - - 11111 0.96875 Pre-Compression Gain (V/V) 7:5 G1_GAIN 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 256 Compression Ratio 000 10:8 11 COMP_RATIO 1:1 001 2:1 010 2.66:1 011 4:1 100 5.33:1 101 8:1 110 10.66:1 111 16:1 UNUSED Post Compression Gain (V/V) 14:12 15 POST_GAIN 000 1 001 1.25 010 1.5 011 2 100 2.5 101 3 110 4 111 8 UNUSED 27 www.ti.com LM48901 BIT 23:16 NAME VALUE DESCRIPTION Array Filter Compression Control Register Select. The Array Filter has four channels, each channel can choose one of two Array Filter Compression Threshold, Pre-Compression Gain, Compression Ratio, and Post Compression Gain settings from the FILTER_COMP2 register Table 4. ARRAY_COMP_SELECT 0000 31:24 Select Setting 0 - - 1111 Select Setting 1 UNUSED COMPRESSOR CONTROL REGISTER 2 (FILTER COMP2) (0x502h) TABLE 6. Compressor Control Register 2 BIT NAME VALUE DESCRIPTION Array Filter Compressor Threshold (Setting 0) 4:0 COMP_TH 00000 0 00001 0.03125 00010 0.0325 - - 10000 - 0.5 - 11000 - 0.75 - 11111 0.96875 Pre-Compression Gain (V/V) (Setting 0) 7:5 G1_GAIN 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 256 Compression Ratio (Setting 0) 10:8 11 www.ti.com COMP_RATIO 000 1:1 001 2:1 010 2.66:1 011 4:1 100 5.33:1 101 8:1 110 10.66:1 111 16:1 UNUSED 28 NAME VALUE LM48901 BIT DESCRIPTION Post Compression Gain (V/V) (Setting 0) 14:12 15 POST_GAIN 000 1 001 1.25 010 1.5 011 2 100 2.5 101 3 110 4 111 8 UNUSED Pre-Filter Compressor Threshold (Setting 1) 20:16 COMP_TH 00000 0 00001 0.03125 00010 0.0325 - - 10000 - 0.5 - 11000 - 0.75 - 11111 0.96875 Pre-Compression Gain (V/V) (Setting 1) 23:21 G1_GAIN 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 256 Compression Ratio (Setting 1) 24:26 27 COMP_RATIO 000 1:1 001 2:1 010 2.66:1 011 4:1 100 5.33:1 101 8:1 110 10.66:1 111 16:1 UNUSED Post Compression Gain (V/V) (Setting 1) 30:28 31 POST_GAIN 000 1 001 1.25 010 1.5 011 2 100 2.5 101 3 110 4 111 8 UNUSED 29 www.ti.com LM48901 FILTER DEBUG REGISTER 1 (FILT_DBG1) (0x504h) TABLE 7. Filter Debug Register 1 BIT NAME VALUE 3:0 ACC_ADDR 4 FILTER_SELECT 5 UNUSED 6 STEP_ENABLE 7 31:8 DESCRIPTION Accumulator Address. Selects which accumulator is read during debug mode 0 Selects Pre-Filter Accumulators 1 Selects Array Filter Accumulators 0 Single Step Disabled 1 Single Step Enabled 0 Debug Mode Disabled. Coefficient memory is inaccessible with Debug mode is disabled. 1 Debug Mode Enabled. Coefficient memory is accessible when Debug mode is enabled. DBG_ENABLE UNUSED FILTER STATISTICS CONTROL REGISTER (FILT_STC) (0x505h) TABLE 8. Filter Statistics Control Register BIT NAME VALUE DESCRIPTION PRE-FILTER Counter Channel Select 3:0 CH_SEL 000 Channel 0 001 Channel 1 010 Channel 2 011 Channel 3 100 Channel 4 101 Channel 5 110 Channel 6 111 Channel 7 Counter 1 Mode Select. Specifies input of Counter 1 7:4 www.ti.com COUNT1_MODE 0000 Sample Count Mode. Every audio sample is counted 0001 Overflow. Overflow events counted 0010 Frequency Error. Indicates input frequency not sufficient for given filter length 1000 MAGN[7} 1001 MAGN[7:6] 1010 MAGN[7:5} 1011 MAGN[7:4} 1100 MAGN[7:3} 1101 MAGN[7:2] 1110 MAGN[7:1} 1111 MAGN[7:0] 30 NAME VALUE DESCRIPTION Counter 2 Mode Select. Specifies input of Counter 2 11:8 COUNT2_MODE 14:12 UNUSED 15 CLEAR 0000 Sample Count Mode. Every audio sample is counted 0001 Overflow. Overflow events counted 0010 Frequency Error. Indicates input frequency not sufficient for given filter length 1000 MAGN[7} 1001 MAGN[7:6] 1010 MAGN[7:5} 1011 MAGN[7:4} 1100 MAGN[7:3} 1101 MAGN[7:2] 1110 MAGN[7:1} 1111 MAGN[7:0] 0 Counter Enabled 1 Counter Cleared ARRAY-FILTER Counter Channel Select 19:16 CH_SEL 000 Channel 0 001 Channel 1 010 Channel 2 011 Channel 3 100 Channel 4 101 Channel 5 110 Channel 6 111 Channel 7 Counter 1 Mode Select. Specifies input of Counter 1 23:20 COUNT1_MODE 0000 Sample Count Mode. Every audio sample is counted 0001 Overflow. Overflow events counted 0010 Frequency Error. Indicates input frequency not sufficient for given filter length 1000 MAGN[7} 1001 MAGN[7:6] 1010 MAGN[7:5} 1011 MAGN[7:4} 1100 MAGN[7:3} 1101 MAGN[7:2] 1110 MAGN[7:1} 1111 MAGN[7:0] 31 www.ti.com LM48901 BIT LM48901 BIT NAME VALUE DESCRIPTION Counter 2 Mode Select. Specifies input of Counter 2 27:24 COUNT2_MODE 30:28 UNUSED 31 CLEAR 0000 Sample Count Mode. Every audio sample is counted 0001 Overflow. Overflow events counted 0010 Frequency Error. Indicates input frequency not sufficient for given filter length 1000 MAGN[7} 1001 MAGN[7:6] 1010 MAGN[7:5} 1011 MAGN[7:4} 1100 MAGN[7:3} 1101 MAGN[7:2] 1110 MAGN[7:1} 1111 MAGN[7:0] 0 Counter Enabled 1 Counter Cleared DELAY REGISTER (DELAY) (0x520h) TABLE 9. Delay Register BIT NAME 15:0 POWER_UP_DELAY 23:16 DEGLITCH_DELAY 31:24 STATE_DELAY VALUE DESCRIPTION Sets I2C Delay Time. Default 10ms delay. Sets ENABLE Bit Polling Timeout. Default 32ms delay Sets Delay Between Power Up/Down States ENABLE AND CLOCK CONFIGURATION REGISTER (ENABLE & CLOCKS) (0x521h) TABLE 10. Enable and Clock Configuration Register BIT NAME 0 ENABLE 1 FORCE 2 PULSE 3 RELY_ON_VREF 7:4 UNUSED VALUE DESCRIPTION 0 Device Disabled in I2C Mode 1 Device Enabled in I2C Mode 0 Device Enabled Via SHDN <<overbar>> Pin 1 Device Enabled Via I2C 0 SHDN<<overbar>> Requires a Stable Logic Level 1 SHDN<<overbar>> Accepts a Pulse Input 0 Device waits for delay time determined by STATE_DELAY to enable. 1 Device waits for stable VREF Selects PLL Input Divider 000 10:8 MCLK_RATE 32fs (1.536MHz) 001 64fs (3.072MHz) 010 128fs (6.114MHz) 011 256fs (12.288MHz) 100 512fs (24.576MHz) 101 UNUSED 110 UNUSED 111 11 www.ti.com I2S_CLK UNUSED 0 MCLK Input to PLL 1 I2S_CLK Input to PLL 32 NAME 12 PMC_CLK_SEL 13 HIFI 14 QSA_CLK_STOP 15 UNUSED 16 ADC_SYNC_SEL 31:17 UNUSED VALUE DESCRIPTION 0 Oscillator Clock Input to Power Management Circuitry 1 External Clock to Power Management Circuitry. Power management circuit uses MCLK or I2S_CLK. Clock source depends on the state of I2S_CLK. External Clock mode disables the internal oscillator. 0 HiFi Mode Disabled 1 HiFi Mode Enabled. PLL always produces a 4096fs clock. 0 QSA Clock Enabled 1 QSA Clock Disabled Following Device Configuration 0 Normal Operation 1 Reverse ADC SYNC Signal for additional timing margin at low supply voltages. DIGITAL MIXER CONTROL REGISTER (DIGITAL MIXER) (0x522h) TABLE 11. Digital Mixer Control Register BIT NAME VALUE DESCRIPTION Sets the Gain of the ADC Path (dB) 000000 5:0 6 7 ADC_LVL MUTE ZXD_DISABLE -76.5 000001 -75 - 1.5dB steps 110010 -1.5 110011 0 110100 1.5 - 1.5dB Steps 111111 18 0 Normal Operation 1 Mute 0 Zero Crossing Detection Enabled 1 Zero Crossing Detection Disabled Sets the Gain of the I2S Path (dB) 000000 13:8 I2S_LVL 15:14 UNUSED 16 I2S_DSP 17 ADC_DSP -76.5 000001 -75 - 1.5dB steps 110010 -1.5 110011 0 (VOUT = 3.36VRMS with 0dBFS input) 110100 1.5 - 1.5dB Steps 111111 18 0 I2S Data Not Passed to DSP 1 I2S Data Passed to DSP 0 ADC Output Not Passed to DSP 1 ADC Output Passed to DSP 33 www.ti.com LM48901 BIT LM48901 BIT NAME VALUE DESCRIPTION Selects Input of Primary I2S Transmitter 19:18 ISA_TX_SEL 00 None 01 ADC 10 DSP1/2 11 DSP3/4 Selects Input of Secondary I2S Transmitter 21:20 ISB_TX_SEL 22 I2SA_ON 23 I2SB_ON 00 None 01 ADC 10 DSP1/2 11 DSP3/4 0 I2SA Data NOT Output on SHDN 1 I2SA Data Output on SHDN 0 I2SB Data NOT Output on SHDN 1 I2SB Data Output on SHDN Selects OUT1 Amplifier Input Source 25:24 OUT1_SEL 00 OUT1 Disabled 01 DSP 10 I2S 11 ADC Selects OUT2 Amplifier Input Source 27:26 OUT2_SEL 00 OUT2 Disabled 01 DSP 10 I2S 11 ADC Selects OUT3 Amplifier Input Source 29:28 OUT3_SEL 00 OUT3 Disabled 01 DSP 10 I2S 11 ADC Selects OUT4 Amplifier Input Source 31:30 OUT4_SEL 00 OUT4 Disabled 01 DSP 10 I2S 11 ADC ANALOG CONFIGURATION REGISTER (ANALOG) (0x523h) TABLE 12. Analog Configuration Register BIT NAME VALUE DESCRIPTION Sets ADC Preamplifier Gain (dB) 1:0 ANA_LVL 00 0 01 2.4 10 3.5 11 2 www.ti.com 6 0 Normal Operation. OUT2 and OUT3 operate as separate amplifiers. 1 Parallel Operation. OUT2 and OUT3 operate in parallel as a single amplifier. PARALLEL 34 NAME 3 ZERO_ANA 4 ZERO_DIG 5 ADCTRIM 6 AUTO_SD 7 BYPASS_MOD 8 TST_SHT 9 SCKT_DIS 10 TSD_DIS 11 PMC_TEST 12 SE_MOD 31:13 UNUSED VALUE LM48901 BIT DESCRIPTION 0 Normal Operation 1 Auto-Shutdown Mode. Automatically disables the amplifiers when no analog input is detected. 0 Normal Operation 1 Auto-Shutdown Mode. Automatically disables the amplifiers when there is no I2S input. 0 ADC Trim Disabled 1 ADC Trim Enabled. Use ADC_COMP_COEFF_C0-C2 to trim ADC. 0 Normal Operation 1 Fault Conditions Disable the Amplifiers 0 Normal Operation 1 Pulse Correction Bypass. Amplifier output stages act as a buffer, passing PWM signal without correction to output. 0 Normal Operation 1 Short Amplifier Inputs. Sets amplifier outputs to 50% duty cycle, minimizing click and pop during power up/ down. 0 Normal Operation 1 Output Short Circuit Protection Disabled 0 Normal Operation 1 Thermal Shutdown Disabled 0 Normal Operation 1 PMC uses PLL Source Clock 0 Normal Operation 1 Single Edge Modulation Mode I2S PORT CONFIGURATION REGISTER (I2S PORT) (0x524h/0x525h) TABLE 13. BIT NAME VALUE DESCRIPTION 0x524h 0 STEREO 1 RX_ENABLE 2 3 4 5 TX_ENABLE 0 Mono Mode 1 Stereo Mode 0 Receive Mode Disabled 1 Receive Mode Enabled 0 Transmit Mode Disabled 1 Transmit Mode Enabled 0 I2S Clock Slave. Device requires an external SCLK for proper operation. 1 I2S Clock Master. Device generates SCLK and transmits when either RX or TX mode are enabled. 0 I2S WS Slave. Device requires an external WS for proper operation. 1 I2S WS Master. Device generates WS and transmits when either RX or TX mode are enabled. 0 I2S Clock Phase. Transmit on falling edge, receive on rising edge. 1 PCM Clock Phase. Transmit on rising edge, receive on falling edge. CLK_MS SYNC_MS CLOCK_PHASE 35 www.ti.com LM48901 BIT NAME VALUE DESCRIPTION 6 STEREO_SYNC _PHASE 0 I2S Data Format: Left, Right 1 I2S Data Format: Right, Left Mono 7 SYNC_MODE Rising edge indicates start of data word. 0 SYNC low = Left, SYNC high = Right 1 SYNC low = Right, SYNC high = left Configures the I2S port master clock half-cycle divider. Program the half-cycle divider by: (ReqDiv*2) 1 000000 13:8 15:14 HALF_CYCLE _DIVIDER BYPASS 000001 1 000010 1.5 000011 2 - - 111101 31 111110 31.5 111111 32 UNUSED Sets the Clock Generator Numberator 18:16 SYNTH_NUM 000 SYNTH_DENOM (1/) 001 100/SYNTH_DENOM 010 96/SYNTH_DENOM 011 80/SYNTH_DENOM 100 72/SYNTH_DENOM 101 64/SYNTH_DENOM 110 48/SYNTH_DENOM 111 19 SYNTH_DENOM 23:20 UNUSED 0/SYNTH_DENOM 0 Clock Generator Denominator = 128 1 Clock Generator Denominator = 125 Sets number of clock cycles before SYNC pattern repeats. MONO MODE 26:24 SYNC_RATE 000 8 001 12 010 16 011 18 100 20 101 24 110 25 111 32 STEREO MODE www.ti.com 000 16 01 24 010 32 011 36 100 40 101 48 110 50 111 64 36 NAME VALUE LM48901 BIT DESCRIPTION Sets SYNC symbol width in Mono Mode 29:27 31:30 MONO_SYNC_WIDTH 000 1 001 2 010 4 011 7 100 8 101 11 110 15 111 16 UNUSED 0x525h Sets number of valid RECEIVE bits. 2:0 RX_WIDTH 000 24 001 20 010 18 011 16 100 14 101 13 110 12 111 8 Sets number of TRANSMIT bits. 5:3 TX_WIDTH 000 24 001 20 010 18 011 16 100 14 101 13 110 12 111 8 Sets number of pad bits after the valid Transmit bits. 7:6 TX_BIT 00 0 01 1 10 High-Z 11 8 RX_MODE High-Z 0 MSB Justified Receive Mode 1 LSB Justified Receive Mode 37 www.ti.com LM48901 BIT NAME VALUE DESCRIPTION MSB location from the frame start (MSB Justified) or LSB location from the frame end (LSB Justified) 13:9 14 15 16 www.ti.com RX_MSB_POSITION RX_COMPAND RX_A/µLAW TX_MODE 00000 0 (DSP/PCM LONG) 00001 1 (I2S/PCM SHORT) 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 17 10010 18 10011 19 10100 20 10101 21 10110 22 10111 23 11000 24 11001 25 11010 26 11011 27 11100 28 11101 29 11110 30 11111 31 0 Normal Operation 1 Audio Data Companded 0 µLaw Compand Mode 1 A-Law Compand Mode 0 MSB Justified Transmit Mode 1 LSB Justified Transmit Mode 38 NAME VALUE DESCRIPTION MSB location from the frame start (MSB Justified) or LSB location from the frame end (LSB Justified) 21:17 22 TX_MSB_POSITION TX_COMPAND 23 TX_A/µLAW 31:24 UNUSED 00000 0 (DSP/PCM LONG) 00001 1 (I2S/PCM SHORT) 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 17 10010 18 10011 19 10100 20 10101 21 10110 22 10111 23 11000 24 11001 25 11010 26 11011 27 11100 28 11101 29 11110 30 11111 31 0 Normal Operation 1 Audio Data Companded 0 µLaw Compand Mode 1 A-Law Compand Mode 39 www.ti.com LM48901 BIT LM48901 ADC TRIM COEFFICIENT REGISTER (ADC_TRIM) (0x526h/0x527) TABLE 14. ADC Trim Coefficient Register BIT NAME VALUE 15:0 ADC_COMP_COEFF_C0 31:16 ADC_COMP_COEFF_C1 DESCRIPTION 0x526h Sets ADC Trim Coefficient C0 Sets ADC Trim Coefficient C1 0x527h 15:0 ADC_COMP_COEFF_C2 Sets ADC Trim Coefficient C2 READBACK REGISTER (READBACK) (0x528h) READ-ONLY TABLE 15. Readback Register www.ti.com BIT NAME VALUE 0 ADCR_CLIP 1 Right Channel ADC Input Clipped DESCRIPTION 1 ADCL_CLIP 1 Left Channel ADC Input Clipped 2 ADCR_LVLCLIP 1 Right Channel ADC Output Clipped 3 ADCL_LVLCLIP 1 Left Channel ADC Output Clipped 4 I2SR_LVLCLIP 1 Right Channel I2S Output Clipped 5 I2SL_LVLCLIP 1 Left Channel I2S Output Clipped 7:6 UNUSED 8 SHORT1 1 OUT1 Output Short Circuit 9 SHORT2 1 OUT2 Output Short Circuit 10 SHORT3 1 OUT3 Output Short Circuit 11 SHORT4 1 OUT4 Output Short Circuit 12 THERMAL 1 Thermal Shutdown Threshold Exceeded 23:13 SPARE 31:24 UNUSED 40 LM48901 SYSTEM CONFIGURATION REGISTER (SYS_CONFIG) (0x530h) TABLE 16. System Configuration Register BIT NAME VALUE 6:0 DEVICE_ID 7 CONFIG_CLK _ENABLE 14:8 ALT_DEVICE_ID 15 ALTID_ENABLE 16 17 DESCRIPTION Sets LM48901 Device ID in slave mode 0 Configuration Loader Clock Disabled 1 Configuration Loader Clock Enabled Sets Alternate Device ID in Slave Mode. 0 Selects DEVICE_ID 1 Selects ALT_DEVICE_ID 0 Configuration Loader Access not Requested 1 Configuration Loader Access Requested. I2C Master Transaction Enabled 0 Configuration Loader Set to READ-ONLY 1 Configuration Loader Set to WRITE CL_REQ CL_W Sets I2C Page Mode Length 20:18 22:21 23 CL_PAGE 00 Single Byte 01 4 Bytes 10 8 Bytes 11 16 Bytes 0 Device Configured as I2C Slave 1 Device Configured as I2C Master 0 Memory BIST Controller 0 Disabled 1 Memory BIST Control 0 Enabled. 0 Memory BIST Controller 1 Disabled 1 Memory BIST Control 1 Enabled. UNUSED CL_ENABLE 24 MBIST0_ENABLE 25 MBIST1_ENABLE 31:26 UNUSED I2C MASTER CONFIGURATION LOADER REGISTER 0 (CL_REG0) (0x531h) TABLE 17. Filter Debug Register 0 BIT NAME 15:0 TRANS_LENGTH VALUE 31:16 REG_START_ADDR DESCRIPTION Sets I2C Master Transaction Length Starting Address of LM48901 Memory I2C MASTER CONFIGURATION LOADER REGISTER 1 (CL_REG1) (0x532h) TABLE 18. Filter Debug Register 1 BIT NAME VALUE 15:0 E2_START_ADDR 31:16 UNUSED DESCRIPTION Sets EEPROM Address. Indicates EEPROM start address where data is stored EEPROM ADDRESS OFFSET REGISTER (E2_OFFSET) (0x533h) TABLE 19. EEPROM Address Offset Register BIT NAME 5:0 E2_OFFSET 31:6 UNUSED VALUE DESCRIPTION EEPROM Address Offset Value. 41 www.ti.com LM48901 I2C EnXT REGISTER (I2CEnXT) (0x534h) TABLE 20. I2C EnXT Register BIT NAME 5:0 E2NXT_OFFSET 6 UNUSED 7 31:8 VALUE DESCRIPTION Sets EEPROM Address Offset for Following LM48901 when devices are Daisy Chained. 0 Next Device in Daisy Chain Disabled. I2C_EX driven Low. 1 Next Device in Daisy Chain Enabled. I2C_EX driven HIGH. I2C_EnXT UNUSED READ-ONLY MBIST STATUS REGISTER (MBIST_STAT) (0x538h) TABLE 21. MBIST Status Register BIT NAME 1:0 MBIST_DONE 3:2 BIST_GO 5:4 MBIST_EN 31:6 UNUSED VALUE DESCRIPTION Logic HIGH indicates memory test complete Logic Low indicates memory fault when MBIST_DONE is HIGH 0 MBIST Read-back Disabled 1 MBIST Read-back Enabled DAISY CHAINING I2C_EN/I2C_EX The LM48901 supports daisy chaining up to 127 devices from a single I2C bus utilizing I2C_EN and I2C_EX in a chain enable scheme. I2C_EX is a push/pull logic output that drives the I2C_EN of the following device in the chain Figure 11. At power up, I2C_EnXT (bit 8, I2C_EnXT Register [0x534h]) is set to 0, resulting in I2C_EN driven low, disabling the I2C interface of the following device. Once device configuration is complete, and I2C_EnXT is set to 1, I2C_EN is driven high, enabling the I2C interface of the following device. Driving I2C_EN high enables the device’s I2C interface, driving I2C_EN low disables the device’s I2C interface. www.ti.com 42 LM48901 30169208 FIGURE 11. I2C_EN/I2C_EX Daisy Chaining Example Device Address The 0110000X is the default LM48901 I2C address hard coded into the device. Two alternate device addresses can be programmed, via the SYS CONFIG (0x530h) Register. Use the default address during initial device configuration. 43 www.ti.com LM48901 GENERAL AMPLIFIER FUNCTION Class D Amplifier The LM48901 features four high-efficiency Class D audio power amplifiers that utilizes Texas Instruments’ filterless modulation scheme external component count, conserving board space and reducing system cost. The Class D outputs transition from VDD to GND with a 384kHz switching frequency. With no signal applied, the outputs switch with a 50% duty cycle, in phase, causing the two outputs to cancel. This cancellation results in no net voltage across the speaker, thus there is no current to the load in the idle state. With the input signal applied, the duty cycle (pulse width) of the LM48901 outputs changes. For increasing output voltage, the duty cycle of OUT_+ increases while the duty cycle of OUT_- decreases. For decreasing output voltages, the converse occurs. The difference between the two pulse widths yield the differential output voltage. Edge Rate Control (ERC) The LM48901 features Texas Instruments’ advanced edge rate control (ERC) that reduces EMI, while maintaining high quality audio reproduction and efficiency. The LM48901 ERC greatly reduces the high frequency components of the output square waves by controlling the output rise and fall times, slowing the transitions to reduce RF emissions, while maximizing THD+N and efficiency performance. The overall result of the E2S system is a filterless Class D amplifier that passes FCC Class B radiated emissions standards with 24in of twisted pair cable, with excellent 0.06% THD+N and high 89% efficiency. POWER DISSIPATION AND EFFICIENCY The major benefit of a Class D amplifier is increased efficiency versus a Class AB. The efficiency of the LM48901 is attributed to the region of operation of the transistors in the output stage. The Class D output stage acts as current steering switches, consuming negligible amounts of power compared to their Class AB counterparts. Most of the power loss associated with the output stage is due to the IR loss of the MOSFET on-resistance, along with switching losses due to gate charge. ANALOG INPUT The LM48901 features a differential input, stereo ADC for analog systems. A differential amplifier amplifies the difference between the two input signals. Traditional audio power amplifiers have typically offered only single-ended inputs resulting in a 6dB reduction of SNR relative to differential inputs. The LM48901 also offers the possibility of DC input coupling which eliminates the input coupling capacitors. A major benefit of the fully differential amplifier is the improved common mode rejection ratio (CMRR) over single ended input amplifiers. The increased CMRR of the differential amplifier reduces sensitivity to ground offset related noise injection, especially important in noisy systems. PARALLEL MODE In Parallel mode, channels OUT2 and OUT3 are driven from the same audio source, allowing the two channels to be connected in parallel, increasing output power to 3.2W into 4Ω at 10% THD+N. Set bit 2 (PARALLEL) of the Analog Configuration Register (0x532h) = 1 to configured the device in Parallel mode. After the device is set to Parallel mode, make an external connection between OUT2+ and OUT3+, and a connection between OUT2- and OUT3- (Figure 2). In Parallel mode, the combined channels are driven from the OUT2 source. OUT1 and OUT4 are unaffected. Signal routing, mixing, filtering, and equalization are done through the Spatial Engine. Make sure the device is configured in Parallel mode, before connecting OUT2 and OUT3 and enabling the outputs. Do not make a connection between OUT2 and OUT3 together while the outputs are enabled. Disable the outputs first, then make the connections between OUT2 and OUT3. GAIN SETTING The LM48901 has three gain stages, the ADC preamplifier, and two independent volume controls in the Digital Mixer, one for the ADC path and one for the I2S path. The ADC preamplifier has four gain settings (0dB, 2.4dB, 3.5dB, and 6dB). The preamplifier gain is set by bits 0 and 1 (ANA_LVL) of the Analog Configuration Register (0x523h). The Digital Mixer has two 64 step volume controls. The ADC path volume control is set by bits 5:0 (ADC_LVL) in the Digital Mixer Control Register (0x522h). The I2S path volume control is set by bits 13:8 (I2S_LVL) in the Digital Mixer Control Register (0x522h). Both volume controls have a range of -76.5dB to 18dB in 1.5dB increments. www.ti.com 44 The AVDD1 (RL package: bump C2, SQ package: pin 12) powers the class D modulators. For maximum output swing, set AVDD1 and PVDD to the same voltage. Table 22 shows the output voltage for different AVDD1 levels. TABLE 22. Amplifier Output Voltage with Variable AVDD1 Voltage AVDD1 (V) VOUT (VRMS) @ PVDD = 5V, THD+N = 1% VOUT (VRMS) @ PVDD = 3.6V, THD+N = 1% 5 3.3 - 4.5 3.1 - 4.2 2.9 - 4 2.7 - 3.6 2.5 2.4 3.3 2.3 2.2 3 2.1 2.1 2.8 2 1.9 CLOCK REQUIREMENTS The LM48901 requires an external clock source for proper operation, regardless of input source or device configuration. The device derives the ADC, digital mixer, DSP, I2S port, and PWM clocks from the external clock. The clock can be derived from either MCLK or SCLK inputs. Set bit 11 (I2S_CLK) of the Enable and Clock configuration register (0x521h) to 0 to select MCLK, set I2S_CLK to 1 to select SCLK. The LM48901 accepts five different clock frequencies, 1.536, 3.072, 6.114, 12.288, and 24.576MHz. Set bits 10:8 (MCLK_RATE) of the Enable and Clock Configuration Register to the appropriate clock frequency. In systems where both MCLK and SCLK are available, choose the lower frequency clock for improved power consumption. SHUTDOWN FUNCTION There are two ways to shutdown the LM48901, hardware mode, and software mode. The default is hardware mode. Set bit 1 (FORCE) of the Enable and Clock Configuration Register (0x521h) to 0 to enable hardware shutdown mode. In hardware mode, the device is enabled and disabled through SHDN. Connect SHDN to VDD for normal operation. Connect SHDN to GND to disable the device. Hardware shutdown mode supports a one shot, or momentary switch SHDN input. When bit 2 (PULSE) of the Enable and Clock Configuration Register (0x521h) is set to 1, the LM48901 responds to a rising edge on SHDN to change the device state. When PULSE = 0, the device requires a stable logic level on SHDN. Set FORCE = 1 to enable software shutdown mode. In software shutdown mode, the device is enabled and disabled through bit 0 (ENABLE) of the Enable and Clock Configuration Register (0x512h). Set ENABLE = 0 to disable the LM48901. Set ENABLE = 1 to enable the LM48901. In either hardware or software mode, the content of the LM48901 memory registers is retained after the device is disabled, as long as power is still applied to the device. Minimize power consumption by disabling the PMC clock oscillator when the LM48901 is shutdown. Set bit 12 (PMC_CLK_SEL) and bit 14 (QSA_CLK_STOP) of the Enable and Clock configuration Register (0x521h) = 1 to disable the PMC clock oscillator. EXTERNAL CAPACITOR SELECTION Power Supply Bypassing and Filtering Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Typical applications employ a voltage regulator with 10μF and 0.1μF bypass capacitors that increase supply stability. These capacitors do not eliminate the need for bypassing of the LM48901 supply pins. A 1μF capacitor is recommended for IOVDD, PLLVDD, DVDD, and AVDD. A 2.2μF capacitor is recommended for PVDD. REF and BYPASS Capacitor Selection For best performance, bypass REF with a 4.7μF ceramic capacitor. 45 www.ti.com LM48901 MODULATOR POWER SUPPLY (AVDD1) LM48901 INPUT CAPACITOR SELECTION The LM48901 analog inputs require input coupling capacitors. Input capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the LM48901. The input capacitors create a high-pass filter with the input resistors RIN. The -3dB point of the high pass filter is found using Equation (1) below. f = 1 / 2πRINCIN Where the value of RIN is 20kΩ. The input capacitors can also be used to remove low frequency content from the audio signal. Small speakers cannot reproduce, and may even be damaged by low frequencies. High pass filtering the audio signal helps protect the speakers. When the LM48901 is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR. PCB LAYOUT GUIDELINES As output power increases, interconnect resistance (PCB traces and wires) between the amplifier, load, and power supply create a voltage drop. The voltage loss due to the traces between the LM48901 and the load results in lower output power and decreased efficiency. Higher trace resistance between the supply and the LM48901 has the same effect as a poorly regulated supply, increasing ripple on the supply line, and reducing peak output power. The effects of residual trace resistance increases as output current increases due to higher output power, decreased load impedance or both. To maintain the highest output voltage swing and corresponding peak output power, the PCB traces that connect the output pins to the load and the supply pins to the power supply should be as wide as possible to minimize trace resistance. The use of power and ground planes will give the best THD+N performance. In addition to reducing trace resistance, the use of power planes creates parasitic capacitors that help to filter the power supply line. The inductive nature of the transducer load can also result in overshoot on one of both edges, clamped by the parasitic diodes to GND and VDD in each case. From an EMI standpoint, this is an aggressive waveform that can radiate or conduct to other components in the system and cause interference. In is essential to keep the power and output traces short and well shielded if possible. Use of ground planes beads and micros-strip layout techniques are all useful in preventing unwanted interference. As the distance from the LM48901 and the speaker increases, the amount of EMI radiation increases due to the output wires or traces acting as antennas become more efficient with length. Ferrite chip inductors places close to the LM48901 outputs may be needed to reduce EMI radiation. www.ti.com 46 LM48901 Revision History Rev Date 1.0 10/31/11 Initial Web released. Description 1.01 12/02/11 Fixed a typo (LM488901 to LM48901) on page 45. 1.02 12/12/11 Added two sections “Modulator Power Supply” and Clock Requirements. 1.03 12/16/11 Changed National to Texas Instruments. 47 www.ti.com LM48901 Physical Dimensions inches (millimeters) unless otherwise noted 36–pin micro SMD Order Number LM48901RL NS Package Number TLA36JSA X1 = 3.204±0.03mm X2 = 3.434±0.03mm X3 = 0.65±0.075mm LLP Package Order Number LM48901SQ NS Package Number SQA32A X1 = 5mm X2 = 5mm X3 = 0.8mm www.ti.com 48 LM48901 Notes 49 www.ti.com LM48901 Quad Class D Spatial Array Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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