HT1647A 64´16 LCD Controller for I/O MCU PATENTED PAT No. : TW 099352 Technical Document · Application Note Features · Operating voltage: 2.7V~5.2V · Eight kinds of time base/WDT selection · Built-in 32kHz RC oscillator · Time base or WDT overflow output · External 32.768kHz crystal oscillator or 32kHz · R/W address auto increment frequency source input · Built-in buzzer driver (2kHz/4kHz) · Standby current: <1mA at 3V, <2mA at 5V · Power down command reduces power consumption · Internal resistor type: 1/5 bias or 1/4 bias, 1/16 duty · Software configuration feature · Two selectable LCD frame frequencies: 89Hz or · Data mode and Command mode instructions 170Hz · Three data accessing modes · Max. 64´16 patterns, 64 segments and 16 commons · Provides VLCD pin to adjust LCD operating voltage · Built-in bit-map display RAM: 1024 bits · Provides three kinds of bias current programming (=64´16 bits) · Control of TN-type, STN-type LCDs and · Built-in internal resistor type bias generator ECB-type LCDs · Six-wire interface (four data wires) · 100-pin LQFP package and in chip form Applications · Leisure products · Cellular phone · Games · Global positioning system · Personal digital assistant · Consumer electronics General Description HT1647A is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 1024 patterns (64 segments and 16 commons). It also supports four data bits interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1647A is a memory mapping and multi-function LCD controller. Since the HT1647A can control ECB-type (Electrically Controlled Rev. 1.40 Birefringence) LCDs in addition to current TN-type (Twisted Nematic) or STN-type (Super Twisted Nematic) LCDs. The software configuration feature of the HT1647A make it suitable for multiple LCD applications including LCD modules and display subsystems. Only six lines (CS, WR, DB0~DB3) are required for the interface between the host controller and the HT1647A. 1 April 29, 2011 PATENTED HT1647A Block Diagram O S C O D is p la y R A M O S C I C S C o n tro l & T im in g C ir c u it R D W R D B 0 C O M 0 C O M 1 5 L C D D r iv e r / B ia s C ir c u it S E G 0 D B 3 S E G 6 3 V D D V L C D V S S B Z W a tc h d o g T im e r & T im e B a s e G e n e r a to r T o n e F re q u e n c y G e n e ra to r B Z N o te : C S : C h ip s B Z , B Z : T o W R , R D : W D B 0 ~ D B 3 : C O M 0 ~ C O IR Q : T im e IR Q e le c tio n n e o u tp u ts R IT E c lo c k , R E A D c lo c k D a ta b u s M 1 5 , S E G 0 ~ S E G 6 3 : L C D o u tp u ts b a s e o r W D T o v e r flo w o u tp u t Pin Assignment S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 C S R D W R D B 0 D B 1 D B 2 D B 3 V S S O S C I O S C O V D D V L C D IR Q B Z B Z T 1 T 2 T 3 T 4 N C C O M 0 C O M 1 C O M 2 C O M 3 C O M 4 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 1 2 7 5 7 4 7 3 3 7 2 4 5 6 7 8 9 1 0 1 1 1 2 H T 1 6 4 7 A 1 0 0 L Q F P -A 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M C O M 1 3 1 2 1 1 1 0 9 8 7 6 5 4 1 5 2 3 2 1 0 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 Rev. 1.40 April 29, 2011 PATENTED HT1647A Pad Assignment S E G 3 7 S E G 3 6 S E G 3 5 S E G 3 4 S E G 3 3 S E G 3 2 S E G 3 1 S E G 3 0 S E G 2 9 S E G 2 8 S E G 2 7 S E G 2 6 S E G 2 5 S E G 2 4 S E G 2 3 S E G 2 2 S E G 2 1 S E G 2 0 S E G 1 9 S E G 1 8 S E G 1 7 1 0 2 1 0 1 1 0 0 S E G 3 8 S E G 3 9 S E G 4 1 S E G 4 0 S E G 4 2 1 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 S E G 1 6 7 6 S E G 1 5 7 5 S E G 1 4 7 4 S E G 1 3 S E G 4 3 2 7 3 S E G 1 2 S E G 4 4 3 7 2 S E G 1 1 4 7 1 S E G 1 0 5 7 0 S E G 9 S E G 4 7 6 6 9 S E G 8 S E G 4 8 7 6 8 S E G 7 S E G 4 9 8 6 7 S E G 6 S E G 5 0 9 6 6 S E G 5 S E G 5 1 1 0 6 5 S E G 4 1 1 6 4 S E G 3 6 3 S E G 2 S E G 1 S E G 0 S E G 4 5 S E G 4 6 S E G 5 2 (0 ,0 ) 1 2 S E G 5 3 S E G 5 4 1 3 6 2 S E G 5 5 1 4 6 1 S E G 5 6 1 5 6 0 S E G 5 7 1 6 5 9 S E G 5 8 1 7 5 8 S E G 5 9 1 8 5 7 S E G 6 0 1 9 5 6 S E G 6 1 2 0 5 5 S E G 6 2 2 1 5 4 S E G 6 3 2 2 5 3 C S 2 3 R D 2 4 W R 2 5 2 6 2 7 2 8 2 9 3 1 3 0 3 2 3 4 3 3 3 5 3 6 3 7 3 9 3 8 4 0 4 1 4 2 4 3 C O M 1 5 C O M 1 4 C O M 1 3 C O M 1 2 C O M 1 1 C O M 1 0 C O M 9 C O M 8 4 4 4 6 4 7 4 8 4 9 5 0 5 1 5 2 C O M 0 C O M 1 C O M 2 C O M 3 C O M 4 C O M 5 C O M 6 C O M 7 T 4 T 3 T 2 T 1 B Z B Z IR Q V L C D V D D O P 1 O S C O O S C I O P 2 O P 3 V S S D B 3 D B 2 D B 1 D B 0 4 5 Chip size: 3255 ´ 3050 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. Pad Coordinates Unit: mm Pad No. X Y Pad No. X Y Pad No. X Y 1 -1379.40 1407.45 35 -336.80 -1310.40 69 1512.50 593.85 2 -1512.50 956.25 36 -233.40 -1310.40 70 1512.50 688.85 3 -1512.50 861.25 37 -125.00 -1310.40 71 1512.50 783.85 4 -1512.50 766.25 38 72 1512.50 878.85 -1512.50 671.25 39 -28.00 77.60 -1310.40 5 -1310.40 73 1512.50 973.85 6 -1512.50 576.25 40 172.60 -1310.40 74 1512.50 1068.85 7 -1512.50 481.25 41 295.20 -1310.40 75 1512.50 1163.85 8 -1512.50 386.25 42 408.80 -1310.40 76 1512.50 1258.85 9 -1512.50 291.25 43 522.40 -1310.40 77 1512.50 1353.85 10 -1512.50 196.25 44 636.00 -1310.40 78 995.60 1407.45 Rev. 1.40 3 April 29, 2011 PATENTED HT1647A Pad No. X Y Pad No. X Y Pad No. X Y 11 -1512.50 101.25 45 781.30 -1410.00 79 900.60 1407.45 12 -1512.50 6.25 46 876.30 -1410.00 80 805.60 1407.45 13 -1512.50 -88.75 47 971.30 -1410.00 81 710.60 1407.45 14 -1512.50 -183.75 48 1066.30 -1410.00 82 615.60 1407.45 15 -1512.50 -278.75 49 1161.30 -1410.00 83 520.60 1407.45 16 -1512.50 -373.75 50 1256.30 -1410.00 84 425.60 1407.45 17 -1512.50 -468.75 51 1351.30 -1410.00 85 330.60 1407.45 18 -1512.50 -563.75 52 1446.30 -1410.00 86 235.60 1407.45 19 -1512.50 -658.75 53 1512.50 -949.55 87 140.60 1407.45 20 -1512.50 -753.75 54 1512.50 -845.55 88 45.60 1407.45 21 -1512.50 -848.75 55 1512.50 -759.55 89 -49.40 1407.45 22 -1512.50 -943.75 56 1512.50 -664.55 90 -144.40 1407.45 23 -1441.90 -1095.00 57 1512.50 -569.55 91 -239.40 1407.45 24 -1441.90 -1190.00 58 1512.50 -474.55 92 -334.40 1407.45 25 -1441.90 -1295.60 59 1512.50 -379.55 93 -429.40 1407.45 26 -1240.80 -1310.40 60 1512.50 -284.55 94 -524.40 1407.45 27 -1145.80 -1310.40 61 1512.50 -166.15 95 -619.40 1407.45 28 -1040.20 -1310.40 62 1512.50 96 -714.40 1407.45 29 -945.20 -1310.40 63 1512.50 -71.15 23.85 97 -809.40 1407.45 30 -842.00 -1310.40 64 1512.50 118.85 98 -904.40 1407.45 31 -743.30 -1310.40 65 1512.50 213.85 99 -999.40 1407.45 32 -637.70 -1310.40 66 1512.50 308.85 100 -1094.40 1407.45 33 -542.70 -1310.40 67 1512.50 403.85 101 -1189.40 1407.45 34 -437.10 -1310.40 68 1512.50 498.85 102 -1284.40 1407.45 Pad Description Pad No. 23 Pad Name CS I/O Description I Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or write to the HT1647A are disabled. The serial interface circuit is also reset. But if the CS is at a logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1647A are all enabled. 24 RD I READ clock input with pull-high resistor. Data in the RAM of the HT1647A are clocked out on the rising edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next falling edge to latch the clocked out data. 25 WR I WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT1647A on the rising edge of the WR signal. 26~29 DB0~DB3 I/O Parallel data input/output with a pull-high resistor 30 VSS ¾ 31 OP1 I Used to select D3, D1 or D2, D0; OP1 input with pull-low resistor. 32 OP2 I OP2 and OP3 are used to select two of four level gray scale; OP2 input with pull-high resistor. 33 OSCI I 34 OSCO O 35 OP3 I Rev. 1.40 Negative power supply for logic circuit, ground The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left open. OP2 and OP3 are used to select two of four level gray scale ; OP3 input with pull-high resistor. 4 April 29, 2011 PATENTED Pad No. Pad Name I/O HT1647A Description 36 VDD ¾ 37 VLCD I Power supply for LCD driver circuit 38 IRQ O Time base or Watchdog Timer overflow flag, NMOS open drain output. 39, 40 BZ, BZ O 2kHz or 4kHz frequency output pair (tristate output buffer) 41~44 T1~T4 I Not connected 45~60 COM0~COM15 O LCD common outputs O LCD segment outputs 61~102, SEG0~SEG63 1~22 Positive power supply for logic circuit Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+5.5V Storage Temperature ............................-50°C to 125°C Input Voltage.............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-25°C to 75°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter VDD Operating Voltage IDD1 Operating Current Ta=25°C Test Conditions VDD Conditions ¾ ¾ 3V 5V IDD2 3V Operating Current 5V IDD11 3V Operating Current 5V IDD22 3V Operating Current 5V ISTB 3V Standby Current 5V VIL No load/LCD ON On-chip RC oscillator No load/LCD ON Crystal oscillator No load/LCD OFF On-chip RC oscillator No load/LCD OFF Crystal oscillator No load, Power down mode 3V Input Low Voltage 3V Input High Voltage IOH1 Rev. 1.40 Max. Unit 2.7 ¾ 5.2 V ¾ 150 250 mA ¾ 250 370 mA ¾ 135 200 mA ¾ 200 300 mA ¾ 15 30 mA ¾ 50 70 mA ¾ 2 10 mA ¾ 3 10 mA ¾ ¾ 1 mA ¾ ¾ 2 mA 0 ¾ 0.6 V 0 ¾ 1.0 V 2.4 ¾ 3 V 4.0 ¾ 5 V DB0~DB3, WR, CS, RD 5V IOL1 Typ. DB0~DB3, WR, CS, RD 5V VIH Min. 3V VOL=0.3V 1.2 2.5 ¾ mA 5V VOL=0.5V 3 6 ¾ mA 3V VOH=2.7V -0.9 -1.8 ¾ mA 5V VOH=4.5V -2 -4 ¾ mA BZ, BZ, IRQ Sink Current BZ, BZ Source Current 5 April 29, 2011 PATENTED Symbol IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 RPH1 Parameter Test Conditions VDD Conditions Typ. Max. Unit VOL=0.3V 1.2 2.5 ¾ mA 5V VOL=0.5V 3 6 ¾ mA 3V VOH=2.7V -0.9 -1.8 ¾ mA 5V VOH=4.5V -2 -4 ¾ mA 3V VOL=0.3V 80 160 ¾ mA 5V VOL=0.5V 180 360 ¾ mA 3V VOH=2.7V -40 -80 ¾ mA 5V VOH=4.5V -90 -180 ¾ mA 3V VOL=0.3V 50 100 ¾ mA 5V VOL=0.5V 120 240 ¾ mA 3V VOH=2.7V -30 -60 ¾ mA 5V VOH=4.5V -70 -140 ¾ mA 150 250 410 kW 60 125 210 kW 150 250 410 kW 60 125 210 kW 150 250 410 kW 60 125 210 kW DB0~DB3 Source Current LCD Common Sink Current LCD Common Source Current LCD Segment Sink Current LCD Segment Source Current 3V Pull-high Resistor DB0~DB3, WR, CS, RD 3V Pull-high Resistor OP2, OP3 5V RPL Min. 3V DB0~DB3 Sink Current 5V RPH2 HT1647A 3V Pull-low Resistor OP1 5V A.C. Characteristics Symbol fSYS1 Parameter Ta=25°C Test Conditions VDD Conditions 3V System Clock 3V System Clock Crystal oscillator 5V 3V fSYS3 System Clock External clock source 5V fLCD1 3V LCD Frame Frequency 3V LCD Frame Frequency Crystal oscillator 5V 3V fLCD3 LCD Frame Frequency External clock source 5V tCOM LCD Common Period fCLK1 4-Bit Data Clock (WR Pin) ¾ n: Number of COM 3V Duty cycle 50% 5V Rev. 1.40 Max. Unit 22 32 40 kHz 24 32 40 kHz ¾ 32.768 ¾ kHz ¾ 32.768 ¾ kHz ¾ 32 ¾ kHz ¾ 32 ¾ kHz 61/117 89/170 111/213 Hz 61/117 89/170 111/213 Hz On-chip RC oscillator 5V fLCD2 Typ. On-chip RC oscillator 5V fSYS2 Min. 6 ¾ 64 ¾ Hz ¾ 64 ¾ Hz ¾ 64 ¾ Hz ¾ 64 ¾ Hz ¾ n/fLCD ¾ sec ¾ ¾ 150 kHz ¾ ¾ 300 kHz April 29, 2011 PATENTED Symbol HT1647A Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit ¾ ¾ 75 kHz ¾ ¾ 150 kHz ¾ 250 ¾ ns ¾ ¾ ms ¾ ¾ ms 3V fCLK2 4-Bit Data Clock (RD Pin) Duty cycle 50% 5V 4-Bit Interface Reset Pulse Width (Figure 3) tCS ¾ CS Write mode 3.34 Read mode 6.67 Write mode 1.67 Read mode 3.34 3V tCLK WR, RD Input Pulse Width (Figure 1) 5V tr, tf Rise/Fall Time Serial Data Clock 3V Width (Figure 1) 5V ¾ ¾ 120 ¾ ns tsu Setup Time for DB to WR, RD Clock 3V Width (Figure 2) 5V ¾ ¾ 120 ¾ ns th Hold Time for DB to WR, RD Clock 3V Width (Figure 2) 5V ¾ ¾ 120 ¾ ns tsu1 Setup Time for CS to WR, RD Clock 3V Width (Figure 3) 5V ¾ ¾ 100 ¾ ns th1 Hold Time for CS to WR, RD Clock 3V Width (Figure 3) 5V ¾ ¾ 100 ¾ ns 20 ¾ ¾ ms 0.05 ¾ ¾ V/ms tOFF VDD OFF Times (Figure 4) ¾ VDD drop down to 0V tSR VDD Rising Slew Rate (Figure 4) ¾ ¾ Note: 1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal Power-on Reset (POR) circuit will not operate normally. 2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for 20ms (min.) before rising to the normal operating voltage. V A L ID tf W R , R D C lo c k 9 0 % 5 0 % 1 0 % tr tC V tC L K ts G N D L K 5 0 % W R , R D C lo c k S V D D 5 0 % th u 1 G N D V D D 1 V 5 0 % F ir s t C lo c k L a s t C lo c k D D 0 V tS tO R F F G N D Figure 3 Rev. 1.40 G N D Figure 2 tC ts D D G N D th u W R , R D C lo c k Figure 1 C S V 5 0 % D B D D D A T A Figure 4. Power-on Reset Timing 7 April 29, 2011 PATENTED HT1647A Functional Description System Oscillator source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the case in the external 32kHz clock source operation. At the initial system power on, the HT1647A is at the SYS DIS state. The HT1647A system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The clock source may be from an on-chip RC oscillator (32kHz), a crystal oscillator (32.768kHz), or an external 32kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is available only for the on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT loses its function as well. O S C I O S C O E x te r n a l C lo c k S o u r c e 3 2 k H z 008H COM0 D0 or D1 COM1 D2 or D3 001H 009H COM2 D0 or D1 D0 or D1 COM3 D2 or D3 D2 or D3 002H 00AH COM4 D0 or D1 COM5 D2 or D3 003H 00BH COM6 D0 or D1 D0 or D1 COM7 D2 or D3 D2 or D3 004H 00CH COM8 D0 or D1 COM9 D2 or D3 005H 00DH COM10 D0 or D1 D0 or D1 COM11 D2 or D3 D2 or D3 006H 00EH COM12 D0 or D1 D0 or D1 COM13 D2 or D3 D2 or D3 007H 00FH COM14 D0 or D1 COM15 D2 or D3 SEG0 SEG1 S y s te m C lo c k O n - c h ip R C O s c illa to r 3 2 k H z System Oscillator Configuration The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, thus serving as a system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency 000H C r y s ta l O s c illa to r 3 2 7 6 8 H z Display Memory - RAM Structure The static display RAM is organized into 512´2 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. 010H ------------------------------1E8H 1F0H 1F8H D0 or D1 D0 or D1 D0 or D1 D2 or D3 D2 or D3 D2 or D3 011H ------------------------------1E9H 012H ------------------------------1EAH 1F1H 1F9H D0 or D1 D0 or D1 D2 or D3 D2 or D3 1F2H 1FAH D0 or D1 D0 or D1 D0 or D1 D2 or D3 D2 or D3 D2 or D3 013H ------------------------------1EBH 1F3H 1FBH D0 or D1 D0 or D1 D2 or D3 D2 or D3 1F4H 1FCH D0 or D1 D0 or D1 D0 or D1 D2 or D3 D2 or D3 D2 or D3 014H ------------------------------1ECH 015H ------------------------------1EDH 016H ------------------------------1EEH 1F5H 1FDH D0 or D1 D0 or D1 D2 or D3 D2 or D3 1F6H 1FEH D0 or D1 D0 or D1 D2 or D3 D2 or D3 1F7H 1FFH D0 or D1 D0 or D1 D0 or D1 D2 or D3 D2 or D3 D2 or D3 SEG62 SEG63 017H ------------------------------1EFH SEG2 --------------------------- SEG61 Note: One bit of RAM maps to LCD¢s one pixel and decide 2-level gray scale. RAM structure depends on OP1, OP2 and OP3 option. Rev. 1.40 8 April 29, 2011 PATENTED HT1647A Write Data Mapping to RAM for Pad Option Pad Option OP1 0 (Select D2 and D0) 1 (Select D3 and D1) OP2 OP3 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Level Selected RAM Data Level2 (1,0) 0 Level3 (0,1) 1 Level4 (0,0) 0 Level3 (0,1) 1 Level2 (1,0) 0 Level1 (1,1) 1 Level4 (0,0) 0 Level1 (1,1) 1 Level3 (0,1) 0 Level2 (1,0) 1 Level4 (0,0) 0 Level2 (1,0) 1 Level3 (0,1) 0 Level1 (1,1) 1 Level4 (0,0) 0 Level1 (1,1) 1 Note Level1 and Level4 are not used Level1 and Level2 are not used Level3 and Level4 are not used Level2 and Level3 are not used Level1 and Level4 are not used Level1 and Level3 are not used Level2 and Level4 are not used Level2 and Level3 are not used Note: OP1 is used to select D3, D1 or D2, D0. OP2 and OP3 are used to select two of four level gray scale. The default value of OP1, OP2 and OP3 are (0,1,1). Gray Scale Level Decision Gray Scale Display HT1647A uses PWM technique to provide gray scale display and only two of four level gray scale can be displayed simultaneously by setting OP1~OP3 pads. OP1 is used to select D3, D1 or D2, D0 and OP2 and OP3 are used to select two of four level gray scale. The four level gray scale are defined below table ²RAM Data Defined Gray Scale Level². MCU write two bits data and only one bit data is written to internal display RAM. The OP1~OP3 pads setting is shown as following table ²Write Data Mapping to RAM for Pad Option². If the user choose 89Hz frame frequency, a max. of 24 sections can be programmed to suit a satisfactory gray scale in every level. Similarly, if the user choose 170Hz frame frequency, a max. of 13 sections can be programmed to suit a satisfactory gray scale in every level. HT1647A provides 5-bit PWM data to control the length of the section. In other words, a max. Of 24 gray scales are generated by 5-bit binary PWM data. At FRAME 89Hz mode, the HT1647A only provides a max. of 24 adjustable gray scales although 32 is the expressed max. value by 5 bits binary code. When 5 bits binary code value is more than 23, the PWM control circuit uniformly regards 23. To increase PWM data indicates to increase the length of the active segment signal. The varied length of the active segment signal displays varied gray scale in TN-type, STN-type LCDs (refer to table 1). Similarly, it displays varied color in ECB-type LCDs. The color display is derived from ECB-type LCD specification. At FRAME 170Hz mode, the HT1647A only provides a max. of 13 adjustable gray scales although 32 is the expressed max. value by 5 bits binary code. When the 5 bits binary code value is more than 12, the PWM control circuit uniformly regards 12. The user must appoint four kinds of PWM data to four kinds of different gray scale level by commanding PWM data (refer to table 2). RAM Data Code (D3, D2) or (D1, D0) Choice Gray Scale Level (1, 1) Level 1 (1, 0) Level 2 (0, 1) Level 3 (0, 0) Level 4 RAM Data Defined Gray Scale Level Frame Frequency HT1647A provides two kinds of frame frequency option by command code; 89Hz and 170Hz respectively. FRAME 89Hz provides 89Hz frame frequency and active segment signal width can be divided into 24 sections concurrently. FRAME 170Hz provides 170Hz frame frequency and active segment signal width can be divided into 13 sections concurrently. The 24 sections display a particularly gray scale more than the 13 sections by PWM data. The default is FRAME 89Hz. Rev. 1.40 9 April 29, 2011 PATENTED Name HT1647A Command Code Function FRAME 170Hz X100-0001-1000-XXXX Select 170Hz frame frequency and active segment signal width can be divided into 13 sections FRAME 89Hz X100-0001-1101-XXXX Select 89Hz frame frequency and active segment signal width can be divided into 24 sections Frame Frequency Selection Command Code Relationship Table between PWM Data and Gray Scale V a lu e 0 1 2 3 5 4 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 1 5 b its P W M B 4 B 3 B 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 d a ta B 1 B 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 (O N 1 1 1 1 1 1 1 1 1 1 2 2 2 P W M w id th ) G r a y S c a le V a lu e 0 (0 /2 3 ) 1 /2 3 2 /2 3 3 /2 3 4 /2 3 5 /2 3 6 /2 3 7 /2 3 8 /2 3 9 /2 3 0 /2 3 1 /2 3 2 /2 3 3 /2 3 4 /2 3 5 /2 3 6 /2 3 7 /2 3 8 /2 3 9 /2 3 0 /2 3 1 /2 3 2 /2 3 1 (2 3 /2 3 ) 1 (2 4 /2 3 ) 5 b its P W M d a ta 1 3 B 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 B 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 B 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 (O N 1 1 1 1 P W M w id 0 (0 /1 1 /1 2 2 /1 2 3 /1 2 4 /1 2 5 /1 2 6 /1 2 7 /1 2 8 /1 2 9 /1 2 0 /1 2 1 /1 2 (1 2 /1 (1 3 /1 th ) 2 ) G r a y S c a le 2 ) 2 ) 1 (3 1 /1 2 ) Table 2: FRAME 170Hz Mode Note: The varied PWM data displays various gray scale in TN-type, STN-type LCDs. The color display derives from ECB-type LCD¢s specification. 1 (3 1 /2 3 ) Table 1: FRAME 89Hz Mode Name Command Code Function GRS LEVEL 1 X100-001 B4-B3 B2 B1 B0-XXXX Set PWM data in gray scale level 1 GRS LEVEL 2 X100-010 B4-B3 B2 B1 B0-XXXX Set PWM data in gray scale level 2 GRS LEVEL 3 X100-011 B4-B3 B2 B1 B0-XXXX Set PWM data in gray scale level 3 GRS LEVEL 4 X100-100 B4-B3 B2 B1 B0-XXXX Set PWM data in gray scale level 4 Four Kinds of Gray Scale Level Command Code Rev. 1.40 10 April 29, 2011 PATENTED 1 6 V 1 HT1647A 2 1 6 1 2 L C D V 1 V 2 C O M V 3 V 4 V S S W V W ' L C D V 1 V 2 S E G V 3 V V 4 S S W ' C O M ~ S E G V L C D 3 /5 V L C D 1 /5 V L C D -1 /5 V L C D -3 /5 V L C D -V L C D W O N 1 fr N o t e : " W '" R e a l a c t iv e s e g m e n t s ig n a l w " W " M a x . a c tiv e s e g m e n t s ig n a l w P W M ( O N w id t h ) : W '/ W , 0 £ W '/ W £ a m id id 1 O N O F F e th ( a d ju s ta b le w id th b y P W M th ( r e fe r to ta b le 1 & ta b e l 2 ) d a ta ) Example of Waveform (B Type) in 1/5 Bias, 1/16 Duty Cycle Drive Time Base and Watchdog Timer - WDT curs, the IRQ pin will remain at a logic low level until the CLR WDT or the IRQ DIS command is issued. The time base generator and WDT share the same counter which is divided by 256. The IRQ clock can be programmed as 1Hz, 2Hz, ...., 128Hz output. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out oc- If an external clock is selected as the system frequency source, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. T im e B a s e C lo c k S o u r c e V C L R IR Q T IM E R E N /D IS /2 5 6 T im e r W D T /4 W D T E N /D IS D D Q D C K IR Q E N /D IS R C L R W D T Time Base and WDT Configurations Rev. 1.40 11 April 29, 2011 PATENTED tion command, a bias current selection command, a gray scale level selection command, a timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. Buzzer Tone Output A simple tone generator is implemented in the HT1647A. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. The following are the data mode ID and the command mode ID: By executing the TONE 4K and TONE 2K commands there are two tone frequency outputs selectable that can turn on the tone output. The TONE 4K and TONE 2K commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned off by invoking the TONE OFF command. The tone outputs, namely BZ and BZ, are a pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ outputs will remain at low level. Name Command Code HT1647A Operation Mode ID READ Data 110 WRITE Data 101 READ-MODIFY-WRITE Data 101 Command 100 COMMAND If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to ²1² and the previous operation mode will also be reset. The CS pin returns to ²0², so a new operation mode ID should be issued first. Function TONE X100-0000-1000-XXXX Turn-off tone output OFF Turn-on tone output, TONE X100-0001-0000-XXXX tone frequency is 4K 4kHz Bias Generator Turn-on tone output, TONE X100-0001-0001-XXXX tone frequency is 2K 2kHz The HT1647A bias voltage belongs to internal resistor type. It provides two kinds of bias option named 1/5 bias and 1/4 bias respectively. It is recommended to select 1/5 bias to fit TN-type, STN-type LCDs and select 1/4 bias to fit ECB-type LCDs. It also provides three kinds of bias current option by programming to suitably drive an LCD panel. The three kinds of bias current are large, middle, and small, respectively. Usually, large panel LCD can be excellently displayed by large bias current. Relatively, it consumes large current when LCD ON command is used. Small bias current provides low power consumption during On condition when the LCD is normally displayed. The following are the reference value table. Buzzer Tone Output Command Code Command Format The HT1647A can be configured by software setting. There are two mode commands to configure the HT1647A resource and to transfer the LCD display data. The configuration mode of the HT1647A is called command mode, and its command mode ID is 100. The command mode consists of a system configuration command, a system frequency selection command, an LCD configuration command, a tone frequency selec- VLCD Bias Large Bias Current Middle Bias Current Small Bias Current 4V 1/5 300mA 100mA 40mA 4V 1/4 375mA 125mA 50mA Rev. 1.40 12 April 29, 2011 PATENTED V D D HT1647A V D D * V L C D * V R V L C D R V R R V 1 V 1 R V 2 R V 2 *V R *V R L C D V 3 L C D V 3 R R V 4 V 4 R R V S S V S S 1 /5 b ia s 1 /4 b ia s * T h e v o lta g e a p p lie d to V L C D p in m u s t b e e q u a l to o r lo w e r th a n V D D . * A d ju s t V R to fit L C D d is p la y , a t V D D = 5 V , V L C D = 4 V , V R = 1 5 k W ± 2 0 % . Internal Resistor Type Bias Generator Configurations Interfacing ing edge of the RD signal, and the clocked out data will then appear on the DB0~DB3 lines. It is recommended that the host controller read correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DB0~DB3 lines are all clocked into the HT1647A on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1647A. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by connecting with the IRQ pin of the HT1647A. Only six lines are required to interface with the HT1647A. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the HT1647A. If the CS pin is set to 1, the data and command issued between the host controller and the HT1647A are first disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of the HT1647A. The DB0~DB3 are the 4-bit parallel data input/output lines. Data to be read or written or commands to be written have to pass through the DB0~DB3 lines. The RD line is the READ clock input. Data in the RAM are clocked out on the fall- Rev. 1.40 13 April 29, 2011 PATENTED HT1647A Timing Diagrams READ mode (command ID code : 1 1 0) C S W R R D A 8 A 7 A 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D B 2 1 A 6 A 2 D 2 1 A 6 A 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 A 5 A 1 D 1 A 5 A 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 0 A 4 A 0 D 0 0 A 4 A 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 C o m m a n d ID A d d re s s (M A ) M e m o ry D a ta (M A ) C o m m a n d ID A d d re s s (M A ) M e m o ry D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) D a ta (M A + 9 ) D a ta (M A + 1 5 ) 1 D B 1 D B 0 1 D a ta (M A + 1 0 ) D a ta (M A + 1 1 ) D a ta (M A + 1 2 ) D a ta (M A + 1 3 ) D a ta (M A + 1 4 ) A 7 A 3 D 3 A 8 A 7 A 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D B 2 1 A 6 A 2 D 2 1 A 6 A 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 A 5 A 1 D 1 A 5 A 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 A 4 A 0 D 0 1 A 4 A 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 M e m o ry D a ta (M A ) C o m m a n d ID A d d re s s (M A ) M e m o ry D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) D a ta (M A + 4 ) D a ta (M A + 5 ) D a ta (M A + 6 ) D a ta (M A + 7 ) D a ta (M A + 8 ) D a ta (M A + 9 ) D a ta (M A + 1 0 ) D a ta (M A + 1 1 ) D a ta (M A + 1 2 ) D a ta (M A + 1 3 ) D a ta (M A + 1 4 ) D a ta (M A + 1 5 ) c o d e A 8 c o d e D B 3 A d d re s s (M A ) D a ta (M A + 8 ) D 3 D a ta (M A + 7 ) A 3 D a ta (M A + 6 ) A 7 D a ta (M A + 5 ) A 8 D a ta (M A + 4 ) D B 3 ( S in g le a d d r e s s r e a d in g ) ( S u c c e s s iv e a d d r e s s r e a d in g ) WRITE mode (command ID code : 1 0 1) C S W R R D 0 D B 1 1 D B 0 0 C o m m a n d ID c o d e c o d e ( S in g le a d d r e s s w r itin g ) Rev. 1.40 ( S u c c e s s iv e a d d r e s s w r itin g ) 14 April 29, 2011 PATENTED HT1647A READ-MODIFY-WRITE mode (command ID code : 1 0 1) C S W R R D D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D B 2 1 A 6 A 2 D 2 D 2 1 A 6 A 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D B 1 0 A 5 A 1 D 1 D 1 A 5 A 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D B 0 1 A 4 A 0 D 0 D 0 1 A 4 A 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 C o m m a n d ID c o d e A d d re s s (M A ) M e m o ry D a ta (M A ) D a ta (M A ) C o m m a n d ID c o d e A d d re s s (M A ) M e m o ry D a ta (M A ) D a ta (M A ) D a ta (M A + 5 ) D a ta (M A + 6 ) D a ta (M A + 6 ) C 8 C 4 C 0 0 ( S in g le a d d r e s s a c c e s s in g ) D a ta (M A + 5 ) A 3 D a ta (M A + 4 ) A 7 D a ta (M A + 4 ) A 8 D a ta (M A + 3 ) D 3 D a ta (M A + 3 ) D 3 D a ta (M A + 2 ) A 3 D a ta (M A + 2 ) A 7 D a ta (M A + 1 ) A 8 D a ta (M A + 1 ) D B 3 ( S u c c e s s iv e a d d r e s s a c c e s s in g ) Command mode (command ID code : 1 0 0) C S W R R D D B 3 X C 8 1 D B 2 0 D B 1 D B 0 0 C 4 C 0 C 7 C 3 X C 6 C 2 C 5 C 1 X 1 0 X X 0 C 8 C 4 C 0 C 8 C 4 C 7 C 3 X C 7 C 3 C 6 C 2 X C 6 C 2 C 5 C 1 X C 5 C 1 C 0 C 8 C 4 C 0 C 8 C 4 C 0 C 8 C 4 C 0 X C 7 C 3 X C 7 C 3 X C 7 C 3 X C 7 C 3 X C 6 C 2 X C 6 C 2 X C 6 C 2 X C 6 C 2 X X C 5 C 1 X C 5 C 1 X C 5 C 1 X C 5 C 1 X X C o m m a n d 6 C o m m a n d 5 C o m m a n d 4 C o m m a n d 3 C o m m a n d 2 C o m m a n d 1 C o m m a n d ID C o m m a n d c o d e C o m m a n d ID c o d e ( S in g le c o m m a n d ) ( S u c c e s s iv e c o m m a n d ) Note: ²X² stands for don¢t care Rev. 1.40 15 April 29, 2011 PATENTED HT1647A Application Circuits Host Controller with an HT1647A Display System C S * V D D R D *V R W R D B 0 ~ D B 3 M C U V L C D H T 1 6 4 7 A *R B Z P ie z o IR Q B Z O S C I C lo c k O u t O S C O C O M 0 ~ C O M 1 5 S E G 0 ~ S E G 6 3 E x te r n a l C lo c k 1 ( 3 2 k H z ) E x te r n a l C lo c k 2 ( 3 2 k H z ) * 1 /5 B ia s ( o r 1 /4 B ia s ) , 1 /1 6 D u ty O n - c h ip O S C L C D P a n e l C ry s ta l 3 2 7 6 8 H z *Note: The connection of IRQ and RD pin can be selected depending on the MCU. The voltage applied to VLCD pin must be equal to or lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW ± 20%. It is recommended to select 1/5 bias to fit TN-type, STN-type LCDs and select 1/4 bias to fit ECB-type LCDs. Adjust R (external pull high resistance) to fit user¢s time base clock. Instruction Set Summary Command Code D/C READ Name A8110-A7A6A5A4A3A2A1A0D3D2D1D0 D Read data from the RAM WRITE A8101-A7A6A5A4A3A2A1A0D3D2D1D0 D Write data to the RAM READ-MODIFYA8101-A7A6A5A4A3A2A1A0D3D2D1D0 WRITE D Read and Write data to the RAM SYS DIS X100-0000-0000-XXXX C Turn Off both system oscillator and LCD bias Yes generator SYS EN X100-0000-0001-XXXX C Turn On system oscillator LCD OFF X100-0000-0010-XXXX C Turn Off LCD display LCD ON X100-0000-0011-XXXX C Turn On LCD display TIMER DIS X100-0000-0100-XXXX C Disable time base output Yes WDT DIS X100-0000-0101-XXXX C Disable WDT time-out flag output Yes TIMER EN X100-0000-0110-XXXX C Enable time base output WDT EN X100-0000-0111-XXXX C Enable WDT time-out flag output TONE OFF X100-0000-1000-XXXX C Turn Off tone outputs CLR TIMER X100-0000-1101-XXXX C Clear the contents of the time base generator CLR WDT X100-0000-1111-XXXX C Clear the contents of the WDT stage TONE 4K X100-0001-0000-XXXX C Turn on tone output, tone frequency output: 4kHz TONE 2K X100-0001-0001-XXXX C Turn on tone output, tone frequency output: 2kHz Rev. 1.40 16 Function Def. Yes Yes April 29, 2011 PATENTED Name Command Code D/C HT1647A Function Def. IRQ DIS X100-0001-0010-XXXX C Disable IRQ output IRQ EN X100-0001-0011-XXXX C Enable IRQ output RC 32K X100-0001-0100-XXXX C System clock source, on-chip RC oscillator EXT (XTAL) X100-0001-0101-XXXX C System clock source, external 32kHz clock source or crystal oscillator 32.768kHz LARGE BIAS X100-0001-0110-XXXX C Large bias current option MIDDLE BIAS X100-0001-0111-XXXX C Middle bias current option SMALL BIAS X100-0001-1000-XXXX C Small bias current option BIAS 1/5 X100-0001-1001-XXXX C LCD 1/5 bias option BIAS 1/4 X100-0001-1010-XXXX C LCD 1/4 bias option FRAME 170Hz X100-0001-1100-XXXX C Selects 170Hz frame frequency and active segment signal width can be divided into 13 sections FRAME 89Hz X100-0001-1101-XXXX C Selects 89Hz frame frequency and active segment signal width can be divided into 24 Yes sections GRS LEVEL1 X100-001 B4-B3 B2 B1 B0-XXXX C Sets PWM data in gray scale level 1 GRS LEVEL2 X100-010 B4-B3 B2 B1 B0-XXXX C Sets PWM data in gray scale level 2 GRS LEVEL3 X100-011 B4-B3 B2 B1 B0-XXXX C Sets PWM data in gray scale level 3 GRS LEVEL4 X100-100 B4-B3 B2 B1 B0-XXXX C Sets PWM data in gray scale level 4 F1 X100-1010-0000-XXXX C Time base clock output: 1Hz The WDT time-out flag after: 4s F2 X100-1010-0001-XXXX C Time base clock output: 2Hz The WDT time-out flag after: 2s F4 X100-1010-0010-XXXX C Time base clock output: 4Hz The WDT time-out flag after: 1s F8 X100-1010-0011-XXXX C Time base clock output: 8Hz The WDT time-out flag after: 1/2s F16 X100-1010-0100-XXXX C Time base clock output: 16Hz The WDT time-out flag after: 1/4s F32 X100-1010-0101-XXXX C Time base clock output: 32Hz The WDT time-out flag after: 1/8s F64 X100-1010-0110-XXXX C Time base clock output: 64Hz The WDT time-out flag after: 1/16s F128 X100-1010-0111-XXXX C Time base clock output: 128Hz The WDT time-out flag after: 1/32s TEST X100-1111-1111-XXXX C Test mode, user don¢t use. NORMAL X100-1111-1110-XXXX C Normal mode Note: Yes Yes Yes Yes Yes Yes ²X² stands for don¢t care A8~A0: RAM address D3~D0: RAM data B4~B0: PWM data D/C: Data/Command mode Def.: Power-on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The tone frequency source and the time base/WDT clock frequency source can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1647A after power-on reset, otherwise, power on reset may fail, which in turn leads to the malfunctioning of the HT1647A. Rev. 1.40 17 April 29, 2011 PATENTED HT1647A Package Information 100-pin LQFP (14mm´14mm) Outline Dimensions C D 7 5 G 5 1 H I 5 0 7 6 F A B E 1 0 0 2 6 K a J 2 5 1 Symbol Nom. Max. A 0.626 ¾ 0.634 B 0.547 ¾ 0.555 C 0.626 ¾ 0.634 D 0.547 ¾ 0.555 E ¾ 0.020 ¾ F ¾ 0.008 ¾ G 0.053 ¾ 0.057 H ¾ ¾ 0.063 I ¾ 0.004 ¾ J 0.018 ¾ 0.030 K 0.004 ¾ 0.008 a 0° ¾ 7° Symbol A Rev. 1.40 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 15.90 ¾ 16.10 B 13.90 ¾ 14.10 C 15.90 ¾ 16.10 D 13.90 ¾ 14.10 E ¾ 0.50 ¾ F ¾ 0.20 ¾ G 1.35 ¾ 1.45 H ¾ ¾ 1.60 I ¾ 0.10 ¾ J 0.45 ¾ 0.75 K 0.10 ¾ 0.20 a 0° ¾ 7° 18 April 29, 2011 PATENTED HT1647A Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.40 19 April 29, 2011