HOLTEK HT16525

HT16525
5x8 Dot Character VFD
Controller & Driver
Feature
Applications
• Logic voltage : 2.7V~5.5V
• Consumer products panel function control
• High voltage: 60V (max.)
• Industrial measuring instrument panel function
control
• 3-line serial interface
• Other similar application panel function control
• Alphanumeric and symbolic display using
integrated ROM
• Suitable for POS terminals or message displays
• 24 x 8-bit display data RAM (DDRAM)
• Integrated 5x8 dot ROM containing 248 character
set
General Description
The HT16525 device is a dot matrix Vacuum
Fluorescent Display, VFD, controller/driver which
displays characters, numerics and symbols. Dot
matrix VFD driving signals are received via a 3-line
serial interface driven by an externally connected
microcontroller. The display data is stored in the
internal ROM and RAM for character and symbol
display.
• 8 user-defined characters stored in character data
RAM (CGRAM)
• Additional symbol display data stored in 24 x 8-bit
RAM (ADRAM)
• Display content:
24 columns by 1 row + 48 symbols - each column
has 1 digit character with 2 symbols
• Supports display output: 40-segment & 24-grid
• Supports symbol output: 2-symbol & 24-grid
• Supports 2-pin general output port - static operation
• Fully integrated oscillator circuit
• 80-pin LQFP package
Ordering Information
Part Number
Rev. 1.00
Information
HT16525-001
80-pin LQFP package with ROM code 001
HT16525-002
80-pin LQFP package with ROM code 002
1
January 18, 2012
HT16525
Block Diagram
VDD
VH
VSS
DDRAM
24w x 8b
CGROM
248w x 40b
CGRAM
8w x 40b
TEST
RST
ADRAM
24w x 2b
CS
SCK
SI
8 bit shift
register
S1
Segment
Driver
S40
AD1
AD
Driver
AD2
Address
Selector
Command
decoder
Write
address
counter
Read
address
counter
Port
Driver
Control
Circuit
Digit
control
Duty
control
Timing
generator1
OSCI
Rev. 1.00
P1
P2
G1
Grid
Driver
G24
Timing
generator2
Oscillator
2
January 18, 2012
HT16525
Pin Assignment
G21
G22
G23
G24
VH
VSS
OSCI
TEST
RST
CS
SCK
SI
VDD
P1
P2
AD2
AD1
S1
S2
S3
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
HT16525
10
51
11
40
80 LQFP-A
12
49
13
48
47
14
46
15
45
16
44
17
43
18
42
19
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3738 39 40
G20
G19
G18
G17
G16
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
NC
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
NC
NC
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
Pin Description
Pin Name
I/O
Description
Power Supply Pins
VDD
—
Positive power supply for logic circuits
VH
—
Power supply for VFD driver circuits
VSS
—
VSS - ground pin
Microcontroller Interface Pins
CS
I
Chip select pin
When “Low”, the device is active.
SCK
I
Serial clock input
Shift clock input with data written on the SCK rising edge.
SI
I
Serial data input.
The serial data is first shifted from LSB.
RST
I
Initialize all the internal registers and commands.
All segments and digits are fixed at “Low” level.
TEST
I
When “Low” or open, the device is in normal mode.
When “High”, the device is in test mode.
S1~S40
O
High-voltage segment output pins.
G1~G24
O
High-voltage grid output pins.
AD1, AD2
O
High-voltage additional data segment output pins.
P1, P2
O
General port output.
Static operation output - can drive LEDs
I
Oscillator input pin
Connected to an external resistor and capacitor to generate the oscillation
frequency.
Output Pins
Oscillator Pin
OSCI
Rev. 1.00
3
January 18, 2012
HT16525
Approximate Internal Connections
CS, SCK, SI, RST
(For Schmit Trigger Type)
P1, P2
S1~S40, G1~G24, AD1, AD2
VDD
VH
VDD
VSS
VSS
VSS
TEST
VDD
VSS
Absolute Maximum Ratings
Segment output current......................... -10mA to 4mA
AD output current................................. -15mA to 4mA
General port output current................. -20mA to 40mA
Storage Temperature............................ -55°C to 125°C
Operation Temperature.......................... -40°C to 85°C
Logic Supply Voltage................ Vss-0.3V to Vss+6.0V
Driver Supply Voltage................ Vss-0.3V to Vss+66V
Input Voltage... ……………….. Vss-0.3V to VDD+0.3V
Output Voltage..........................Vss-0.3V to VDD+0.3V
Grid output current................................ -20mA to 4mA
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings”
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those listed in the specification is not implied and prolonged exposure to extreme conditions may affect
device reliability.
Rev. 1.00
4
January 18, 2012
HT16525
D.C. Characteristics
Symbol
Parameter
VH=50V, VSS=0V, Ta=-40°C ~ 85°C
Test Condition
VDD
Condition
Min.
Typ.
Max.
Unit
VDD
Logic Supply Voltage
—
—
2.7
5.0
5.5
V
VH
VFD Supply Voltage
—
—
20
—
60
V
5V
fOSC=2MHz, no load, Duty=15/16,
Digit=1 to 24, All output lights
ON, MCU no write data or
command, P2 and P1=high
—
—
2
—
—
1
fOSC=2MHz, no load, Duty=15/16,
Digit=1 to 24, Stop scan, MCU
no write data or command, P2
and P1=high
—
—
2
—
—
1
—
2
—
—
2
—
—
fOSC=2MHz, no load, Duty=15/16,
Digit=1 to 24, All output lights
ON, MCU no write data or
command, P2 and P1=high
—
—
1
mA
—
fOSC=2MHz, no load, Duty=15/16,
Digit=1 to 24, Stop scan, MCU
no write data or command, P2
and P1=high
—
—
20
μA
—
Standby mode
—
—
20
μA
CS, SCK, SI, RST
0.8VDD
—
—
V
CS, SCK, SI, RST
—
—
0.2VDD
V
VIH=VDD, CS, SCK, SI, RST
—
—
1
μA
VIL=0V, CS, SCK, SI, RST
-1
—
—
μA
G1~G24, IOH1=-15mA
45
—
—
V
AD1, AD2, IOH2=-7mA
46
—
—
V
S1~S40, IOH3=-1mA
46
—
—
V
IOH4=-2mA
0.9VDD
—
—
IOH4=-1mA
0.9VDD
—
—
G1~G24, IOL1=1mA
—
—
5
V
AD1, AD2, IOL2=1mA
—
—
5
V
S1~S40, IOL3=1mA
—
—
5
V
IOL4=20mA
—
—
1
IOL4=10mA
—
—
1
—
50
100
kW
—
100
200
kW
IDD1
VDD Operating Current
3V
5V
IDD2
VDD Operating Current
ISTB
VDD Standby Current
IH1
VH Operating Current
IH2
VH Operating Current
IH_STB
VH Standby Current
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current
IIL
Low Level Input Current
3V
5V
3V
5V
3V
5V
3V
5V
3V
3V
5V
VOH2
High Level Output Voltage
VOH3
3V
5V
3V
5V
VOH4
3V
5V
VOL1
3V
5V
VOL2
Low Level Output Voltage
VOL3
3V
5V
3V
5V
VOL4
Rev. 1.00
5V
5V
VOH1
RPD
3V
3V
Pull Down Resistor
5V
3V
Standby mode
P1, P2
P1, P2
TEST Pin
5
mA
mA
μA
V
V
January 18, 2012
HT16525
A.C. Characteristics
Serial Interface Timing
TCSH
TSTART
TSTOP
CS
TCYC
TL-SCK
TH-SCK
SCK
TSETUP
THOLD
SI
CS
TDEC
TDEC
SCK
SI
Rev. 1.00
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
2nd byte
3rd byte
6
January 18, 2012
HT16525
Output Timing
tR
tF
0.8VH
All outputs
0.2VH
VH=50V, VSS=0V, Ta =-40oC ~ 85oC
Symbol
Parameter
fOSC
Oscillation Frequency
fFR
Frame Frequency
TCYC
Write Cycle Time
TL-SCK
Low Pulse of SCK
TH-SCK
High Pulse of SCK
TSETUP
Data Setup Time
THOLD
Data Hold Time
TSTART
Command Start Wait Time
TSTOP
Command Stop Wait Time
TCSH
CS Off Time
TDEC
Command/Data Decode Time
All Output Slew Rate
Rev. 1.00
Min.
Typ.
Max.
Unit
R1=120kW, C1=0.1μF
1.5
2
2.5
MHz
Digit=1 to 24, R1=120kW,
C1=0.1μF
130
175
220
Hz
—
—
2
—
—
2
250
—
—
250
—
—
250
—
—
250
—
—
250
—
—
250
—
—
250
—
—
250
—
—
250
—
—
250
—
—
16
—
—
16
—
—
250
—
—
250
—
—
8
—
—
8
—
—
Ci=100pF, tR=20 to 80%
—
—
2
μs
Ci=100pF, tF=80 to 20%
—
—
2
μs
Condition
VDD
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
SCK
SCK
SCK
SCK, SI
SCK, SI
SCK, SI
SCK, CS
5V
—
3V
5V
—
3V
5V
tR
tF
Test Condition
3V
5V
3V
7
MHz
ns
ns
ns
ns
ns
μs
ns
μs
January 18, 2012
HT16525
Reset and Wake-up Timing
Hardware Reset
0.8VDD
VDD
TRSON
0V
TRW
TPOF
RST
VIH
0.5VDD
VIL
TRSOFF
VIH
SI
VIL
Ta=-40oC ~ 85oC
Symbol
Parameter
Test Condition
5V
TRSON
Oscillator Stable Time
3V
5V
3V
5V
VDD Off Time
TPOF
3V
TRW
RST Pulse Width
TRSOFF
SI Wait Time
Condition
VDD
5V
3V
RST signal is an external input
from a microcontroller etc.
R2=1kΩ, C2=0.1μF
VDD drop down to 0V
RST signal is an external input
from a microcontroller etc.
5V
—
3V
Min.
Typ.
Max.
250
—
—
250
—
—
—
1000
—
—
1000
—
40
—
—
μs
ms
10
—
—
400
—
—
400
—
—
3
—
—
3
—
—
Unit
ns
μs
ns
μs
Wake-up Timing
TOS
TWU
CS
SCK
SI
Ta=-40oC ~ 85oC
Symbol
Parameter
TWU
Wake-up Time
TOS
Oscillation Stable Time
Rev. 1.00
Test Condition
VDD
Min.
Typ.
Max.
Unit
—
200
—
—
ns
—
1000
—
—
μs
Condition
5V
3V
5V
3V
8
January 18, 2012
HT16525
Digit Output Timing
For 24-digits display, at a duty of 15/16
T=2/fOSC
Frame cycle t1=5760T (t1=5760µs when fOSC=2MHz)
Display timing t2=225T (t2=225µs when fOSC=2MHz)
Blank timing t3=15T
(t3=15µs when fOSC=2MHz)
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
AD1,2
S1~40
Rev. 1.00
9
January 18, 2012
HT16525
Segment and AD Position
Positional relationship between S1~S40 and AD1 ~ AD2 - single digit
C0 AD1
ADRAM written data.
Corresponds to 2nd byte.
C1 AD2
C0
S1
C1
S2
C2
S3
C3
S4
C4
S5
C5
S6
C6
S7
C7
S8
C8
S9
C9
S10
C10
S11
C11
S12
C12
S13
C13
S14
C14
S15
C15
S16
C16
S17
C17
S18
C18
S19
C19
S20
C20
S21
C21
S22
C22
S23
C23
S24
C24
S25
C25
S26
C26
S27
C27
S28
C28
S29
C29
S30
C30
S31
C31
S32
C32
S33
C33
S34
C34
S35
C35
S36
C36
S37
C37
S38
C38
S39
C39
S40
CGRAM written data. Corresponds to 2nd byte (1st column)
CGRAM written data. Corresponds to 3rd byte (2nd column)
CGRAM written data. Corresponds to 4th byte (3rd column)
CGRAM written data. Corresponds to 5th byte (4th column)
CGRAM written data. Corresponds to 6th byte (5th column)
Rev. 1.00
10
January 18, 2012
HT16525
Command Table
Function Byte
R/W
Bit7
Bit6
(MSB)
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
Note
Default
DDRAM
data write
1st
W
0
0
0
X4
X3
X2
X1
X0
Xn: Address specification
for each RAM
DDRAM
data
2nd
W
C7
C6
C5
C4
C3
C2
C1
C0
Cn: character code
specification for each RAM
CGRAM
data write
1st
W
0
0
1
*
*
X2
X1
X0
Xn: Address specification
for each RAM
CGRAM
Data
2nd
W
C35
C30
C25
C20
C15
C10
C5
C0
—
CGRAM
Data
3rd
W
C36
C31
C26
C21
C16
C11
C6
C1
—
CGRAM
Data
4th
W
C37
C32
C27
C22
C17
C12
C7
C2
CGRAM
Data
5th
W
C38
C33
C28
C23
C18
C13
C8
C3
—
CGRAM
Data
6th
W
C39
C34
C29
C24
C19
C14
C9
C4
—
ADRAM
data write
1st
W
0
1
0
X4
X3
X2
X1
X0
Xn: Address specification
for each RAM
ADRAM
Data
2nd
W
*
*
*
*
*
*
C1
C0
Cn: character code
specification for each RAM
General
output
port set
1st
W
0
1
1
*
*
*
P2
P1
Pn: General output port
status specification
63H
Display
duty set
1st
W
1
0
0
*
*
D2
D1
D0
Dn: display duty
specification
80H
Number
of digits
set
1st
W
1
0
1
*
K3
K2
K1
K0
Kn: Number of digits
specification
A0H
C0H
E0H
Cn: character code
specification for each RAM
All lights
ON/OFF
1st
W
1
1
0
*
D
S
H
L
D: display on/off instruction
S: standby mode instruction
H: all lights ON instruction
L: all lights OFF instruction
TEST
mode
1st
W
1
1
1
0
0
0
0
0
For HOLTEK internal
testing
Rev. 1.00
11
00H
—
20H
—
40H
—
January 18, 2012
HT16525
Functional Description
Command and Data Transfer Methods
Complete access to the VFD driver consists of display
commands and the display data. The number of the
transmitted data bytes for a complete access depends
upon the command and memory type as the Command
Table shows. The display control commands and data
are transmitted using a 3-wire serial interface from
the host MCU. The following steps show how the
operation of the serial interface circuitry.
Timing Generation Circuit
A timing generation circuit generates timing signals
for the operation of internal circuits such as the
DDRAM, CGRAM, CGROM and ADRAM.
VFD Driver Circuit
The VFD driver circuit consists of 24 grid signal
drivers and 40 segment signal drivers. When the
number of digits are selected by a corresponding
command, the required grid signal drivers
automatically output drive waveforms, while the other
grid signal drivers continue to output non-selection
waveforms. Sending serial data is latched when the
display data character pattern corresponds to the last
address of the display data RAM (DDRAM).
• Setting the CS pin to a “Low” level will enable a
data transfer.
• Data is 8-bits wide and is sequentially shifted-in on
the SI pin from LSB to MSB (LSB first)
• Data shifted into the register is ready at the rising
edge of the serial shift clock SCK. If the 8-bit
data is to be written in, then internal signals are
automatically generated and the data will be written
into the corresponding register and RAM.
Data Display RAM - DDRAM
• Setting the CS pin to “High” will disable the
command and data transfer
The Display Data RAM (DDRAM) stores the display
data in 8-bit character codes. Its extended capacity is
24x8 bits or 24 characters.
• When data is written into the RAM area including
DDRAM, ADRAM and CGRAM continuously,
the command used to specify the RAM area is
contained in the first shifted-in command byte
together with the start address. Then the RAM
address will be internally incremented by 1
automatically. Therefore, it is not necessary to
specify the start address of the data to be written
after the command byte.
DDRAM Data Write Command
Reset Function
Byte
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
1st
W
0
0
0
X4
X3
X2
X1
Bit0
X0
2nd
W
C7
C6
C5
C4
C3
C2
C1
C0
3rd
W
C7
C6
C5
C4
C3
C2
C1
C0
4th
W
C7
C6
C5
C4
C3
C2
C1
C0
:
:
:
:
:
:
:
:
:
:
The DDRAM data write command descriptions are
shown in the following:
When the RST pin is set to “Low”, the module is
initialized to the following conditions:
• X4~X0: DDRAM address is for 24 characters
addressed from 00H to 17H. The addresses ranged
from 18H to 1FH are unused and unavailable
addresses.
• Address will be reset to 00H for each RAM
including DDRAM, ADRAM and CGRAM
• The contents of the RAM including DDRAM,
ADRAM and CGRAM are undefined.
• C7~C0: character code of the CGROM (internal
248 characters) or CGRAM (user-defined 8
characters)
• All general output ports go “High”.
• Display duty setting will be reset to 8/16 duty
(register value D2, D1, D0=0, 0, 0).
• To specify the character code of the CGROM or
CGRAM continuously, only the character code
needs to be specified
• Number of digits setting will be reset to 24 digits
(register value K3, K2, K1, K0=0, 0, 0, 0).
• The addresses of the DDRAM are automatically
incremented by 1.
• All display lights ON/OFF settings will be
switched to the “display off” mode (register value
D,S,H,L=0,0,0,0)
• The address will be wrapped around to the start
address when the DDRAM data write function is
successively executed and the DDRAM address is
greater than the maximum available address
• All segment outputs go “Low”.
• All AD outputs go “Low”.
• All grid outputs go “Low”.
Note: After a power on reset, all the RAM including
DDRAM, ADRAM and CGRAM will be
cleared.
Rev. 1.00
12
January 18, 2012
HT16525
• Grid positions and set DDRAM addresses
HEX
X4
X3
X2
X1
X0
Grid Position
0
0
0
0
0
0
G1
1
0
0
0
0
1
G2
2
0
0
0
1
0
G3
3
0
0
0
1
1
G4
4
0
0
1
0
0
G5
5
0
0
1
0
1
G6
6
0
0
1
1
0
G7
7
0
0
1
1
1
G8
8
0
1
0
0
0
G9
9
0
1
0
0
1
G10
A
0
1
0
1
0
G11
B
0
1
0
1
1
G12
C
0
1
1
0
0
G13
D
0
1
1
0
1
G14
E
0
1
1
1
0
G15
F
0
1
1
1
1
G16
10
1
0
0
0
0
G17
11
1
0
0
0
1
G18
12
1
0
0
1
0
G19
13
1
0
0
1
1
G20
14
1
0
1
0
0
G21
15
1
0
1
0
1
G22
16
1
0
1
1
0
G23
17
1
0
1
1
1
G24
Note: If the specified address in this command is not defined (X4~X0=18H~1FH), the function will not be
changed.
Rev. 1.00
13
January 18, 2012
HT16525
Character Generator ROM - CGROM
• The CGROM for generating character patterns of 5x8 dots from 8-bit character codes generates 248 types of
character patterns
• The character codes are shown on the following page
• Character codes 00H to 07H are allocated to the CGRAM
LSB
MSB
0000
0000
RAM0
(CGRAM)
0001
RAM1
(CGRAM)
0010
RAM2
(CGRAM)
0011
RAM3
(CGRAM)
0100
RAM4
(CGRAM)
0101
RAM5
(CGRAM)
0110
RAM6
(CGRAM)
0111
RAM7
(CGRAM)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1000
1001
1010
1011
1100
1101
1110
1111
Character Code Table for ROM Code 001
Rev. 1.00
14
January 18, 2012
HT16525
MSB
LSB
0000
0000
RAM0
0001
RAM1
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
(CGRAM)
(CGRAM)
0010
RAM2
0011
RAM3
(CGRAM)
(CGRAM)
0100
RAM4
0101
RAM5
(CGRAM)
(CGRAM)
0110
RAM6
(CGRAM)
0111
RAM7
(CGRAM)
1000
1001
1010
1011
1100
1101
1110
1111
Character Code Table for ROM Code 002
Rev. 1.00
15
January 18, 2012
HT16525
Character Generator RAM - CGRAM
• A character pattern stored in the CGRAM can be
displayed and addressed by the character code
specified in the DDRAM
The CGRAM stores the pixel information (1=pixel
on, 0=pixel off) for the eight user-defined 5x7
characters. Valid CGRAM addresses are 00H to 07H.
Character codes 00H~07H are assigned to the userdefined characters.
• To specify character pattern data continuously, only
the character pattern data needs to be specified
• The addresses of the CGRAM are automatically
incremented by 1
CGRAM Data Write Command
Byte
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
• The address will be wrapped around to the start
address when the CGRAM data write function is
successively executed and the CGRAM address is
greater than the maximum available address
Bit0
1st
W
0
0
1
*
*
X2
X1
X0
2nd
W
C35
C30
C25
C20
C15
C10
C5
C0
3rd
W
C36
C31
C26
C21
C16
C11
C6
C1
4th
W
C374
C32
C27
C22
C17
C12
C7
C2
5th
W
C38
C33
C28
C23
C18
C13
C8
C3
6th
W
C39
C34
C29
C24
C19
C14
C9
C4
• CGROM addresses and set CGRAM addresses
HEX
X2
X1
X0
CGRAM
Mapping to
CGROM Address
*: Don’t care
00
0
0
0
RAM00
00000000B
The CGRAM data write command descriptions are
described by the following:
01
0
0
1
RAM01
00000001B
• X2~X0: CGRAM addresses for 8 user-defined
characters
02
0
1
0
RAM02
00000010B
03
0
1
1
RAM03
00000011B
04
1
0
0
RAM04
00000100B
05
1
0
1
RAM05
00000101B
06
1
1
0
RAM06
00000110B
07
1
1
1
RAM07
00000111B
• C39~C0: character pattern data, 40-bit outputs per
digit. The relationship between the 40-bit character
pattern data and the dot positions for each digit is
shown in the accompanying diagram.
• Relationship between the CGRAM output data and the character dot position
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
area that corresponds to 2nd byte (1st column)
area that corresponds to 3rd byte (2nd column)
area that corresponds to 4th byte (3rd column)
area that corresponds to 5th byte (4th column)
area that corresponds to 6th byte (5th column)
Rev. 1.00
16
January 18, 2012
HT16525
Additional Symbol Display RAM - ADRAM
HEX
A
B
C
D
E
F
10
11
12
13
14
15
16
17
The ADRAM stores the additional symbol
information (1=symbol on, 0=symbol off) for the
24 digits. For each 5x8 digit there are two symbols
displayed together with the character. The positional
relationship is shown in the accompanying diagram.
ADRAM Data Write Command
Byte
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
1st
W
0
1
0
X4
X3
X2
X1
Bit0
X0
2nd
W
*
*
*
*
*
*
C1
C0
3rd
W
*
*
*
*
*
*
C1
C0
4th
W
*
*
*
*
*
*
C1
C0
:
:
:
:
:
:
:
:
:
:
*: Don’t care
The ADRAM data write command descriptions are
described by the following:
• X4~X0: ADRAM addresses for 24 digits
• C1~C0: 2 bits Symbol data for each digit
• Symbol data specified by the ADRAM is directly
output regardless of the CGRAM data and the
CGROM code
• The ADRAM can store 2 types of symbol pattern
for each digit
• The ADRAM contents output to the terminal can
be used as a cursor for each digit
• The address of the ADRAM is automatically
incremented by 1
• The address will be wrapped around to the start
address when the ADRAM data write function is
successively executed and the ADRAM address is
greater than the maximum available address
• Grid positions and ADRAM addresses
HEX
0
1
2
3
4
5
6
7
8
9
X4
0
0
0
0
0
0
0
0
0
0
Rev. 1.00
X3
0
0
0
0
0
0
0
0
1
1
X2
0
0
0
0
1
1
1
1
0
0
X1
0
0
1
1
0
0
1
1
0
0
X0
0
1
0
1
0
1
0
1
0
1
X4
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X3
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Grid Position
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
Note: If the specified address in this command is not
defined (X4~X0=18H~1FH), the function will
not be changed.
General Output Port Command
Byte
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1st
W
0
1
1
*
*
*
P2
P1
*: Don’t care
The general output port command descriptions are
described by the following:
• P2, P1: general output port data
• The general output port supports 2-bit static output
operation
• Used to control other I/O devices or controls the
LEDs
• When the general output port data is set to a high
level, the related pin will output a VDD level while
the related pin will output a GND level when the
general output port data is cleared to a low level
• Relationship between the general output port data
and the output pin status
Grid Position
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
P2 P1
Comment
0
0
Sets P2 to low; Sets P1 to low
—
0
1
Sets P2 to low; Sets P1 to high
—
1
0
Sets P2 to high; Sets P1 to low
—
1
Default state when power
Sets P2 to high; Sets P1 to high is applied or when the RST
input is at a low level.
1
17
Display State of
General Output Port
January 18, 2012
HT16525
Display Duty Set Command
All Display Lights On/Off Set Command
Byte
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Byte
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1st
W
1
0
0
*
*
D2
D1
D0
1st
W
1
1
0
*
D
S
H
L
*: Don’t care
*: Don’t care
The display duty set command descriptions are
described by the following:
• D2~D0: Display duty selections
• The display duty adjusts the contrast in 8 stages
using 3 selection bits to adjust the pulse width of
the segment output
• The relationship between the setup data and the
grid duty is shown in the table.
The display ON/OFF set command descriptions are
described by the following:
• S bit: S=“1” is standby mode; S=“0” is normal
mode
• D bit: D=“1” is display ON; D=“0” is display OFF
• H bit: set all lights ON
• L bit: set all lights OFF
• When S bit = “1”, the internal oscillator stops and
all outputs are set to low and the general port is set
to high (P2 and P1 are all at high levels)
• When S bit = “1”, all registers will keep their
original value
• After being woken up, the device will set the S and
D bits to “0”
• The “All display lights ON” command is used
primarily for display testing
• The “All display lights OFF” command is primarily
used for display flashing
• The command bits, including D, H and L bits, can
not control the general output port
• The relationship between the control bits and
display state of G1~G24, S1~S40 and AD1~AD2
pins is shown in the table.
HEX
0
D2
D1
0
D0
0
Grid Duty
Comment
8/16
Default state when power is
applied or when RST input is at a
low level.
0
1
0
0
1
9/16
—
2
0
1
0
10/16
—
3
0
1
1
11/16
—
4
1
0
0
12/16
—
5
1
0
1
13/16
—
6
1
1
0
14/16
—
7
1
1
1
15/16
—
Number of Digits Set Command
Byte
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1st
W
1
0
1
*
K3
K2
K1
K0
*: Don’t care
The number of digits set command descriptions is are
described by the following:
D S H
L
1
0
0 Normal display
—
• K3~K0: number of digit selections
1
0
0
Sets all segments and AD to Low
1 All grids keep scan
General ports active
—
1
0
1
*
Sets all segments and AD to High
All grids keep scan
General ports active
—
Display off mode
(Default state when
power is applied or
when the RST input
is at a low level.)
Standby mode
• The number of display digits can be from 9 to 24
digits using the 4 selection bits.
• The relationship between setup data and the
displayed grid is shown in the table.
HEX K3 K2 K1 K0
Number of
Digits of Grid
Comment
G1 to G24
Default state when power
is applied or when the RST
input is at a low level.
0
0
0
0
0
1
0
0
0
1
G1 to G9
—
2
0
0
1
0
G1 to G10
—
3
0
0
1
1
G1 to G11
—
4
0
1
0
0
G1 to G12
—
5
0
1
0
1
G1 to G13
—
6
0
1
1
0
G1 to G14
—
7
0
1
1
1
G1 to G15
—
8
1
0
0
0
G1 to G16
—
9
1
0
0
1
G1 to G17
—
A
1
0
1
0
G1 to G18
—
B
1
0
1
1
G1 to G19
—
C
1
1
0
0
G1 to G20
—
D
1
1
0
1
G1 to G21
—
E
1
1
1
0
G1 to G22
—
F
1
1
1
1
G1 to G23
—
Rev. 1.00
0
Driver Output Status
Comment
0
0
*
*
Sets all segments and AD to Low
Sets all grids to Low
General ports active
*
1
*
*
Sets all segments and AD to Low
Sets all grids to Low
Set General ports to high
*: Don’t care
18
January 18, 2012
HT16525
Wake-up Setting
TEST Command
The wake-up behavior is described by the following:
Byte
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1st
W
1
1
1
0
0
0
0
0
• The device is woken up when a CS low pulse is
asserted i.e. when a CS signal falling edge occurs.
The TEST command is described by the following:
• The D and S control bits described in the preceding
section will be set to “0” - display off mode
• Only when the TEST pin is high is the TEST
command “E0H” is valid
• The oscillator starts to oscillate after wake-up
• This command is used by HOLTEK for internal
testing.
• The VFD driver does not display until the host
MCU transmits commands to it.
Wake-up
CS
SCK
SI
Rev. 1.00
19
January 18, 2012
HT16525
Setting Flowchart
Power Applied Included
Apply VDD
Apply VH
All display lights OFF
Status of all outputs by
RST signal input
General output port
setting
Number of digits setting
Display duty setting
Select a RAM to be used
CGRAM
Data write mode
(with address setting)
DDRAM
Data write mode
(with address setting)
Address is automatically
incremented
Address is automatically
incremented
DDRAM
Is character code
write ended?
Address is automatically
incremented
CGRAM
Character code
DDRAM
Character code
NO
ADRAM
Data write mode
(with address setting)
NO
CGRAM
Is character code
write ended?
YES
ADRAM
Character code
NO
ADRAM
Is character code
write ended?
YES
YES
YES
Another RAM
to be set?
NO
Releases all display lights
Display operation mode
OFF mode
End
Rev. 1.00
20
January 18, 2012
HT16525
Power-off Flowchart
Display operation mode
Turn off VH
Turn off VDD
Application Circuit
RST Pin is Connected to a MCU
5x8 dot matrix fluorescent display tube
CSB
SCK
SI
RST
Microcontroller
VSS VDD
VDD
2
40
24
AD1-2
S1-40
G1-24
VH
R4
R3
VH
LED
VDD
TEST
VSS
P1-2
OSCI
2
C4
ZD
VDD
VDD
R1
C3
C1
GND
RST Pin is Connected to External Resistor and Capacitor
5x8 dot matrix fluorescent display tube
CSB
SCK
SI
Microcontroller
VDD
2
40
24
AD1-2
S1-40
G1-24
VH
R4
R3
VH
LED
VSS VDD
VDD
RST
TEST
VSS
P1-2
OSCI
R2
VDD
C3
VDD
2
C4
ZD
R1
C2
C1
GND
Note: 1. The VDD value depends on the power supply voltage of the microcontroller used. Adjust the values of
the components R2, R4, C2, C3 and C4 according to the power supply voltage used.
2. The VH value depends on the fluorescent display tube used. Adjust the values of the components R3 and
ZD according to the power supply voltage used.
3. R1=120kW, C1=0.1μF.
Rev. 1.00
21
January 18, 2012
HT16525
Package Information
Package Information
LQFP Outline Dimensions
80-pin80-pin
LQFP
(10mmx10mm)
Outline
Dimensions
LQFP
(10mm10mm) Outline
Dimensions
Dimensions in inch
Symbol
Min.
Nom.
Dimensions
in inch
Max.
Nom.
0.476
0.398
Symbol
A
Min.
0.469
A
B
0.469
0.390
―
B
C
0.390
0.469
―
0.476
C
D
0.469
0.390
―
0.398
0.390
0.016
―
―
0.016
0.006
0.057
0.063
0.004
0.030
0.008
7
D
E
F
G
H
I
J
E
F
G
H
I
J
K
K
α
―
0.053
―
―
0.018
0.004
Symbol
0°
0.053
A
D
E
F
G
H
I
Rev. 1.00
E
F
G
H
I
J
11.90
9.90
―
―
1.35
K
―
―
J
0.45
K
0.10
α
0°
10.10
0.40
0.16
1.45
1.60
0.16
0.45
―
0.10
―
0.10
Max.
12.10
10.10
12.10
10.10
―
―
1.45
0.75
1.60
0.20
7―
―
0.75
―
0.20
April 1, 2010
―
22
7°
10.10
1
―
0.030
12.10
―
0
0.063
0.40
0.10
0.057
12.10
―
1.35
―
―
―
―
0.398
Max.
Nom.
9.90
0.476
Nom.
Dimensions in mm
11.90
0.398
0.008
―
Min.
C
C
―
Dimensions in mm
9.90
9.90
―
0
11.90
D
0.004
0.004
B
B
―
0.018
A
11.90
―
Symbol
Min.
0.006
Max.
0.476
7°
January 18, 2012
HT16525
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright © 2012 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication.
However, Holtek assumes no responsibility arising from the use of the specifications described.
The applications mentioned herein are used solely for the purpose of illustration and Holtek makes
no warranty or representation that such applications will be suitable without further modification,
nor recommends the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical components in life
support devices or systems. Holtek reserves the right to alter its products without prior notification. For
the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
23
January 18, 2012