HOLTEK HT24LC02_10

HT24LC02
CMOS 2K 2-Wire Serial EEPROM
Features
· Operating voltage:
· Partial page write allowed
2.2V~5.5V for temperature -40°C to +85°C
· 8-byte Page write modes
· Low power consumption
· Write operation with built-in timer
- Operation: 5mA max.
- Standby: 2mA max.
· Hardware controlled write protection
· 40-year data retention
· Internal organization: 256´8
· 106 erase/write cycles per word
· 2-wire serial interface
· Industrial temperature range (-40°C to +85°C)
· Write cycle time: 5ms max.
· 8-pin DIP/SOP/TSSOP , SOT23-5 package.
· Automatic erase-before-write operation
General Description
The HT24LC02 is a 2K-bit serial read/write non-volatile
memory device using the CMOS floating gate process.
Its 2048 bits of memory are organized into 256 words
and each word is 8 bits. The device is optimized for use
in many industrial and commercial applications where
low power and low voltage operation are essential. Up
to eight HT24LC02 devices may be connected to the
same 2-wire bus. The HT24LC02 is guaranteed for 1M
erase/write cycles and 40-year data retention.
Block Diagram
Pin Assignment
S C L
S D A
I/O
C o n tro l
L o g ic
H V P u m p
X
D
W P
M e m o ry
C o n tro l
L o g ic
E E P R O M
A rra y
E
C
A 0
1
8
V C C
A 1
2
7
W P
A 2
3
6
S C L
V S S
4
5
S D A
H T 2 4 L C 0 2
8 D IP -A /S O P -A /T S S O P -A
P a g e B u f
Y D E C
A 0 ~ A 2
A d d re s s
C o u n te r
S C L
V V P
5
4
1
S D A
T o p
V ie w
2
3
V S S
V C C
H T 2 4 L C 0 2
S O T 2 3 -5 -A
S e n s e A M P
R /W C o n tro l
N o te : F o r u s e o f S O T 2 3 - 5 p a c k a g e , th e s o ftw a r e A 2 , A 1 , a n d A 0 b its in th e
d e v ic e a d d r e s s w o r d m u s t b e s e t to z e r o to p r o p e r ly c o m m u n ic a te .
V C C
V S S
Pin Description
Pin Name
A0~A2
I/O
I
Description
Address inputs
SDA
I/O
SCL
I
Serial clock data input
WP
I
Write protect
VSS
¾
Negative power supply, ground
VCC
¾
Positive power supply
Rev. 1.70
Serial data inputs/output
1
May 6, 2010
HT24LC02
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VCC+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
Test Conditions
VCC
Conditions
Min.
Typ.
Max.
Unit
VCC
Operating Voltage
¾
-40°C to +85°C
2.2
¾
5.5
V
ICC1
Operating Current
5V
Read at 100kHz
¾
¾
2
mA
ICC2
Operating Current
5V
Write at 100kHz
¾
¾
5
mA
Input Low Voltage
¾
¾
-1
¾
0.3VCC
V
Input High Voltage
¾
¾
0.7VCC
¾
VCC+0.5
V
IOL=2.1mA
¾
¾
0.4
V
¾
¾
1
mA
VIL
VIH
VOL
Output Low Voltage
2.4V
ILI
Input Leakage Current
5V
VIN=0 or VCC
ILO
Output Leakage Current
5V
VOUT=0 or VCC
¾
¾
1
mA
ISTB
Standby Current
2.2V~
5.5V
VIN=0 or VCC
¾
¾
2
mA
CIN
Input Capacitance (See Note)
¾
f=1MHz 25°C
¾
¾
6
pF
COUT
Output Capacitance (See Note)
¾
f=1MHz 25°C
¾
¾
8
pF
Note:
These parameters are periodically sampled but not 100% tested
Rev. 1.70
2
May 6, 2010
HT24LC02
A.C. Characteristics
Symbol
Parameter
Standard
Mode*
Remark
Min.
Max.
VCC=3V±10%
VCC=5V±10%
Min.
Max.
Min.
Max.
Unit
fSK
Clock Frequency
¾
¾
100
¾
400
¾
1000
kHz
tHIGH
Clock High Time
¾
4000
¾
600
¾
400
¾
ns
tLOW
Clock Low Time
¾
4700
¾
1200
¾
600
¾
ns
tr
SDA and SCL Rise Time
Note
¾
1000
¾
300
¾
300
ns
tf
SDA and SCL Fall Time
Note
¾
300
¾
300
¾
100
ns
tHD:STA
START Condition Hold Time
After this period the first
clock pulse is generated
4000
¾
600
¾
250
¾
ns
tSU:STA
START Condition Setup Time
Only relevant for repeated
START condition
4000
¾
600
¾
250
¾
ns
tHD:DAT
Data Input Hold Time
¾
0
¾
0
¾
¾
¾
ns
tSU:DAT
Data Input Setup Time
¾
200
¾
100
¾
100
¾
ns
tSU:STO
STOP Condition Setup Time
¾
4000
¾
600
¾
250
¾
ns
tAA
Output Valid from Clock
¾
¾
3500
¾
900
50
550
ns
4700
¾
1200
¾
500
¾
ns
¾
100
¾
50
¾
50
ns
¾
5
¾
5
¾
5
ms
tBUF
Bus Free Time
Time in which the bus must
be free before a new transmission can start
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time
tWR
Write Cycle Time
Note:
¾
These parameters are periodically sampled but not 100% tested
* The standard mode means VCC= 2.2V to 5.5V at Ta= -40°C to +85°C
For relative timing, refer to timing diagrams
Rev. 1.70
3
May 6, 2010
HT24LC02
Functional Description
· Serial clock (SCL)
· Acknowledge
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
· Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
D a ta a llo w e d
to c h a n g e
S D A
· A0, A1, A2
S C L
The A2, A1 and A0 pins are device address inputs that
are hard wired for the HT24LC02. As many as eight
2K devices may be addressed on a single bus system
(the device addressing is discussed in detail under the
Device Addressing section).
S ta rt
c o n d itio n
The 2K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
The HT24LC02 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when connected to the
VSS. When the write protect pin is connected to Vcc,
the write protection feature is enabled and operates
as shown in the following table.
The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These three bits must
compare to their corresponding hard-wired input pins.
Protect Array
At VCC
Full Array (2K)
At VSS
Normal Read/Write Operations
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Memory Organization
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
· HT24LC02, 2K Serial EEPROM
Internally organized with 256 8-bit words, the 2K requires an 8-bit data word address for random word addressing.
1
0
Device Operations
1
0
A 2
A 1
A 0
R /W
D e v ic e A d d r e s s
· Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
Write Operations
· Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
· Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
· Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).
Rev. 1.70
S to p
c o n d itio n
Device Addressing
· Write protect (WP)
WP Pin
Status
N o A C K
s ta te
A d d re s s o r
a c k n o w le d g e
v a lid
4
May 6, 2010
HT24LC02
· Page write
S e n d W r ite C o m m a n d
The 2K EEPROM is capable of an 8-byte page write.
A page write is initiated the same as byte write, but the
microcontroller does not send a stop condition after
the first data word is clocked in. Instead, after the
EEPROM acknowledges the receipt of the first data
word, the microcontroller can transmit up to seven
more data words. The EEPROM will respond with a
z e ro a f t e r e a c h d a t a w or d r e c ei v e d . T h e
microcontroller must terminate the page write sequence with a stop condition.
The data word address lower three (2K) bits are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row location (refer to Page write timing).
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
S e n d C o tr o ll B y te
w ith R /W = 0
N o
(A C K = 0 )?
Y e s
N e x t O p e r a tio n
· Acknowledge polling
Acknowledge Polling Flow
To maximise bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
· Current address read
The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This address stays valid
between operations as long as the chip power is maintained. The address roll over during read from the last
byte of the last memory page to the first byte of the first
page. The address roll over during write from the last
byte of the current page to the first byte of the same
page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is serially clocked out. The microcontroller should respond a
No ACK (High) signal and following stop condition (refer to Current read timing).
· Write protect
The HT24LC02 has a write-protect function and programming will then be inhibited when the WP pin is
connected to VCC. Under this mode, the HT24LC02 is
used as a serial ROM.
· Read operations
The HT24LC02 supports three read operations,
namely, current address read, random address read
and sequential read. During read operation execution,
the read/write select bit should be set to ²1².
B y te W r ite T im in g
D e v ic e a d d r e s s
S D A
S
W o rd a d d re s s
D A T A
A 2 A 1 A 0
P
R /W
S ta rt
A C K
A C K
A C K
S to p
P a g e W r ite T im in g
D e v ic e a d d r e s s
S D A
W o rd a d d re s s
D A T A n
D A T A n + 1
S
D A T A n + x
P
S ta rt
A C K
A C K
S to p
A C K
A C K
C u r r e n t R e a d T im in g
D e v ic e a d d r e s s
S D A
S
S ta rt
Rev. 1.70
D A T A
S to p
A 2 A 1 A 0
P
A C K
N o A C K
5
May 6, 2010
HT24LC02
· Random read
· Sequential read
A random read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller should respond with a
²no ACK² signal (high) followed by a stop condition.
(refer to Random read timing).
R a n d o m
R e a d T im in g
D e v ic e a d d r e s s
S
S D A
Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an
acknowledgment. As long as the EEPROM receives an
acknowledgment, it will continue to increment the data
word address and serially clock out sequential data
words. When the memory address limit is reached, the
data word address will roll over and the sequential read
continues. The sequential read operation is terminated
when the microcontroller responds with a ²no ACK² signal (high) followed by a stop condition.
A 2
W o rd a d d re s s
D A T A
D e v ic e a d d r e s s
S to p
P
S
A 1 A 0
A C K
S ta rt
A C K
S ta rt
A C K
N o A C K
S e q u e n tia l R e a d T im in g
D e v ic e a d d r e s s
S D A
D A T A n
D A T A n + 1
D A T A n + x
S to p
P
S
A C K
S ta rt
N o A C K
A C K
Timing Diagrams
tf
tr
tL
S C L
tS
U
:S
tH
T A
tS
S D A
tH
IG H
D
O W
:S
T A
tH
D
:D
A T
tS
:D
U
A T
tS
U
tB
U F
:S
T O
P
tA
S D A
A
V a lid
O U T
V a lid
S C L
8 th b it
S D A
A C K
W o rd n
tW
S to p
C o n d itio n
Note:
R
S ta rt
C o n d itio n
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start
condition of sequential command.
Rev. 1.70
6
May 6, 2010
HT24LC02
Package Information
8-pin DIP (300mil) Outline Dimensions
A
8
5
B
1
4
H
C
D
I
G
E
F
Symbol
Nom.
Max.
A
0.355
¾
0.375
B
0.240
¾
0.260
C
0.125
¾
0.135
D
0.125
¾
0.145
E
0.016
¾
0.020
0.070
F
0.050
¾
G
¾
0.100
¾
H
0.295
¾
0.315
I
¾
0.375
¾
Symbol
A
Rev. 1.70
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
9.02
¾
9.53
B
6.10
¾
6.60
C
3.18
¾
3.43
D
3.18
¾
3.68
E
0.41
¾
0.51
F
1.27
¾
1.78
G
¾
2.54
¾
H
7.49
¾
8.00
I
¾
9.53
¾
7
May 6, 2010
HT24LC02
8-pin SOP (150mil) Outline Dimensions
5
8
A
B
4
1
C
C '
G
H
D
E
=
F
· MS-012
Symbol
Nom.
Max.
A
0.228
¾
0.244
B
0.150
¾
0.157
C
0.012
¾
0.020
C¢
0.188
¾
0.197
D
¾
¾
0.069
E
¾
0.050
¾
F
0.004
¾
0.010
G
0.016
¾
0.050
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
A
Rev. 1.70
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
5.79
¾
6.20
B
3.81
¾
3.99
C
0.30
¾
0.51
C¢
4.78
¾
5.00
D
¾
¾
1.75
E
¾
1.27
¾
F
0.10
¾
0.25
G
0.41
¾
1.27
H
0.18
¾
0.25
a
0°
¾
8°
8
May 6, 2010
HT24LC02
8-pin TSSOP Outline Dimensions
8
5
E 1
1
4
E
D
A
L
A 2
e
R
0 .1 0
A 1
B
C
L 1
y
G
(4 C O R N E R S )
Symbol
Min.
Nom.
Max.
A
0.041
¾
0.047
A1
0.002
¾
0.006
A2
0.031
¾
0.041
B
¾
0.010
¾
C
0.004
¾
0.006
D
0.114
¾
0.122
E
0.244
¾
0.260
E1
0.169
¾
0.177
e
¾
0.026
¾
L
0.020
¾
0.028
L1
0.035
¾
0.043
y
¾
¾
0.004
q
0°
¾
8°
Symbol
Rev. 1.70
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
1.05
¾
1.20
A1
0.05
¾
0.15
A2
0.80
¾
1.05
B
¾
0.25
¾
C
0.11
¾
0.15
D
2.90
¾
3.10
E
6.20
¾
6.60
E1
4.30
¾
4.50
e
¾
0.65
¾
L
0.50
¾
0.70
L1
0.90
¾
1.10
y
¾
¾
0.10
q
0°
¾
8°
9
May 6, 2010
HT24LC02
5-pin SOT23-5 Outline Dimensions
D
C
L
H
E
G
e
A
A 2
b
Symbol
Dimensions in inch
Min.
Nom.
Max.
0.039
¾
0.051
A1
¾
¾
0.004
A2
0.028
¾
0.035
A
b
0.014
¾
0.020
C
0.004
¾
0.010
D
0.106
¾
0.122
E
0.055
¾
0.071
e
¾
0.075
¾
H
0.102
¾
0.118
L
0.015
¾
¾
q
0°
¾
9°
Symbol
Rev. 1.70
A 1
Dimensions in mm
Min.
Nom.
Max.
A
1.00
¾
1.30
A1
¾
¾
0.10
A2
0.70
¾
0.90
b
0.35
¾
0.50
C
0.10
¾
0.25
D
2.70
¾
3.10
E
1.40
¾
1.80
e
¾
1.90
¾
H
2.60
¾
3.00
L
0.37
¾
¾
q
0°
¾
9°
10
May 6, 2010
HT24LC02
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 8N, TSSOP 8L
Symbol
Description
A
Reel Outer Diameter
Dimensions in mm
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
2.0±0.5
12.8+0.3/-0.2
18.2±0.2
SOT23-5
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
178.0±1.0
B
Reel Inner Diameter
62.0±1.0
C
Spindle Hole Diameter
13.0±0.2
D
Key Slit Width
2.50±0.25
T1
Space Between Flange
8.4+1.5/-0.0
T2
Reel Thickness
11.4+1.5/-0.0
Rev. 1.70
11
May 6, 2010
HT24LC02
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
P
B 0
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 8N
Symbol
Description
Dimensions in mm
12.0+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
5.5±0.1
D
Perforation Diameter
1.55±0.10
D1
Cavity Hole Diameter
1.50+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.4±0.1
B0
Cavity Width
5.2±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
0.30±0.05
9.3±0.1
TSSOP 8L
Symbol
Description
W
Carrier Tape Width
P
Cavity Pitch
E
Perforation Position
Dimensions in mm
12.0+0.3/-0.1
8.0±0.1
1.75±0.10
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.5+0.1/-0.0
D1
Cavity Hole Diameter
1.5+0.1/-0.0
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
7.0±0.1
B0
Cavity Width
3.6±0.1
K0
Cavity Depth
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.70
5.5±0.5
1.6±0.1
0.300±0.013
9.3±0.1
12
May 6, 2010
HT24LC02
SOT23-5
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
8.0±0.3
P
Cavity Pitch
4.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
3.50±0.05
D
Perforation Diameter
1.5+0.1/-0.0
D1
Cavity Hole Diameter
1.5+0.1/-0.0
P0
Perforation Pitch
P1
Cavity to Perforation (Length Direction)
2.00±0.05
A0
Cavity Length
3.15±0.10
B0
Cavity Width
3.2±0.1
K0
Cavity Depth
1.4±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.70
4.0±0.1
0.20±0.03
5.3±0.1
13
May 6, 2010
HT24LC02
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http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.70
14
May 6, 2010