H High CMR Analog Isolation Amplifiers Technical Data HCPL-7820 HCPL-7825 Features Applications • Fast Propagation Delays for Over-Current and Fault Detection Sensing • High Common Mode Rejection (CMR): 30 kV/µs at VCM = 1000 V* • 3% Gain Tolerance: HCPL-7820 5% Gain Tolerance: HCPL-7825 • 0.05% Nonlinearity • Low Offset Voltage and Offset Drift vs. Temperature • 200 kHz Bandwidth • Performance Specified for Common Motor Control Applications over -40°C to 100°C Temperature Range • Worldwide Safety and Regulatory Approval: UL 1577 (3750 V rms/1 Min), VDE 0884 and CSA • Compact Auto-Insertable Standard 8-Pin DIP Package • Advanced Sigma-Delta (Σ∆) A/D Converter Technology • 1 µm CMOS IC Technology • Motor Phase and Rail Current Sensing • General Purpose Current Sensing and Monitoring • High-Voltage Monitoring • Switched Mode Power Supply Signal Isolation • General Purpose Analog Signal Isolation • Transducer Isolation Description The HCPL-7820/7825 high CMR isolation amplifier consists of a sigma-delta analog-to-digital converter optically coupled to an integrated output digital-to-analog converter. When used with a shunt resistor in the current path, the HCPL-7820/7825 provides a cost-effective, auto-insertion compatible current sense solution. Fast propagation delays allow this part to be used in either motor drive or inverter applications for either phase current monitoring or rail current fault detection applications. High isolation mode rejection makes this product suitable for noisy electrical environments, such as those generated by the high switching rates of power IGBTs. Low offset voltage together with low offset change vs. temperature permits accurate use of auto-calibration techniques. Tight gain tolerance with good nonlinearity further provide the characteristics needed to insure highly accurate motor speed control. A high operating temperature range with specified performance parameters allow Functional Diagram VDD1 VIN+ VIN– GND1 1 2 3 IDD1 IDD2 + + – – 4 8 7 6 5 VDD2 VOUT+ VOUT– GND2 CMR SHIELD A 0.1 µF bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8. *The terms common-mode rejection (CMR) and isolation-mode rejection (IMR) are used interchangeably throughout this data sheet. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 5965-3591E 1-233 this device to be used in hostile industrial environments. This performance is delivered in an auto-insertable, industry standard 8-pin DIP package that meets major worldwide regulatory and safety approval ratings to help ensure that your equipment can be certified in many geographic areas. Ordering Information HCPL-782x 0 = ± 3% Gain Tolerance 5 = ± 5% Gain Tolerance Option yyy 300 = Gull Wing Surface Mount Lead Option 500 = Tape/Reel Package Option (1 k min.) Option datasheets available. Contact your Hewlett-Packard sales representative or authorized distributor for information. Package Outline Drawings Standard DIP Package 9.40 (0.370) 9.90 (0.390) 8 7 6 5 TYPE NUMBER DATE CODE HP 7820 7.36 (0.290) 7.88 (0.310) YYWW PIN ONE 1.19 (0.047) MAX. 1 2 3 5° TYP. 4 1.78 (0.070) MAX. 4.70 (0.185) MAX. PIN ONE 0.51 (0.020) MIN. 2.92 (0.115) MIN. 0.76 (0.030) 1.24 (0.049) 0.65 (0.025) MAX. 2.28 (0.090) 2.80 (0.110) DIMENSIONS IN MILLIMETERS AND (INCHES). 1-234 0.20 (0.008) 0.33 (0.013) 6.10 (0.240) 6.60 (0.260) PIN DIAGRAM VDD2 8 1 VDD1 2 VIN+ VOUT+ 7 3 VIN– VOUT– 6 4 GND1 GND2 5 Gull Wing Surface Mount Option 300* PIN LOCATION (FOR REFERENCE ONLY) 9.65 ± 0.25 (0.380 ± 0.010) 6 7 8 1.02 (0.040) 1.19 (0.047) 5 4.83 TYP. (0.190) HP 7820 6.350 ± 0.25 (0.250 ± 0.010) YYWW 1 MOLDED 3 2 9.65 ± 0.25 (0.380 ± 0.010) 4 1.19 (0.047) 1.78 (0.070) 9.65 ± 0.25 (0.380 ± 0.010) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 0.380 (0.015) 0.635 (0.025) 7.62 ± 0.25 (0.300 ± 0.010) 0.20 (0.008) 0.33 (0.013) 4.19 MAX. (0.165) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 0.51 ± 0.130 (0.020 ± 0.005) 2.540 (0.100) BSC 12° NOM. DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005 LEAD COPLANARITY MAXIMUM: 0.102 (0.004) *Refer to Option 300 Data Sheet for more information. TEMPERATURE – °C Maximum Solder Reflow Thermal Profile 260 240 220 200 180 160 140 120 100 80 ∆T = 145°C, 1°C/SEC ∆T = 115°C, 0.3°C/SEC ∆T = 100°C, 1.5°C/SEC 60 40 20 0 0 1 2 3 4 5 6 7 8 9 10 11 12 TIME – MINUTES (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.) 1-235 Regulatory Information The HCPL-7820/7825 has been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, FILE E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. VDE Approved according to VDE 0884/06.92. Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Min. External Air Gap (External Clearance) Min. External Tracking Path (External Creepage) Min. Internal Plastic Gap (Internal Clearance) L(IO1) 7.4 mm L(IO2) 8.0 mm 0.5 mm 175 V Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity DIN IEC 112/VDE 0303 Part 1 Tracking Resistance (Comparative Tracking Index) Isolation Group CTI III a Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 – surface mount classification is Class A in accordance with CECC 00802. VDE 0884 (06.92) Insulation Characteristics Description Installation classification per DIN VDE 0110, Table 1 for rated mains voltage ≤ 300 V rms for rated mains voltage ≤ 600 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1)* Maximum Working Insulation Voltage Input to Output Test Voltage, Method b** VPR = 1.875 x VIORM, Production test with tp = 1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a** VPR = 1.5 x VIORM, Type and sample test with tp = 60 sec, Partial discharge < 5 pC Highest Allowable Overvoltage** (Transient Overvoltage tTR = 10 sec) Safety-limiting values (Maximum values allowed in the event of a failure, also see Figure 22) Case Temperature Input Power Output Power Insulation Resistance at TS, VIO = 500 V Symbol Characteristic Unit VIORM VPR I-IV I-III 40/100/21 2 848 1591 V peak V peak VPR 1273 V peak VTR 6000 V peak TS PS,Input PS,Output RS 175 80 250 ≥ 1x1012 °C mW mW Ω *This part may also be used in Pollution Degree 3 environments where the rated mains voltage is ≤ 300 V rms (per DIN VDE 0110). **Refer to the front of the optocoupler section of the current catalog for a more detailed description of VDE 0884 and other product safety requirements. Note: Optocouplers providing safe electrical separation per VDE 0884 do so only within the safety-limiting values to which they are qualified. Protective cut-out switches must be used to ensure that the safety limits are not exceeded. 1-236 Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Storage Temperature Ambient Operating Temperature Supply Voltages Steady-State Input Voltage Two Second Transient Input Voltage Output Voltages Lead Solder Temperature (1.6 mm below seating plane, 10 sec.) TS TA VDD1, VDD2 VIN+, VIN- -55 - 40 0.0 -2.0 -6.0 -0.5 125 100 5.5 VDD1 +0.5 °C °C V V VDD2 +0.5 260 V °C VOUT+, VOUTTLS Reflow Temperature Profile Note 1 See Package Outline Drawings Section Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltages Input Voltage Symbol Min. Max. Unit Note TA VDD1, VDD2 VIN+, VIN- -40 4.5 -200 100 5.5 200 °C V mV 2 1-237 DC Electrical Specifications All specifications are at the nominal (typical) operating conditions of VIN+ = 0 V, VIN- = 0 V, TA = 25°C, VDD1 = 5 V and VDD2 = 5 V, unless otherwise noted. Parameter Input Offset Voltage Absolute Value of Input Offset Change vs. Temperature Gain: HCPL-7820 Gain: HCPL-7825 200 mV Nonlinearity 100 mV Nonlinearity Maximum Input Voltage Before Output Clipping Symbol Min. Typ. Max. Unit VOS -0.8 0.45 1.7 mV -2.0 0.45 2.9 |∆VOS /∆T| G G 7.76 8.00 8.24 7.60 8.00 8.40 7.60 8.00 8.40 7.44 8.00 8.56 0.06 0.15 NL100 0.03 |VIN+| max -40°C ≤ TA ≤ 100°C 4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V µV/°C 7.8 NL200 Test Conditions V/V -200 mV ≤ VIN+ ≤ 200 mV -200 mV ≤ VIN+ ≤ 200 mV -200 mV ≤ VIN+ ≤ 200 mV -40°C ≤ TA ≤ 100°C 4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V % -200 mV ≤ VIN+ ≤ 200 mV 0.3 -200 mV ≤ VIN+ ≤ 200 mV -40°C ≤ TA ≤ 100°C 4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V 0.08 -100 mV ≤ VIN+ ≤ 100 mV 0.1 -100 mV ≤ VIN+ ≤ 100 mV -40°C ≤ TA ≤ 100°C 4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V 1,2,3 3,4 5 5,6,7 5 5,6,7 5,8 5 5,8, 9,10, 12 5,8 5,8, 9,11, 12 4 13 6 4 7 -1 µA Average Input Resistance RIN 280 kΩ Input DC Common-Mode Rejection Ratio CMRRIN 52 dB Output Resistance RO 1.2 Ω Output Low Voltage VOL 1.30 V VIN+ = 400 mV Output High Voltage VOH 3.90 V VIN+ = -400 mV Output CommonMode Voltage VOCM Input Supply Current -400 mV < VIN+ < 400 mV -40°C ≤ TA ≤ 100°C 4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V Output Supply Current 1-238 3 mV IIN Output Short-Circuit Current 1 320 Average Input Bias Current 2.30 Note 1,2 -200 mV ≤ VIN+ ≤ 200 mV -40°C ≤ TA ≤ 100°C 4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V V/V Fig. 2.60 2.90 V IDD1 11.1 17.0 mA IDD2 10.0 14.0 mA |IOSC| 12 mA 14 15 VOUT = 0 V or VDD2 8 AC Electrical Specifications All specifications and figures are at the nominal (typical) operating conditions of VIN+ = 0 V, VIN- = 0 V, TA = 25°C, VDD1 = 5 V and VDD2 = 5 V, unless otherwise noted. Parameter Isolation Mode Rejection Isolation Mode Rejection Ratio at 60 Hz Propagation Delay to 50% Propagation Delay to 90% Rise/Fall Time (10-90%) Small-Signal Bandwidth (-3 dB) Small-Signal Bandwidth (-45°) RMS Input-Referred Noise Power Supply Rejection Symbol Min. IMR 20 IMRR tPD50 tPD90 tR/F f-3dB 1.20 1.60 0.85 150 Typ. Max. Unit Test Conditions 30 kV/µs VIM = 1 kV -40°C < TA ≤ 100°C 4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V >140 dB 1.85 2.75 1.50 200 2.85 4.10 2.25 380 Fig. Note 16 10 µs VIN+ = 0 to 100 mV step 17,18 -40°C ≤ TA ≤ 100°C 4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V kHz -40°C ≤ TA ≤ 100°C 17,19, 4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V 20 f-45° 85 VN 1.4 mV rms PSR 150 mV p-p 9 In recommended application circuit 21,24 11 12 Package Characteristics All specifications and figures are at the nominal (typical) operating conditions of VIN+ = 0 V, VIN- = 0 V, TA = 25°C, VDD1 = 5 V and VDD2 = 5 V, unless otherwise noted. Parameter Symbol Min. Typ. Input-Output Momentary VISO 3750 Withstand Voltage* Input-Output RI-O 1012 1013 Resistance 1011 Input-Output CI-O 0.7 Capacitance Input IC Junction-toθjci 96 Case Thermal Resistance Output IC Junction-toθjco 114 Case Thermal Resistance Max. Unit V rms Ω pF °C/W Test Conditions t = 1 min., RH ≤ 50% TA = 25°C VI-O = 500 Vdc TA = 100°C f = 1 MHz Fig. Note 13,14 13 Thermocouple located at center underside of package °C/W *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification, or HP Application Note 1074, “Optocoupler Input-Output Endurance Voltage.” 1-239 Notes: 1. HP recommends the use of nonchlorine activated fluxes. 2. If VIN- is brought above VDD1-2 V with respect to GND1 an internal test mode may be activated. This test mode is not intended for customer use. 3. Exact offset value is dependent on layout of external bypass capacitors. The offset value in the data sheet corresponds to HP’s recommended layout (see Figures 26 and 27). 4. Data sheet value is the average magnitude of the difference in offset voltage from TA = 25°C to TA = 100°C, expressed in microvolts per °C. 5. Nonlinearity is defined as half of the peak-to-peak deviation from the bestfit gain line, expressed as a percentage of the full-scale differential output voltage. 6. Because of the switched-capacitor nature of the input sigma-delta A/D converter, time-averaged values are shown. 7. When the differential input signal exceeds approximately 320 mV, the outputs will limit at the typical values shown. 1-240 8. Short-circuit current is the amount of output current generated when either output is shorted to VDD2 or ground. 9. IMR (also known as CMR or Common Mode Rejection) specifies the minimum rate of rise of an isolation mode noise signal at which small output perturbations begin to appear. These output perturbations can occur with both the rising and falling edges of the isolation mode waveform and may be of either polarity. A CMR failure is defined as a perturbation exceeding 200 mV at the output of the recommended application circuit (Figure 24). See applications section for more information on CMR. 10. IMRR is defined as the ratio of differential signal gain (signal applied differentially between pins 2 and 3) to the isolation mode gain (input pins tied to pin 4 and the signal applied between the input and the output of the isolation amplifier) at 60 Hz, expressed in dB. 11. Output noise comes from two primary sources: chopper noise and sigmadelta quantization noise. Chopper noise results from chopper stabilization of the output op-amps. It occurs at a specific frequency (typically 500 kHz) and is not attenuated by the on-chip output filter. The on-chip filter does eliminate most, but not all, of the sigma-delta quantization noise. An external filter circuit may be easily added to the external post-amplifier to reduce the total RMS output noise. See applications section for more information. 12. Data sheet value is the amplitude of the transient at the differential output of the HCPL-7820/7825 when a 1 Vp-p, 1 MHz square wave with 200 ns rise and fall times (measured at pins 1 and 8) is applied to both VDD1 and VDD2. 13. This is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together. 14. In accordance with UL 1577, for devices with minimum VISO specified at 3750 V rms, each optocoupler is proof-tested by applying an insulation test voltage greater than 4500 V rms for one second (leakage current detection limit II-O < 5 µA). This test is performed before the method b, 100% production test for partial discharge shown in the VDE 0884 Insulation Characteristics Table. VDD2 +15 V 0.1 µF 1 8 0.1 µF 2 7 10 K + HCPL-7820/7825 0.1 µF 6 3 4 VOUT 10 K 5 – 0.47 µF AD624CD GAIN = 100 0.47 µF 0.1 µF ∆VOS – INPUT OFFSET CHANGE – mV VDD1 0.6 0.5 0.4 VDD1 = 5 V VDD2 = 5 V 0.3 0.2 0.1 0 -0.1 -40 -20 -15 V 40 60 80 100 Figure 2. Input Offset Change vs. Temperature. 4.0 0.5 vs. VDD1 (VDD2 = 5 V) 0.4 VO – OUTPUT VOLTAGE – V ∆VOS – INPUT OFFSET CHANGE – mV 20 TA – TEMPERATURE – °C Figure 1. Input Offset Voltage Test Circuit. vs. VDD2 (VDD1 = 5 V) 0.3 TA = 25°C 0.2 0.1 0 -0.1 -0.2 4.4 4.6 4.8 5.0 5.2 5.4 3.5 NEGATIVE OUTPUT 2.5 2.0 VDD1 = 5 V VDD2 = 5 V TA = 25°C 1.5 1.0 -0.6 5.6 POSITIVE OUTPUT 3.0 -0.4 -0.2 0 0.4 0.2 0.6 VIN – INPUT VOLTAGE – V VDD – SUPPLY VOLTAGE – V Figure 3. Input Offset Change vs. VDD1 and VDD2. Figure 4. Output Voltages vs. Input Voltage. VDD2 VDD1 +15 V +15 V 0.1 µF 1 404 0.1 µF 2 7 10 K + HCPL-7820/7825 13.2 0.1 µF 8 0.1 µF VIN 0 3 6 4 5 10 K VOUT – 0.01 µF 0.47 µF + AD624CD GAIN = 4 0.47 µF – AD624CD GAIN = 10 0.1 µF -15 V 0.1 µF -15 V 10 K 0.47 µF Figure 5. Gain and Nonlinearity Test Circuit. 1-241 0.3 0.2 0.1 0 -0.1 0.3 0.04 0.2 0.02 0.1 0 -0.1 -0.2 -0.3 -40 -20 0 20 40 60 80 -0.5 4.4 100 Figure 6. Gain Change vs. Temperature. 5.0 5.2 5.4 -0.04 -0.06 -0.08 -0.10 -0.2 5.6 0.08 VDD1 = 5 V VDD2 = 5 V VIN– = 0 V 0.06 0.04 0.02 0 -40 -20 0 20 40 60 80 100 0.075 TA = 25°C 0.065 0.060 0.055 Figure 9. Nonlinearity vs. Temperature. 4.6 4.8 5.0 5.2 5.4 0.05 VDD1 = 5 V VDD2 = 5 V 0 ±0.05 ±0.10 ±0.15 ±0.20 ±0.25 ±0.30 FS – FULL-SCALE VALUE – V Figure 12. Nonlinearity vs. Full-Scale Value. IIN – INPUT CURRENT – mA 0.10 0.036 0.032 0.030 0.028 -4 VDD1 = 5 V VDD2 = 5 V VIN– = 0 V TA = 25°C -8 -4 -2 0 2 4 VIN+ – INPUT VOLTAGE – V Figure 13. Input Current vs. Input Voltage. 4.8 5.0 5.2 5.4 5.6 Figure 11. 100 mV Nonlinearity vs. VDD1 and VDD2. -2 -6 4.6 VDD – SUPPLY VOLTAGE – V 0 -10 -6 TA = 25°C 0.034 0.024 4.4 5.6 2 TA = 100°C TA = 25°C TA = -40°C vs. VDD1 (VDD2 = 5 V) 0.026 Figure 10. 200 mV Nonlinearity vs. VDD1 and VDD2. 0.50 0.2 0.1 vs. VDD2 (VDD1 = 5 V) VDD – SUPPLY VOLTAGE – V TA – TEMPERATURE – °C 0 0.038 vs. VDD2 (VDD1 = 5 V) 0.070 0.050 4.4 -0.1 0.040 NL – NONLINEARITY – % NL – NONLINEARITY – % 0.12 VDD1 = 5 V VDD2 = 5 V VIN– = 0 V TA = 25°C Figure 8. Nonlinearity Error Plot vs. Input Voltage. vs. VDD1 (VDD2 = 5 V) 0.10 200 mV ERROR 100 mV ERROR VIN+ – INPUT VOLTAGE – V 0.080 200 mV NL 100 mV NL 0.14 NL – NONLINEARITY – % 4.8 Figure 7. Gain Change vs. VDD1 and VDD2. 0.16 NL – NONLINEARITY – % 4.6 -0.02 VDD – SUPPLY VOLTAGE – V TA – TEMPERATURE – °C 1-242 vs. VDD1 (VDD2 = 5 V) vs. VDD2 (VDD1 = 5 V) -0.4 -0.2 0.01 TA = 25°C -0.3 0 6 IDD1 – INPUT SUPPLY CURRENT – mA ∆G – GAIN CHANGE – % ∆G – GAIN CHANGE – % VDD1 = 5 V VDD2 = 5 V ERROR – % OF FULL SCALE 0.5 0.4 14 13 TA = 100°C TA = 25°C TA = -40°C 12 11 10 VDD1 = 5 V VDD2 = 5 V VIN– = 0 V 9 8 7 -0.4 -0.2 0 0.2 VIN+ – INPUT VOLTAGE – V Figure 14. Input Supply Current vs. Input Voltage. 0.4 10 K 75 pF VDD2 78L05 +15 V IDD2 – OUTPUT SUPPLY CURRENT – mA IN OUT 12 TA = 100°C TA = 25°C TA = -40°C 11 0.1 µF VDD1 = 5 V VDD2 = 5 V VIN– = 0 V 1 0.1 µF 0.1 µF 8 0.1 µF 2 2K 7 – HCPL-7820/7825 9V 3 6 4 5 VOUT 2K + MC34081 10 0.1 µF 10 K 9 75 pF PULSE GEN. 8 -0.4 -0.2 0 0.2 0.4 -15 V – + VIM VIN+ – INPUT VOLTAGE – V Figure 15. Output Supply Current vs. Input Voltage. Figure 16. Isolation Mode Rejection Test Circuit. 10 K VDD1 VDD2 +15 V 3.0 0.1 µF 1 0.1 µF 8 2.5 2 VIN 2K 7 – HCPL-7820/7825 0.01 µF 3 6 4 5 VOUT 2K + MC34081 t – TIME – µs 0.1 µF DELAY TO 90% DELAY TO 50% RISE/FALL TIME 2.0 VDD1 = 5 V VDD2 = 5 V 1.5 0.1 µF VIN– = 0 V VIN+ = 0 TO 100 mV STEP 10 K 1.0 -40 -20 -15 V f (-3 dB) – 3 dB BANDWIDTH – kHz RELATIVE AMPLITUDE – dB 260 -1 VDD1 = 5 V VDD2 = 5 V TA = 25 °C -2 -3 -4 1 5 10 50 100 f – FREQUENCY – kHz Figure 19. Amplitude Response vs. Frequency. 500 250 240 230 220 VDD1 = 5 V VDD2 = 5 V 210 200 190 -40 -20 0 20 20 40 60 80 100 Figure 18. Propagation Delays and Rise/Fall Time vs. Temperature. 40 60 80 TA – TEMPERATURE – °C Figure 20. 3 dB Bandwidth vs. Temperature. 100 VN – RMS INPUT-REFERRED NOISE – mV Figure 17. Propagation Delay, Rise/Fall Time and Bandwidth Test Circuit. 0 0 TA – TEMPERATURE – °C 3.0 VIN+ = 200 mV VIN+ = 100 mV VIN+ = 0 mV 2.5 VDD1 = 5 V VDD2 = 5 V VIN– = 0 V TA = 25 °C 2.0 1.5 1.0 0.5 0 5 10 50 100 500 1000 f – FREQUENCY – kHz Figure 21. RMS Input-Referred Noise vs. Recommended Application Circuit Bandwidth. 1-243 Applications Information 300 Functional Description Figure 23 shows the primary functional blocks of the HCPL7820/7825. In operation, the sigma-delta modulator converts the analog input signal into a high-speed serial bit stream. The time average of this bit stream is directly proportional to the input signal. This stream of digital data is encoded and optically transmitted to the detector circuit. The detected signal is decoded and converted back into an analog PSi – POWER – mW 250 PS, OUTPUT 200 PS, INPUT 150 MAX. OPERATING TEMP. IS 100 °C 100 50 0 0 50 100 150 200 TA – TEMPERATURE – °C Figure 22. Dependence of SafetyLimiting Values on Temperature. VOLTAGE REGULATOR CLOCK GENERATOR signal, which is filtered to obtain the final output signal. Application Circuit The recommended application circuit is shown in Figure 24. A floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 V using a simple three-terminal voltage regulator (U1). The voltage from the current sensing resistor, or shunt (RSENSE), is applied to the input of VOLTAGE REGULATOR ISOLATION BOUNDARY ISO-AMP INPUT Σ∆ MODULATOR LED DRIVE CIRCUIT ENCODER DETECTOR CIRCUIT DECODER AND D/A FILTER ISO-AMP OUTPUT Figure 23. HCPL-7820/7825 Block Diagram. FLOATING SUPPLY HV+ GATE DRIVE CIRCUIT C5 75 pF • • • R3 FLOATING SUPPLY 10.0 KΩ U1 78L05 +5 V +15 V C8 0.1 µF IN OUT C1 C2 0.1 µF 0.1 µF R5 39 Ω 1 8 2 7 C4 0.1 µF R1 2.00 KΩ C3 0.01 3 µF U2 6 R2 – U3 + MC34081 2.00 KΩ MOTOR • • • + – 4 C7 5 RSENSE HCPL-7820/7825 C6 75 pF R4 10.0 KΩ -15 V • • • HV– Figure 24. Recommended Application Circuit. 1-244 0.1 µF VOUT the HCPL-7820/7825 through an RC anti-aliasing filter (R5, C3). And finally, the differential output of the isolation amplifier is converted to a ground-referenced single-ended output voltage with a simple differential amplifier circuit (U3 and associated components). Although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. Supplies and Bypassing As mentioned above, an inexpensive 78L05 three-terminal regulator can be used to reduce the gate-drive power supply voltage to 5 V. To help attenuate highfrequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass filter with the regulator’s input bypass capacitor. As shown in Figure 24, 0.1 µF bypass capacitors (C2, C4) should be located as close as possible to the input and output power supply pins of the HCPL-7820/7825. The bypass capacitors are required because of the high-speed digital nature of the signals inside the isolation amplifier. A 0.01 µF bypass capacitor (C3) is also recommended at the input pin(s) due to the switched-capacitor nature of the input circuit. The input bypass capacitor should be at least 1000 pF to maintain gain accuracy of the isolation amplifier. Inductive coupling between the input power-supply bypass capacitor and the input circuit, which includes the input bypass capacitor and the input leads of the HCPL-7820/7825, can introduce additional DC offset in the circuit. Several steps can be taken to minimize the mutual coupling between the two parts of the circuit, thereby improving the offset performance of the design. Separate the two bypass capacitors C2 and C3 as much as possible (even putting them on opposite sides of the PC board), while keeping the total lead lengths, including traces, of each bypass capacitor less than 20 mm. PC board traces should be made as short as possible and placed close together or over ground plane to minimize loop area and pickup of stray magnetic fields. Avoid using sockets, as they will typically increase both loop area and inductance. And finally, using capacitors with small body size and orienting them perpendicular to each other on the PC board can also help. For more information concerning inductive coupling, see the Application Note Designing with Hewlett-Packard Isolation Amplifiers. Shunt Resistor Selection The current-sensing shunt resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). The value of the shunt should be chosen as a compromise between minimizing power dissipation by making the shunt resistance smaller and improving circuit accuracy by making it larger and using more of the input range of the HCPL-7820/7825. HewlettPackard recommends 4 different shunts which can be used to sense average currents in motor drives up to 35 A and 35 hp. Table 1 shows the maximum current and horsepower range for each of the LVR-series shunts from Dale. Even higher currents can be sensed with lower value shunts available from vendors such as Dale, IRC, and Isotek (Isabellenhuette). When sensing currents large enough to cause significant heating of the shunt, the temperature coefficient of the shunt can introduce nonlinearity due to the amplitude dependent temperature rise of the shunt. Using a heat sink for the shunt or using a shunt with a lower tempco can help minimize this effect. The Application Note Designing with Hewlett-Packard Isolation Amplifiers contains additional information on designing with current shunts. The recommended method for connecting the isolation amplifier to the shunt resistor is shown in Table 1. Current Shunt Summary Shunt Resistor Part Number Shunt Resistance Maximum Power Dissipation Maximum RMS Current Maximum Horsepower Range LVR-3.05-1% LVR-3.02-1% LVR-3.01-1% LVR-5.005-1% 50 mΩ 20 mΩ 10 mΩ 5 mΩ 3W 3W 3W 5W 3A 8A 15 A 35 A 0.8-3.0 hp 2.2-8.0 hp 4.1-15 hp 9.6-35 hp 1-245 Figure 24. Pin 2 (VIN+) is connected to the positive terminal of the shunt resistor, while pin 3 (VIN-) is shorted to pin 4 (GND1), with the power-supply return path functioning as the sense line to the negative terminal of the current shunt. This allows a single pair of wires or PC board traces to connect the isolation amplifier circuit to the shunt resistor. In some applications, however, supply currents flowing through the power-supply return path may cause offset or noise problems. In this case, better performance may be obtained by connecting pin 3 to the negative terminal of the shunt resistor separately from the power supply return path. When connected this way, both input pins should be bypassed. Whether two or three wires are used, it is recommended that twisted-pair wire or very close PC board traces be used to connect the current shunt to the isolation amplifier circuit to minimize electromagnetic interference to the sense signal. The 39 Ω resistor in series with the input lead forms a low-pass anti-aliasing filter with the input bypass capacitor with a 400 kHz bandwidth. The resistor performs another important function as well; it dampens any ringing which might be present in the circuit formed by the shunt, the input bypass capacitor, and the wires or traces connecting the two. Undamped ringing of the input circuit near the input sampling frequency can alias into C5 75 pF +5 V R3 10.0 KΩ +5 V +5 V C8 0.1 µF R4A 20.0 KΩ 1 8 2 7 C4 0.1 µF R1 – U3 + MC34071 10.0 KΩ U2 R2 6 3 VOUT the baseband producing what might appear to be noise at the output of the device. PC Board Layout In addition to affecting offset, the layout of the PC board can also affect the common mode rejection (CMR) performance of the isolation amplifier, due primarily to stray capacitive coupling between the input and the output circuits. To obtain optimal CMR performance, the layout of the printed circuit board (PCB) should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground plane on the PCB does not pass directly below or extend much wider than the HCPL-7820/7825. Using surface-mount components can help achieve many of the PCB objectives discussed in the preceding paragraphs. An example through-hole PCB layout illustrating some of the more important layout recommendations is shown in Figures 26 and 27. See the Application Note Designing with Hewlett-Packard Isolation Amplifiers for more information on PCB layout considerations. 10.0 KΩ 4 5 C6 75 pF HCPL-7820/7825 R4B 20.0 KΩ Figure 25. Single-Supply Post-Amplifier Circuit. C2 R5 C4 TO VDD1 C3 Figure 26. Top Layer of Printed Circuit Board Layout. 1-246 TO RSENSE+ TO RSENSE– TO VDD2 VOUT+ VOUT– Figure 27. Bottom Layer of Printed Circuit Board Layout. Post-Amplifier Circuit The recommended application circuit (Figure 24) includes a post-amplifier circuit that serves three functions: to reference the output signal to the desired level (usually ground), to amplify the signal to appropriate levels, and to help filter output noise. The particular op-amp used in the post-amp is not critical; however, it should have low enough offset and high enough bandwidth and slew rate so that it does not adversely affect circuit performance. The offset of the opamp should be low relative to the output offset of the HCPL-7820/ 7825, or less than about 5 mV. To maintain overall circuit bandwidth, the post-amplifier circuit should have a bandwidth at least twice the minimum bandwidth of the isolation amplifier, or about 400 kHz. To obtain a bandwidth of 400 kHz with a gain of 5, the op-amp should have a gainbandwidth greater than 2 MHz. The post-amplifier circuit includes a pair of capacitors (C5 and C6) that form a single-pole low-pass filter. These capacitors allow the bandwidth of the post-amp to be adjusted independently of the gain and are useful for reducing the output noise from the isolation amplifier (doubling the capacitor values halves the circuit bandwidth). The component values shown in Figure 24 form a differential amplifier with a gain of 5 and a cutoff frequency of approximately 200 kHz and were chosen as a compromise between low noise and fast response times. The overall recommended application circuit has a bandwidth of 130 kHz, a rise time of 2.6 µs and delay to 90% of 4.2 µs. The gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate CMRR and gain tolerance for the overall circuit. Resistor networks with even better ratio tolerances can be used which offer better performance, as well as reducing the total component count and board space. The post-amplifier circuit can be easily modified to allow for singlesupply operation. Figure 25 shows a schematic for a post-amplifier for use in 5 V single-supply applications. One additional resistor is needed and the gain is decreased to allow circuit operation over the full input voltage range. See the Application Note Designing with Hewlett-Packard Isolation Amplifiers for more information on the post-amplifier circuit. Other Information As mentioned above, reducing the bandwidth of the post amplifier circuit reduces the amount of output noise. Figure 21 shows how the output noise changes as a function of the post-amplifier bandwidth. The post-amplifier circuit exhibits a first-order lowpass filter characteristic. For the same filter bandwidth, a higherorder filter can achieve even better attenuation of modulation noise due to the second-order noise shaping of the sigma-delta modulator. For more information on the noise characteristics of the HCPL-7820/7825, see the Application Note Designing with Hewlett-Packard Isolation Amplifiers. The HCPL-7820/7825 can also be used to isolate signals with amplitudes larger than its recommended input range with the use of a resistive voltage divider at its input. The only restrictions are that the impedance of the divider be relatively small (less than 1 kΩ) so that the input resistance (280 kΩ) and input bias current (1 µA) do not affect the accuracy of the measurement. An input bypass capacitor is still required, although the 39 Ω series damping resistor is not (the resistance of the voltage divider provides the same function). The low-pass filter formed by the divider resistance and the input bypass capacitor may limit the achievable bandwidth. 1-247