H 2 – 26.5 Medium Power Amplifier Technical Data HMMC-5027 Features • Wide-Frequency Range: 2-26.5 GHz • Moderate Gain: 7 dB • Gain Flatness: 1 dB • Return Loss: Input -13 dB Output -11 dB • Low-Frequency Operation Capability: < 2 GHz • Gain Control: 30 dB Dynamic Range • Medium Power: 20 GHz: P-1dB: 22 dBm Psat: 24 dBm 26.5 GHz: P-1dB: 19 dBm Psat: 21 dBm Description The HMMC-5027 is a broadband GaAs MMIC Traveling Wave Amplifier designed for medium output power and moderate gain over the full 2 to 26.5 GHz frequency range. Seven MESFET cascode stages provide a flat gain response, making the HMMC-5027 an ideal wideband power block. Optical lithography is used to produce gate lengths of ≈ 0.5 mm. The HMMC-5027 incorporates advanced MBE technology, Ti-Pt-Au gate metallization, silicon nitride passivation, and polyimide for scratch protection. Chip Size: Chip Size Tolerance: Chip Thickness: Pad Dimensions: 2980 x 770 µm (117.3 x 30.3 mils) ± 10 µm (± 0.4 mils) 127 ± 15 µm (5.0 ± 0.6 mils) 75 x 75 µm (2.95 x 2.95 mils), or larger Absolute Maximum Ratings[1] Symbol Parameters/Conditions Units Min. Max. VDD Positive Drain Voltage V 8.0 IDD Total Drain Current mA 300 VG1 First Gate Voltage V -5 0 IG1 First Gate Current mA -1 +1 VG2 Second Gate Voltage V -2.5 +5 IG2 Second Gate Current mA -25 PDC DC Power Dissipation watts 2.4 Pin CW Input Power dBm 23 Tch Operating Channel Temp. °C +150 Tcase Operating Case Temp. °C -55 TSTG Storage Temperature °C -65 Tmax Maximum Assembly Temp. (for 60 seconds maximum) °C +165 +300 Note: 1. Operation in excess of any one of these conditions may result in permanent damage to this device. TA = 25°C except for Tch, TSTG, and Tmax. 6-47 5965-5447E HMMC-5027 DC Specifications/Physical Properties [1] Symbol IDSS Vp VG2 IDSOFF(VG1) IDSOFF(VG2) θch-bs Parameters and Test Conditions Saturated Drain Current (VDD = 8.0 V, VG1 = 0.0 V, VG2 = open circuit) First Gate Pinch-off Voltage (VDD = 8.0 V, IDD = 30 mA, VG2 = open circuit) Second Gate Self-Bias Voltage (VDD = 8.0 V, VG1 = 0.0 V) First Gate Pinch-off Current (VDD = 8.0 V, VG1 = -3.5 V, VG2 = open circuit) Second Gate Pinch-off Current (VDD = 5.0 V, VG1 = 0.0 V, VG2 = -3.5 V) Thermal Resistance (Tbackside = 25°C) Units mA Min. 200 Typ. 300 Max. 500 V -2.2 -1.3 -.5 V 1.8 (0.27 x VDD) mA 7 mA 10 °C/W 28 Note: 1. Measured in wafer form with Tchuck = 25°C. (Except θch-bs.) HMMC-5027 RF Specifications[1], Top = 25°C, VD1 = VD2 = 5 V, VG1 = VG2= Open, ZO = 50 Ω, unless otherwise noted Symbol BW S21 ∆ S21 RLin RLout S12 P-1dB Psat H2 H3 NF Parameters and Test Conditions Guaranteed Bandwidth[2] Small Signal Gain Small Signal Gain Flatness Input Return Loss Output Return Loss Reverse Isolation Output Power @ 1dB Gain Compression Saturated Output Power Second Harmonic Power Level (2 < ƒo < 20) [Po(ƒo) = 21 dBm or P-1dB, whichever is less] Third Harmonic Power Level (2 < ƒo < 20) [Po(ƒo) = 21 dBm or P-1dB, whichever is less] Noise Figure Units GHz dB dB dB dB dB dBm dBm dBc Min. 2 6 16.5 18.5 Typ. 7 ± 0.8 -13 -11 -28 19 21 -21 dBc -32 dB 11 Max. 26.5 -10 -10 -25 -18 -18 Notes: 1. Small-signal data measured in wafer form with Tchuck = 25°C. Large-signal data measured on individual devices mounted in an HP83040 Series Modular Microcircuit Package at TA = 25°C. 2. Performance may be extended to lower frequencies through the use of appropriate off-chip circuitry. Upper corner frequency ~ 30 GHz. 6-48 HMMC-5027 Applications The HMMC-5027 series of traveling wave amplifiers are designed for use as general purpose wideband power stages in communication systems and microwave instrumentation. They are ideally suited for broadband applications requiring a flat gain response and excellent port matches over a 2 to 26.5 GHz frequency range. Dynamic gain control and low-frequency extension capabilities are designed into these devices. Biasing and Operation These amplifiers are biased with a single positive drain supply (VDD) and a single negative gate supply (VG1). The recommended bias conditions for the HMMC-5027 are VDD = 8.0V, IDD␣ =␣ 250␣ mA or I DSS, whichever is less. To achieve this drain current level, VG1 is typically biased between 0 V and -0.6 V. No other bias supplies or connections to the device are required for 2 to 26.5 GHz operation. The gate voltage (VG1) MUST be applied prior to the drain voltage (VDD) during power up and removed after the drain voltage during power down. See Figure 3 for assembly information. The auxiliary gate and drain contacts are used only for lowfrequency performance extension below ≈ 1.0 GHz. When used, these contacts must be AC coupled only. (Do not attempt to apply bias to these pads.) The second gate (VG2) can be used to obtain 30 dB (typical) dynamic gain control. For normal operation, no external bias is required on this contact and its self-bias potential is between +1.5 and +2.5 volts. Applying an external bias between its open circuit potential and -2.5 volts will adjust the gain while maintaining a good input/output port match. Assembly Techniques Solder die-attach using a fluxless AuSu solder preform is the recommended assembly method. Gold thermosonic wedge bonding with 0.7 mil diameter Au wire is recommended for all bonds. Tool force should be 22 ± 1 gram, stage temperature should be 150 ± 2°C, and ultrasonic power and duration should be 64 ± 1 dB and 76␣ ± ␣ 8 msec, respectively. The bonding pad and chip backside metallization is gold. For more detailed information see HP application note #999 “GaAs MMIC Assembly and Handling Guidelines.” GaAs MMICs are ESD sensitive. Proper precautions should be used when handling these devices. Seven Identical Stages Drain Bias (VDD) RF Output 7.5 50 Aux. Drain Second Gate Bias (VG2) 248 248 RF Input 15K 50 17K 5.5 30K Single Stage Shown First Gate Bias (VG1) Aux. Gate Notes: FET gate periphery in microns. All resistors in ohms. (Ω), (or in K-ohms, where indicated) Figure 1. HMMC-5027 Schematic. 6-49 VDD RF Output Aux. Drain VG2 RF Input VG1 Chip ID No. Aux. Gate 2910 70 (VDD and Aux Drain Pads) (RF Output Pad) 700 555 770 465 (±10 µm) 285 220 75 0 70 (RF Input Pad) 2290 2580 2900 (VG2 Pad) 2980 (± 10 µm) Notes: All dimensions in microns. Rectangular Pad Dim: 75 x 75 µm. Octagonal Pad Dim: 90 µm dia. All other dimensions ±5 µm (unless otherwise noted). Chip thickness: 127 ± 15 µm. Figure 2. HMMC-5027 Bonding Pad Locations. 1.5 mil dia.Gold Wire Bond to ≥15 nF DC Feedthru ≥68 pF Capacitor Input and Output Thin Film Circuit with ≥8 pF DC Blocking Capacitor 4 nH Inductor (1.0 mil Gold Wire Bond with length of 200 mils) Gold Plated Shim 2.0 mil nom. gap Trace Offset 168 µm (6.6 mils) VDD IN OUT VG1 Trace Offset 168 µm (6.6 mils) 2.0 mil nom. gap Bonding Island 0.7 mil dia. Gold Bond Wire (Length NOT important) Figure 3. HMMC-5027 Assembly Diagram. 1.5 mil dia.Gold Wire Bond to ≥15 nF DC Feedthru Note: Total offset between RF input and RF output pad is 335 µm (13.2 mils). 6-50 HMMC-5027 Typical Performance –20 7 6 –30 5 4 –40 3 2 –50 1 0 –60 2 4 6 8 10 12 14 16 18 20 22 24 26.5 VDD = 8.0 V, IDD = 250 mA[1] –15 –15 –20 –20 –25 –25 –30 –30 –35 –35 –40 –40 2 4 6 8 10 12 14 16 18 20 22 24 26.5 FREQUENCY (GHz) Figure 4. Typical Gain and Reverse Isolation vs. Frequency. –10 OUTPUT RETURN LOSS,S22 (dB) 9 8 –10 –10 INPUT RETURN LOSS, S11 (dB) VDD = 8.0 V, IDD = 250 mA[1] REVERSE ISOLATION, S12 (dB) SMALL-SIGNAL GAIN, S21 (dB) 10 FREQUENCY (GHz) Figure 5. Typical Input and Output Return Loss vs. Frequency. Typical Scattering Parameters[1], (Tchuck = 25°C, VDD = 8.0 V, IDD = 250 mA or IDSS, whichever is less, Zin = Zo = 50 Ω S21 S12 Freq. S11 GHz dB Mag Ang dB Mag Ang dB Mag Ang 2.0 -18.7 0.116 -139.5 -57.7 0.0013 -165.2 8.7 2.717 116.6 3.0 -20.1 0.099 -159.0 -54.9 0.0018 144.2 8.4 2.635 94.8 4.0 -21.5 0.084 -175.7 -52.0 0.0025 154.0 8.3 2.612 72.0 5.0 -24.6 0.059 167.8 -49.9 0.0032 111.3 8.4 2.634 48.2 6.0 -32.0 0.025 167.4 -48.2 0.0039 91.3 8.6 2.699 23.3 7.0 -30.8 0.029 -94.8 -46.9 0.0045 74.9 8.8 2.763 -3.5 8.0 -22.7 0.073 -103.2 -45.5 0.0053 21.0 8.8 2.768 -30.9 9.0 -18.9 0.114 -121.5 -45.2 0.0055 10.3 8.8 2.744 -58.9 10.0 -17.2 0.137 -142.6 -44.7 0.0058 -15.5 8.5 2.673 -85.9 11.0 -17.4 0.135 -163.9 -43.5 0.0067 -33.4 8.3 2.608 -112.5 12.0 -19.3 0.108 175.6 -41.5 0.0084 -45.4 8.2 2.564 -138.5 13.0 -25.6 0.052 170.3 -40.6 0.0093 -75.8 8.2 2.578 -164.9 14.0 -27.0 0.045 -113.0 -38.6 0.0118 -95.9 8.3 2.610 167.1 15.0 -19.2 0.109 -111.0 -37.8 0.0129 -124.7 8.3 2.605 138.4 16.0 -15.6 0.167 -127.9 -37.1 0.0139 -149.1 8.2 2.574 108.8 17.0 -14.3 0.193 -148.4 -36.3 0.0153 -174.5 8.0 2.510 79.7 18.0 -14.8 0.182 -166.6 -35.8 0.0163 164.1 7.8 2.444 50.9 19.0 -17.1 0.140 -179.3 -34.7 0.0185 141.5 7.7 2.418 22.1 20.0 -21.4 0.086 -166.2 -32.9 0.0227 112.6 7.8 2.466 -7.5 21.0 -18.4 0.121 -129.5 -31.6 0.0262 80.7 8.1 2.527 -39.9 22.0 -13.8 0.205 -137.2 -30.9 0.0285 42.7 8.0 2.512 -74.0 23.0 -12.1 0.247 -152.7 -30.6 0.0296 13.3 7.6 2.395 -108.4 24.0 -12.3 0.244 -169.8 -30.3 0.0304 -15.5 7.4 2.344 -142.5 25.0 -14.7 0.184 -175.8 -29.7 0.0329 -44.9 7.3 2.315 -175.6 26.0 -16.7 0.146 -149.3 -28.5 0.0375 -78.1 7.9 2.469 148.1 26.5 -14.1 0.197 -141.6 -28.0 0.0399 -98.5 8.0 2.503 126.9 Note: 1. Data obtained from on-wafer measurements. 6-51 dB -13.0 -13.0 -13.5 -14.0 -15.3 -16.9 -18.4 -21.3 -18.9 -17.9 -18.2 -19.3 -22.1 -31.2 -23.5 -18.1 -15.2 -13.7 -13.9 -16.8 -25.3 -19.8 -13.7 -11.3 -11.7 -13.0 S22 Mag 0.223 0.224 0.212 0.200 0.171 0.143 0.120 0.086 0.114 0.127 0.123 0.108 0.078 0.028 0.067 0.124 0.174 0.207 0.202 0.145 0.054 0.102 0.207 0.272 0.259 0.223 Ang 173.5 150.0 127.1 101.6 71.7 39.5 -2.2 -46.9 -90.7 -129.6 -162.6 163.4 126.5 56.7 -33.3 -80.7 -115.2 -147.6 177.9 136.7 66.9 -56.2 -103.5 -136.7 -171.3 172.3 HMMC-5027 Typical Performance VDD = 8.0 V, IDD [@TA = 25°C] = 250 mA .012 dB/°C –55°C –25°C 0° C + 25°C + 55°C + 85°C +100°C .022 dB/°C 10 9 8 7 6 5 4 2 4 6 8 10 12 14 16 18 20 22 24 26.5 VDD = 8.0 V, VGI ≅ –0.2 V 10 VG2 = +2.0 V, IDD = 250 mA VG2 = 0.0 V, IDD = 218 mA VG2 = –0.5 V, IDD = 180 mA VG2 = –1.0 V, IDD = 119 mA VG2 = –1.5 V, IDD = 62 mA VG2 = –3.0 V, IDD = 12 mA VG2 = –2.5 V, IDD = 13 mA VG2 = –2.0 V, IDD = 26 mA 0 –10 –20 –30 –40 –50 2 4 6 8 10 12 14 16 18 20 22 24 26.5 FREQUENCY (GHz) FREQUENCY (GHz) Figure 6. Typical Small-Signal Gain vs. Temperature. Figure 7. Typical Gain vs. Second Gate Control Voltage. VDD = 8.0 V, IDD (Q) = 250 mA –10 8 Psat P–1dB 20 18 –20 HARMONICS (dBc) OUTPUT POWER (dBm) 22 10 –15 26 24 VDD = 8.0 V, IDD (Q) = 250 mA 4 –25 –30 –35 –40 –45 –50 16 3rd Harmonic –55 14 2 4 6 8 10 12 14 16 18 20 22 24 26.5 FREQUENCY (GHz) Figure 8. Typical 1 dB Gain Compression and Saturated Output Power vs. Frequency. 6 2nd Harmonic –60 2 4 6 8 10 12 14 16 18 20 22 24 26.5 FUNDAMENTAL FREQUENCY, fo (GHz) Figure 9. Typical Second and Third Harmonic vs. Fundamental Frequency at POUT = +21 dBm. Note: 1. All data measured on individual devices mounted in an HP83040 Series Modular Microcircuit Package @ TA = 25°C (except where noted). This data sheet contains a variety of typical and guaranteed performance data. The information supplied should not be interpreted as a complete list of circuit specifications. In this data sheet the term typical refers to the 50th percentile performance. For additional information contact your local HP sales representative. 6-52 NOISE FIGURE (dB) 28 12 2 10 ASSOCIATED GAIN (dB) 11 20 TCASE .015 dB/°C SMALL-SIGNAL GAIN, S21 (dB) SMALL-SIGNAL GAIN, S21 (dB) 12 8 6 4 2 2 4 6 8 10 12 14 16 18 20 22 24 26.5 FREQUENCY (GHz) Figure 10. Typical Noise Figure Performance. Nominal Bias: VDD = 8.0 V, IDD = 250 mA Optimal NF Bias: VDD = 6.5 V, IDD = 130 mA