DDR Termination Regulator TJ2995 FEATURES z z z z z z z z SOP8 / SOP8-PP PKG Low Output Voltage Offset Works with +5V, +3.3V, and 2.5V Rails Source and Sink Current Low External Component Count No External Resistors Required Linear Topology Available in SOP8, SOP8-PP Package Low Cost and Easy to Use APPLICATION ORDERING INFORMATION z DDR-I and DDR-II Termination Voltage z SSTL-2 and SSTL-3 Termination Device (Marking) Package TJ2995D SOP8 TJ2995DP SOP8-PP DESCRIPSION The TJ2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transient. This device can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. With an independent VSENSE pin, the TJ2995 can provide superior load regulation. The TJ2995 provides a VREF output as the reference for the chipset and DDR DIMMS. The TJ2995 can easily provide the accurate VTT and VREF voltages without external resistors that PCB areas can be reduced. The quiescent current is low to meet the low power consumption applications. Absolute Maximum Ratings CHARACTERISTIC SYMBOL MIN. MAX. UNIT PVIN AVIN VDDQ -0.3 -0.3 -0.3 6.0 6.0 6.0 V Supply Voltage to GND Lead Temperature (Soldering, 10 sec) TSOL 260 ℃ Storage Temperature Range TSTG -65 150 ℃ Operating Junction Temperature Range TJOPR -40 125 ℃ SYMBOL MIN. MAX. UNIT AVIN to GND AVIN 2.3 5.5 V PVIN to GND PVIN 0 AVIN V Recommended Operation Range CHARACTERISTIC Ordering Information Package Order No. Description Package Marking Supplied As SOP8 TJ2995D DDR Termination Regulator TJ2995 Reel SOP8-PP TJ2995DP DDR Termination Regulator TJ2995 Reel Oct. 2009 - Rev. 1.1 1/9 HTC DDR Termination Regulator TJ2995 PIN CONFIGURATION NC 1 8 VTT GND 2 NC 1 7 PVIN 8 VTT GND 2 Exposed 7 PVIN Thermal VSENSE 3 6 AVIN VREF 4 VSENSE 3 5 VDDQ PAD VREF 4 6 AVIN 5 VDDQ SOP8 SOP8-PP PIN DESCRIPTION Pin No. Pin Name 1 NC 2 GND 3 VSENSE 4 VREF Buffered Internal Reference Voltage of VDDQ/2 5 VDDQ Input for Internal Reference Equal to VDDQ/2 6 AVIN Analog Input Pin 7 PVIN Power Input Pin 8 VTT Output Voltage for Connection to Termination Resistors Exposed Thermal PAD Pin Function No Internal Connection Ground Feedback Pin for Regulating VTT Exposed Thermal Connection. Connect to Ground. (SOP8-PP Only) TYPICAL APPLICATION Oct. 2009 - Rev. 1.1 2/9 HTC DDR Termination Regulator TJ2995 ELECTRICAL CHARACTERISTICS (1) Specifications with standard typeface are for TJ = 25°. Unless otherwise specified, AVIN = PVIN = 2.5V, VDDQ = 2.5V.(1), (4) PARAMETER VREF Voltage VTT Output Voltage VTT Output Voltage Offset (2) Quiescent Current (3) SYMBOL TEST CONDITION VREF VDDQ = 2.3V VDDQ = 2.5V VDDQ = 2.7V VTT IOUT = 0 A VDDQ = 2.3V VDDQ = 2.5V VDDQ = 2.7V IOUT = ± 1.5 A VDDQ = 2.3V VDDQ = 2.5V VDDQ = 2.7V VOSVTT IQ VDDQ Input Impedance ZVDDQ VSENSE Input Current ISENSE Thermal Shutdown (5) TSD IOUT = 0 A IOUT = +1.5 A IOUT = -1.5 A IOUT = 0A MIN. TYP. MAX. UNIT 1.11 1.21 1.31 1.15 1.25 1.35 1.19 1.29 1.39 V 1.11 1.21 1.31 1.15 1.25 1.35 1.19 1.29 1.39 1.11 1.21 1.31 1.15 1.25 1.35 1.19 1.29 1.39 -40 -40 -40 0 0 0 40 40 40 mV - 250 2000 uA - 100 - kΩ - 0.1 uA 165 - ℃ - V Note 1. Stresses listed as the absolute maximum ratings may cause permanent damage to the device. These are for stress ratings. Functional operating of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibly to affect device reliability. Note 2: VTT offset is the voltage measurement defined as VTT subtracted from VREF. Note 3: Quiescent current defined as the current flow into AVIN. Note 4: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation. Note 5. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal resistance, θJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal shutdown. Oct. 2009 - Rev. 1.1 3/9 HTC DDR Termination Regulator TJ2995 TYPICAL OPERATING CHARACTERISTICS AVIN = 2.0V/Div, VDDQ/PVIN = 1.0V/div, VREF = 500mV/div, VTT = 500mV/div, Time = 10ms/div AVIN = 2.0V/Div, VDDQ/PVIN = 1.0V/div, VREF = 500mV/div, VTT = 500mV/div, Time = 10ms/div Start Up Shut Down AVIN = 2.0V/Div, VDDQ/PVIN = 2.0V/div, VTT = 100mV/div, IOUT = 1A/div, Time = 10ms/div AVIN = 2.0V/Div, VDDQ/PVIN = 2.0V/div, VTT = 100mV/div, IOUT = 1A/div, Time = 10ms/div Load (0A → 1A) Load (1A → 0A) VDDQ = 2.5V AVIN vs. Quiescent Current Oct. 2009 - Rev. 1.1 4/9 HTC DDR Termination Regulator TJ2995 DESCRIPTION The TJ2995 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-3. The TJ2995 is capable of sinking and sourcing current at the output VTT, regulating the voltage to equal VDDQ / 2. A buffered reference voltage that also tracks VDDQ / 2 is generated on the VREF pin for providing a global reference to the DDR-SDRAM and Northbridge Chipset. VTT is designed to track the VREF voltage with a tight tolerance over the entire current range while preventing shoot through on the output stage. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR RAM. The most common form of termination is Class II single parallel termination. This involves using one RS series resistor from the chipset to the memory and one RT termination resistor. This implementation can be seen below in Figure 1. FIGURE 1. SSTL-Termination Scheme PIN DESCRIPTION AVIN AND PVIN AVIN and PVIN are the input supply pins for the TJ2995. AVIN is used to supply all the internal control circuitry for the two op-amps and the output stage of VREF. PVIN is used exclusively to provide the rail voltage for the output stage on the power operational amplifier used to create VTT. For SSTL-2 applications AVIN and PVIN pins should be connected directly and tied to the 2.5V rail for optimal performance. This eliminates the need for bypassing the two supply pins separately. VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of two internal 50㏀ resistors. This guarantees that VTT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 2.5V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be a 2.5V signal, which will create a 1.25V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT over temperature). Oct. 2009 - Rev. 1.1 5/9 HTC DDR Termination Regulator TJ2995 VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the TJ2995, then the long trace will cause a significant IR drop, resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus. If remote load regulation is not used, then the VSENSE pin must still be connected to VTT. VREF VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.1 µF to 0.01 µF is recommended. This output remains active during the shutdown state and thermal shutdown events for the suspend to RAM functionality. VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VDDQ / 2. The TJ2995 is designed to handle peak transient currents of up to ± 3A with a fast transient response. If a transient is expected to last above the maximum continuous current rating for a significant amount of time then the output capacitor should be sized large enough to prevent an excessive voltage drop. Despite the fact that the TJ2995 is designed to handle large transient output currents it is not capable of handling these for long durations, under all conditions. The reason for this is the standard packages are not able to thermally dissipate the heat as a result of the internal power loss. If large currents are required for longer durations, then care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal derating should always be used (please refer to the Thermal Dissipation section). THERMAL DISSIPATION Since the TJ2995 is a linear regulator any current flow from VTT will result in internal power dissipation generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate the part dependent on the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise, TRmax can be calculated given the maximum ambient temperature, TAmax of the application and the maximum allowable junction temperature, TJmax. TRmax = TJmax − TAmax From this equation, the maximum allowable power dissipation, PDmax of the part can be calculated: PDmax = TRmax / θ JA Oct. 2009 - Rev. 1.1 6/9 HTC DDR Termination Regulator TJ2995 The maximum allowable value for junction-to-ambient thermal resistance, θJA, can be calculated using the formula: θJA = TRmax / PD = (TJmax – TAmax) / PD The θJA of the TJ2995 will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow. For instance, the θJA of the SOP8 is 165°C/W with the package mounted to a standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value can be reduced to 152°C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard. Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. Using larger traces and more copper on the top side of the board can also help. With careful layout it is possible to reduce the θJA further than the nominal values. Additional improvements in lowering the θ JA can also be achieved with a constant airflow across the package. Optimizing the θJA and placing the TJ2995 in a section of a board exposed to lower ambient temperature allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by summing the three main sources of loss: output current at VTT, either sinking or sourcing, and quiescent current at AVIN and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation can be calculated from the following equations: PD = PAVIN + PVDDQ + PVTT Where, PAVIN = PVDDQ = IAVIN x VAVIN VVDDQ x IVDDQ = VVDDQ2 x RVDDQ To calculate the maximum power dissipation at VTT both conditions at VTT need to be examined, sinking and sourcing current. Although only one equation will add into the total, VTT cannot source and sink current simultaneously. PVTT = VVTT x ILOAD (Sinking) or PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing) The power dissipation of the TJ2995 can also be calculated during the shutdown state. During this condition the output VTT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN and the constant impedance that is seen at the VDDQ pin. PD = PAVIN + PVDDQ , Where, PAVIN = IAVIN x VAVIN PVDDQ Oct. 2009 - Rev. 1.1 = VVDDQ x IVDDQ = VVDDQ2 7/9 x RVDDQ HTC DDR Termination Regulator TJ2995 TYPICAL APPLICATION INFORMATION The typical application circuit used for SSTL-2 termination schemes with DDR-SDRAM can be seen in Figure 2. FIGURE 2. SSTL-2 Implementation For SSTL-3 and other applications, it may be desirable to change internal reference voltage scaling from the VDDQ / 2. An external resistor in series with the VDDQ pin can be used to lower the reference voltage. Internally two 50 kΩ resistors set the output VTT to be equal to VDDQ / 2. The addition of a 11.1 kΩ external resistor will change the internal reference voltage causing the two outputs to track VDDQ * 0.45. An implementation of this circuit can be seen in Figure 3. FIGURE 3. SSTL-3 Implementation Another application that is sometimes required is to increase the VTT output voltage from the scaling factor of VDDQ * 0.5. This can be accomplished independently of VREF by using a resistor divider network between VTT, VSENSE and Ground. An example of this circuit can be seen in Figure 4. FIGURE 4. Increased VTT from the Scaling Factor Oct. 2009 - Rev. 1.1 8/9 HTC DDR Termination Regulator TJ2995 PCB LAYOUT CONSIDERATIONS 1. AVIN and PVIN should be tied together for optimal performance. A local bypass capacitor should be placed as close as possible to the PVIN pin. 2. GND should be connected to a ground plane with multiple vias for improved thermal performance. 3. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For motherboard applications an ideal location would be at the center of the termination bus. 4. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage. 5. VREF should be bypassed with a 0.01 μF or 0.1 μF ceramic capacitor for improved performance. This capacitor should be located as close as possible to the VREF pin. Oct. 2009 - Rev. 1.1 9/9 HTC