HY63V8400 Series 512Kx8bit CMOS FAST SRAM PRELIMINARY DESCRIPTION FEATURES The HY63V8400 is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8-bits. The HY63V8400 uses eight common input and output lines and has an output enable pin which operates faster than. address access time at read cycle. The device is fabricated using Hyundai's advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications • • • • Single 3.3V±0.3V Power Supply Fully static operation and Tri-state output TTL compatible inputs and outputs Low data Retention Voltage: - 2.0V(min) –L-ver. Only • Center Power/Ground Pin Configuration • Standard pin configuration - 36pin 400mil SOJ - 44pin 400mil TSOP-ll Product No. Supply Voltage(V) Speed (ns) Operation Current(mA) HY63V8400 HY63V8400 HY63V8400 3.3 3.3 3.3 10 12 15 200 190 180 NC NC A0 A1 A2 A3 A4 /C S I/O1 I/O2 Vcc Vss I/O3 I/O4 /W E A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 T S O P - I I 33 54 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 /O E I/O8 I/O7 Vss Vcc I/O6 I/O5 A14 A13 A12 A11 A10 NC NC NC DECODER NC A18 A17 A16 A15 /OE I/O8 I/O7 Vss Vcc I/O6 I/O5 A14 A13 A12 A11 A10 NC MEMORY ARRAY 512x1024x8 I/O1 OUTPUT BUFFER SOJ 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 SENSE AMP ROW DECODER ADD INPUT BUFFER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 1 1 BLOCK DIAGRAM A0 A0 A1 A2 A3 A4 /CS I/O1 I/O2 Vcc Vss I/O3 I/O4 /WE A5 A6 A7 A8 A9 10 10 10 WRITE DRIVER PIN CONNECTION Standby Current(mA) L I/O8 A18 /CS /OE /WE SOJ TSOP-II PIN DESCRIPTION Pin Name /CS /WE /OE I/O1~I/O8 Pin Function Chip Select Write Enable Output Enable Data Input/Output Pin Name A0~A18 Vcc Vss NC Pin Function Address Input Power(+3.3V) Ground No Connection This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.02 / Jan.99 Hyundai Semiconductor HY63V8400 Series ABSOLUTE MAXIMUM RATINGS(1) Symbol VIN, VOUT Vcc TA TSTG PD Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Commercial Operating Temperature Industrial Storage Temperature Power Dissipation Rating -0.5 to 4.6 -0.5 to 5.5 0 to 70 -40 to 85 -65 to 150 1.0 Unit V V °C °C °C W Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (TA=0°C to 70°C) Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3(1) Type 3.3 0 - Max. 3.6 0 Vcc+0.3(2) 0.8 Unit V V V V Note 1. VIL (min)= -2.0V a.c(pulse width less than 8ns) for I < 20mA 2. VIH(max) = Vcc + 2.0V a.c(pulse width less than 8ns) for I < 20mA DC ELECTRICAL CHARACTERISTICS (Vcc = 3.3V±0.3V, TA = 0°C to 70°C, unless otherwise specified.) Symbol Parameter Test Conditions ILI Input Leakage Current VSS < VIN < VCC Output Leakage Current VSS < VOUT < VCC, ILO /CS = VIH or /OE = VIH or /WE = VIL /CS = VIL, VIN = VIH, 10ns ICC Operating Current II/O = 0mA 12ns Min. Duty Cycle = 100% 15ns TTL Standby Current /CS = VIH, VIN=VIH or VIL Min. Cycle ISB (TTL Inputs) ISB1 CMOS Standby Current /CS > VCC-0.2V, VIN > (CMOS Inputs) VCC-0.2V or VIN < 0.2V L VOL Output Low Voltage IOL = 8.0mA VOH Output High Voltage IOH = -4.0mA Min -2 -2 Typ - Max 2 2 Unit uA uA - - 200 190 180 60 mA mA mA mA 2.4 - 10 1 0.4 - mA mA V V - Note : Typical values are at Vcc = 3.3V, TA = 25°C Rev.02 / Jan.99 2 HY63V8400 Series AC CHARACTERISTICS (Vcc = 3.3V ± 0.3V, TA = 0°C to 70°C, unless otherwise specified.) 10ns # Symbol Parameter Min Max 12ns Min Max 15ns Min Max Unit READ CYCLE 1 2 3 4 5 6 7 8 9 tRC tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tOH Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Deselecting to Output in High Z Out Disable to Output in High Z Output Hold from Address Change 10 3 0 0 0 3 10 10 5 5 5 - 12 3 0 0 0 3 12 12 6 6 6 - 15 3 0 0 0 3 15 15 7 7 7 - ns ns ns ns ns ns ns ns ns Write Cycle Time Chip Select to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width(/OE High) Write Pulse Width(/OE Low) Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 10 7 7 0 7 10 0 0 5 0 3 5 - 12 8 8 0 8 12 0 0 6 0 3 6 - 15 10 10 0 10 15 0 0 7 0 3 7 - ns ns ns ns ns ns ns ns ns ns ns WRITE CYCLE 10 11 12 13 14 15 16 17 18 19 20 tWC tCW tAW tAS tWP tWP1 tWR tWHZ tDW tDH tOW NOTE : Above parameters are also guaranteed at industrial temperature range. Rev.02 / Jan.99 3 HY63V8400 Series AC TEST CONDITIONS (Vcc = 3.3V±0.3V, TA = 0°C to 70°C, unless otherwise specified.) Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load Value 0V to 3V 3ns 1.5V See below AC TEST CONDITIONS Output Load (A) Output Load (B) (for tCHZ, tCLZ, tOHZ, tOLZ, tWHZ & tOW) +3.3V Zo=50Ω Dout RL=50Ω Dout 5pF * 353Ω VL = 1.5V Note : *Including jig and scope capacitance CAPACITANCE Temp = 25°C, f= 1.0MHz Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Condition VIN = 0V VI/O = 0V Max. 7 8 Unit pF pF Note : This parameter is sampled and not 100% tested TIMING DIAGRAM Rev.02 / Jan.99 4 HY63V8400 Series READ CYCLE 1 tRC ADDR tAA OE tOE tOH tOLZ CS tACS tOHZ tCHZ tCLZ Data Out High-Z Data Valid Note (Read Cycle) 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. /WE is high for read cycle. READ CYCLE 2 tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid Note (Read Cycle) 1. /WE is high for read cycle. 2. Device is continuously selected /CS=VIL. 3. /OE=VIL. Rev.02 / Jan.99 5 HY63V8400 Series WRITE CYCLE 1(/OE Clocked) tWC ADDR OE tAW tCW CS tAS tWR tWP WE tDW Data In tDH Data Valid tOHZ Data Out WRITE CYCLE 2(/OE Low Fixed) tWC ADDR tAW tCW tWR CS tAS tWP WE tDW Data In tDH Data Valid tWHZ tOW (7) (8) Data Out Notes(Write Cycle) 1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among /CS going low, and /WE going low : A write ends at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. If /OE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state, inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high impedance state. 7. DOUT is the same phase of latest written data in the write cycle. 8. DOUT is the read data of the new address. Rev.02 / Jan.99 6 HY63V8400 Series FUNCTIONAL DESCRIPTION /CS /WE /OE /LB /UB MODE H L L X H X X* H X L H L L L X X X H L H L L H L X X H H L L H L L I/O Pin Not Select I/O1 - I/O8 High-Z I/O9 - I/O16 High-Z Output Disable High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Dout Dout High-Z Din Din Read Write Supply Current Isb,Isb1 Icc Icc Icc * NOTE : X means Don,t Care DATA RETENTION ELECTRIC CHARATERISTIC (TA = 0¡ Éto 70¡ É) Symbol Parameter VDR Vcc for Data Retention Data Retention Current IDR tCDR tR Test Condition /CS > Vcc - 0.2V Min 2.0 Typ - Max 3.6 Vcc = 3.0V, /CS > Vcc - 0.2V Vin > Vcc - 0.2V or < 2.0V - - 0.9 Vcc = 2.0V, /CS > Vcc - 0.2V Vin > Vcc - 0.2V or < 2.0V - - 0.7 0 5 - - Data Retention Set-Up Time Recovery Time Unit V mA ns ms DATA RETENTION TIMING DIAGRAM DATA RETENTION MODE VCC 3.0/2.7V tCDR tR 2.2V VDR CS>Vcc-0.2V CS VSS Rev.02 / Jan.99 7 HY63V8400 Series PACKAGE INFORMATION 44pin 400mil Thin Small Outline Package (T2) #44 #23 UNIT : INCH(mm) #1 #22 0.470(11.938) 0.462(11.735) 0.729(18.517) 0.721(18.313) 0.016(0.4) 0.012(0.3) 0.047(1.194) 0.039(0.991) 0.0059(0.150) 0.0315(0.800) 0.002(0.050) BSC 0.10MAX 0.004MAX 0.0083(0.21) 0.0047(0.120 ) 0.404(10.262) 0.396(10.058) 0.0235(0.597) 0.0160(0.406) 0~5 36pin 400mil Small Outline J-Form Package (J) 0.030(0.762) 0.040(1.016) 0.026(0.660) 0.032(0.813) 0.395(10.033) 0.405(10.287) 0.368(9.348) 0.380(9.652) 0.436(11.074) 0.444(11.278) 0.929(23.597) 0.921(23.393) 0.138(3.505) 0.148(3.759) 0.050(1.27) BSC. Rev.02 / Jan.99 UNIT : INCH(mm) 0.016(0.406) 0.020(0.508) 8