200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver. This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply • All inputs and outputs are compatible with SSTL_1.8 interface • Posted CAS • Programmable CAS Latency 3 ,4 ,5 • OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) • Fully differential clock operations (CK & CK) • Programmable Burst Length 4 / 8 with both sequential and interleave mode • Auto refresh and self refresh supported • 8192 refresh cycles / 64ms • Serial presence detect with EEPROM • DDR2 SDRAM Package: 60ball(x8), 84ball(x16) FBGA • 67.60 x 30.00 mm form factor • Lead-free Products are RoHS compliant ORDERING INFORMATION Density Organization # of DRAMs # of ranks Materials HYMP532S646-E3/C4 256MB 32Mx64 4 1 Leaded HYMP564S648-E3/C4 512MB 64Mx64 8 1 Leaded HYMP564S646-E3/C4 512MB 64Mx64 8 2 Leaded HYMP112S64M8-E3/C4 1GB 128Mx64 16 2 Leaded HYMP532S64P6-E3/C4 256MB 32Mx64 4 1 Lead free HYMP564S64P8-E3/C4 512MB 64Mx64 8 1 Lead free HYMP564S64P6-E3/C4 512MB 64Mx64 8 2 Lead free 1GB 128Mx64 16 2 Lead free Part Name HYMP112S64MP8-E3/C4 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Feb. 2005 1 1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE & KEY PARAMETERS E3 (DDR2-400) C4 (DDR2-533) Unit Speed@CL3 400 400 Mbps Speed@CL4 400 533 Mbps Speed@CL5 - - Mbps CL-tRCD-tRP 3-3-3 4-4-4 tCK ADDRESS TABLE Density Organization Ranks SDRAMs # of DRAMs # of row/bank/column Address Refresh Method 256MB 32M x 64 1 32Mb x 16 4 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms 512MB 64M x 64 2 64Mb x 8 8 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms 512MB 64M x 64 1 32Mb x 16 8 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 8K / 64ms 1GB 128M x 64 2 64Mb x 8 16 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms Rev. 1.0 / Feb. 2005 2 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN DESCRIPTION Symbol Type Polarity Pin Description The system clock inputs. All adress an commands lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. CK[1:0], CK[1:0] Input Cross Point CKE[1:0] Input Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. S[1:0] Input Active Low Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 RAS, CAS, WE Input Active Low When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS and WE define the operation to be excecuted by the SDRAM. BA[1:0] Input ODT[1:0] Input Selects which DDR2 SDRAM internal bank of four is activated. Active High Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 SDRAM mode register. A[9:0], A10/AP, A[15:11] Input During a Bank Activate command cycle, difines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. DQ[63:0] In/Out Data Input/Output pins. DM[7:0] Input DQS[7:0], DQS[7:0] In/Out Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. Cross point The data strobe, associated with one data byte, sourced whit data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed approriately. VDD, VDDSPD,VSS Supply Power supplies for core, I/O, Serial Presense Detect, and ground for the module. SDA In/Out This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister must be connected to VDD to act as a pull up. SCL Input This signals is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up. SA[1:0] Input Address pins used to select the Serial Presence Detect base address. TEST In/Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SODIMMs). Rev. 1.0 / Feb. 2005 3 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN ASSIGNMENT Pin NO. Front Side Pin NO. Back Side Pin NO. Front Side Pin NO. Back Side Pin NO. Front Side Pin NO. Back Side Pin NO. Front Side Pin NO. Back Side 1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47 5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS 7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS 157 DQ48 158 DQ52 9 VSS 10 DM0 59 VSS 60 VSS 109 WE 110 S0 159 DQ49 160 DQ53 11 DQS0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS 13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODT0 163 NC,TEST 164 CK1 15 VSS 16 DQ7 65 VSS 66 VSS 115 NC/S1 116 A13 165 VSS 166 CK1 17 DQ2 18 VSS 67 DM3 68 DQS3 117 VDD 118 VDD 167 DQS6 168 VSS 19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6 21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS 23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS 29 DQS1 30 CK0 79 CKE0 80 DQS4 130 DM4 179 DQ56 180 DQ60 31 DQS1 32 CK0 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61 33 VSS 34 VSS 83 NC 84 NC/A15 133 VSS 134 DQ38 183 VSS 184 VSS 35 DQ10 36 DQ14 85 BA2 86 NC/A14 135 DQ34 136 DQ39 185 DM7 186 DQS7 37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7 39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS 41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63 NC/CKE1 129 45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS5 195 SDA 196 VSS 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 49 DQS2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 Pin Location 2 Back Front 1 39 41 Rev. 1.0 / Feb. 2005 200 40 42 199 4 1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 256MB(32Mbx64) : HYMP532S646-E3/C4 3 Ω + /− 5 % /S 1 N .C . O D T1 N .C . CKE1 N .C . CKE0 ODT0 /S 0 DQS0 LDQS DQS4 LDQS /D Q S 0 /U D Q S /D Q S 4 /L D Q S LDM DM4 DM0 /C S ODT CKE I/O 0 DQ32 I/O 0 DQ1 I/O 1 DQ33 I/O 1 DQ2 I/O 2 DQ34 I/O 2 DQ3 I/O 3 DQ35 I/O 3 DQ4 I/O 4 DQ36 I/O 4 DQ5 I/O 5 I/O 5 DQ6 I/O 6 DQ7 I /O 7 DQ37 DQ38 DQ39 D0 UDQS DQS1 /U D Q S UDM DM1 DQ8 I/O 6 DQS5 UDQS /U D Q S DQ 40 DQ8 I/O 9 DQ 41 I/O 9 I/O 1 0 DQ 42 I/O 1 0 DQ 11 I/O 1 1 DQ 43 I/O 1 1 DQ 12 I/O 1 2 DQ 44 I/O 1 2 DQ 13 I/O 1 3 DQ 45 I/O 1 3 DQ 14 DQ15 I/O 1 4 DQ 46 DQ 47 I /O 1 5 I /O 1 5 /L D Q S DM2 /C S ODT CKE DQS6 LDQS /D Q S 6 /L D Q S I/O 0 DQ 48 I/O 0 DQ 17 I/O 1 DQ 49 I/O 1 DQ 18 I/O 2 DQ 50 I/O 2 DQ 19 I/O 3 DQ 51 I/O 3 DQ 20 I/O 4 DQ 52 I/O 4 DQ 21 I/O 5 DQ 53 I/O 5 DQ 22 I/O 6 DQ 54 I/O 6 DQ 23 I/O 7 DQ 55 I/O 7 D1 DQS3 UDQS DQS7 UDQS /D Q S 3 /U D Q S /D Q S 7 /U D Q S DM7 UDM I/O 8 DQ 56 DQ 25 I/O 9 DQ 57 I /O 9 DQ 26 I /O 1 0 DQ 58 I/O 1 0 DQ 27 I /O 1 1 DQ 59 I/O 1 1 DQ 28 I /O 1 2 DQ 60 I/O 1 2 DQ 29 I /O 1 3 DQ 61 I/O 1 3 DQ 30 I /O 1 4 DQ 62 I/O 1 4 DQ 31 I/O 1 5 DQ 63 I/ O 1 5 SCL 3 Ω + /- 5 % SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS D 0 -3 D 0 -3 D 0 -3 D 0 -3 D 0 -3 SA0 SA1 VDD SP D CK0 2 lo a d s V REF SCL A0 A1 A2 D3 UDM DQ 24 B A 0 -B A 1 A 0 -A N /R A S /C A S /W E /C S LDM DQ 16 DM3 CKE I/O 1 4 DM6 LDM ODT I/O 8 DQ 10 LDQS D2 UDM DM5 DQS2 CKE I/O 7 /D Q S 5 I/O 8 /D Q S 2 ODT LDM DQ0 /D Q S 1 /C S I /O 8 SDA SDA S e r ia l P D WP S e r ia l P D S D R A M S D O -D 3 /C K 0 CK1 2 lo a d s VDD S D R A M S D O -D 3 , V D D a n d V D D Q VSS S D R A M S D O -D 3 , S P D /C K 1 N o te s : 1 . R e s is to r v a lu e s a r e 2 2 O h m + /- 5 % Rev. 1.0 / Feb. 2005 5 1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB(64Mbx64) : HYMP564S648-E3/C4 3 Ω + /− 5 % /S 1 N .C . ODT1 N .C . CKE1 N .C . CKE0 ODT0 DQS0 DQS0 DQS DQS4 DQS /D Q S 0 /D Q S /D Q S 4 /D Q S DM DM4 DM0 /C S ODT CKE I/O 0 DQ 33 I/O 1 DQ 34 I/O 2 I/O 3 DQ 35 I/O 3 I/O 4 DQ 36 I/O 4 DQ5 I/O 5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQ 37 DQ38 DQ39 I/O 0 DQ1 I/O 1 DQ2 I/O 2 DQ3 DQ4 D0 DQS DQS5 DQS /D Q S /D Q S 5 /D Q S DM DM5 DM1 DQ8 I/O 0 CKE D1 I/O 0 DQ8 I/O 1 DQ 41 I/O 1 I/O 2 DQ 42 I/O 2 DQ 11 I/O 3 DQ 43 I/O 3 DQ 12 I/O 4 DQ 44 I/O 4 DQ 13 I/O 5 DQ 45 I/O 5 DQ 14 I/O 6 DQ 46 I/O 6 D Q 15 I/O 7 DQ 47 I/O 7 DQS2 DQS DQS6 DQS /D Q S 2 /D Q S /D Q S 6 /D Q S DM DM6 DM2 ODT CKE I/O 0 DQ 49 I/O 1 DQ 50 I/O 2 I/O 3 DQ 51 I/O 3 I/O 4 DQ 52 I/O 4 DQ 21 I/O 5 DQ 53 I/O 5 DQ 22 I/O 6 DQ 54 I/O 6 D Q 23 I/O 7 DQ 55 I/O 7 I/O 0 DQ 17 I/O 1 DQ 18 I/O 2 DQ 19 DQ 20 D2 DQS3 DQS DQS0 DQS /D Q S 3 /D Q S /D Q S 0 /D Q S DM DM0 DM3 /C S ODT CKE I/O 0 DQ 57 I/O 1 DQ 58 I/O 2 I/O 3 DQ 59 I/O 3 I/O 4 DQ 60 I/O 4 DQ 29 I/O 5 DQ 61 I/O 5 DQ 30 I/O 6 DQ 62 I/O 6 D Q 31 I/O 7 DQ 63 I/O 7 I/O 0 DQ 25 I/O 1 DQ 26 I/O 2 DQ 27 DQ 28 D3 SCL 3 Ω + /- 5 % B A 0 -B A 1 A 0 -A N /R A S /C A S /W E SDRAMS SDRAMS SDRAMS SDRAMS SDRAMS D 0 -7 D 0 -7 D 0 -7 D 0 -7 D 0 -7 SCL A0 A1 A2 SA0 SA1 VDD S P D V REF ODT CKE ODT CKE D5 /C S D6 /C S DM DQ 56 DQ 24 CKE DM DQ 48 DQ 16 /C S DM DQ 40 DQ 10 /C S ODT D4 I/O 6 DQS1 ODT CKE I/O 7 /D Q S 1 /C S ODT DM DQ 32 DQ0 /C S SDA D7 SDA S e r ia l P D WP S e r ia l P D S D R A M S D O -D 7 CK0 4 lo a d s /C K 0 VDD S D R A M S D O -D 7 , V D D a n d V D D Q VSS S D R A M S D O -D 7 , S P D CK1 4 lo a d s /C K 1 Rev. 1.0 / Feb. 2005 N o te s : 1 . R e s is to r v a lu e s a re 2 2 O h m + /- 5 % 6 1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB(64Mbx64): HYMP564S646-E3/C4 3 Ω +/− 5 % O DT 1 O DT 0 CKE 1 CKE 0 /S 1 /S 0 LDQS LDM LDM LDM LDM DQ 0 I/ O 0 I/ O 0 DQ 32 I/ O 0 I/ O 0 DQ 1 I/ O 1 I/ O 1 DQ 33 I/ O 1 I/ O 1 DQ 2 I/ O 2 I/ O 2 DQ 34 I/ O 2 I/ O 2 DQ 3 I/ O 3 I/ O 3 DQ 35 I/ O 3 I/ O 3 DQ 4 I/ O 4 I/ O 4 DQ 36 I/ O 4 I/ O 4 DQ 5 I/ O 5 I/ O 5 I/ O 5 I/ O 5 DQ 6 I/ O 6 I/ O 6 DQ 7 I/ O 7 DQ 37 DQ 38 DQ 39 DM 0 DQ S 1 / DQ S 1 DM 1 DQ 8 D0 I/ O 7 UDQS UDQ S / UDQ S / UDQ S UDM UDM I/ O 8 DM 4 D4 DQ S 5 / DQ S 5 I/ O 6 I/ O 7 I/ O 6 D2 I/ O 7 UDQ S UDQ S / UDQ S / UDQ S I/ O 8 DQ 40 I/ O 8 I/ O 8 DQ 8 I/ O 9 I/ O 9 DQ 41 I/ O 9 I/ O 9 DQ 10 I/ O 10 I/ O 10 DQ 42 I/ O 10 I/ O 10 DQ 11 I/ O 11 I/ O 11 DQ 43 I/ O 11 I/ O 11 DQ 12 I/ O 12 I/ O 12 DQ 44 I/ O 12 I/ O 12 DQ 13 I/ O 13 I/ O 13 DQ 45 I/ O 13 I/ O 13 DQ 14 I/ O 14 I/ O 14 DQ 46 I/ O 14 I/ O 14 DQ 15 I/ O 15 I/ O 15 DQ 47 I/ O 15 I/ O 15 LDM LDM LDM LDM DQ 16 I/ O 0 I/ O 0 DQ 48 I/ O 0 I/ O 0 DQ 17 I/ O 1 I/ O 1 DQ 49 I/ O 1 I/ O 1 DQ 18 I/ O 2 I/ O 2 DQ 50 I/ O 2 I/ O 2 DQ 19 I/ O 3 I/ O 3 DQ 51 I/ O 3 I/ O 3 DQ 20 I/ O 4 I/ O 4 DQ 52 I/ O 4 I/ O 4 DQ 21 I/ O 5 I/ O 5 DQ 53 I/ O 5 DQ 22 I/ O 6 I/ O 6 DQ 54 I/ O 6 DQ 23 I/ O 7 DQ 55 I/ O 7 DQ S 3 / DQ S 3 DM 3 D1 UDQ S UDQ S DQ S 7 / UDQ S / UDQ S / DQ S 7 UDM DM 7 UDM I/ O 8 DQ 24 I/ O 7 D5 DQ 56 I/ O 5 D3 I/ O 6 I/ O 7 UDQ S UDQ S / UDQ S / UDQ S UDM I/ O 8 I/ O 8 D7 UDM I/ O 8 DQ 25 I/ O 9 I/ O 9 DQ 57 I/ O 9 I/ O 9 DQ 26 I/ O 10 I/ O 10 DQ 58 I/ O 10 I/ O 10 DQ 27 I/ O 11 I/ O 11 DQ 59 I/ O 11 I/ O 11 DQ 28 I/ O 12 I/ O 12 DQ 60 I/ O 12 I/ O 12 DQ 29 I/ O 13 I/ O 13 DQ 61 I/ O 13 I/ O 13 DQ 30 I/ O 14 I/ O 14 DQ 62 I/ O 14 I/ O 14 DQ 31 I/ O 15 DQ 63 I/ O 15 I/ O 15 I/ O 15 / CS ODT DM 6 LDQS / UDQ S CKE LDQ S / CS / LDQ S ODT DQ S 6 / DQ S 6 CKE / CS ODT LDQ S / UDQ S CKE DM 2 ODT LDQ S / CS / LDQS CKE DQ S 2 / DQ S 2 D6 UDM UDM DM 5 / CS / UDQ S ODT / CS CKE LDQ S / UDQ S ODT DQ S 4 / DQ S 4 CKE / CS ODT LDQ S / UDQ S CKE / CS ODT LDQ S / UDQ S CKE DQ S 0 / DQ S 0 3 Ω +/- 5 % BA0 - BA1 A 0- AN / RAS / CAS /WE SDRAM S SDRAM S SDRAM S SDRAM S SDRAM S D 0 -7 D 0 -7 D 0 -7 D 0 -7 D 0 -7 SCL SCL A0 A1 A2 SA 0 SA 1 V DD SPD CK0 SDA SDA Serial PD WP Notes : 1. Resistor values are 22 Ohm +/- 5% Serial PD 4 loads / CK 0 CK 1 V REF SDRAM S DO -D 3 V DD SDRAM S DO - D 3 , V DD and V DD Q V SS SDRAM S DO - D 3 , SPD 4 loads / CK 1 Rev. 1.0 / Feb. 2005 7 1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 1GB(128Mbx64) : HYMP112S64M8-E3/C4 3 Ω+/− 5 % CKE 1 ODT 1 /S1 CKE 0 ODT 0 /S 0 DQS 0 DQS DQS 4 DQS / DQ S 0 / DQS / DQS 4 / DQS DM DM 4 DM 0 DQ 0 I/ O 0 DQ 1 I/ O 1 DQ 2 I/ O 2 DQ 3 / CS 0 ODT 0 CKE 0 / CS 1 ODT 1 CKE 1 I/ O 0 DQ 33 I/ O 1 DQ 34 I/ O 2 I/ O 3 DQ 35 I/ O 3 DQ 4 I/ O 4 DQ 36 I/ O 4 DQ 5 I/ O 5 I/ O 5 DQ 6 I/ O 6 DQ 7 I/ O 7 DQ 37 DQ 38 DQ 39 I/ O 6 DQS 1 DQS DQ S 5 DQS / DQ S / DQ S 5 / DQS DM DM 5 DM 1 DQ 8 I/ O 0 / CS 1 ODT 1 CKE 1 I/ O 0 DQ 41 I/ O 1 DQ 42 I/ O 2 DQ 8 I/ O 1 I/ O 2 DQ 11 I/ O 3 DQ 43 I/ O 3 DQ 12 I/ O 4 DQ 44 I/ O 4 DQ 13 I/ O 5 DQ 45 I/ O 5 DQ 14 I/ O 6 DQ 46 I/ O 6 DQ 15 I/ O 7 DQ 47 I/ O 7 DQS 2 DQS DQ S 6 DQS / DQS 2 / DQ S / DQ S 6 / DQS DM DM 6 DM 2 DQ 16 I/ O 0 DQ 17 I/ O 1 DQ 18 I/ O 2 DQ 19 / CS 0 ODT 0 CKE 0 / CS 1 ODT 1 CKE 1 I/ O 0 DQ 49 I/ O 1 DQ 50 I/ O 2 I/ O 3 DQ 51 I/ O 3 DQ 20 I/ O 4 DQ 52 I/ O 4 DQ 21 I/ O 5 DQ 53 I/ O 5 DQ 22 I/ O 6 DQ 54 I/ O 6 DQ 23 I/ O 7 DQ 55 I/ O 7 DQS 3 DQS DQ S 7 DQS / DQS 3 / DQ S / DQ S 7 / DQS DM DM 7 DM 3 DQ 24 I/ O 0 DQ 25 I/ O 1 DQ 26 I/ O 2 DQ 27 / CS 0 ODT 0 CKE 0 / CS 1 ODT 1 CKE 1 I/ O 0 DQ 57 I/ O 1 DQ 58 I/ O 2 I/ O 3 DQ 59 I/ O 3 DQ 28 I/ O 4 DQ 60 I/ O 4 DQ 29 I/ O 5 DQ 61 I/ O 5 DQ 30 I/ O 6 DQ 62 I/ O 6 DQ 31 I/ O 7 DQ 63 I/ O 7 SCL 10Ω+/-5 % BA0 - BA1 A 0 - AN / RAS / CAS / WE SDRAM S SDRAM S SDRAM S SDRAM S SDRAM S D 0 - 15 D 0 - 15 D 0 - 15 D 0 - 15 D 0 - 15 SCL A0 A1 A2 SA 0 SA 1 / CS 0 ODT 0 CKE 0 / CS 1 ODT 1 CKE 1 D 6,D 14 ( DDP ) / CS 0 ODT 0 CKE 0 / CS 1 ODT 1 CKE 1 SDA D 7,D 15 ( DDP ) SDA Serial PD WP : 8 loads V DD SPD /CK0 8 loads V REF SDRAMS DO - D 15 CK1 8 loads V DD SDRAMS DO - D 15 , V DD and V DD Q 8 loads V SS SDRAMS DO - D 15 , SPD CK0 D 5, D 13 ( DDP ) DM DQ 56 D 3 , D 11 ( DDP ) / CS 1 ODT 1 CKE 1 DM DQ 48 D 2 , D 10 ( DDP ) / CS 0 ODT 0 CKE 0 DM DQ 40 DQ 10 D 1, D 9 ( DDP ) D 4 ,D 12 ( DDP ) I/ O 7 / DQS 1 / CS 0 ODT 0 CKE 0 / CS 1 ODT 1 CKE 1 DM DQ 32 D 0, D 8 ( DDP ) / CS 0 ODT 0 CKE 0 Serial PD 9.1 pF 9.1 pF /CK1 Rev. 1.0 / Feb. 2005 Notes : 1. Resistor values are 22 Ohm +/- 5% 8 1200pin Unbuffered DDR2 SDRAM SO-DIMMs ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Note Voltage on VDD pin relative to Vss VDD - 1.0 V ~ 2.3 V V 1 Voltage on VDDQ pin relative to Vss VDDQ - 0.5 V ~ 2.3 V V 1 VIN, VOUT - 0.5 V ~ 2.3 V V 1 Storage Temperature TSTG -50 ~ +100 Storage Humidity(without condensation) HSTG 5 to 95 Voltage on any pin relative to Vss C 1 % 1 o Notes: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con ditions for extended periods may affect reliablility. OPERATING CONDITIONS Parameter Symbol Rating DIMM Operating temperature(ambient) TOPR 0 ~ +55 DIMM Barometric Pressure(operating & storage) PBAR 105 to 69 DRAM Component Case Temperature Range TCASE 0 ~+95 Units Notes o C K Pascal o C 1 2 Notes: 1. Up to 9850 ft. 2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. DC OPERATING CONDITIONS (SSTL_1.8) Parameter Min Max Unit VDD 1.7 1.9 V VDDQ 1.7 1.9 V 1 Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 2 EEPROM Supply Voltage VDDSPD 1.7 3.6 V Termination Voltage VTT VREF-0.04 VREF+0.04 V Power Supply Voltage Symbol Note 3 Notes: 1. VDDQ must be less than or equal to VDD. 2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc) 3. VTT of transmitting device must track VREF of receiving device. Rev. 1.0 / Feb. 2005 9 1200pin Unbuffered DDR2 SDRAM SO-DIMMs INPUT DC LOGIC LEVEL Parameter Symbol Min Max Unit Input High Voltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V Min Max Unit Note INPUT AC LOGIC LEVEL Parameter Symbol AC Input logic High VIH(AC) VREF + 0.250 - V AC Input logic Low VIL(AC) - VREF - 0.250 V Note AC INPUT TEST CONDITIONS Symbol Condition Value Units Notes 0.5 * VDDQ V 1 VREF Input reference voltage VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2, 3 Notes: 1. 2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSWING(MAX) VSS delta TF Falling Slew = delta TR VREF - VIL(ac) max delta TF Rising Slew = VIH(ac)min - VREF delta TR < Figure : AC Input Test Signal Waveform> Rev. 1.0 / Feb. 2005 10 1200pin Unbuffered DDR2 SDRAM SO-DIMMs Differential Input AC logic Level Symbol Parameter Min. Max. Units Note VID (ac) ac differential input voltage 0.5 VDDQ + 0.6 V 1 VIX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC). VDDQ VTR Crossing point VID VIX or VOX VCP VSSQ < Differential signal levels > Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross. DIFFERENTIAL AC OUTPUT PARAMETERS Symbol VOX (ac) Parameter ac differential cross point voltage Min. Max. Units Note 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1 Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Rev. 1.0 / Feb. 2005 11 1200pin Unbuffered DDR2 SDRAM SO-DIMMs OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS Symbol Parameter SSTL_18 Units Notes VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V 1 Notes: 1. The VDDQ of the device under test is referenced. OUTPUT DC CURRENT DRIVE Symbol Parameter SSTl_18 Units Notes IOH(dc) Output Minimum Source DC Current - 13.4 mA 1, 3, 4 IOL(dc) Output Minimum Sink DC Current 13.4 mA 2, 3, 4 Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement. Rev. 1.0 / Feb. 2005 12 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz ) 256MB : HYMP532S64[P]6 Pin Symbol Min Max Unit CK, CK CCK 12 15 pF CKE, ODT,CS CI1 27 30 pF Address, RAS, CAS, WE CI2 25 32 pF DQ, DM, DQS, DQS CIO 6.0 7.5 pF Symbol Min Max Unit CK, CK CCK 13 21 pF CKE, ODT, CS CI1 24 38 pF Address, RAS, CAS, WE CI2 23 40 pF DQ, DM, DQS, DQS CIO 5 8 pF Symbol Min Max Unit CK, CK CCK 17 20 pF CKE, ODT,CS CI1 22 25 pF Address, RAS, CAS, WE CI2 28.5 37.0 pF DQ, DM, DQS, DQS CIO 10.0 12.0 pF Symbol Min Max Unit CK, CK CCK 25 49 pF CKE, ODT,CS CI1 32 58 pF Address, RAS, CAS, WE CI2 47 96 pF DQ, DM, DQS, DQS CIO 16 20 pF 512MB : HYMP564S64[P]8 Pin 512MB : HYMP564S64[P]6 Pin 1GB : HYMP512S64M[P]8 Pin Notes: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. Rev. 1.0 / Feb. 2005 13 1200pin Unbuffered DDR2 SDRAM SO-DIMMs IDD SPECIFICATIONS (TCASE : 0 to 95oC) 256MB, 32M x 64 SO- DIMM : HYMP532S64[P]6 Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Unit note IDD0 500 520 mA IDD1 540 560 mA IDD2P 24 28 mA IDD2Q 140 160 mA IDD2N 160 180 mA IDD3P(F) 80 100 mA IDD3P(S) 20 24 mA IDD3N 260 300 mA IDD4R 600 760 mA IDD4W 720 880 mA IDD5B 660 700 mA IDD6 22 22 mA 1 IDD6(L) 12 12 mA 1 IDD7 1320 1320 mA 512MB, 64M x 64 SO- DIMM : HYMP564S64[P]8 Symbol E3(DDR2 400@CL3) C4(DDR2 533@CL 4) Unit note IDD0 640 720 mA IDD1 720 800 mA IDD2P 48 56 mA IDD2Q 280 320 mA IDD2N 320 360 mA IDD3P(F) 160 200 mA IDD3P(S) 40 48 mA IDD3N 440 520 mA IDD4R 1040 1280 mA IDD4W 1200 1440 mA IDD5B 1320 1400 mA IDD6 44 44 mA 1 IDD6(L) 32 32 mA 1 IDD7 1760 1760 mA Notes: 1. IDD6 current values are guaranted up to Tcase of 85℃ max. Rev. 1.0 / Feb. 2005 14 1200pin Unbuffered DDR2 SDRAM SO-DIMMs 512MB, 64M x 64 SO - DIMM : HYMP564S64[P]6 Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Unit note IDD0 760 820 mA IDD1 800 860 mA IDD2P 48 56 mA IDD2Q 280 320 mA IDD2N 320 360 mA IDD3P(F) 160 200 mA IDD3P(S) 40 48 mA IDD3N 520 600 mA IDD4R 860 1060 mA IDD4W 980 1180 mA IDD5B 920 1000 mA IDD6 44 44 mA 1 IDD6(L) 32 32 mA 1 IDD7 1580 1620 mA 1GB, 128M x 64 SO - DIMM : HYMP112S64M[P]8 Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Unit note IDD0 1080 1240 mA IDD1 1160 1320 mA IDD2P 96 112 mA IDD2Q 560 640 mA IDD2N 640 720 mA IDD3P(F) 320 400 mA IDD3P(S) 80 96 mA IDD3N 880 1040 mA IDD4R 1480 1800 mA IDD4W 1640 1960 mA IDD5B 1760 1920 mA IDD6 88 88 mA 1 IDD6(L) 64 64 mA 1 IDD7 2200 2280 mA Notes: 1. IDD6 current values are guaranted up to Tcase of 85℃ max. Rev. 1.0 / Feb. 2005 15 1200pin Unbuffered DDR2 SDRAM SO-DIMMs IDD Meauarement Conditions Symbol Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W mA IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Fast PDN Exit MRS(12) = 0 Other control and address bus inputs are STABLE; Data bus inputs are FLOATSlow PDN Exit MRS(12) = 1 ING IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W mA IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85℃ max. mA IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions mA mA mA Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin ≤ VILAC(max) HIGH is defined as Vin ≥ VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 1.0 / Feb. 2005 16 1200pin Unbuffered DDR2 SDRAM SO-DIMMs Electrical Characteristics & AC Timings Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin Speed DDR2-533 (C4) DDR2-400 (E3) Unit Bin(CL-tRCD-tRP) 4-4-4 3-3-3 Parameter min min CAS Latency 4 3 ns tRCD 15 15 ns tRP 15 15 ns tRC 60 55 ns tRAS 45 40 ns AC Timing Parameters by Speed Grade Parameter Symbol DDR2-400 DDR2-533 Min Max Min Max Unit Note Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps DQS-Out edge to Clock edge Skew tDQSCK -500 500 -450 450 ns Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK tHP min (tCL,tCH) - min (tCL,tCH) - ns System Clock Cycle Time tCK 5000 8000 3750 8000 ps DQ and DM input setup time tDS 275 - 225 - ps 1 DQ and DM input hold time tDH 150 - 100 - ps 1 Clock Half Period DQ and DM input setup time(single-ended strobe) tDS1 DQ and DM input hold time(single-ended strobe) tDH1 Control & Address input Pulse Width for each input tIPW 0.6 - 0.6 - tCK DQ and DM input pulse witdth for each input pulse width for each input tDIPW 0.35 - 0.35 - tCK tHZ - tAC max - tAC max ps Data-out high-impedance window from CK, /CK DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 - 300 ps DQ hold skew factor tQHS - 450 - 400 ps DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps First DQS latching transition to associated clock edge tDQSS -0.25 +0.25 -0.25 +0.25 tCK DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write preamble tWPRE 0.35 - - tCK Rev. 1.0 / Feb. 2005 0.35 17 1200pin Unbuffered DDR2 SDRAM SO-DIMMs - Continued Parameter Symbol DDR2-400 DDR2-533 Min Max Min Max Unit Note Address and control input setup time tIS 350 - 250 - ps Address and control input hold time tIH 475 - 375 - ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Auto-Refresh to Active/Auto-Refresh command period tRFC 105 - 105 - ns Row Active to Row Active Delay for 1KB page size tRRD 7.5 - 7.5 - ns Row Active to Row Active Delay for 2KB page size tRRD 10 - 10 - ns Four Activate Window for 1KB page size tFAW 37.5 - 37.5 - ns Four Activate Window for 2KB page size tFAW 50 - 50 - ns CAS to CAS command delay tCCD 2 Write recovery time tWR 15 - 15 - ns Auto Precharge Write Recovery + Precharge Time tDAL tWR+tRP - tWR+tRP - tCK Write to Read Command Delay tWTR 10 - 7.5 - ns Internal read to precharge command delay 2 tCK tRTP 7.5 7.5 Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 Exit self refresh to a read command tXSRD 200 - 200 - tCK tXP 2 - 2 - tCK tXARD 2 2 tCK tXARDS 6 - AL 6 - AL tCK CKE 3 3 tCK AOND 2 Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay t t tAON tAC(min) tAONPD tAC(min)+2 ODT turn-on ODT turn-on(Power-Down mode) t ODT turn-off delay AOFD t ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval 2.5 AOF tAC(min) AOFPD tAC(min)+2 tANPD tAXPD tOIT 3 8 0 tDelay tIS+tCK+tIH tREFI tREFI - t 2 tAC(max)+ 1 2tCK+tAC( max)+1 2.5 tAC(max)+ 0.6 2.5tCK+tA C(max)+1 12 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8 0 ns ns 2 tAC(max)+ 1 2tCK+tAC( max)+1 2.5 tAC(max)+ 0.6 2.5tCK+tA C(max)+1 12 tIS+tCK+tIH 7.8 3.9 - tCK ns ns tCK ns ns tCK tCK ns ns 7.8 3.9 us us 2 3 Notes: 1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS12[8/16]21(L)F). 2. 0°C ≤ TCASE ≤ 85°C 3. 85°C ＜ TCASE ≤ 95°C Rev. 1.0 / Feb. 2005 18 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE 32Mx64 - HYMP532S64[P]6 Front 67.60 20.00 Min Side 3.80 max 4.00 +/-0.10 30.00 (Front) 20.00 PIN 39 PIN 41 PIN 199 11.40 2.70 4.20 2.45 11.40 2.40 PIN 2 47.40 Back 4.20 PIN 40 PIN 42 1.00 ± 0.10 6.00 PIN 1 47.40 PIN 200 note: 1. all dimension Units are millimeters. 2. all outline dimensions and tolerances match up to the JEDEC standard. Rev. 1.0 / Feb. 2005 19 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE 64Mx64 - HYMP564S64[P]8 Front 67.60 20.00 Min Side 3.8 max 4.00 +/-0.10 30.00 (Front) 20.00 PIN 1 PIN 39 PIN 41 PIN 199 2.45 11.40 2.40 PIN 2 1.00 ± 0.10 6.00 11.40 2.70 4.20 Back 4.20 PIN 40 PIN 42 47.40 PIN 200 note: note: 1.1.all alldimension dimension Units Units are are millimeters. millimeters. 2.2.all outline dimensions and tolerancesmatch matchup upto tothe theJEDEC JEDECstandard. standard. all outline dimensions and tolerances Rev. 1.0 / Feb. 2005 20 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE 64Mx64 - HYMP564S64[P]6 Front 67.60 20.00 Min Side 3.80 max 4.00 +/-0.10 30.00 (Front) 20.00 PIN 39 PIN 41 PIN 199 11.40 2.70 4.20 2.45 11.40 2.40 PIN 2 47.40 Back 4.20 PIN 40 PIN 42 1.00 ± 0.10 6.00 PIN 1 47.40 PIN 200 note: 1. all dimension units are millimeters. 2. all outline dimensions and tolerances match up to the JEDEC standard. Rev. 1.0 / Feb. 2005 21 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE 128Mx64 - HYMP112S64M[P]8 Front Side 67.60 3.8 max 20.00 Min 4.00 +/-0.10 30.00 20.00 PIN 1 PIN 39 PIN 41 PIN 199 1.00 +/- 0.10 2.45 11.40 2.40 PIN 2 6.00 11.40 2.70 4.20 Back 4.20 PIN 40 PIN 42 47.40 PIN 200 note: 1. all dimension Units are millimeters. 2. all outline dimensions and tolerances match up to the JEDEC standard. Rev. 1.0 / Feb. 2005 22 1200pin Unbuffered DDR2 SDRAM SO-DIMMs REVISION HISTORY Revision 1.0 History First Version Release - Data sheet coverage is changed from an individual module part to a component based module family. Rev. 1.0 / Feb. 2005 Date Remark Feb.2005 23