iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 1/21 FEATURES APPLICATIONS Ë Real-time interpolator with a programmable resolution of up to 256 steps/period Ë Calibration features permit adaptation of distorted sine/cosine signals Ë Output with A/B/Z incremental signals of up to 400kHz, as a parallel 8-bit absolute vector or via a serial interface Ë Error messaging with excessive input frequency Ë Programmable index position Ë Fast 24-bit multiturn counting (position capture with target position interrupt) Ë 8-bit µP interface Ë Interrupt controller Ë Adjustable clock oscillator Ë Front-end amplifiers configurable externally Ë Chip setup can be loaded from a serial EEPROM Ë TTL-compatible inputs, TTL-/CMOS-compatible outputs Ë Inputs and outputs protected against destruction by ESD Ë Absolute and incremental angle interpolation from orthogonal sinusoidal input signals Ë Interpolating interface for MR sensors and optical analog encoders PACKAGES SO28 SSOP28 BLOCK DIAGRAM 14 28 27 VDD SCL SDA CLK INPUT/OSCILLATOR 13 2V 24 NSIN 22 PSIN COS 20 NCOS 19 PCOS Comparator Resolution, Hysteresis A × sin Binary Up/Down Counter INPUT SIN 21 µP INTERFACE Segment MUX A × sin tan(phi) tan TAN D/A Converter phi D/A OFFS A × cos INPUT COS 18 ZERO 17 NZERO 16 PZERO 4 D0 5 D1 6 D2 7 D3 8 D4 9 D5 10 D6 11 D7 12 internal data bus 4-FOLD EDGE EVALUATION phi A4 DIGITAL SIGNAL PROCESSING VREF 3 NWR Converter Function Adaptation (per segment) INPUT INDEX/ZERO 15 NRD SINE / DIGITAL CONVERTER PGA SIN 23 STATE CONTROL SERIAL EEPROM INTERFACE R/f RCLK 26 NRES B4 REFERENCE VOLTAGE 2.4V Z4 GND 25 Copyright © 2006, iC-Haus 24-Bit Counter RPM/Speed Aquisition Interrupt Controller Index/Zero Pulse Justification Incremental Signal Generator Mode Switch (Frequency Overrun) iC-NG NER 1 ERROR MONITOR MFP 2 http://www.ichaus.com iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 2/21 DESCRIPTION iC-NG is a monolithic A/D converter which determines the angle value of two sinusoidal input signals phaseshifted at 90° with a given resolution and hysteresis. In this process a cycle is divided into 8 segments; each of these segments can be given a resolution of up to 32 angular steps. Resolutions of 1 to 256 divisions per cycle are possible. The converter can be adjusted for each individual segment to suit various types of input signal, meaning that even distorted sine signals or triangular signals, for example, can be converted. In addition, the direction of rotation can be inverted and the zero position can be set in steps of 45°. Output values and parameters are stored in registers connected to the internal 8-bit data bus. A parallel microcontroller interface gives read and write access to these registers. If an EEPROM is connected to the serial interface, the chip setup can be automatically read in following a reset. The output value consists of an 8-bit word for interpolation within a cycle and a 24-bit position counter which logs the number of turns. In addition to normal accessibility, the output value can also be transferred serially. The position counter can be reset via the zero pulse or stopped and started using the bi-directional MFP pin. When programmed as an output, pin MFP shows the change in output value or indicates when a certain position has been reached (interrupt output). After a reset, the interpolation result is correct after just a few clock cycles, even with static input signals. If incremental mode is selected, the changes in angle are output as square-wave signals phase-shifted at 90° at pins D0(AX) and D1(BX) with a selected resolution and at pins D3(A4) and D4(B4) with a resolution of four. The suitably prepared zero signal is at D2(ZX) and D5(Z4). Pin D6(ROT) shows the direction of rotation. Tracks AX and BX are EX-OR-gated at pin D7(AXB). The front-end amplifier connections are all lead out, enabling current or voltage inputs to be made. Complementary input signals can also be connected. The front-end amplifiers are compensated internally; the value of compensation can be programmed. The internal clock frequency can be adjusted using an external resistor or can be fed in via pin RCLK. The clock pulses which occur between two changes in output are counted in order to calculate the number of revolutions. Low voltage and excessive input frequency errors are signaled at output NER (open drain). These error codes are stored in the relevant register. iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 3/21 PACKAGE SO28, SSOP28 to JEDEC Standard PIN CONFIGURATION SO28 PIN FUNCTIONS (top view) No. Name Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NER MFP NRD NWR D0 D1 D2 D3 D4 D5 D6 D7 RCLK VDD VREF PZERO NZERO ZERO PCOS NCOS COS PSIN NSIN SIN GND NRES SDA SCL Error Message Output, low active Multi-Functional I/O Pin Read Signal, low active 1) / SSI Clock Write Signal, low active 1) / SSI Output Data Bus / Incremental Output A (AX) Data Bus / Incremental Output B (BX) Data Bus / Index Output Z (ZX) Data Bus / Sine-to-Square Output A (A4) Data Bus / Cosine-to-Square Output B (B4) Data Bus / Index-to-Square Output Z (Z4) Data Bus / CW-CCW Signal (ROT) Data Bus / AX EXOR BX (AXB) Clock Input / Clock Oscillator Setting +5V Supply Voltage Reference Center Voltage Zero Amplifier Positive Input Zero Amplifier Negative Input Zero Amplifier Output Cosine Amplifier Positive Input Cosine Amplifier Negative Input Cosine Amplifier Output Sine Amplifier Positive Input Sine Amplifier Negative Input Sine Amplifier Output Ground Reset, low active Mode Select / Data (Serial Interface) Mode Select / Clock (Serial Interface) NER MFP NRD NWR D0 D1 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 D2 D3 GND SIN NSIN COS PCOS RCLK VDD NRES NCOS D5 D7 SDA PSIN D4 D6 SCL ZERO NZERO PZERO VREF Notes: 1) wiring to VDD recommended when not in use. PIN CONFIGURATION SSOP28 5.3mm (top view) NER MFP NRD NWR D0 D1 D2 D3 D4 D5 D6 D7 RCLK VDD 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 SCL SDA NRES GND SIN NSIN PSIN COS NCOS PCOS ZERO NZERO PZERO VREF iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 4/21 ABSOLUTE MAXIMUM RATINGS Values beyond which damage may occur; device operation is not guaranteed. Item Symbol Parameter Conditions Fig. Unit Min. Max. G001 VDD Supply Voltage -0.3 6.0 V G002 V() Voltage at SIN, NSIN, PSIN, COS, NCOS, PCOS, ZERO, NZERO, PZERO, VREF, MFP, RCLK, NER, D0..7, NRD, NWR, NRES, SCL, SDA -0.3 VDD+0.3 V G003 Imx(VDD) Current in VDD -50 50 mA G004 Imx(GND) Current in GND -50 50 mA G005 Ic() MFP, D0..7, NWR Current in Clamping Diodes SIN, NSIN, PSIN, COS, NCOS, PCOS, ZE- with input function RO, NZERO, PZERO, VREF, MFP, RCLK, NER, D0..7, NRD, NWR, NRES, SCL, SDA -5 5 mA G006 I() Current in SIN, COS, ZERO, VREF, MFP, NER, D0..7, NWR, SCL MFP, D0..7, NWR with output function -10 10 mA G007 Ilu() Pulse Current in all Pins (Latch-Up Strength) pulse duration # 10µs -100 100 mA E001 Vd() ESD Susceptibility at all Pins MIL-STD-883, Method 3015, HBM; 100pf discharged through 1.5kΩ 2 kV TG1 Tj Junction Temperature -40 150 °C TG2 Ts Storage Temperature -40 150 °C THERMAL DATA Operating conditions: VDD= 5V ±10% Item Symbol Parameter Conditions Fig. Unit Min. T1 Ta Operating Ambient Temperature Range (extended temperature range on request) All voltages are referenced to ground unless otherwise noted. All currents into the device pins are positive; all currents out of the device pins are negative. -20 Typ. Max. 70 °C iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 5/21 ELECTRICAL CHARACTERISTICS Operating conditions: VDD= 5V ±10%, Tj= -40..125°C, unless otherwise noted. Item Symbol Parameter Conditions Tj °C Fig. Unit Min. Typ. Max. Total Device 001 VDD Permissible Supply Voltage 002 I(VDD) Supply Current 003 Vt()hi Input Threshold Voltage hi at D0..D7, MFP,NRD,NWR,NRES 004 Vt()lo Input Threshold Voltage lo at D0..D7, MFP,NRD,NWR,NRES 005 Vt()hys Input Hysteresis at D0..D7, MFP,NRD,NWR,NRES 006 Iin() Input Current at D0..D7, MFP,NRD,NWR,NRES outputs not active Vt()hys= Vt()hi -Vt()lo 4.5 5.5 V 5 25 mA 2 V 0.8 V 100 mV -1 +1 µA 7 Vs()lo Saturation Voltage lo at D0..D7, MFP I()= 4mA 0.4 V 8 Vs()hi Saturation Voltage hi at D0..D7, MFP Vs()hi= VDD -V(); I()= -4mA 0.4 V E001 Vc()hi Clamp Voltage hi at all Pins Vc()hi= V() -VDD; I()= 1mA, other pins open 0.3 1.5 V E002 Vc()lo Clamp Voltage lo at all Pins I()= -1mA, other pins open -1.5 -0.3 V 1 3.5 Vpp Input Amplifiers SIN, COS, INDEX/ZERO 101 Vin() Recommended Input Voltage Range 102 Vos() Input Offset Voltage 103 Iin() Input Current 104 Vcm() Common Mode Voltage Range Vin()= 1V..VDD -1V Iout()= 0..±5mA -10 +10 mV -50 +50 nA 0.1 VDD1.0 V 105 Vs()hi Saturation Voltage hi Vs()hi= VDD -V(), Iout()= -5mA 0.5 V 106 Vs()lo Saturation Voltage lo Iout()= 5mA 0.5 V 107 SR0 Slew-Rate CL= 0, CC= 0 (CC programmed) 4 V/µs 108 SR1 Slew-Rate CL= 300pF, CC= 4pF 2 V/µs 109 SR2 Slew-Rate CL= 800pF, CC= 6.4pF 1.2 V/µs 110 SR3 Slew-Rate CL= 1.5nF, CC= 12pF 0.8 V/µs 111 GBW0 Gain Bandwidth Product CL= 0, CC= 0 (CC programmed) 4.1 MHz 112 GBW1 Gain Bandwidth Product CL= 300pF, CC= 4pF 1 MHz 113 GBW2 Gain Bandwidth Product CL= 800pF, CC= 6.4pF 0.75 MHz 114 GBW3 Gain Bandwidth Product CL= 1.5nF, CC= 12pF 0.4 MHz Reference VREF 115 V(VREF) Reference Voltage I(VREF)= 0..-1mA 2.2 2.4 2.6 V 0.2 0.7 V 21 mA 10 µA Error Monitor NER 201 Vs()lo Saturation Voltage lo at NER I(NER)= 5mA 202 Isc()lo Short-Circuit Current lo in NER V(NER)= 0.4..VDD+0.3V 203 I0() Leakage Current in NER V(NER)= 0..VDD+0.3V, NER= hi oder VDD< 0.3V 204 VDDon Turn-on Threshold VDD 205 VDDoff Undervoltage Threshold VDD decreasing voltage VDD 206 VDDhys Hysteresis VDDhys= VDDon -VDDoff 207 VDDerr Supply Voltage VDD for Monitor Operation 5 4.7 V 4.5 V 200 2.2 mV 5.5 V iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 6/21 ELECTRICAL CHARACTERISTICS Operating conditions: VDD= 5V ±10%, Tj= -40..125°C, unless otherwise noted. Item Symbol Parameter Conditions Tj °C Fig. Unit Min. Typ. Max. 5 MHz 550 1.6 670 1.8 800 2.0 kHz MHz 500 kΩ Oscillator RCLK 301 fmax Permissible Oscillator Frequency 302 fosc Oscillator Frequency Rosc= 56kΩ Rosc= 18.2kΩ 303 R(RCLK) Permissible Resistor 5 304 Vt()hi Threshold Voltage hi 3 305 Vt()lo Threshold Voltage lo tw()lo< 10µs 0.8 306 Vt()hys Hysteresis Vt()hys= Vt()hi -Vt()lo 100 307 tmx()lo Permissible Pulse Width lo when applying external clock signals V V mV 10 µs Serial EEPROM Interface SCL, SDA 401 Vt()hi Threshold Voltage hi 402 Vt()lo Threshold Voltage lo 403 Vt()hys Input Hysteresis 2 Vt()hys= Vt()hi -Vt()lo 404 Vs()lo Saturation Voltage lo I()= 4mA 405 Vs()hi Saturation Voltage hi Vs()hi= VDD -V(); I()= -4mA 406 Rpu() Pull-up Resistor V 0.8 V 300 mV 0.26 5 10 0.4 V 0.4 V 20 kΩ Converter Accuracy 501 AAabs 502 AArel Absolute Angular Accuracy Relative Angular Accuracy referred to 360° input signal; VDD= 5V, V(SIN,COS)= 3Vpp, RES= 256, ADAP= 0, FREQ= 1; Rosc= 56kΩ, Tj= -20..70°C Rosc= 18.2kΩ, Tj= -20..70°C Rosc= 18.2kΩ, Tj= -40..125°C -0.8 -1.6 -2.8 +0.8 +1.6 +2.8 DEG DEG DEG see 501, referred to period of AX output signal; Rosc= 56kΩ, Tj= -20..70°C Rosc= 18.2kΩ, Tj= -20..70°C Rosc= 18.2kΩ, Tj= -40..125°C -20 -30 -30 +20 +30 +30 % % % ELECTRICAL CHARACTERISTICS DIAGRAMS 8 10 FREQ= 0 7 10 6 FREQ= 1 (reset entry) 10 5 10 3 10 10 4 R(CLK) Fig. 1: oscillator frequency characteristics. 10 5 iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 7/21 OPERATING REQUIREMENTS: Logic Operating conditions: VCC= 5V ±10%, Ta= -20..70°C, CL()= 150pF, input levels lo= 0..0.45V, hi= 2.4V..VCC, see Fig. 2 for reference levels and waveforms Item Symbol Parameter Conditions Fig. Unit Min. Max. Read cycle I1 tRD 1st access with latching NG and COUNT data Read Data Access Time: data valid after NRD hi6lo 3 1.5x td(CLK) ongoing access I2 tDF Read Data Hold Time: ports high impedance after NRD lo6hi 3 I3 tRL Required Read Signal Duration at NRD 3 120 ns 65 ns ns 200 SSI signal 2.5x td(CLK) Write cycle I4 tDW Write Data Setup Time: data valid before NWR lo6hi 3 100 ns I5 tWD Write Data Hold Time: data valid after NWR lo6hi 3 10 ns I6 tWL Required Write Signal Duration at NWR 3 200 ns 3 2× td(CLK) ns Write / read timing I7 tcyc Recovery Time between Cycles: NRD lo6hi to NRD hi6lo, NRD lo6hi to NWR hi6lo, NWR lo6hi to NWR hi6lo, NWR lo6hi to NRD hi6lo Fig. 2: reference levels Fig. 3: read / write timing iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 8/21 DESCRIPTION OF FUNCTIONS Converter principle iC-NG is an analog-digital tracking-type converter (compensation process). The output value is stored in an up/down counter. This is converted to analog voltage by a D/A converter and compared to the input signal by a comparator. The comparator output controls the direction input of the counter. The count direction is maintained until the output voltage of the D/A converter, which is proportional to the output value, corresponds to the value of the input voltage. SINUS / DIGITAL CONVERTER PGA The phase is available at the input in the form A x SIN(PHI) and A x COS(PHI). From the output value, the tangent function is formed in the feedback loop and multiplied by COS(PHI). The result is compared to SIN(PHI). The rule for regulation is as follows: A(SIN(Φ)' A(COS(Φ) × TAN(φ) Since the tangent function has pole points and cannot be formed over a whole cycle, a cycle is divided into eight segments. For certain segments the input signals are reversed and the cotangent function is formed in the feedback loop. The segment changeover function is indicated in the following table: Resolution, Hysteresis Comparator A × sin Segments Binary Up/Down-Counter Segment MUX A × sin tan(phi) tan TAN D/A Converter phi D/A OFFS A × cos Converter Function Adaptation (per segment) Comparator Inputs 1 phi= 0°..45° A×SIN(PHI) A×COS(PHI) × |TAN(phi)| 2 phi= 45°..90° A×COS(PHI) A×SIN(PHI) × |COT(phi)| 3 phi= 90°..135° !A×COS(PHI) A×SIN(PHI) × |COT(phi)| 4 phi= 135°..180° A×SIN(PHI) !A×COS(PHI) × |TAN(phi)| 5 phi= 180°..225° !A×SIN(PHI) !A×COS(PHI) × |TAN(phi)| 6 phi= 225°..270° !A×COS(PHI) !A×SIN(PHI) × |COT(phi)| 7 phi= 270°..315° A×COS(PHI) !A×SIN(PHI) × |COT(phi)| 8 phi= 315°..360° !A×SIN(PHI) A×COS(PHI) × |TAN(phi)| VREF Fig. 4: core of the TAN D/A converter In contrast to conventional A/D converters, the output value in the sine/digital converter is proportional not to the input voltage but to its phase. In the following, the input value is referred to as “PHI“ and the output value as “phi“. A × SIN(n) e1 PGA 1 e2 + - 45E e2 × Ftan(n) FA VREF 0E OFFS OFFS = (-0.33 .. 0.33) × COS Fig. 5: converter principle The sine/digital converter automatically runs via the shortest route into the correct segment and thus, with a static input signal, reaches its operating point after a maximum of n/2 clock cycles (n corresponds to the resolution). comparator GAIN = 0.5 .. 2 1. segment A × COS(n) G × e1 Fig. 6: segmentation A converter of the type described above will never reach a quiescent state. With a constant input signal, the counter would continuously increment or decrement one LSB, which is prevented here by hysteresis. A range is set up by the programmable hysteresis on both sides of the counter value and the input signal is checked over two clock cycles as to whether it is still within this range. The output frequency is therefore only half the clock frequency. iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 9/21 Interfaces The chip must be configured for the application in use after being switched on and after every reset. The settings and output values are stored in registers in iCNG. first access and the date by the second. The internal address register is automatically increased by one after each write. The registers of successive addresses can thus be easily written without having to reload the address register. A write cycle to address 10 and a subsequent read out are indicated in Figure 9. There are various ways of accessing these registers. If a serial EEPROM (e.g. SDA 2516, ST24CO2) is con-nected to pins SDA and SCL, all parameters will be read in automatically from there. The access mode is also determined by the EEPROM (ACCMOD(1:0)). In the absence of an EEPROM, the access mode is set directly by pins SDA and SCL, which are equipped with internal pull-up resistors. Three modes are supported: SDA SCL 0 0 Access Mode (no EEPROM) Parallel absolute mode 1 0 Serial mode 1 1 Incremental mode Fig. 7: access modes 1. Parallel-absolute mode This mode is suitable for using iC-NG as peripheral chip in an 8-bit bus system. The registers can be accessed via the data ports D0 to D7, controlled by read / write access inputs NWR and NRD. The two pins should not simultaneously receive low level. Addressing is controlled via an internal address register and a status machine. The internal status (A or B) determines whether write access affects the address register or a data register addressed by it. The chip is in status A after a reset and each read, and in status B after each write (Figure 8). Fig. 9: write access to address 10 and subsequent read out. Read access For a read cycle, the register address is also given first (write access), the data content then being read out with NRD at low. The length of the output value is set to 1..4 bytes with the OUTSEL(1:0) registers. OUTSEL also influences the content of the internal address counter after a read. It is not increased if the length of the output value is set to one byte. Other settings reset the address counter to zero after the highest byte of the output value has been read, otherwise it is increased by one. The outputs remain constant during the read process, even if the relevant register changes (except incremental signals and interrupt and error status). The NG, COUNT and TACHO registers are again stored with the falling edge at NRD if OUTSEL has been programmed to zero or the address counter is at zero. It is thus possible to read a 4-byte output value in four accesses. The interval between two consecutive pulses to NRD or NWR must be at least 3 clock cycles. The cyclic read out of a 2-byte output value (OUTSEL(1:0)= 1) is shown in Figure 10. Fig. 8: status control. Write access The data to be written is applied to pins D0 to D7 and a low pulse to NWR. The data is accepted with the rising edge at NWR. A write cycle consists of at least two accesses. The register address is given by the Fig. 10: cyclic read out of the output value (16-bit). iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 10/21 2. Synchronous-serial mode with 33-bit format Resolution RES(4:0) and RES(6,5) In this mode, communication is via a synchronous twowire connection. The registers cannot be accessed; only the output value and the error bit are transmitted. One period of the input signal is internally divided into eight segments. The following segments [45°..90°, 90°..135°, 135°..180° etc. to 360°] are mapped on the first segment [0°..45°]. The resulting output resolution thus amounts to 8 times that of the TAN D/A converter. The two-wire connection exists of a clock input (NRD) and a data output with driver at NWR. Data transmission is controlled externally by the clock line. The output value is latched with the first falling edge at NRD. With every subsequent rising edge the output value is serially output to NWR in binary code, beginning with the MSB set by OUTSEL. The error bit is transmitted after the output value. In this mode, pin SDA can be used as serial data input. The data read in here at the beginning of the data transmission is output after the error bit. A cyclic read out can be achieved by linking NWR to SDA. A one is output after the error bit as a stop bit. To store the output value for a new data transmission, an interval of at least 64 clock pulses must be maintained at the clock input. Fig. 11: synchronous-serial data transmission. 3. Incremental mode Here, every change of angle with respect to the set resolution is signaled as a change in output on track DO(AX) or D1(BX). The square-wave signals produced have a phase shift of plus or minus 90°, depending on the direction of rotation. In addition, the input signals are compared to reference voltage VREF and output to pins D3(A4) and D4(B4). This corresponds to a resolution of four. The zero signals, suitably prepared, are available at pins D2(ZX) and D5(Z4). A direction signal is also output to D6(ROT) and signals AX and BX are EX-ORgated at D7(AXB). Incremental mode can be emulated in parallel-absolute mode by reading address 4. The converter resolution per segment can be set to all whole-number values between 17 and 32. Subresolutions result only if every nth subdivision is used. A further decrease is possible by effecting a right shift by n-bit of the output value. The following table shows all possible settings and resulting resolutions. With equal values, settings with more favorable characteristics are shown in bold type. iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 11/21 TAN D/A Converter Resolution (per segment) Resolution 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 256 248 240 232 224 216 208 200 192 184 176 168 160 152 144 136 "00" [1F] [1E] [1D] [1C] [1B] [1A] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] 2 128 120 112 104 96 88 80 72 "00" [0F] [0E] [0D] [0C] [0B] [0A] [09] [08] 4 64 56 48 40 "00" [07] [06] [05] [04] 8 32 24 "00" [03] [02] 16 16 "00" [01] 32 8 "00" [00] 1 128 64 32 16 8 "01" 120 124 112 56 116 60 104 108 100 52 28 96 48 24 92 88 44 80 40 84 76 20 12 72 36 68 4 2 64 32 16 8 4 "10" 60 62 56 28 58 30 52 54 50 26 14 48 24 12 46 44 22 40 20 42 38 10 6 36 18 34 2 3 32 16 8 4 2 "11" 30 31 28 14 29 15 26 27 25 13 7 24 12 6 23 22 11 21 3 20 10 19 5 18 9 17 1 Fig. 12: programming the resolution: hexadecimal [1F] for RES(4:0), binary "00" for RES(6:5). Hysteresis If the maximum possible converter resolution is not used, hysteresis can be obtained from free resolution steps. In so doing, the resolution chosen determines the number of possible hysteresis settings. The following are possible in compliance with the upper half of the table of resolution printed above: Hysteresis given in % (resistive) H Y S 0 625 12. 187 25 31. 37. 43. 50 56. 62. 68. 75 81. 87. 93. 100 5 5 25 5 75 25 5 75 25 5 75 1 - - - - - - - - - - - - - - - - 30 2 20 - - - - - - - - - - - - - - - 30 4 20 - - - - - - - 28 - - - - - - - 30 - - 2C - - 8 20 - - - 24 - - - 28 - - 30 16 20 - 22 - 24 - 26 - 28 - 2A - 2C - 2E - 30 32 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 Fig. 13: resistive hysteresis. '-' indicates unauthorized programming. When setting high converter resolutions which use all resolution steps, to produce hysteresis the resolution of the converter is increased in an intermediate step by switching on a capacitive voltage divider. Hysteresis can be set in intervals of 5% from 0..95% in conjunction with the output values given in the upper half of the above table of resolution (output values are without a right shift). Hysteresis given in % (capacitive) H 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 Y S 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17 1C 1D 1E 1F Fig. 14: capacitive hysteresis. iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 12/21 Programming the zero position Fig. 15: programming the zero position. A zero crossing can be set to multiples of 45° via register ZCONF(2:0) (Figure 15). If the value is an even number (ZCONF0= 0), then each of the zero pulses (ZX and Z4) are 1/2 period in width; otherwise their width is only 1/4 period. This two-step adaptation procedure is performed accordingly in all segments. To activate converter adaptation, bit ADAP must be set and the entire storage area of the adaptation parameters written in one write cycle. Z4 remains ungated when ZCONF3= 1. ROT inverts the direction of rotation referred to the zero point set by ZCONF. Restrictions: read access to the signal adaptation registers is not permitted. The internal address register must not point to the adaptation register during converter operation (addresses 16..127 are not permitted during operation). Converter adaptation to non-sinusoidal input signals Adaptation is carried out in two steps and is performed separately for each of the eight segments. In the first step, the offset and gain of the programmable gain amplifier (PGA) are set. The offset is corrected so that at the beginning of the first segment the signal at the PGA output is zero (sin0°= 0). The signal at the end of the first segment is then adapted to the cosine signal (sin45°= cos45°) with the gain setting. This adjustment should be tested by changing the direction of rotation and also by increasing the resolution. The following diagram shows how the transfer function must be adapted in the feedback loop in the first segment should triangular signals be available at the input. 1 0.9 0.8 0.7 0.6 0.4 adapted converter function: 0.3 Ftan(n) = n / (90° - n) 0.2 FA15[1]= 3 FA15D[1]= 0 0.1 0 In the second step, the transfer function in the TAN D/A converter is set to the value e1/e2 (e= input signal). In the basic setting (e1 = sin, e2 = cos), the PGA has a gain of one and an offset of zero. The tangent function is formed in the feedback loop. Ftan(n)= tan(n) FA15[1]= 0 0.5 0E 5E 10E 15E 20E 25E 30E 35E 40E Fig. 16: transfer function in feedback loop (1st segment). The transfer function is more sharply curved for triangular input signals. 45E iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 13/21 Period counter System clock The 24-bit position counter can be read via the COUNT registers (addresses 1..3). Write access is not possible, yet the counter can be reset by CLC. An internal oscillator is available as a clock generator. The frequency is determined by an external resistor. Under normal circumstances (SIC= 0), the counter is increased or decreased by an overflow of the 8-bit interpolation register NG (address 0), according to the direction of run. Together with register NG, the output value is 4 bytes. The counter stimulus is monitored by the separate fourfold edge evaluation feature and guarantees that the count functions perform properly even when input frequencies are excessively high, provided the phase does not step by more than 90°. If this is the case, error flag STEPINP is set. CBZ must be set should the counter be reset by the zero pulse. Counting is enabled by pin MFP (SLCNTEN= 1) or alternatively by register COUNTEN (SLCNTEN= 0). For measurement applications, the position counter input can also be switched to the interpolated output pulse (SIC= 1). Interrupt and error messages The occurrence of an interrupt or error is indicated in the interrupt and error status register at address 6. Using registers LATINT and LATERR (address 11), the user can decide whether the information is to be displayed only as long as the interrupt or error persists or whether this information should be stored. Pins MFP for interrupts (active high) and NER for errors (active low) are available for message outputs; authorization for signaling must be granted. Pin MFP must have output function (SLCNTEN= 0) to enable displaying. RPM/Speed acquisition The TACHO speed data register can be used to access a very simple RPM/speed log. The number of clock pulses between two consecutive output values is recorded here as a ones complement. The register is updated with each change in output value. No digital filtering is performed. In addition, register FREQ can be used to increase the clock rate tenfold. This is prudent with a high input frequency if merely the number of revolutions is to be determined. Alternatively, the system clock can be fed in externally. The frequency should be between 0Hz and fmax and should not exceed the maximum low pulse duration (see characteristics), as otherwise the internal clock oscillator switches in. iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 14/21 PROGRAMMING Register Configuration Adr read write 0-3 Data Output Register Target Position 4 Incremental Signals - 5 Speed Data - 6 Interrupt / Error Messages - 7 Rotation Direction, Resolution Setting Rotation Direction, Resolution Setting 8 Data Shift, PGA Bypass, Converter Hysteresis Data Shift, PGA Bypass, Converter Hysteresis Operation Mode, Counter Depth, Z Index Position 9 Operation Mode, Counter Depth, Z Index Position 10 Counter Settings Counter Settings 11 Interrupt / Error Message Enable Interrupt / Error Message Enable 12 Input Amplifier Compensation Input Amplifier Compensation 13 Clock Frequency Select Clock Frequency Select 16-23 - Gain / Fullscale Calibration 24-31 - Offset Adjustment 32-127 - TAN Function Adaptation Register Configuration Name Adr 7 Reset entry 6 5 0 3-1 4 4 3 ROT Z4 B4 A4 ERRV 7 ROT 8 NGLJ ACCMOD(1:0) AX MAXFREQ POSCOMP NGUPDT LATERR LATINT ! ! 1F OUTSEL(1:0) 30 (B0)1 00 (01)2 ZCONF(3:0) CLC CBZ COUNTEN SLCNTEN SIC 00 EN4 EN3 EN2 EN1 EN0 05 FREQ reserved3 reserved3 reserved3 CZERO(3:0) CSIN(3:0) FF 08 16-23 Gain / Fullscale Calibration 24-31 Offset Adjustment FF 32-127 TAN Function Adaptation FF Synchronous-serial mode Incremental mode 3 Register programming to 1 is not permitted 2 BX HYS(5:0) 13 1 00 00 00 ZX ! STEPINP ADAP 7:0 00 RES(6:0) 10 12 0 TACHO(7:0) 6 11 1 COUNT(23:0) resp. TPOS(31:8) AXB 5 9 2 NG(7:0) resp. TPOS(7:0) FF iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 15/21 Data Output Register Interpolation (read only) Bit Name 7 NG7 6 NG6 5 NG5 4 NG4 Adr: 0 3 NG3 2 NG2 1 NG1 0 NG0 Period Count 1.Byte (write only) Bit Name 7 COUNT7 6 COUNT6 5 COUNT5 4 COUNT4 Adr: 1 3 COUNT3 2 COUNT2 1 COUNT1 0 COUNT0 Period Count 2.Byte (write only) Bit Name Adr: 2 7 6 5 4 3 2 1 COUNT15 COUNT14 COUNT13 COUNT12 COUNT11 COUNT10 COUNT9 0 COUNT8 Period Count 3. Byte (write only) Bit Name Adr: 3 7 6 5 4 3 2 1 0 COUNT23 COUNT22 COUNT21 COUNT20 COUNT19 COUNT18 COUNT17 COUNT16 ADR 0, NG(7:0) ADR 3:1, COUNT(23:0) Target Position 1. Byte (write only) Bit Name 7 TPOS7 6 TPOS6 Adr: 0 5 TPOS5 4 TPOS4 3 TPOS3 2 TPOS2 1 TPOS1 0 TPOS0 2. Byte (write only) Bit Name 7 TPOS15 6 TPOS14 Adr: 1 5 TPOS13 4 TPOS12 3 TPOS11 2 TPOS10 1 TPOS9 0 TPOS8 3. Byte (write only) Bit Name 7 TPOS23 6 TPOS22 Adr: 2 5 TPOS21 4 TPOS20 3 TPOS19 2 TPOS18 1 TPOS17 0 TPOS16 4. Byte (write only) Bit Name 7 TPOS31 6 TPOS30 Adr: 3 5 TPOS29 4 TPOS28 3 TPOS27 2 TPOS26 1 TPOS25 0 TPOS24 ADR 3:0, TPOS(31:0) Incremental Signals (read) Bit Name 7 AXB Bit 0, AX 6 ROT Adr: 4 5 Z4 4 B4 3 A4 2 ZX Incremental track A (with the set resolution) Bit 1, BX Incremental track B (with the set resolution) Bit 2, ZX Zero signal (gated with AX, BX in accordance with ZCONF(2:0) definition) Bit 3, A4 Incremental track A (with a resolution of 4) Bit 4, B4 Incremental track B (with a resolution of 4) Bit 5, Z4 Bit 6 ROT Bit 7, AXB Zero signal (gated with A4, B4 in accordance with ZCONF(3:0) definition) 0 1 Counterclockwise. Output value decreases. Sine is 90° ahead of cosine Clockwise. Output value increases. Sine is 90° behind cosine Incremental tracks AX and BX EX-OR-gated 1 BX 0 AX iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 16/21 Speed Data (read only) Bit Name 7 TACHO7 Adr: 5 6 5 4 3 TACHO6 TACHO5 TACHO4 TACHO3 2 TACHO2 1 TACHO1 0 TACHO0 Adr 5, TACHO(7:0) Interrupt / Error Messages (active high, read only) Bit Name 7 6 5 4 ERRV Adr: 6 3 STEPINP 2 MAXFREQ 1 0 POSCOMP NGUPDT This register is always set even if the necessary interrupts or errors are not enabled to be displayed. Data Output Change (Interrupt) Bit 0, NGUPDT Output value has changed (message is set over a clock cycle) Target Position Check (Interrupt) Bit 1, POSCOMP Output value matches target position (depth of comparison in accordance with OUTSEL(1:0) definition) Frequency Error 1 (Error) Bit 2, MAXFREQ Input frequency is to high for the set resolution. COUNT(23:0) valid, AX/BX invalid (monitoring prudent in incremental mode) Frequency Error 2 (Error) Bit 3, STEPINP The input signal phase has turned 90°-270° during a clock cycle, i.e. A4 and B4 have changed simultaneously. COUNT(23:0) invalid (monitoring prudent in parallel-absolute mode) Undervoltage (Error) Bit 4, ERRV Supply voltage too low Resolution Setting, Rotation Direction Bit Name 7 ROT 6 RES6 5 RES5 Adr: 7 4 RES4 3 RES3 2 RES2 Resolution Setting Bit 4..0 RES(4:0) '00'h .. '1F'h TAN D/A converter resolution per segment = 1 .. TAN D/A converter resolution per segment = 32 Bit 6,5 RES(6:5) 00 01 10 11 Resolution equals 8 times the TAN D/A converter resolution Output value shifted 1 bit to the right (resolution halved) Output value shifted 2 bits to the right Output value shifted 3 bits to the right Rotation Direction Bit 7 ROT 0 1 Output value increases if cosine before sine (mathematically positive) Output value decreases if cosine before sine 1 RES1 0 RES0 iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 17/21 Hysteresis, Data Shift, PGA Bypass Bit Name 7 NGLJ 6 ADAP Adr: 8 5 HYS5 4 HYS4 3 HYS3 2 HYS2 1 HYS1 0 HYS0 Hysteresis Bit 5:0 HYS(5:0) '00'h .. '3F'h Hysteresis according to the tables on page 11 0 1 Programmable gain amplifier (PGA) deactivated Programmable gain amplifier (PGA) activated Data Shift Bit 6 ADAP PGA Bypass Bit 7 NGLJ 0 1 Output value is justified right Output value is shifted left (only practical in synchronous-serial mode for resolutions smaller than 136) Z Index Position, Counter Depth, Operation Mode Bit Name 7 ACCMOD1 6 ACCMOD0 Adr: 9 5 4 3 OUTSEL1 OUTSEL0 ZCONF3 2 ZCONF2 1 0 ZCONF1 ZCONF0 Z Index Position Bit 2:0 ZCONF(2:0) 000 001 010 011 100 101 110 111 Zero crossing at 0° Zero crossing at 45° Zero crossing at 90° Zero crossing at 135° Zero crossing at 180° Zero crossing at 225° Zero crossing at 270° Zero crossing at 315° (Sin = 0, COS = 1) (Sin = COS > 0) (Sin = 1, COS = 0) (Sin = -COS > 0) (Sin = 0, COS = -1) (Sin = COS < 0) (Sin = -1, COS = 0) (Sin = -COS < 0) (ZX, Z4 both ½ cycle wide) (ZX,Z4 both ¼ cycle wide) (ZX,Z4 both ½ cycle wide) (ZX,Z4 both ¼ cycle wide) (ZX,Z4 both ½ cycle wide) (ZX,Z4 both ¼ cycle wide) (ZX,Z4 both ½ cycle wide) (ZX,Z4 both ¼ cycle wide) If the ZERO inputs do not receive a true zero signal from the sensor, different wiring is necessary to produce ZERO = 1 (via V(PZERO) > V(NZERO)). Bit 3 ZCONF3 0 1 Z4 gated with A4 and B4 (width of Z4 = ¼), Z4 gated with A4 or B4 (width of Z4 = ½) Z4 not gated Counter Depth Bit 5:4 OUTSEL(1:0) 00 01 10 11 Output value consists of NG(7:0) Output value consists of COUNT(7:0) & NG(7:0) Output value consists of COUNT(15:0) & NG(7:0) Output value consists of COUNT(23:0) & NG(7:0) This setting affects target position evaluation and sets the MSB to synchronous-serial mode Operation Mode Bit 7:6 ACCMOD(1:0) 00 10 11 Parallel mode Synchronuous-serial mode Incremental mode 01 not permitted The access mode is determined when the configuration is loaded from the serial EEPROM and cannot be altered during operation. If no EEPROM is available, the access mode can be set via pins SDA and SCL. iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 18/21 Position Counter Settings Bit Name 7 6 Adr: 10 5 4 CLC 3 CBZ 2 COUNTEN 1 SLCNTEN 0 SIC Input Select Bit 0 SIC 0 1 The position counter is increased/decreased with each zero crossing The position counter is increased/decreased with each interpolation step Enable Select Bit 1 SLCNTEN 0 1 Count operation is enabled via the COUNTEN register; MFP is an output pin Count operation is enabled via pin MFP; MFP is an input pin 0 1 Position counter is stopped (with SLCNTEN = 0) Position counter enabled (with SLCNTEN = 0) Enable Bit 2 COUNTEN Reset Enable Bit 3 CBZ 0 1 Position counter is not reset with a zero pulse Position counter is reset with every zero pulse 0 1 Position counter is not reset Position counter is reset Reset Bit 4 CLC Interrupt / Error Message Enable (active high) Bit Name 7 6 5 LATERR LATINT 4 EN4 Adr: 11 3 EN3 2 EN2 1 EN1 Interrupts are shown active high at pin MFP if this is programmed as an output. Errors are shown active low at pin NER. Bit 0, EN0 0 1 Disabled NGUPDT enabled. Status following a reset (message to pin MFP) Bit 1, EN1 0 1 Disabled POSCOMP enabled (message to pin MFP) Bit 2, EN2 0 1 Disabled MAXFREQ enabled. Status following a reset (Message to pin NER) Bit 3, EN3 0 1 Disabled STEPINP enabled (message to pin NER) Bit 4, EN4 0 1 Disabled ERRV enabled (message to pin NER) Bit 5, LATINT 0 1 Interrupts are only shown while the cause for the interrupt persists Interrupt status is saved (programming 1-0-1 resets the registers of address 6) Bit 6, LATERR 0 1 Errors are only shown while the cause for the error persists Error status is saved (programming 1-0-1 resets the registers of address 6) 0 EN0 iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 19/21 Input Amplifier Compensation Bit Name 7 CZERO3 Adr: 12 6 5 4 CZERO2 CZERO1 CZERO0 3 CSIN3 2 CSIN2 1 CSIN1 0 CSIN0 SIN, COS Inputs Bit 3:0 CSIN(3:0) '0'h .. 'F'h 0.0pF 0.8pF / LSB 12.0pF '0'h .. 'F'h 0.0pF 0.8pF / LSB 12.0pF ZERO Input Bit 7:4 CZERO(3:0) Clock Frequency Select 6 Adr: 13 Bit Name 7 5 4 3 FREQ 2 reserved Bit 3 FREQ 0 1 Clock frequency has increased ca. tenfold (only valid when no external clocking pulse is fed in) Clock frequency not multiplied Bit 2:0 reserved 0 Registers must always be programmed to 0 PGA Gain (write only) Bit Name 7 G7[i] Bit 7:0 G(7:0)[i] '00'h '01'h .. '7F'h 'FF'h .. '81'h '80'h 7 O7[i] Bit 7:0 O(7:0)[i] '00'h .. '7F'h 'FF'h .. '80'h 0 reserved Adr: 16-23 (1.-8. Segment) 6 G6[i] 5 G5[i] 255/128 . 1.992 . 1.984 4 G4[i] 3 G3[i] 2 G2[i] 1 G1[i] 0 G0[i] 1/128 pro LSB ×0.0078 128/128 = 1 255/255 = 1 . 0.50592 128/255 . 0.502 1/255 pro LSB ×0.00392 PGA Offset (write only) Bit Name 1 reserved Adr: 24-31 (1.-8. Segment) 6 O6[i] 5 O5[i] 4 O4[i] 3 O3[i] -127/384×A . -0.33×A -1/384×A pro LSB -0/384×A = 0 0/384×A = 0 1/384×A pro LSB 127/384×A . 0.33×A A = input signal amplitude 2 O2[i] 1 O1[i] 0 O0[i] iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 20/21 TAN Function Adaptation base 1-4 (write only) Bit Name 7 FA4H[i] 6 FA4L[i] 5 FA3H[i] Bit Name 7 FA8H[i] 6 FA8L[i] 5 FA7H[i] Bit Name 7 FA12H[i] 6 FA12L[i] 5 FA11H[i] 4 FA3L[i] Adr: 32-39 (1.-8. Segment) 3 FA2H[i] 2 FA2L[i] 1 FA1H[i] 3 FA6H[i] 2 FA6L[i] 1 FA5H[i] 2 FA10L[i] 1 FA9H[i] base 5-8 (write only) 4 FA7L[i] Adr: 40-47 (1.-8. Segment) base 9-12 (write only) 4 FA11L[i] 3 FA10H[i] 7 FA16H[i] 6 FA16L[i] 5 FA15H[i] 4 FA15L[i] 3 FA14H[i] 7 FA20H[i] 6 FA20L[i] 5 FA19H[i] Bit Name 7 FA24H[i] 6 FA24L[i] 5 FA23H[i] Bit Name 7 FA28H[i] 6 FA28L[i] 5 FA27H[i] 4 FA19L[i] 3 FA18H[i] 2 FA14L[i] 3 FA22H[i] 2 FA18L[i] 1 FA17H[i] 2 FA22L[i] 1 FA21H[i] 3 FA26H[i] 2 FA26L[i] 1 FA25H[i] 7 K1[i] 6 K0[i] 5 FA31H[i] 4 FA31L[i] 3 FA30H[i] 2 FA30L[i] 00 10 01 11 No adaptation of function at base J Adaptation of function at base J with an intensity of 1 Adaptation of function at base J with an intensity of 2 Adaptation of function at base J with an intensity of 3, always in segment i K1[i], K0[i] 11 Reserved; register must stay set at 1 base 1-8 (write only) Bit Name 7 FA8D[i] 6 FA7D[i] 5 FA6D[i] Bit Name 7 FA16D[i] 6 FA15D[i] 5 FA14D[i] Bit Name 7 FA24D[i] 6 FA23D[i] 5 FA22D[i] 4 FA5D[i] 3 FA4D[i] 3 FA12D[i] 2 FA3D[i] 3 FA20D[i] FajD[i] 7 6 FA31D[i] 0 1 5 FA30D[i] 4 FA29D[i] Upward adaptation of function at base J Downward adaptation of function at base J 3 FA28D[i] 0 FA29L[i] 1 FA2D[i] 0 FA1D[i] 1 FA10D[i] 0 FA9D[i] Adr: 112-119 (1.-8. Segment) 2 FA19D[i] base 25-31 (write only) Bit Name 1 FA29H[i] Adr: 104-111 (1.-8. Segment) 2 FA11D[i] base 17-24 (write only) 4 FA21D[i] 0 FA25L[i] Adr: 96-103 (1.-8. Segment) base 9-16 (write only) 4 FA13D[i] 0 FA21L[i] Adr: 88-95 (1.-8. Segment) FajH[i], FAjL[i] TAN Function Adaptation 0 FA17L[i] Adr: 80-87 (1.-8. Segment) base 29-31 (write only) Bit Name 0 FA13L[i] Adr: 72-79 (1.-8. Segment) base 25-28 (write only) 4 FA27L[i] 1 FA13H[i] Adr: 64-71 (1.-8. Segment) base 21-24 (write only) 4 FA23L[i] 0 FA9L[i] Adr: 56-63 (1.-8. Segment) base 17-20 (write only) Bit Name 0 FA5L[i] Adr: 48-55 (1.-8. Segment) base 13-16 (write only) Bit Name 0 FA1L[i] 1 FA18D[i] 0 FA17D[i] Adr: 120-127 (1.-8. Segment) 2 FA27D[i] 1 FA26D[i] 0 FA25D[i] iC-NG 8-BIT Sin/D CONVERTER-PROCESSOR Rev D3, Page 21/21 APPLICATIONS NFORMATION Application notes for iC-NG and details on the demo board are available separately. ORDERING INFORMATION Type Package Order Designation iC-NG iC-NG SO28 SSOP28 5.3mm iC-NG SO28 iC-NG SSOP28 Evaluation board iC-NG EVAL NGD The evaluation board includes: S board 100 mm x 160 mm S interface cable for the serial interface S 3.5" floppy disk containing the control program S iC-NG data sheet S description Information on prices, delivery dates, possible deliveries of other packages etc. are available from: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel. +49-6135-9292-0 Fax +49-6135-9292-192 www.ichaus.com This specification is for a newly developed product. iC-Haus therefore reserves the right to change or update, without notice, any information contained herein, design and specification; and to discontinue or limit production or distribution of any product versions. Please contact iC-Haus to ascertain the current data. Copying - even as an excerpt - is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.