ICS307-01/02 SERIALLY PROGRAMMABLE CLOCK SOURCE Description Features The ICS307-01 and ICS307-02 are versatile serially programmable clock sources which take up very little board space. They can generate any frequency from 6 to 200 MHz and have a second configurable output. The outputs can be reprogrammed on the fly and will lock to a new frequency in 10 ms or less. Smooth transitions (in which the clock duty cycle remains near 50%) are guaranteed if the output divider is not changed. • Packaged in 16-pin (150 mil wide) SOIC • ICS307M-02 and -02I available in Pb (lead) free The devices includes a PDTS pin which tri-states the output clocks and powers down the entire chip. The ICS307-02 features a default clock output at start-up and is recommended for all new designs. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output skew, use the ICS527-01. package • Highly accurate frequency generation • Serially programmable: user determines the output frequency via a 3 wire interface • • • • • • • • Eliminates need for custom quartz Input crystal frequency of 5 - 27 MHz Output clock frequencies up to 200 MHz Power down tri-state mode Very low jitter Operating voltage of 3.3 V or 5 V 25 mA drive capability at TTL levels Industrial temperature version available Block Diagram VDD TTL SCLK DATA Shift Register STROBE 2 C1:C0 3 S2:S0 2 F1:F0 VCO Divider 7 R6:R7 X1/ICLK Crystal or clock input V8:V0 9 Crystal Oscillator X2 Reference Divider CLK1 Phase Comparator, Charge Pump, and Loop Filter Output Divider VCO PDTS Function Select 3 S2:S0 Optional crystal capacitors CLK2 3 F1:F0 GND 1 MDS 307-01/02 F I n t e gra te d C i r c u i t S y s t e m s ● 5 25 Race Stre et, San Jo se, CA 9 5126 Revision 121304 ● te l (40 8) 2 97-12 01 ● w w w. i c st . c o m ICS307-01/02 SERIALLY PROGRAMMABLE CLOCK SOURCE Pin Assignment X1/ICLK 1 16 X2 NC 2 15 NC VDD 3 14 NC NC 4 13 PDTS GND 5 12 DATA CLK2 6 11 CLK1 NC 7 10 SCLK 8 9 NC STRO BE 16 pin (150 m il) SO IC Pin Descriptions Pin Number Pin Name Pin Type 1 X1/ICLK XI 2 NC - 3 VDD Power 4 NC - 5 GND Power Connect to ground. 6 CLK2 Output Output clock 2, determined by F0 - F1. Can be reference, REF/2, CLK1/2 , or off. 7 NC - 8 SCLK Input Serial clock. See timing diagram. 9 STROBE Input Strobe to load data. See timing diagram. 10 NC - 11 CLK1 Output 12 DATA Input Data input. Serial input for three words which set the output clock(s). 13 PDTS Input Powers down entire chip, tri states CLK1 and CLK2 outputs when low. Internal pull-up. 14 NC - No connect. Do not connect anything to this pin. 15 NC - No connect. Do not connect anything to this pin. 16 X2 XO Crystal connection (REF frequency). Connect to a parallel resonant crystal or an input clock. No connect. Do not connect anything to this pin. Connect to 3.3 V or 5 V. No connect. Do not connect anything to this pin. No connect. Do not connect anything to this pin. No connect. Do not connect anything to this pin. Output clock 1, determined by R0 - R6, V0 - V8, S0 - S2, and input frequency. Input crystal connection. Connect to a crystal or leave unconnected for clock input. 2 MDS 307-01/02 F In te grated Circuit Systems Pin Description ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121304 ● tel (4 08) 297 -1 201 ● w w w. i c s t . c o m ICS307-01/02 SERIALLY PROGRAMMABLE CLOCK SOURCE Determining the Output Frequency On power-up, the ICS307-01 on-chip registers can have random values so almost any frequency may be output from the part. CLK1 will always have some clock signal present, but CLK2 could possibly be OFF (low). The ICS307-02 on-chip registers are initially configured to provide a x1 output clock on both the CLK1 and CLK2 outputs. The output frequency will be the same as the input clock or crystal. This is useful if the ICS307 will provide the initial system clock at power-up. Since this feature is an advantage in most systems, the ICS307-02 is recommended for new designs. To determine the best combination of VCO, reference, and output dividers, see the online calculator at http://www.icst.com/products/ics307inputForm.html or contact ICS by sending an e-mail to [email protected] with the desired input crystal or clock and the desired output frequency. With programming, the user has full control in changing the desired output frequency to any value over the range shown in Table 1 on page 4. The output of the ICS307 can be determined by the following equation: VDW + 8 CLK1Frequency = InputFrequency ⋅ 2 ⋅ ------------------------------------------( RDW + 2 ) ⋅ OD Where: VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3 are not permitted) Reference Divider Word (RDW) = 1 to 127 (0 is not permitted) Output Divider = values on page 4 The following operating ranges should be observed. For the commercial temperature range: VDW + 8 55MHz < InputFrequency ⋅ 2 ⋅ ------------------------ < 400MHz RDW + 2 InputFrequency 200kHz < ---------------------------------------------RDW + 2 And for the industrial temperature range: VDW + 8 60MHz < InputFrequency ⋅ 2 ⋅ ------------------------ < 360MHz RDW + 2 Input Frequency 200kHz < ------------------------------------------RDW + 2 3 MDS 307-01/02 F In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121304 ● tel (4 08) 297 -1 201 ● w w w. i c s t . c o m ICS307-01/02 SERIALLY PROGRAMMABLE CLOCK SOURCE Setting the Device Characteristics The tables below show the settings which can be configured, as well as the VCO and Reference dividers. Table 1. Output Divide and Maximum Output Frequency S2 S1 S0 CLK1 Output Divide Max. Frequency 5 V or 3.3 V (MHz) Max. Frequency Industrial Temp. Version 0 0 0 10 40 36 0 0 1 2 200 180 0 1 0 8 50 45 0 1 1 4 100 90 1 0 0 5 80 72 1 0 1 7 55 50 1 1 0 3 135 120 1 1 1 6 67 60 Table 2. CLK2 Output F1 F0 CLK2 0 0 REF 0 1 FREF/2 1 0 OFF (Low) 1 1 FCLK1/2 Table 3. Output Duty Cycle Configuration TTL Duty Cycle Measured At Recommended VDD 0 1.4 V 5V 1 VDD/2 3.3 V Note: The TTL bit optimizes the duty cycle at different VDD. When VDD is 5 V, set to 0 for a near-50% duty cycle with TTL levels. When VDD is 3.3 V, set this bit to 1 so the 50% duty cycle is achieved at VDD/2. Table 4. Crystal Load Capacitance C1 C0 VDD = 5V VDD = 3.3V 0 0 22.3 - 0.083 f 22.1 - 0.094 f 0 1 23.1 - 0.093 f 22.9 - 0.108 f 1 0 23.7 - 0.106 f 23.5 - 0.120 f 1 1 24.4 - 0.120 f 24.2 - 0.135 f Note: f is the crystal frequency in MHz between 10 and 27 MHz. Effective load capacitance will be higher for crystal frequencies lower than 10 MHz. If a clock input is used, set C1 = 0 and C0 = 0. 4 MDS 307-01/02 F In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121304 ● tel (4 08) 297 -1 201 ● w w w. i c s t . c o m ICS307-01/02 SERIALLY PROGRAMMABLE CLOCK SOURCE Bypass Mode If R6:0 is programmed to 0000000, the PLL is powered down and bypassed; the reference frequency will come from both CLK1 and CLK2. It is possible to generate glitches going into and out of this mode. Configuring the ICS307 The ICS307 can be programmed to set the output functions and frequencies. The three data bytes are written in DATA pin in this order: C1 C0 F1 TTL F0 S2 S1 MSB S0 V8 LSB MSB V7 V6 V5 V4 V3 V2 V1 V0 LSB MSB R6 R5 R4 R3 R2 R1 C1 is loaded into the port first and R0 last. R6:R0 Reference Divder Word (RDW) V8:V0 VCO Divider Word (VDW) S2:S0 Output Divider Select (OD) F1:F0 Function of CLK2 Output TTL Duty Cycle Settings C1:C0 Internal Load Capacitance for Crystal The ICS307 can be reprogrammed at any time during operation. If R6:0, V8:0, TTL, or C1:0 are changed, the frequency will transition smoothly to the new value over about 1 ms, without glitches or short cycles. If S2:0 is changed, it is possible to generate glitches on CLK1 and also on CLK2 for F1:0 = 1 1. Changing F1:0 will generate glitches on CLK2. Power up default values for ICS307-02 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 The input frequency will come from both outputs. A warning about using the default configuration with input frequencies lower than 13.75 MHz The VCO will run only as low as its minimum frequency, which is guaranteed to be no more than 55 MHz. So, in the powerup default condition, the PLL is guaranteed to lock to the input frequency down to 55/4 = 13.75 MHz. However, the part will typically run much slower. The typical minimum VCO frequency is about 30 - 40 MHz, depending on voltage, temperature, and lot variation; so in the powerup default setting, the CLK2 output will be a minimum of 7.5 - 10 MHz even if the input frequency is lower than that. The output is not locked to the reference input and so the frequency is not very stable and the phase noise is higher. In this condition, the CLK2 output will accurately provide the reference frequency down to 0 Hz because this signal path bypasses the PLL. 5 MDS 307-01/02 F In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121304 ● R0 LSB tel (4 08) 297 -1 201 ● w w w. i c s t . c o m ICS307-01/02 SERIALLY PROGRAMMABLE CLOCK SOURCE Programming Example To generate 66.66 MHz from a 14.31818 MHz input, the RDW should be 59, the VDW should be 276, and the Output Divide is 2. Selecting the minimum internal load capacitance, CMOS duty cycle, and CLK2 to be OFF means that the following three bytes are sent to the ICS307: 00110001 10001010 00111011 Byte 1 Byte 2 Byte 3 As show in Figure 2, after these 24 bits are clocked into the ICS307, taking STROBE high will send this data to the internal latch and the CLK output will lock within 10 ms. Note: If STROBE is in the high state and SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will change accordingly. Although this will not damage the ICS307, it is recommended that STROBE be kept low while DATA is being clocked into the ICS307 in order to avoid unintended changes on the output clocks. AC Parameters for Writing to the ICS307 Parameter Condition Min. tSETUP Setup time 10 ns tHOLD Hold time after SCLK 10 ns tW Data wait time 10 ns tS Strobe pulse width 40 ns SCLK Frequency DATA C1 C0 tsetup TTL F1 R1 Max. Units 50 MHz R0 thold SCLK tw ts STROBE Figure 2. Timing Diagram for Programming the ICS307 External Components/Crystal Selection The ICS307 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be connected close to the ICS307 to minimize lead inductance. A 33Ω terminating resistor can be used in series with CLK1 and CLK2 outputs. A parallel resonant, fundamental mode crystal with a load (correlation) capacitance of C should be used, where C is the value calculated from Table 4. For crystals with a specified load capacitance greater than C, additional crystal capacitors may be connected from each of the pins X1 and X2 to ground as shown in the Block Diagram on page 1. The value (in pF) of these crystal caps should be = (CL-C)*2, where CL is the crystal load capacitance in pF and C is the capacitance value from Table 4. These external capacitors are only required for applications where the exact frequency is critical. For a clock input, connect to X1 and leave X2 unconnected (no capacitors on either pin). 6 MDS 307-01/02 F In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121304 ● tel (4 08) 297 -1 201 ● w w w. i c s t . c o m ICS307-01/02 SERIALLY PROGRAMMABLE CLOCK SOURCE Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS307-01/02. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Ambient Operating Temperature, Industrial -40 to +85°C Storage Temperature -65 to +150°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Max. Units 0 +70 °C +3.0 +5.5 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. DC Electrical Characteristics VDD=3.3 V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise Parameter Symbol Conditions Min. Typ. 3.0 Max. Units 5.5 V Operating Voltage VDD Input High Voltage Input Low Voltage Input High Voltage VIH VIL VIH X1/ICLK only X1/ICLK only Input Low Voltage VIL PDTS on ICS307-01 0.4 V All other inputs, ICS307-01/02 0.8 V (VDD/2)+1 VDD/2 VDD/2 (VDD/2)-1 2 V V V Output High Voltage VOH IOH = -25 mA Output Low Voltage VOL IOL = 25 mA Output High Voltage, CMOS level VOH IOH = -4 mA Operating Supply Current IDD 20 MHz crystal No load, 100 MHz out 26 mA 100 MHz out, 3.3 V 13 mA V 0.4 VDD-0.4 ● 525 Ra ce Street, San Jose, CA 9512 6 V V 7 MDS 307-01/02 F In te grated Circuit Systems 2.4 Revision 121304 ● tel (4 08) 297 -1 201 ● w w w. i c s t . c o m ICS307-01/02 SERIALLY PROGRAMMABLE CLOCK SOURCE Parameter Symbol Short Circuit Current Conditions Min. Typ. CLK outputs Input Capacitance CIN On-Chip Pull-up Resistor RPU Pin 13 Max. Units ±70 mA 4 pF 270 kΩ AC Electrical Characteristics VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Parameter Input Frequency Symbol FIN Conditions Min. Typ. Max. Units Fundamental crystal 5 27 MHz Clock 2 6 50 200 MHz MHz I-temp version 6 180 MHz Output Frequency (see Table 1) Output Clock Rise Time tOR 0.8 to 2.0 V, Note 1 1 ns Output Clock Fall Time tOF 2.0 to 8.0 V, Note 1 1 ns Output Clock Duty Cycle Power-up Time even output divides 45 odd output divides 40 3 STROBE goes high until CLK out One Sigma Clock Period Jitter Maximum Absolute Jitter tja 49-51 Deviation from mean 55 % 60 % 10 ms 50 ps ±120 ps Note 1: Measured with 15 pF load. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 120 °C/W θJA 1 m/s air flow 115 °C/W θJA 3 m/s air flow 105 °C/W 58 °C/W θJC 8 MDS 307-01/02 F In te grated Circuit Systems Symbol ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121304 ● tel (4 08) 297 -1 201 ● w w w. i c s t . c o m ICS307-01/02 SERIALLY PROGRAMMABLE CLOCK SOURCE Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number ICS307M-01 ICS307M-01T ICS307M-01I ICS307M-01IT ICS307M-02 ICS307M-02T ICS307M-02LF ICS307M-02LFT ICS307M-02I ICS307M-02IT ICS307M-02ILF ICS307M-02ILFT Marking ICS307M-01 ICS307M-01 ICS307M-01I ICS307M-01I ICS307M-02 ICS307M-02 ICS307M-02LF ICS307M-02LF ICS307M-02I ICS307M-02I ICS307M02ILF ICS307M02ILF Shipping packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C -40 to +85° C -40 to +85° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 9 MDS 307-01/02 F In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121304 ● tel (4 08) 297 -1 201 ● w w w. i c s t . c o m