ICS ICS3726M

ICS3726-02
PRELIMINARY INFORMATION
HIGH PERFORMANCE VCXO
Description
Features
The ICS3726-02 is a low cost, low-jitter,
high-performance 3.3 volt VCXO designed to replace
expensive discrete VCXOs modules. The ICS3726-02
offers a wider operating frequency range and improved
power supply noise rejection. The on-chip Voltage
Controlled Crystal Oscillator accepts a 0 to 3.3 V input
voltage to cause the output clocks to vary by ±200 ppm.
Using ICS’ patented VCXO techniques, the device
uses an inexpensive external pullable crystal in the
range of 20 to 52 MHz to produce a VCXO output clock
at that same frequency.
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This part is ideal for Set-Top Box, multimedia clock
synthesizers and ADSL/VDSL applications.
The frequency of the on-chip VCXO is adjusted by an
external control voltage input into pin VIN. Because
VIN is a high-impedance input, it can be driven directly
from an PWM RC integrator circuit. Frequency output
increases with VIN voltage input. The usable range of
VIN is 0 to VDD.
Packaged in 8-pin SOIC
Operational frequency range of 20 MHz to 52 MHz
Uses an inexpensive external crystal
On-chip patented VCXO with pull range of 400 ppm
VCXO tuning voltage of 0 to VDD
Output Enable control
Operating voltage of 3.3 V
12 mA output drive capability at TTL levels
Works with surface mount crystal with CL=10 pF
Advanced, low-power, sub-micron CMOS process
Available in Pb (lead) free package
Block Diagram
VDD
VIN
X1
20 to 52 MHz
Pullable Crystal
X2
Voltage
Controlled
Crystal
Oscillator
Optional tuning
crystal capacitors
OE
1
MDS 3726-02 B
I n t e gra te d C i r c u i t S y s t e m s
GND
20 to 52 MHz
Clock (REFOUT)
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525 Race Stre et, San Jo se, CA 9 5126
Revision 120505
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ICS3726-02
PRELIMINARY INFORMATION
HIGH PERFORMANCE VCXO
Pin Assignment
X1
1
8
X2
NC
2
7
OE
VI N
3
6
VDD
GND
4
5
REFOUT
I CS 3 7 2 6 - 0 2
8 - P i n ( 1 5 0 mi l ) S OI C
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
XI
Input
2
NC
—
3
VIN
Input
Voltage input to VCXO. Zero to VDD signal which controls the
VCXO frequency.
4
GND
Power
Connect to ground.
5
REFOUT
Output
VCXO CMOS level clock output matches the nominal frequency of
the crystal.
6
VDD
Power
Connect to +3.3 V (0.01 µf decoupling capacitor recommended).
7
OE
Input
Output enable, OE=1 enables outputs, OE=0 disables REFOUT,
internal pull-up.
8
X2
Input
Crystal connection. Connect to a pullable 20 to 52 MHz crystal.
Crystal connection. Connect to the external pullable crystal.
Do connet to this pin.
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MDS 3726-02 B
In te grated Circuit Systems
Pin Description
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525 Ra ce Street, San Jose, CA 9512 6
Revision 120505
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ICS3726-02
PRELIMINARY INFORMATION
HIGH PERFORMANCE VCXO
External Component Selection
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS3726-02. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal. See application note MAN05.
The ICS3726-02 requires a minimum number of
external components for proper operation.
Decoupling Capacitors
A decoupling capacitor of 0.01 µF should be connected
between VDD and GND on pins 6 and 4 as close to the
ICS3726-02 as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50Ω trace (a commonly used
trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF. This chip has internal load
capacitors and is designed to work with surface mount
crystals with 10 pF load capacitance.
The procedure for determining the value of these
capacitors can be found in application note MAN05.
Quartz Crystal
The ICS3726-02 VCXO function consists of the
external crystal and the integrated VCXO oscillator
circuit. To assure the best system performance
(frequency pull range) and reliability, a crystal device
with the recommended parameters (shown below)
must be used, and the layout guidelines discussed in
the following section shown must be followed.
The oscillation frequency of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The ICS3726-02 incorporates on-chip
variable load capacitors that pull (change) the
frequency of the crystal. The crystal specified for use
with the ICS3726-02 is designed to have zero
frequency error when the total of on-chip + stray
capacitance is 10 pF.
Recommended Crystal Parameters:
Initial Accuracy at 25°C
Temperature Stability
Aging
Load Capacitance
Shunt Capacitance, C0
C0/C1 Ratio
Equivalent Series Resistance
3
MDS 3726-02 B
In te grated Circuit Systems
±20 ppm
±30 ppm
±20 ppm
14 pF
7 pF max
250 max
35 Ω max
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525 Ra ce Street, San Jose, CA 9512 6
Revision 120505
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ICS3726-02
PRELIMINARY INFORMATION
HIGH PERFORMANCE VCXO
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS3726-02. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70°C
Storage Temperature
-65 to +150°C
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
Typ.
Max.
Units
0
–
+70
°C
+3.45
V
+3.15
Reference crystal parameters
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MDS 3726-02 B
In te grated Circuit Systems
Refer to page 3
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525 Ra ce Street, San Jose, CA 9512 6
Revision 120505
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ICS3726-02
PRELIMINARY INFORMATION
HIGH PERFORMANCE VCXO
DC Electrical Characteristics
VDD=3.3 V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol
Conditions
Operating Voltage
VDD
Output High Voltage
VOH
IOH = -12 mA
Output Low Voltage
VOL
IOL = 12 mA
Output High Voltage (CMOS
Level)
VOH
IOH = -4 mA
Operating Supply Current
IDD
No load
Short Circuit Current
IOS
VIN, VCXO Control Voltage
VIA
Min.
Typ.
3.15
Max.
Units
3.45
V
2.4
V
0.4
V
VDD-0.4
V
6
mA
±50
mA
0
3.3
V
AC Electrical Characteristics
VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Output Frequency
FO
20
52
MHz
Crystal Pullability
FP
0V< VIN < 3.3 V, Note 1
+ 200
ppm
VCXO Gain
VIN = VDD/2 + 1 V, Note 1
150
ppm/V
Output Rise Time
tOR
0.8 to 2.0 V, CL=15 pF
1.5
ns
Output Fall Time
tOF
2.0 to 0.8 V, CL=15 pF
1.5
ns
Output Clock Duty Cycle
tD
Measured at 1.4 V, CL=15 pF
60
%
Period Jitter RMS
tJ
CL=15 pF @35.328 MHz
6.7
ps
Period Jitter P- P
tJ
CL=15 [email protected] MHz
46
ps
Integrated Jitter RMS
Integrated 12 kHz to 20 MHz
@ 35.328 MHz
1
ps
Phase Noise relative to
Carrier
@35.328 MHz Carrier
frequency
@10 Hz
-65
dBc/Hz
@100 Hz
-90
dBc/Hz
@1 kHz
-120
dBc/Hz
@10 kHz
-140
dBc/Hz
@100 kHz
-147
dBc/Hz
@1 MHz
-147
dBc/Hz
40
50
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
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MDS 3726-02 B
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 120505
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ICS3726-02
PRELIMINARY INFORMATION
HIGH PERFORMANCE VCXO
Package Outline and Package Dimensions (8-pin SOIC)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
8
Symbol
E
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
Min
Max
Min
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.1890
.1968
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
*For reference only. Controlling dimensions in mm.
A
h x 45
A1
C
-Ce
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS3726M-02
ICS3726M-02T
ICS3726M-02LF
ICS3726M-02LFT
3726M-02
3726M-02
3726M02L
3726M02L
Tubes
Tape and Reel
Tubes
Tape and Reel
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
6
MDS 3726-02 B
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 120505
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m