Preliminary Information ICS527-03 Clock Slicer User Configurable PECL Output Zero Delay Buffer Description Features The ICS527-03 is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. • • • • • • The ICS527-03 aligns rising edges on CLKIN with FBPECL at a ratio determined by the reference and feedback dividers. For a PECL input and output clock with zero delay, use the ICS527-04. • • • • • • • Packaged as 28 pin SSOP (150 mil body) Synchronizes fractional clocks rising edges CMOS in to PECL out Pin selectable dividers Zero input to output skew User determines the output frequency - no software needed Slices frequency or period Input clock frequency of 1.5 MHz to 200 MHz Output clock frequencies from 2.5 MHz to 160 MHz Very low jitter Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low power CMOS process Block Diagram R6:R0 7 CLKIN Divide by 2 2 68 ohm 1 0 Reference Divider PECL 180 ohm Phase Comparator, Charge Pump, and Loop Filter FBPECL Divide by 2 FBPECL 1 0 Feedback Divider DIV2 7 F6:F0 VCO Output Divider VDD 68 ohm PECL 180 ohm 2 GND 2 S1:S0 PDTS 1 MDS 527-03 B Integrated Circuit Systems, Inc. VDD VDD ● 525 Race Street, San Jose, CA 95126 Revision 122804 ● tel (408) 297-1201 ● www.icst.com Preliminary Information ICS527-03 Clock Slicer User Configurable PECL Output Zero Delay Buffer Pin Assignment R5 1 28 R4 R6 2 27 R3 DIV2 3 26 R2 S0 4 25 R1 S1 5 24 R0 VDD 6 23 VDD FBPECL 7 22 PECL FBPECL 8 21 PECL GND 9 20 GND CLKIN 10 19 RES PDTS 11 18 F6 F0 12 17 F5 F1 13 16 F4 F2 14 15 F3 Output Frequency and Output Divider Table S1 S0 Output Divider Output Frequency (MHz) 10 - 80 0 0 2 0 1 4 5 - 40 1 0 8 2.5 - 20 1 1 1 20 -160 28 pin 150 mil body SSOP Pin Descriptions Pin Number Pin Name Pin Type 1,2, 24-28 R5, R6, R0-R4 Input Reference divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up. 3 DIV2 Input Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based on the table above. Internal pull-up. 4, 5 S0, S1 Input Select pins for output divider determined by user. See table above. Internal pull-up. 6, 23 VDD Power Connect to +3.3 V. 7 FPECL Input PECL feedback input. 8 FPECL Input Complementary PECL feedback input. 9, 20 GND Power Connect to ground 10 CLKIN Input Clock input. 11 PDTS Input Power Down. Active low. Turns off entire chip when low, both clock outputs are tri-stated. Internal pull-up. 12-18 F0-F6 Input Feedback divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up 19 RES BIAS Resistor connection to VDD for setting level of PECL outputs. 21 PECL Output Complementary PECL input clock. 22 PECL Output PECL input clock. 2 MDS 527-03 B Integrated Circuit Systems, Inc. Pin Description ● 525 Race Street, San Jose, CA 95126 Revision 122804 ● tel (408) 297-1201 ● www.icst.com Preliminary Information ICS527-03 Clock Slicer User Configurable PECL Output Zero Delay Buffer External Components FDW + 2 RDW + 2 FB Frequency = Input Frequency × ------------------------ Decoupling Capacitors As with any high performance mixed-signal IC, the ICS527-03 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. They must be connected close to the device to minimize lead inductance. Where: Reference Divider Word (RDW) = 0 to 127 Feedback Divider Word (FDW) = 0 to 127 FB Frequency is the same as either CLK1 or CLK2 depending on feedback connection Also, the following operating ranges should be observed: Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Determining (setting) the ICS527-03 Dividers The user has full control in setting the desired output clock over the range shown in the table on page 2. The user should connect the divider select input pins directly to ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit Board layout, so the ICS527-03 automatically produces the correct clock when all components are soldered. It is also possible to connect the inputs to parallel I/O ports in order to switch frequencies. Input Frequency 300kHz < ------------------------------------------- < 20 MHz RDW + 2 The output divide should be selected depending on the frequency of CLK1. The table on page 2 gives the ranges. The dividers are expressed as integers. For example, if a 50 MHz output on CLK1 is desired from a 40 MHz input, the reference divider word (RDW) should be 2 and the feedback divider word (FDW) should be 3 which gives the required 5/4 multiplication. If multiple choices of dividers are available, then the lowest numbers should be used. In this example, the output divide (OD) should be selected to be 2. Then R6:R0 is 0000010, F6:F0 is 0000011 and S1:S0 is 00. Also, this example assumes CLK1 is connected to FBIN. If you need assistance determining the optimum divider settings, please send an e-mail to [email protected] with the desired input clock and the desired output frequency. The output of the ICS527-03 can be determined by the following simple equation: 3 MDS 527-03 B Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 122804 ● tel (408) 297-1201 ● www.icst.com Preliminary Information ICS527-03 Clock Slicer User Configurable PECL Output Zero Delay Buffer Typical Example The following connection diagram shows the implementation of the example from the previous section. This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will produce the waveforms shown on the right. VDD 0.01 F R5 R4 R6 R3 DIV2 R2 S0 R1 S1 R0 VDD 0.01 F VDD VDD FBPECL PECL FBPECL PECL GND GND CLKIN RES PDTS F6 F0 F5 F1 F4 F2 F3 50 MHz 560 PECL output resistor network is not shown, but is identical to PECL 40 MHz (PECLIN shown) 50 MHz PECL 50 MHz PECL Note: The series termination resistor is located before the feedback 4 MDS 527-03 B Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 122804 ● tel (408) 297-1201 ● www.icst.com Preliminary Information ICS527-03 Clock Slicer User Configurable PECL Output Zero Delay Buffer Multiple Output Example In this example, an output clock of 125 MHz is used. Four copies of 50 MHz are required, de-skewed and aligned to the 125 MHz input clock. The following solution uses the ICS554-01A which has buffers with low pin to pin skew. The layout diagram below will produce the waveforms shown on the bottom. PCB Layout Recommendations 2) PECL termination networks should be located as close to the outputs as possible. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 5 MDS 527-03 B Integrated Circuit Systems, Inc. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS527-03. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. ● 525 Race Street, San Jose, CA 95126 Revision 122804 ● tel (408) 297-1201 ● www.icst.com Preliminary Information ICS527-03 Clock Slicer User Configurable PECL Output Zero Delay Buffer Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS527-03. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Junction Temperature 175°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Typ. Max. Units Ambient Operating Temperature, ICS527R-02 0 +70 °C Ambient Operating Temperature, ICS527R-02I 0 +70 °C +3.45 V Power Supply Voltage (measured in respect to GND) +3.15 +3.3 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70°C Parameter Symbol Operating Voltage VDD Supply Current IDD Supply Current, Power Down IDDPD Conditions Min. Typ. Max. Units 3.15 3.3 3.45 V 15 MHz in, 60MHz out, no load 15 mA PDTS=0 20 µA Input High Voltage VIH Input Low Voltage VIL Input High Voltage, PECLIN and FBIN VIH Input Low Voltage, PECLIN and FBIN VIL Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA 0.4 6 Revision 122804 MDS 527-03 B Integrated Circuit Systems, Inc. ● 2 V 0.8 V VDD/2+1 VDD/2-1 525 Race Street, San Jose, CA 95126 2.4 ● tel (408) 297-1201 V V V ● V www.icst.com Preliminary Information ICS527-03 Clock Slicer User Configurable PECL Output Zero Delay Buffer Parameter Symbol Conditions Min. Typ. Max. Units Input Capacitance, except PECLIN and FBIN CIN 5 pF Short Circuit Current IOS ±70 mA On-chip pull-up resistor RPU 270 kΩ AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70°C Parameter Symbol Input Frequency Conditions Min. FIN Output Frequency, CLK1 FOUT 0 to +70°C -40 to +85°C Typ. Max. Units 1.5 200 MHz 2.5 160 MHz 4 140 MHz Output Rise Time tOR 0.8 to 2.0V, CL=15pF 1 ns Output Fall Time tOF 2.0 to 0.8V, CL=15pF 1 ns Output Duty Cycle (% high time) tOD Measured at VDD/2, CL=15pF 45 55 % Power Down Time, PDTS low to clocks tri-stated 50 ns Power Up ime, PDTS high to clocks stable 10 ms Deviation from mean Absolute Clock Period Jitter tja One sigma Clock Period Jitter tjs Input to output skew tIO PECLIN to CLK1, Note 1 Device to device skew tpi Common PECLIN, measured at FBIN 50 ± 90 ps 40 ps -250 0 250 ps 500 ps Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2. 7 MDS 527-03 B Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 122804 ● tel (408) 297-1201 ● www.icst.com Preliminary Information ICS527-03 Clock Slicer User Configurable PECL Output Zero Delay Buffer Package Outline and Package Dimensions (28 pin SSOP, 150 mil Body, 0.025 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters 28 Symbol E1 E INDEX AREA 1 2 D A 2 Min A A1 A2 b C D E E1 e L α aaa Inches Max Min 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 9.80 10.00 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0° 8° -0.10 Max .053 .069 .0040 .010 -.059 .008 .012 .007 .010 .386 .394 .228 .244 .150 .157 0.025 Basic .016 .050 0° 8° -0.004 A A 1 c -Ce SEATING PLANE b L aaa C Ordering Information Part / Order Number Marking Shipping packaging Package Temperature ICS527R-03 ICS527R-03 Tubes 28 pin SSOP 0 to +70°C ICS527R-03T ICS527R-03 Tape and Reel 28 pin SSOP 0 to +70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments 8 MDS 527-03 B Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 122804 ● tel (408) 297-1201 ● www.icst.com