ICS ICS650-01B

ICS650-01B
System Peripheral Clock Source
Description
Features
The ICS650-01B is a low cost, low jitter, high
performance clock synthesizer for system
peripheral applications. Using analog/digital
Phase-Locked Loop (PLL) techniques, the device
accepts a parallel resonant 14.31818 MHz crystal
input to produce up to eight output clocks. The
device provides clocks for PCI, SCSI, Fast
Ethernet, Ethernet, and AC97. The user can select
from multiple interface frequencies, and also one
of three AC97 audio frequencies. The OE pin puts
all outputs into a high impedance state for board
level testing. All frequencies are generated with less
than one ppm error, meeting the demands of SCSI
and Ethernet clocking.
The ICS650 can be mask customized to produce
any frequencies from 1 to 150 MHz.
• Packaged in 20 pin tiny SSOP (QSOP)
ª Operating VDD of 3.3V or 5V
• Less than one ppm synthesis error in all clocks
• Inexpensive 14.31818 MHz crystal or clock input
• Provides Ethernet and Fast Ethernet clocks
• Provides SCSI clocks
• Provides PCI clocks
• Selectable AC97 audio clock
• Selectable interface clock
• OE pin tri-states the outputs for testing
• Selectable frequencies on three clocks
• Duty cycle of 40/60
• Advanced, low power CMOS process
Block Diagram
PSEL1:0
ASEL
Clock
Synthesis
Circuitry
BSEL
14.31818 MHz
crystal X1
Crystal
Oscillator
X2
Output
Buffer
2
4
Processor Clocks
(Fast Ethernet,
SCSI, PCI )
Output
Buffer
Audio Clock
Output
Buffer
B Clock 1
Output
Buffer
B Clock 2
Output
Buffer
14.31818 MHz
Output Enable (all outputs)
1
Revision 041499
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax
MDS 650-01B A
ICS650-01B
System Peripheral Clock Source
Pin Assignment
Processor Clock (MHz)
BSEL
1
20
PSEL1
X2
2
19
PSEL0
X1
3
18
PCLK2
VDD
4
17
PCLK3
GND
5
16
VDD
GND
6
15
ASEL
BCLK1
7
14
GND
BCLK2
8
13
14.318M
ACLK
9
12
PCLK1
PCLK4
10
11
OE
20 pin (150 mil) SSOP
PSEL1 PSEL0
PCLK1
PCLK2,3
PCLK4
0
0
25.00
50.00
18.75
0
M
TEST
TEST
TEST
0
1
TEST
TEST
TEST
M
0
40.00
80.00
20.00
M
M
33.3334
66.6667
25.00
M
1
20.00
40.00
25.00
1
0
20.00
33.3334
25.00
1
M
20.00
66.6667
25.00
1
1
Stops low all cloocks except BCL
LK2.
B Clocks (MHz)
BSEL
0
M
1
BCLK1
3.688
50
80
BCLK2
4.917
25
40
Audio Clock (MHz)
ASEL
0
M
1
ACLK
49.152
24.576
12.288
0 = connect directly to ground, 1 = connect directly
to VDD, M=leave unconnected (floating)
Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
BSEL
X2
X1
VDD
GND
GND
BCLK1
BCLK2
ACLK
PCLK4
OE
PCLK1
14.318M
GND
ASEL
VDD
PCLK3
PCLK2
PSEL0
PSEL1
Type
I
XO
XI
P
P
P
O
O
O
O
I
O
O
P
I
P
O
O
I
I
Description
BCLK1 and BCLK2 Select pin. Determines frequency of B clocks per table above.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal. Leave open for clock.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal, or clock.
Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
Connect to ground.
Connect to ground.
BCLK1 output. Determined by BSEL pin per table above.
BCLK2 output. Determined by BSEL pin per table above. Only clock active if PSEL1, 0=1.
AC97 Audio clock output per table above.
PCLK output number 4 per table above.
Output Enable. Tri-states all outputs when low.
PCLK output number 1 per table above.
14.31818 MHz buffered reference clock output.
Connect to ground.
ACLK Select pin. Determines frequency of Audio clock per table above.
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
PCLK output number 3 per table above.
PCLK output number 2 per table above.
Processor Select pin #0. Determines frequencies on PCLKs 1-4 per table above.
Processor Select pin #1. Determines frequencies on PCLKs 1-4 per table above.
Key: I = Input; XO/XI = crystal connections; O = output; P = power supply connection
2
Revision 041499
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax
MDS 650-01B A
ICS650-01B
System Peripheral Clock Source
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
7
VDD+0.5
70
260
150
V
V
°C
°C
°C
5.5
V
V
V
V
V
V
mA
mA
mA
pF
ABSOLUTE MAXIMUM RATINGS (n
note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
Referenced to GND
Referenced to GND
-0.5
0
Max of 10 seconds
-65
DC CHARACTERISTICS (VDD = 3.3V
V or 5V unless noted))
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, VDD = 3.3 or 5V
Operating Supply Current, IDD, at 5V
Operating Supply Current, IDD, at 3.3V
Short Circuit Current, VDD = 3.3
Input Capacitance
3.0
2
Select inputs, OE
Select inputs, OE
VDD=3.3V, IOH=-8mA
2.4
VDD=3.3V, IOL=8mA
IOH=-8mA
VDD-0.4
No Load, note 2
No Load, note 2
Each output
Except X1
0.8
0.4
50
25
±50
7
AC CHARACTERISTICS (VDD = 3.3V
V or 5V unless noted)
Input Crystal or Clock Frequency
Output Clocks Accuracy (synthesis error)
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
One Sigma Jitter
One Sigma Jitter
Absolute Clock Period Jitter
Notes:
14.31818
All clocks
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
Except ACLK
ACLK
PCLK, UCLK, BCLK
40
- 500
50
75
170
1
1.5
1.5
60
500
MHz
ppm
ns
ns
%
ps
ps
ps
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With all clocks at highest frequencies.
External Components
The ICS650 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between VDD and GND (on pins 4 and 6, and pins 16 and 14),
as close to the chip as possible. A series termination resistor of 33 Ω may be used for each clock output. The
14.31818 MHz crystal must be connected as close to the chip as possible. The crystal should be a
fundamental mode, parallel resonant, 30 ppm or better (to meet the Ethernet specs). Crystal capacitors
should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by
the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-12) x 2. So for a
crystal with 16pF load capacitance, two 8pF caps should be used. If a clock input is used, drive it into X1
and leave X2 unconnected.
3
Revision 041499
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax
MDS 650-01B A
ICS650-01B
System Peripheral Clock Source
Package Outline and Package Dimensions
20 pin SSOP
Millimeters
Symbol
E
H
c
Q
e
b
Max
A
1.55
1.73
b
0.203
0.305
c
0.190
0.254
D
8.560
8.740
E
3.810
4.000
H
5.840
6.200
e
0.635 BSC
h
h x 45°
D
Min
0.410
L
0.016
0.035
Q
0.127
0.250
A
L
Ordering Information
Part/Order Number
ICS650R-01
ICS650R-01T
ICS650R-01I
ICS650R-01IT
Marking
ICS650R-01
ICS650R-01
ICS650R01I
ICS650R01I
Package
20 pin SSOP
20 pin SSOP
20 pin SSOP
20 pin SSOP
Shipping
Tubes
Tape and Reel
Tubes
Tape and Reel
Temperature
0 to 70 °C
0 to 70 °C
-40 to 85 °C
-40 to 85 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
4
Revision 041499
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax
MDS 650-01B A