ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83948I-01 is a low skew, 1-to-12 Differential-to-LVCMOS Fanout Buffer and a member HiPerClockS™ of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS83948I-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines. • 12 LVCMOS outputs ,&6 The ICS83948I-01 is characterized at 3.3V core/3.3V output. Guaranteed output and part-to-part skew characteristics make the ICS83948I-01 ideal for those clock distribution applications demanding well defined performance and repeatability. • Selectable LVCMOS clock or differential CLK, nCLK inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 150MHz • Output skew: 350ps (maximum) • Part to part skew: 1.5ns (maximum) • 3.3V core, 3.3V output • -40°C to 85°C ambient operating temperature • Pin compatible with the MPC948/948L BLOCK DIAGRAM PIN ASSIGNMENT Q3 VDDO Q2 GND Q1 VDDO Q Q0 GND D CLK_EN 32 31 30 29 28 27 26 25 LVCMOS_CLK 1 CLK nCLK 0 Q0 Q1 CLK_SEL Q2 Q3 Q4 CLK_SEL 1 24 GND LVCMOS_CLK 2 23 Q4 CLK 3 22 VDDO nCLK 4 21 Q5 CLK_EN 5 20 GND OE 6 19 Q6 VDD 7 18 VDDO GND 8 17 Q7 Q5 GND Q8 VDDO Q9 GND Q10 VDDO Q7 9 10 11 12 13 14 15 16 Q11 Q6 ICS83948I-01 Q8 Q9 Q10 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Q11 OE 83948AYI-01 www.icst.com/products/hiperclocks.html 1 REV. A SEPTEMBER 23, 2002 ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 CLK_SEL Input Pullup 2 LVCMOS_CLK Input Pullup Description Clock select input. Selects LVCMOS clock input when HIGH. Selects CLK, nCLK inputs when LOW. LVCMOS / LVTTL interface levels. Clock input. LVCMOS / LVTTL interface levels. 3 CLK Input Pullup Non-inver ting differential clock input. 4 nCLK Input 5 CLK_EN Input Pullup Pullup Pulldown Inver ting differential clock input. Clock enable. LVCMOS / LVTTL interface levels. 6 OE Input 7 8, 12, 16, 20, 24, 28, 32 9, 11, 13, 15, 17, 19, 21, 23 25, 27, 29, 31 10, 14, 18, 22, 26, 30 VDD Power Core supply pin. GND Power Power supply ground. Output Clock outputs. LVCMOS / LVTTL interface levels. Power Output supply pins. Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0 VDDO Output enable. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN 25 pF RPULLUP Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ROUT Output Impedance 7 Ω CPD Test Conditions Minimum Typical Maximum Units 4 pF TABLE 3A. CLOCK SELECT FUNCTION TABLE Control Input Clock CLK_SEL CLK, nCLK LVCMOS_CLK 0 Selected De-selected 1 De-selected Selected TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs Input to Output Mode Polarity Differential to Single Ended Non Inver ting HIGH Differential to Single Ended Non Inver ting LOW Single Ended to Single Ended Non Inver ting Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inver ting CLK_SEL LVCMOS_CLK CLK nCLK Q0:Q12 0 — 0 1 LOW 0 — 1 0 0 — 0 Biased; NOTE 1 0 — 1 0 — Biased; NOTE 1 0 HIGH Single Ended to Single Ended Inver ting 0 — Biased; NOTE 1 1 LOW Single Ended to Single Ended Inver ting 1 0 — — LOW Single Ended to Single Ended Non Inver ting 1 1 — — HIGH Single Ended to Single Ended Non Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 83948AYI-01 www.icst.com/products/hiperclocks.html 2 REV. A SEPTEMBER 23, 2002 ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, Tstg 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40° TO 85° Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Input Supply Voltage 3.0 3.3 3.6 V VDDO Output Supply Voltage 3.0 3.3 3.6 V IDD Quiescent Supply Current 55 mA Maximum Units 3.6 V TABLE 4B. DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40° TO 85° Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage LVCMOS/LVTTL VIL Input Low Voltage LVCMOS/LVTTL 0.8 V VPP CLK, nCLK 0.15 1.3 V CLK, nCLK GND + 0.5 VDD - 0.85 V IIN Peak-to-Peak Input Voltage Input Common Mode Voltage; NOTE 1, 2 Input Current ±100 µA VOH Output High Voltage VCMR 2 IOH = -20mA 2.5 Output Low Voltage IOL = 20mA VOL NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 83948AYI-01 www.icst.com/products/hiperclocks.html 3 V 0.4 V REV. A SEPTEMBER 23, 2002 ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40° TO 85° Symbol Parameter fMAX Maximum Output Frequency CLK, nCLK; NOTE 1A Propagation Delay tPD LVCMOS_CLK; NOTE 1B tsk(o) Output Skew; NOTE 2, 6 tsk(pp) Par t-to-Par t Skew; NOTE 3, 6 tR tF Output Rise Time Output Fall Time tPW Output Pulse Width tPZL, tPZH Output Disable Time; NOTE 4 Test Conditions Minimum 150 Maximum Units MHz 2.5 6.5 ns 3 5.5 ns 350 ps 1.5 ns 0.2 0.2 2 1.0 1.0 ns ns ns tPeriod/2 - 800 tPeriod/2 + 800 ps 11 ns Measured on rising edge @VDDO/2 CLK, nCLK LVCMOS_CLK Measured on rising edge @VDDO/2 0.8V to 2V 0.8V to 2V tPLZ, tPHZ Typical Output Enable Time; NOTE 4 11 CLK_EN to 1 Clock Enable CLK Setup Time; tS CLK_EN to NOTE 5 0 LVCMOS_CLK CLK to 0 Clock Enable CLK_EN Hold Time; tH LVCMOS_CLK NOTE 5 1 to CLK_EN NOTE 1A: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 1B: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Setup and Hold times are relative to the falling edge of the input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. 83948AYI-01 www.icst.com/products/hiperclocks.html 4 ns ns ns ns ns REV. A SEPTEMBER 23, 2002 ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±0.15V SCOPE VDD, VDDO Qx LVCMOS GND -1.65V±0.15V 3.3V OUTPUT LOAD TEST CIRCUIT VDD nCLK V PP Cross Points V CMR CLK GND DIFFERENTIAL INPUT LEVEL 83948AYI-01 www.icst.com/products/hiperclocks.html 5 REV. A SEPTEMBER 23, 2002 ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER VDDO 2 Qx VDDO 2 Qy tsk(o) OUTPUT SKEW PART 1 VDDO 2 Qx VDDO 2 PART 2 Qy tsk(pp) PART-TO-PART SKEW 2V 2V 0.8V 0.8V Clock Outputs t OUTPUT RISE 83948AYI-01 t R AND F FALL TIME www.icst.com/products/hiperclocks.html 6 REV. A SEPTEMBER 23, 2002 ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER V DD 2 LVCMOS_CLK nCLK CLK V DDO 2 Q0:Q11 t ➤ ➤ PD PROPAGATION DELAY V Q0:Q11 V DDO DDO 2 2 t t t DDO 2 PW t odc = V PERIOD PW PERIOD tPW & tPERIOD 83948AYI-01 www.icst.com/products/hiperclocks.html 7 REV. A SEPTEMBER 23, 2002 ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 2 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 83948AYI-01 www.icst.com/products/hiperclocks.html 8 REV. A SEPTEMBER 23, 2002 ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83948I-01 is: 1040 83948AYI-01 www.icst.com/products/hiperclocks.html 9 REV. A SEPTEMBER 23, 2002 ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.10 REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-026 83948AYI-01 www.icst.com/products/hiperclocks.html 10 REV. A SEPTEMBER 23, 2002 ICS83948I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS83948AYI-01 ICS83948AYI01 32 Lead LQFP 250 per tray -40°C to 85°C ICS83948AYI-01T ICS83948AYI01 32 Lead LQFP on Tape and Reel 1000 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83948AYI-01 www.icst.com/products/hiperclocks.html 11 REV. A SEPTEMBER 23, 2002